VSG stability evaluation and grading current limiting method based on fault power angle characteristics

Abstract

The invention relates to a VSG stability evaluation and grading current limiting method based on fault power angle characteristics. The method comprises the following steps: carrying out transient stability quantitative evaluation on current amplitude limiting control and transient virtual impedance based on an equal area criterion, and generating optimization design suggestions of the current amplitude limiting controller and the transient virtual impedance; generating a power grid fault judgment logic containing a buffer area as an intermediate state based on the optimization design suggestion; respectively generating power outer ring overcurrent limiting strategies under the condition of power overload and the condition of fault ride-through; internal current limiting strategies including transient virtual impedance current limiting control and apparent current amplitude limiting control are generated respectively; and designing and generating a current-limiting state machine based on a power grid fault judgment logic, a power outer ring overcurrent limiting strategy and an internal current-limiting strategy to realize graded current limiting. According to the invention, dynamic switching of the current limiting state is realized through the adaptive power reference and impedance adjustment mechanism, and the fault current is effectively suppressed without affecting the synchronization capability of the power grid.

Description

Technical Field

[0001] This disclosure relates to the field of energy storage converter control, and more specifically, to a method and apparatus for VSG stability assessment and graded current limiting based on fault power angle characteristics. Background Technology

[0002] With the large-scale integration of renewable energy sources (such as solar and wind power) into the power system, the stability and reliability of the power grid face unprecedented challenges. The intermittency and volatility of renewable energy make the frequency and voltage stability of the power grid more difficult to predict. To address this challenge, PCS-VSG (Power Storage Converter-Virtual Generator) based on virtual synchronous machine control has become one of the key devices supporting grids with high renewable energy penetration. PCS-VSG can provide key services such as grid frequency regulation and voltage stabilization, becoming an effective way to achieve a new type of power system that is 100% based on power electronics.

[0003] While PCS-VSGs provide essential support for microgrid / grid stability, their overcurrent characteristics differ significantly from those of traditional synchronous generators (SGs). Traditional SGs can provide short-circuit currents several times their rated value for a short period when facing faults. However, once disturbances occur in the microgrid or grid (such as short-circuit faults, phase skipping, frequency hopping, overload, motor starting, black start, etc.), PCS-VSGs may be forced into an overcurrent state. Furthermore, their overcurrent capacity is limited by software design and the inherent limitations of power semiconductor devices, typically only able to withstand overcurrents slightly above the nominal value. Therefore, designing effective current-limiting strategies to ensure stable operation of PCS-VSGs under fault or overload conditions and prevent equipment shutdown due to overcurrent has become a core research issue.

[0004] The design of current limiting strategies is not only for hardware protection but also determines their dynamic performance under non-nominal grid disturbances. The design of current limiters needs to consider the following aspects: device-level stability; transient system stability; power system protection and fault recovery [Overcurrent Limiting in Grid-Forming Inverters: A Comprehensive Review and Discussion]. Currently, a large amount of research has been dedicated to current limiting control strategies for GFMs, which can be summarized as follows: 1. Software direct current limiting strategy: As the name suggests, this strategy directly limits the fault current. The software method is current loop limiting, which limits the overcurrent caused by the fault by limiting the inner current loop reference. In fact, this strategy is also very common in DC-DC power supplies and VF-controlled inverters.

[0005] II. Hardware Direct Current Limiting: The essence of the wave-by-wave current limiting strategy is to check for overcurrent in each control interrupt cycle, and if so, to provide a PWM blocking signal. In practice, it's not difficult to observe that the direct current limiting strategy cannot maintain the VSG's network characteristics at the time of a fault. Although we cannot theoretically assess the merits of this phenomenon, without anti-saturation PI control as the inner current loop during fault recovery, the outer voltage loop is likely to saturate, leading to VSG malfunction.

[0006] III. Indirect Current Limitation: The idea behind indirect current limiting is to reduce the fault current by adjusting the PCS port voltage in real time to maintain consistency with the PCC fault point voltage. Its typical control strategy keeps the original Vvsg modulation wave unchanged and adds the difference between the PCC voltage and the reference voltage; this approach incorporates voltage feedforward. One advantage of this control strategy is its rapid response. If the grid voltage, Vg, drops to 0V, to prevent current from flowing out, the modulation index needs to be reduced as much as possible. At this point, the proposed strategy comes into play; Vg - Vgn becomes a negative number, pulling down the modulation wave amplitude. Considering steady-state conditions, Vg and Vgn remain approximately equal, and under normal conditions, VVC has no effect. In fact, the virtual impedance limiting strategy is similar to this strategy, except that the voltage difference used in this strategy is calculated as the product of the overcurrent value and the impedance.

[0007] IV. Composite Current Limiting Strategy: A composite current limiting strategy can be achieved by combining software current limiting, hardware current limiting, and indirect current limiting. Different types of current limiters work together, leveraging their unique advantages to enhance overcurrent limiting capabilities and provide greater control over finite currents. Combining direct software current limiting with indirect current limiting achieves better current limiting performance and stability. Furthermore, integrating both grid-connected and grid-connected modes into the PCS is advantageous, as grid-connected current limiting is relatively easier and does not have stability issues. During fault conditions, seamless switching between operating modes achieves the current limiting effect. Simultaneously, existing technologies also offer rapid switching to a voltage hysteresis comparator during fault conditions, achieving current limiting while maintaining voltage source characteristics.

[0008] Although various overcurrent limiting strategies have been developed for PCS-VSG (Physical Synchronous Machine-based Energy Storage Converters), these existing technologies all have significant drawbacks. Direct software current limiting forces the converter out of grid mode, losing its voltage and frequency support capabilities, and is prone to control loop saturation, leading to slow or even unstable fault recovery. Hardware wave-by-wave current limiting, while fast, is too "brutal," completely interrupting energy output and severely threatening system transient stability. Indirect current limiting strategies (such as virtual impedance or voltage feedforward) can maintain certain voltage source characteristics, but the virtual impedance they introduce continuously generates voltage drops and power coupling in both steady and transient states, degrading power quality and affecting dynamic performance. Composite schemes combining different strategies, while intended to compensate for each other's shortcomings, significantly increase the complexity of the control system and the difficulty of parameter tuning, and improperly designed mode-switching logic can introduce new stability risks.

[0009] Therefore, one or more methods are needed to solve the above problems.

[0010] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0011] The purpose of this disclosure is to provide a method and apparatus for VSG stability assessment and graded current limiting based on fault power angle characteristics, thereby overcoming at least to some extent one or more problems caused by the limitations and defects of related technologies.

[0012] According to one aspect of this disclosure, a method for VSG stability assessment and graded current limiting based on fault power angle characteristics is provided, comprising: Based on the equal area criterion EAC, a transient stability quantitative evaluation of the current limiting control CL and the transient virtual impedance TVI is carried out. The dynamic response characteristics and stability differences under fault disturbances are analyzed, and optimization design suggestions for the current limiting controller and the transient virtual impedance are generated. Based on the aforementioned optimization design recommendations, a power grid fault determination logic is generated that includes a buffer as an intermediate state. Generate power outer loop overcurrent limiting strategies for power overload and fault ride-through conditions respectively; Generate internal current limiting strategies that include transient virtual impedance current limiting control and apparent current limiting control respectively; Based on the aforementioned power grid fault determination logic, power outer loop overcurrent limiting strategy, and internal current limiting strategy, a current limiting state machine is designed and generated to achieve graded current limiting.

[0013] In one exemplary embodiment of this disclosure, the method further includes: Based on the equal area criterion EAC, a transient stability quantitative assessment of current limiting control CL is carried out, and a stability criterion under the equal area criterion EAC is generated. The maximum power angle under the current limiting control (CL) is obtained based on the stability criterion. Based on the maximum power angle result under the current limiting control CL, optimization design suggestions for the current limiting controller are generated.

[0014] In one exemplary embodiment of this disclosure, the method further includes: After performing time-domain analysis on the transient virtual impedance TVI, the transient stability of the transient virtual impedance TVI is quantitatively evaluated based on the equal area criterion EAC. The maximum power angle of the system under the transient virtual impedance TVI current limiting strategy is obtained based on the equal area criterion EAC. Based on the system's maximum power angle result of the transient virtual impedance TVI, optimization design suggestions for the transient virtual impedance are generated.

[0015] In one exemplary embodiment of this disclosure, the method further includes dividing the power grid fault region into a clearing zone, a buffer zone, and a fault zone based on the dynamic response of the apparent voltage at the common coupling point (PPC) at different times, wherein: The voltage in the clearing zone is maintained above 0.95 pu, the system operates stably, and no fault handling measures are required; The buffer voltage is between 0.9 and 0.95 pu, and there is a possibility of slight disturbance, but it is not immediately identified as a fault. When the voltage in the fault zone is below 0.9 pu, the system enters a fault state and requires low voltage ride-through (LVRT) strategy control. Wherein, pu stands for per unit, or per unit value.

[0016] In one exemplary embodiment of this disclosure, the method further includes: Under power overload conditions, when the apparent current exceeds the outer loop current limit threshold, a reactive power priority control strategy is adopted, and the active power is corrected based on the hysteresis comparator.

[0017] In one exemplary embodiment of this disclosure, the method further includes: In fault ride-through scenarios, the active and reactive power reference values ​​are adjusted a second time based on preset power grid specifications to achieve power outer loop limiting.

[0018] In one exemplary embodiment of this disclosure, the transient virtual impedance current limiting control in the method further includes: When the overcurrent detection module determines that the instantaneous current exceeds the set value, the hysteresis comparator outputs a high-level signal to avoid frequent switching of control modes; The dynamic virtual resistance is calculated based on the virtual impedance calculation module, and the virtual reactance value is then calculated by setting the X / R coefficient. The voltage drop calculation module uses virtual reactance and virtual resistance values ​​to introduce voltage drop compensation into the voltage controller to adjust the output voltage and limit the peak current.

[0019] In one exemplary embodiment of this disclosure, the apparent current limiting control in the method further includes: By normalizing and scaling the dq-axis current, the current amplitude is ensured to not exceed the preset saturation value.

[0020] In one exemplary embodiment of this disclosure, the current limiting state machine in the method consists of four operating states: In the unrestricted state, the system operates within its normal operating range, with an output current below 1.0 pu and no current limiting operation is performed. In TVI current limiting mode, when the output current is greater than 1.0pu, the transient virtual impedance TVI control mechanism is triggered, which suppresses the current rising trend by adjusting the virtual impedance. In the first-level current limiting state, if the current further increases and exceeds the first-level limit of 1.4 pu during TVI operation, the system switches to the first-level current limiting stage and enables fast current limiting control to ensure hardware safety margin. In the second-level current limiting state, after the first-level current limiting stage is maintained for 1ms, the system enters the second-level current limiting stage, and the current limiting threshold is reduced to 1.1pu, realizing the convergence control of the current and ensuring the stable operation recovery process; Wherein, pu stands for per unit, or per unit value.

[0021] In one aspect of this disclosure, a VSG stability assessment and graded current limiting device based on fault power angle characteristics is provided, comprising: The optimization design module is used to conduct transient stability quantitative evaluation of the current limiting control CL and transient virtual impedance TVI based on the equal area criterion EAC, analyze the dynamic response characteristics and stability differences under fault disturbances, and generate optimization design suggestions for the current limiting controller and transient virtual impedance. A power grid fault determination module is used to generate power grid fault determination logic that includes a buffer as an intermediate state based on the optimized design suggestions. The outer loop overcurrent limiting module is used to generate power outer loop overcurrent limiting strategies under power overload and fault ride-through conditions, respectively. An internal current limiting module is used to generate internal current limiting strategies that include transient virtual impedance current limiting control and apparent current limiting control, respectively. The current limiting state machine generation module is used to design and generate a current limiting state machine based on the power grid fault judgment logic, the power outer loop overcurrent limiting strategy and the internal current limiting strategy to achieve graded current limiting.

[0022] An exemplary embodiment of this disclosure discloses a VSG stability assessment and graded current limiting method based on fault power angle characteristics. The method includes: performing transient stability quantitative assessment of current limiting control and transient virtual impedance based on the equal area criterion, generating optimized design suggestions for the current limiting controller and transient virtual impedance; generating grid fault determination logic including a buffer as an intermediate state based on the optimized design suggestions; generating power outer-loop overcurrent limiting strategies under power overload and fault ride-through conditions respectively; generating internal current limiting strategies including transient virtual impedance current limiting control and apparent current limiting control respectively; and designing and generating a current limiting state machine based on the grid fault determination logic, power outer-loop overcurrent limiting strategy, and internal current limiting strategy to achieve graded current limiting. This disclosure achieves dynamic switching of the current limiting state through an adaptive power reference and impedance adjustment mechanism, effectively suppressing fault current without affecting grid synchronization capability.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The above and other features and advantages of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0025] Figure 1 A flowchart is shown of a VSG stability assessment and graded current limiting method based on fault power angle characteristics according to an exemplary embodiment of the present disclosure; Figure 2 A schematic diagram comparing energy storage VSG and SG is shown in an exemplary embodiment of the present disclosure, illustrating a VSG stability assessment and graded current limiting method based on fault power angle characteristics. Figure 3 A synchronous generator EAC criterion diagram is shown for a VSG stability assessment and graded current limiting method based on fault power angle characteristics according to an exemplary embodiment of the present disclosure; Figure 4 The diagram illustrates the relationship between the limiting clearing angle of an energy storage VSG under different inertia time constants and fault clearing times according to an exemplary embodiment of the present disclosure, based on the VSG stability assessment and graded current limiting method according to the fault power angle characteristics. Figure 5 The diagram illustrates the switching of operating characteristics of an energy storage VSG under current limiting control, based on a VSG stability assessment and graded current limiting method according to an exemplary embodiment of the present disclosure. Figure 6 A schematic diagram of the dynamic trajectory of the power angle and acceleration / deceleration area analysis of an energy storage VSG under current limiting control is shown, based on an exemplary embodiment of the present disclosure and a VSG stability assessment and graded current limiting method according to fault power angle characteristics. Figure 7 A schematic diagram of the maximum power angle under CL current limiting control based on the EAC criterion is shown in an exemplary embodiment of the present disclosure for VSG stability assessment and graded current limiting method based on fault power angle characteristics. Figure 8 A schematic diagram illustrating the influence of CL current limiting mode on the limiting power angle under different control parameters of a VSG stability assessment and graded current limiting method based on fault power angle characteristics according to an exemplary embodiment of the present disclosure is shown. Figure 9 The diagram illustrates the switching of operating characteristics of an energy storage VSG under transient virtual impedance control, based on a VSG stability assessment and graded current limiting method according to an exemplary embodiment of the present disclosure. Figure 10 The diagram illustrates the dynamic trajectory of the power angle and acceleration / deceleration area analysis of an energy storage VSG under transient virtual impedance control, based on a VSG stability assessment and graded current limiting method according to an exemplary embodiment of the present disclosure. Figure 11 A schematic diagram of solving the maximum power angle under TVI current limiting control based on the EAC criterion is shown in an exemplary embodiment of the present disclosure for VSG stability assessment and graded current limiting method based on fault power angle characteristics. Figure 12 A schematic diagram illustrating the influence of TVI current limiting on the limiting power angle under different control parameters of a VSG stability assessment and graded current limiting method based on fault power angle characteristics according to an exemplary embodiment of the present disclosure is shown. Figure 13 A schematic diagram of a current limiting strategy for a VSG stability assessment and graded current limiting method based on fault power angle characteristics according to an exemplary embodiment of the present disclosure is shown. Figure 14 The fault ride-through response voltage curve and region determination diagram of a VSG stability assessment and graded current limiting method based on fault power angle characteristics according to an exemplary embodiment of the present disclosure are shown. Figure 15 A schematic diagram of a fault region determination state machine model for a VSG stability assessment and graded current limiting method based on fault power angle characteristics, according to an exemplary embodiment of the present disclosure, is shown. Figure 16A flowchart of the power outer loop overcurrent limiting algorithm of a VSG stability assessment and graded current limiting method based on fault power angle characteristics according to an exemplary embodiment of the present disclosure is shown. Figure 17 A schematic diagram of a transient virtual impedance control framework and a current over-limit triggering mechanism for a VSG stability assessment and graded current limiting method based on fault power angle characteristics, according to an exemplary embodiment of the present disclosure, is shown. Figure 18 The diagram illustrates a current-limiting state machine and a multi-stage current-limiting logic design for a VSG stability assessment and graded current-limiting method based on fault power angle characteristics, according to an exemplary embodiment of the present disclosure. Figure 19 A schematic block diagram of a VSG stability assessment and graded current limiting device based on fault power angle characteristics according to an exemplary embodiment of the present disclosure is shown. Detailed Implementation

[0026] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0027] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0028] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0029] In this example embodiment, a method for VSG stability assessment and graded current limiting based on fault power angle characteristics is first provided; refer to Figure 1 As shown, this method for VSG stability assessment and graded current limiting based on fault power angle characteristics may include the following steps: Step S110: Based on the equal area criterion EAC, perform transient stability quantitative evaluation on the current limiting control CL and the transient virtual impedance TVI, analyze the dynamic response characteristics and stability differences under fault disturbance, and generate optimization design suggestions for the current limiting controller and the transient virtual impedance. Step S120: Generate power grid fault determination logic that includes a buffer as an intermediate state based on the optimized design suggestions; Step S130: Generate power outer loop overcurrent limiting strategies for power overload and fault ride-through conditions, respectively. Step S140: Generate internal current limiting strategies that include transient virtual impedance current limiting control and apparent current limiting control, respectively. Step S150: Based on the power grid fault determination logic, the power outer loop overcurrent limiting strategy, and the internal current limiting strategy, design and generate a current limiting state machine to achieve graded current limiting.

[0030] An exemplary embodiment of this disclosure discloses a VSG stability assessment and graded current limiting method based on fault power angle characteristics. The method includes: performing transient stability quantitative assessment of current limiting control and transient virtual impedance based on the equal area criterion, generating optimized design suggestions for the current limiting controller and transient virtual impedance; generating grid fault determination logic including a buffer as an intermediate state based on the optimized design suggestions; generating power outer-loop overcurrent limiting strategies under power overload and fault ride-through conditions respectively; generating internal current limiting strategies including transient virtual impedance current limiting control and apparent current limiting control respectively; and designing and generating a current limiting state machine based on the grid fault determination logic, power outer-loop overcurrent limiting strategy, and internal current limiting strategy to achieve graded current limiting. This disclosure achieves dynamic switching of the current limiting state through an adaptive power reference and impedance adjustment mechanism, effectively suppressing fault current without affecting grid synchronization capability.

[0031] The following will further explain a method for VSG stability assessment and graded current limiting based on fault power angle characteristics in this example embodiment.

[0032] Example 1: In step S110, the transient stability of the current limiting controller CL and the transient virtual impedance TVI can be quantitatively evaluated based on the equal area criterion EAC. The dynamic response characteristics and stability differences under fault disturbances are analyzed, and optimization design suggestions for the current limiting controller and the transient virtual impedance are generated.

[0033] In this example embodiment, the method further includes: Based on the equal area criterion EAC, a transient stability quantitative assessment of current limiting control CL is carried out, and a stability criterion under the equal area criterion EAC is generated. The maximum power angle under the current limiting control (CL) is obtained based on the stability criterion. Based on the maximum power angle result under the current limiting control CL, optimization design suggestions for the current limiting controller are generated.

[0034] In this example embodiment, the method further includes: After performing time-domain analysis on the transient virtual impedance TVI, the transient stability of the transient virtual impedance TVI is quantitatively evaluated based on the equal area criterion EAC. The maximum power angle of the system under the transient virtual impedance TVI current limiting strategy is obtained based on the equal area criterion EAC. Based on the system's maximum power angle result of the transient virtual impedance TVI, optimization design suggestions for the transient virtual impedance are generated.

[0035] In step S120, a power grid fault determination logic that includes a buffer as an intermediate state can be generated based on the optimized design suggestions.

[0036] In this example embodiment, the method further includes dividing the power grid fault area into a clearing zone, a buffer zone, and a fault zone based on the dynamic response of the apparent voltage at the common coupling point (PPC) at different times, wherein: The voltage in the clearing zone is maintained above 0.95 pu, the system operates stably, and no fault handling measures are required; The buffer voltage is between 0.9 and 0.95 pu, and there is a possibility of slight disturbance, but it is not immediately identified as a fault. When the voltage in the fault zone is below 0.9 pu, the system enters a fault state and requires low voltage ride-through (LVRT) strategy control. Wherein, pu stands for per unit, or per unit value.

[0037] In step S130, power outer loop overcurrent limiting strategies can be generated under power overload conditions and fault ride-through conditions, respectively.

[0038] In this example embodiment, the method further includes: Under power overload conditions, when the apparent current exceeds the outer loop current limit threshold, a reactive power priority control strategy is adopted, and the active power is corrected based on the hysteresis comparator.

[0039] In this example embodiment, the method further includes: In fault ride-through scenarios, the active and reactive power reference values ​​are adjusted a second time based on preset power grid specifications to achieve power outer loop limiting.

[0040] In step S140, internal current limiting strategies including transient virtual impedance current limiting control and apparent current limiting control can be generated respectively.

[0041] In this example embodiment, the transient virtual impedance current limiting control in the method further includes: When the overcurrent detection module determines that the instantaneous current exceeds the set value, the hysteresis comparator outputs a high-level signal to avoid frequent switching of control modes; The dynamic virtual resistance is calculated based on the virtual impedance calculation module, and the virtual reactance value is then calculated by setting the X / R coefficient. The voltage drop calculation module uses virtual reactance and virtual resistance values ​​to introduce voltage drop compensation into the voltage controller to adjust the output voltage and limit the peak current.

[0042] In this example embodiment, the apparent current limiting control in the method further includes: By normalizing and scaling the dq-axis current, the current amplitude is ensured to not exceed the preset saturation value.

[0043] In step S150, a current limiting state machine can be designed and generated based on the power grid fault determination logic, the power outer loop overcurrent limiting strategy, and the internal current limiting strategy to achieve graded current limiting.

[0044] In this example embodiment, the current limiting state machine in the method consists of four operating states: In the unrestricted state, the system operates within its normal operating range, with an output current below 1.0 pu and no current limiting operation is performed. In TVI current limiting mode, when the output current is greater than 1.0pu, the transient virtual impedance TVI control mechanism is triggered, which suppresses the current rising trend by adjusting the virtual impedance. In the first-level current limiting state, if the current further increases and exceeds the first-level limit of 1.4 pu during TVI operation, the system switches to the first-level current limiting stage and enables fast current limiting control to ensure hardware safety margin. In the second-level current limiting state, after the first-level current limiting stage is maintained for 1ms, the system enters the second-level current limiting stage, and the current limiting threshold is reduced to 1.1pu, realizing the convergence control of the current and ensuring the stable operation recovery process; Wherein, pu stands for per unit, or per unit value.

[0045] In this example embodiment, the multi-stage current-limiting control strategy combining current limiting (CL) and transient virtual impedance (TVI) aims to improve the stability and fault ride-through capability of the energy storage virtual synchronous generator (VSG) under different fault conditions. By utilizing the equal area criterion (EAC), this paper quantifies the performance of different current-limiting methods under fault conditions, particularly their impact on the maximum power angle. The approach is as follows: given the fault clearing time, the fault clearing angle can be calculated. Then, the limiting power angle is calculated to evaluate the stability of the grid-connected energy storage converter. The proposed strategy achieves dynamic switching of the current-limiting state through adaptive power reference and impedance adjustment mechanisms, effectively suppressing fault current without affecting grid synchronization capability. Experiments included various scenarios such as resistive load, overload, and motor starting, as well as typical fault types such as single-phase, two-phase, and three-phase grid faults, verifying that the proposed strategy can effectively suppress overcurrent and maintain system stability. The innovation of this disclosure lies in: (1) A stability evaluation method based on EAC is proposed to quantify the impact of different current limiting strategies on fault clearing time and maximum power angle, and then evaluate the transient stability and system recovery capability of VSG; (2) A dual-state machine framework was designed and implemented to realize the dynamic switching of the current limiting strategy, ensure that the overcurrent is quickly suppressed during the fault period, and ensure voltage stability; (3) The effectiveness of the proposed strategy under different fault and load conditions was verified by hardware-in-the-loop (HIL) experiments, demonstrating the superior performance of the method under high current disturbance conditions.

[0046] Example 2: In this example embodiment, the following table is the parameter table of this disclosure:

[0047] In this example embodiment, the basic concepts of energy storage VSG and EAC rules, including the design of energy storage VSG current-carrying capacity and current-carrying point, include: The overcurrent point for energy storage VSG fault ride-through depends to some extent on the hardware design. The overcurrent point design should also cooperate with the hardware. Generally, the greater the overcurrent capacity supported by the hardware, the easier it is for the energy storage VSG to pass through the fault ride-through. However, this will increase the hardware cost to some extent (such as choosing an IGBT module with a larger capacity, a cooling fan with a higher power or a water cooling system, or need to optimize the overall machine cooling structure again). This disclosure adopts the conventional design in the industry, so that without changing the existing hardware structure, the fault ride-through of the energy storage VSG can be achieved only by optimizing the algorithm. The energy storage converter operates normally in the range of 0 to 1 p.u., can operate for a long time in the range of 1 to 1.2 p.u., and can continuously operate for 30 s in the range of 1.2 p.u. to 1.5 p.u. The hardware overcurrent point is set at 1.5 p.u. When the output current amplitude exceeds 1.5 p.u., the hardware protection will be quickly triggered, resulting in shutdown. The default of this disclosure follows the design of the hardware overcurrent point of 1.5 p.u., and the goal is to control the output current of the energy storage VSG at the overcurrent moment to avoid hardware overcurrent protection and continue to operate or shut down as planned.

[0048] The proposed current limiting strategy has multiple current thresholds. To help readers better understand the current limiting means of this disclosure, all current limiting values are given in the per-unit form of the output apparent current. The overall current range is divided into five sections: 1. Normal Operation (normal operation area): is < 1.0 p.u., the system is in a steady state and no current limiting control is required.

[0049] 2. Long Term Run (long-term sustainable operation area): 1.0 p.u. < is ≤ 1.2 p.u., which is the area where the current is slightly out of limit, corresponding to the working range of the TVI current limiting strategy. Among them: iCLmax2 = 1.1 p.u.: the limit value of the CL secondary current limiter; iPmax = 1.15 p.u.: the limit value of the maximum power point iTVmax = 1.2 p.u.: the TVI current limiting upper limit.

[0050] [[ID=ID=17]]3. 30s short-term operation area: 1.2 p.u. < is ≤ 1.4 p.u., which is the area where the system is allowed to withstand overcurrent for a short time, mainly relying on the first-level CL current limiter to suppress the current.

[0051] iCLmax1 = 1.4 p.u.: the CL first-level current limiting threshold.

[0052] 4. Shut down (shutdown area): is > 1.5 p.u., the hardware current limiting threshold. Exceeding this value may trigger the overcurrent protection action, and the system enters the shutdown or derating operation state.

[0053] In this example embodiment, the comparison between energy storage VSG and synchronous generator (SG) includes: A virtual synchronous generator (VSG) based on energy storage reconstructs the inertial and damping characteristics primarily by simulating the rotor motion equations, analogous to the operating principle of a synchronous generator (SG). Its equivalent relationship is as follows: Figure 2 As shown.

[0054] In terms of structure and function, the energy storage battery is equivalent to the prime mover in the SG, providing kinetic energy support for the system. The prime mover in the SG outputs mechanical power. P m In VSG, this corresponds to active reference power. P ref SG's output power P e Then, with respect to the output power of the VSG P o The correspondence is consistent. The inertia of the VSG is supported by the energy storage unit, and the rotational inertia is simulated through a control algorithm. J (or inertial time constant) H This allows for dynamic response adjustment of the system frequency.

[0055] In this example embodiment, the application of the equal area criterion EAC with the synchronous generator (SG) includes: In a synchronous generator system, the prime mover applies mechanical torque to the shaft. T m (Unit N) m), while the motor body generates electromagnetic torque during its interaction with the power grid. T e When the system is disturbed, if T m > T e This will generate a positive accelerating torque. T a This causes the rotor to accelerate. The accelerating torque can be expressed as: (1) Ignoring non-electromagnetic torques such as friction, iron loss, and wind resistance, T a This will cause the rotor to accelerate. The moment of inertia of the generator system is composed of both the prime mover and the generator body, and is measured in kg. m 2 During the disturbance, the rotor angle δ (Unit: rad) The dynamic change satisfies the oscillation equation: (2) in, HThe system's inertial constant (unit: s) and moment of inertia. J The relationship is: (3) in S base The system's rated capacity is expressed in VA. ω 0 represents the system's rated angular frequency.

[0056] Under transient disturbances, if the system can eventually reduce the rotor angle δ If a system oscillates around a certain equilibrium point with a finite amplitude, it is considered transiently stable; if δ A monotonically increasing trend indicates that the system has lost synchronization and is in a transient unstable state. In a single-machine infinite bus system, the complete oscillation curve does not need to be plotted; instead, the system stability can be determined graphically using the equal area criterion (EAC).

[0057] After converting power into torque and substituting it into the oscillation equation, we get: (4) Multiply both sides simultaneously dδ / dt By integrating over the period of disturbance, we obtain: (5) Where δ0 is the steady-state rotor angle before the disturbance, and δm is the maximum value reached by the rotor angle. In a stable system, the rotor angle will first accelerate to δm, then decelerate and fall back, completing one full oscillation cycle. Therefore, at δ=δm, the rate of change of angular velocity must be zero, that is: (6) The above equation shows that the kinetic energy (area Aa) gained by the rotor during the acceleration phase must be equal to the energy lost (area Ad) during the deceleration phase in order to ensure system stability.

[0058] Figure 3 The diagram illustrates the power-angle curves and corresponding oscillation paths under transiently stable and unstable conditions. The only difference between the two cases is the fault clearing time. The arrows in the diagram indicate the direction of rotor angle movement along the power angle trajectory. In the stable scenario, Aa = Ad, and the rotor angle reaches its maximum value and then swings back; however, in the unstable scenario, due to the lag in fault clearing, Aa > Ad, the rotor angle continues to rise, and the system becomes unstable.

[0059] The EAC criterion is commonly used to calculate the ultimate clearing time and ultimate clearing angle of synchronous generators under fault scenarios. δ RM This allows us to determine the stability margin of the system under a specific fault duration, providing a theoretical basis for fault clearing strategies and protection action timing.

[0060] In this example embodiment, the analysis of the relationship between the inertial response time and the ultimate cutoff power angle of the energy storage VSG includes: Unlike the power angle stability limit of synchronous generators in power systems, the fault clearance time limit of energy storage VSGs has been specified in relevant standards. Typically, the upper limit of fault ride-through time can be obtained by referring to tables in relevant standards, while the overload capacity depends on the engineering capabilities of the energy storage converter and its supporting components.

[0061] The power angle of the energy storage VSG at the initial operating moment is denoted as: δ According to standards, the required support time for the energy storage converter varies depending on the fault depth, typically ranging from 0.15s, 0.625s, and 2s. Considering the most severe three-phase ground fault scenario, the VSG must operate continuously for at least 0.15s to meet the ride-through requirement. The inertia time constant of the energy storage system... H The design time is typically between 3 and 12 seconds.

[0062] When a disturbance occurs in the system, the accelerating torque causes the rotor angle to accelerate, and its angular acceleration (unit: rad / s²) can be expressed as: (7) Based on this, the fault limit cutoff power angle of the energy storage VSG δ RM (Unit: rad) can be expressed as: (8) As can be seen from the above relationship, the ultimate resection angle depends on the fault clearance time. t With the system's inertia time constant H Therefore, under the condition of fault ride-through, in order to ensure transient stability, the fault clearing time should be controlled to not exceed the critical value.

[0063] Figure 4 The limit cut-off power angle is shown under different inertia time constants and fault clearing times. δ RM The three-dimensional relationship diagram can be used to analyze the changing trend of VSG transient stability margin.

[0064] In electrical engineering, it is generally believed that when the limiting cut-off angle... δ RM When the system approaches π / 2, it reaches the boundary of transient stability; while when δ RM When the voltage exceeds π, the system will completely lose its synchronous stability. At this point, the generator will switch from power generation mode to electric operation mode, and the same applies to VSG energy storage. Therefore, π / 2 and π are set as reference planes in the figure to define the stability limits.

[0065] As shown in the figure, with the fault clearance time t The increase in the angle of resection δ RM It gradually increases, eventually approaching the stability boundary. δ RM When the voltage exceeds π, the power angle of the energy storage VSG exceeds a critical value, and its operating mode will switch from generation to motoring. This process has been verified in electromagnetic transient simulations. Similarly, the inertia time constant... H The smaller the value, the larger the limiting cut-off angle of the system, indicating that its transient stability is worse.

[0066] As shown in Equation (8), the ultimate cutoff angle δRM under fault conditions can be calculated by combining the operating power angle δ0 before the VSG failure and the inertia coefficient H set in the control strategy. This result will serve as the basis for the subsequent analysis of the maximum power angle δm under different current limiting strategies, thereby providing quantitative support for transient stability assessment.

[0067] In this example embodiment, the transient stability assessment of the two current-limiting strategies for energy storage VSG includes: Currently, various current limiting methods have been proposed for VSG control strategies. This disclosure selects two typical methods—current limit control (CL) and transient virtual impedance control (TVI)—and conducts a quantitative assessment of transient stability based on the equal area criterion EAC to analyze their dynamic response characteristics and stability differences under fault disturbances.

[0068] In this example embodiment, the transient stability assessment of the current limiting control (CL) includes: When a fault or disturbance causes the apparent current output of the energy storage VSG to... I When Is exceeds the preset limit, the control system will switch to constant current source mode to protect the converter devices and energy storage unit. When Is returns to below the limit, the control system will automatically exit the current limiting state and return to voltage source mode.

[0069] During transient processes, the current limiting mechanism (CL) dynamically adjusts the voltage output amplitude and phase to achieve current control, thereby affecting the transient energy release path of the system. Its operating characteristics alter the equivalent Pe curve, which in turn affects the distribution of acceleration and deceleration areas in the EAC criterion. Therefore, dynamic stability assessment must be conducted in conjunction with the power angle change process and the current limiting threshold.

[0070] like Figure 5The figure shows the external characteristics of an energy storage VSG under current limiting (CL) control. In the figure, EEE represents the output voltage amplitude of the energy storage VSG, Vg is the grid-side voltage amplitude, Lg and Rg are the line inductance and resistance, respectively, δ is the power angle of the energy storage VSG, and φ is an adjustable parameter, which is usually adjusted by setting idref and iqref to rotate the current reference vector.

[0071] When a fault occurs and the output current Is exceeds the limit value Imax, the system enters the current limiting state. At this time, the outer loop regulation is suppressed. The controller changes the angle and amplitude of the output current by resetting the current reference components idref and iqref, thereby affecting the power angle change path of the VSG and making it exhibit P-δ characteristics different from those under normal operating conditions.

[0072] Under CL control, the active power of the energy storage VSG can be approximated as a piecewise form: (9) in, k This is the voltage coefficient scaling factor at the time of the fault. φ The reference angle for current control is expressed as: (10) After entering the current-limited state, the VSG outer loop (i.e., the Pf loop) is not cut off. At this time, the equal area criterion can still be used for transient stability analysis, which is especially suitable for evaluating the dynamic evolution process under strong disturbances.

[0073] like Figure 6 The figure shows the power angle characteristic curve of the energy storage VSG under current limiting (CL) control and the power trajectory curve under normal voltage source control mode. After the fault disturbance occurs, the power angle response path of the system goes through a→b→c→d→e in sequence.

[0074] Before the fault occurred, the system operated in steady state at point a (corresponding to the initial power angle δ0). When the fault occurred, the energy storage VSG entered current-limiting mode, and the system moved to point b, starting to operate in constant current source mode and continuously accelerating, with the power angle gradually increasing until it reached the limit cutoff angle δRM. If the fault is cleared or the current-limiting control is disengaged at this point, the system power curve returns to its normal trajectory and continues operating from point c. After the power angle reaches its maximum value δm, it falls back and eventually returns to the steady-state point a.

[0075] During this process, the kinetic energy gained by the work angle during the acceleration phase corresponds to the area Aa, which is calculated as follows: (11) The energy release area Ad corresponding to the deceleration phase is: (12) The stability criterion can be derived from the equal area criterion EAC: (13) Since equation (13) is a transcendental equation, it cannot be solved analytically. Therefore, it needs to be solved using MATLAB numerical methods. After substituting the actual system parameters, the limiting power angle obtained is as follows: Figure 7 As shown in the figure, the simulation results show that if the current limiting control is not enabled, the energy storage VSG cannot maintain transient stability; however, with the current limiting control enabled, the system can operate stably up to the maximum power angle of 0.93 rad (53.51°). Therefore, this method can be used to evaluate the stability boundary of the energy storage VSG under fault conditions.

[0076] To further evaluate the influence of different parameters on the limiting work angle δm Figure 7 This paper illustrates the influence of relevant control variables on the transient stability margin of the system under network control (i.e., CL current-limiting mode). Three typical cases are selected in the figure, and by fixing one parameter, the influence trends of the other two variables on δm are analyzed.

[0077] exist Figure 8 The above figure shows the fixed active reference power. Research on flow limiting capabilities The effect of the current phase angle φ. The results show that, with... As the current factor decreases and φ decreases (approaching unity power factor), the system's limiting power angle increases significantly, indicating an improved transient stability margin. This trend suggests that appropriately lowering the current limiting threshold and controlling reactive power output helps enhance system stability during fault ride-through.

[0078] exist Figure 8 The image shows a fixed current limiting capacity. Further analysis The coupling effect with φ. It can be observed that... Increasing φ will exacerbate power injection, leading to a decrease in system δm; while increasing φ introduces more reactive components, which actually helps improve system stability. Therefore, adopting a "reactive power priority" mode during faults helps improve the system's disturbance rejection capability.

[0079] Figure 8 The diagram below shows a further fixed current phase angle φ = 20°. ,exhibit and The interaction effects. The overall trend shows that, under fixed phase angle conditions, the matching relationship between current-limiting parameters is highly sensitive to the system stability margin. Especially in high... Smaller In cases where this is common in severe faults such as zero-voltage ride-through, the limiting power angle δm decreases rapidly, making the system more prone to instability.

[0080] Based on the above analysis, to ensure that the current limiting controller has good transient stability and current limiting robustness under fault conditions, the following four aspects can be optimized in the design: (1) Reduce the active power reference value. In the early stage of the fault (i.e., when the overcurrent occurs), appropriately reduce the active power reference power P. This can effectively reduce the acceleration area of ​​the system and increase the deceleration area, thereby improving the stability margin of the system.

[0081] (2) Increase the system inertia constant. The deceleration area of ​​the system is proportional to the inertia constant H. Therefore, appropriately increasing H in the control strategy can improve the system's ability to buffer transient disturbances.

[0082] (3) Appropriately increase the current limiting threshold Imax. Increasing the maximum current limit can increase the active peak value in the current limiting power curve, thereby reducing the acceleration area in the early stage of the fault and helping to maintain system stability. However, this strategy may compress the maximum power angle δmax of the system, limiting its power angle swing range.

[0083] (4) A two-level current limiting strategy is adopted. In order to balance current limiting protection and system transient stability, this disclosure proposes a two-level current limiting mechanism (Two-Level CL), which realizes flexible adjustment of power dynamic changes by setting current limits in stages, and makes up for the limitations of single limit control in maximum power angle control.

[0084] In this example embodiment, the TVI time-domain analysis of the impact of TVI on transient stability includes: Considering that the VI is generally responsible for power distribution during grid connection or networking, this disclosure retains the original VI function during fault ride-through and adopts transient virtual impedance (TVI).

[0085] When a grid fault occurs, the internal electromotive force of the VSG can be approximated. E The amplitude and phase remain essentially unchanged, that is: (14) in, E (0 - The electromotive force (EMF) within the grid converter before the fault occurred. E (0 + The voltage difference before and after the fault is expressed as: (15) V f (0- ), V f (0 + ) represent the voltage at the fault point before the fault and during the fault, respectively; Δ V f This refers to the voltage change at the fault point (including amplitude and phase changes).

[0086] During a power grid fault, the VSG voltage and current dynamically satisfy the basic circuit equations (assuming the current loop is not in a limiting state at this transient moment, i.e., the CT does not start): (16) The fault current can be expressed as: (17) Ig(0 - Let be the steady-state operating current of the virtual synchronous generator; and let Ig be the fault current caused by voltage dips. The transient component of the fault current decays according to the time constant Leq / Req. Increasing the equivalent resistance can accelerate the decay of the transient current component. Ignoring the dynamic process of the transient current component, the fault current of the VSG can be expressed as: (18) in conclusion: R v / L v The larger the value, the faster the fault current decays; a separate boost... R or X It can suppress the fault current of GFM at the time of fault.

[0087] In this example embodiment, the TVI area analysis includes: The TVI current limiter reduces the output current by decreasing the reference voltage of the feed-in voltage controller, thereby maintaining the inherent voltage source characteristics of the GFM inverter. Figure 8 This is a schematic diagram showing the switching of the operating characteristics of an energy storage VSG under transient virtual impedance control.

[0088] The power angle relationship between the normal period and the TVI current-limited period can be obtained as follows: (19) Figure 10 In the middle, the angle of fault clearing RM Setting the same parameters facilitates comparison of the changing trends of acceleration area Aa and deceleration area Ad during fault crossing under different control parameters.

[0089] exist Figure 10 In the upper left center, the system does not adopt the TVI strategy and has a small inertia. During the fault, the power angle changes rapidly, the obtained deceleration area is limited, and the transient stability margin is low.

[0090] Figure 10 The upper right corner shows the case of increasing the system's inertia. It can be observed that the deceleration area of ​​the system increases significantly after the inertia is increased, while the limiting power angle... m The expansion helps improve the system's stability recovery capability after fault disturbances.

[0091] Figure 10 The lower left shows the effect of introducing TVI regulation in the early stage of a fault. TVI increases the system output impedance transiently, changing the power angle-power characteristic curve during the fault period. This allows the system to obtain a smoother power angle response and a larger deceleration area during the transient process of transitioning from normal operation to fault state, thereby improving transient stability.

[0092] Figure 10 The lower right corner further illustrates another strategy: by adjusting the controller's reference power angle at the moment of fault occurrence, a lateral shift in the power angle-power characteristic is achieved, thereby reducing the acceleration area. This strategy can also effectively improve the system's stability margin and enhance the fault adaptability under VSG control during fault ride-through.

[0093] Applying the EAC equal area, the system acceleration area at the TVI time is: (20) After the fault is cleared, the output impedance recovers, and the deceleration area is: (twenty one) By balancing the area: (twenty two) Here is a semi-analytical expression for the limiting angle of work: (twenty three) In equation (23) P * , δ 0, δ RM , E , V g , Z g , k All of these can be considered known constants. Since the variables in this expression are all in radians and the unit is per unit, the limiting power angle of the system under different TVI parameter configurations can be numerically solved using MATLAB. max.

[0094] Figure 11The results of calculating the maximum power angle of the system under the TVI current-limiting strategy based on the equal area criterion (EAC) are presented. Comparison with the calculation results of the CL current-limiting strategy shown in the figure reveals that, under the same control parameters and initial power angle conditions, the limiting power angles obtained by the two current-limiting methods are quite close. Specifically, the maximum power angle under the CL current-limiting strategy is approximately 0.93 rad, while that under the TVI strategy is 0.98 rad.

[0095] Although the difference in the limiting power angle values ​​is not significant, the two strategies fundamentally differ in their control methods: the CL current-limiting strategy suppresses the current reference value, temporarily equipping the energy storage VSG with a current source operation mode; while the TVI strategy retains the voltage source characteristics of the VSG during faults and achieves current suppression by injecting virtual impedance. Therefore, TVI is more advantageous in maintaining the system's grid-connected capability and voltage support performance, exhibiting a significant advantage in control characteristics.

[0096] However, the TVI strategy is not as fast as CL current limiting in terms of fault current suppression response speed. Because TVI needs to recalculate the reference voltage based on the virtual inductance and resistance and complete the control response through the outer loop, there is a certain delay in dynamic adjustment; while the CL control strategy directly applies the limit in the inner current loop, resulting in a fast control response and achieving a more efficient current limiting effect.

[0097] Therefore, in practical engineering applications, TVI and CL control strategies can be flexibly selected or combined according to the system operation mode, network requirements and the need for current suppression speed, in order to achieve stable operation and protection goals under fault conditions.

[0098] To further evaluate the effect of control parameters on the system's limiting power angle δ max The impact, Figure 12 This study demonstrates the effect of different control parameter configurations on the transient stability of the system under the TVI current limiting strategy.

[0099] As shown in the figure, changes in the transient virtual impedance value have a certain impact on the limiting power angle. When the equivalent impedance value in the TVI gradually increases, the limiting power angle of the system shows a slight decreasing trend. Based on the aforementioned time-domain analysis results, a larger virtual impedance helps to enhance the suppression capability of fault current and improve the current limiting effect. However, the results in the figure also indicate that a larger virtual impedance is not always better; excessively high transient virtual impedance will compress the deceleration area of ​​the system, reduce the limiting power angle, and may adversely affect the transient stability of the system. Therefore, in TVI design, it is necessary to reasonably balance the relationship between the current limiting strength and the system stability margin.

[0100] The figure also assesses the impact of fault ride-through depth on the limiting power angle. The trend is consistent with conventional understanding: as the voltage drop increases (i.e., the lower the fault ride-through voltage), the system's ride-through difficulty increases, resulting in a significant decrease in stability. Specifically, as the fault ride-through coefficient k decreases, the limiting power angle gradually decreases, making it more difficult for the system to maintain synchronization; conversely, as k increases, indicating a higher voltage level, the limiting power angle of the system rises rapidly, and the stability margin is significantly improved.

[0101] In this example embodiment, the control strategy design includes: This disclosure organically integrates transient virtual impedance control with current limiting mechanism, and designs a multi-level current limiting control strategy, the overall structure of which is as follows: Figure 13 As shown, the proposed grid-type energy storage converter current limiting control system adopts an innovative "three-module dual-state machine" architecture, which achieves precise suppression of fault current and simultaneous guarantee of system stability through a hierarchical collaborative mechanism.

[0102] The core of this control architecture lies in the coordinated operation of five functional modules: (1) Power grid fault determination state machine: Based on key operating parameters such as voltage and current, the power grid status is monitored in real time, and the fault crossing state machine is driven to accurately identify the fault type and severity. (2) Current limiting strategy switching state machine: Automatically switch TVI control, current inner loop limiting and other strategies according to the fault level to realize the dynamic optimal configuration of the current limiting mechanism; (3) Adaptive power command module: dynamically adjusts the active / reactive power reference values ​​during current limiting to ensure the rationality of power allocation and the stability of power angle; (4) Adaptive TVI parameter adjustment module: Adjusts the virtual impedance parameter in real time according to the system response to achieve a dynamic trade-off between current limiting capability and system stability; (5) Ring current limiter module: As the final protection stage, it accurately controls the current amplitude to prevent over-limit impact.

[0103] This current limiting strategy has three main characteristics: "rapid response, multi-level control, and adaptive adjustment". It can suppress current in stages under fault disturbances, effectively improving the overload capacity and grid adaptability of the energy storage system.

[0104] In this example embodiment, the power grid fault determination logic includes: Figure 14 Demonstrates voltage V s At different times t ( sThe system dynamically responds to data and is divided into three zones: Clear Zone, Buffer Zone, and Fault Zone. These three zones are defined as follows: Clear Zone (Upper): The voltage is maintained above 0.95 pu, the system operates stably, and no fault handling measures are required.

[0105] Buffer Zone (middle): The voltage is between 0.9 and 0.95 pu. Slight disturbances may occur, but they are not immediately identified as faults.

[0106] Fault Zone (lower part): When the voltage is below 0.9 pu, the system enters a fault state and requires Low Voltage Ride-Through (LVRT) strategy control.

[0107] Introducing a buffer zone as an intermediate state effectively avoids false triggering of fault protection, improving the system's dynamic response and disturbance rejection capability. Through hierarchical control, the buffer zone allows the system to make slight adjustments under short-term disturbances, improving power supply reliability. Furthermore, it can adapt to different types of grid disturbances. For transient voltage drops (such as momentary short circuits, lightning strikes, load surges, etc.), the buffer zone allows for short-term voltage fluctuations without immediately triggering fault handling. For long-term low-voltage issues, the buffer zone provides a transitional state, ensuring that the voltage is indeed below the safe threshold before triggering fault zone protection. This makes the low-voltage ride-through (LVRT) strategy more flexible, reduces unnecessary disconnection of renewable energy grid-connected equipment, and improves system stability.

[0108] During fault ride-through, all possible voltage change curves are as follows: Figure 14 Curves ①-⑤ are shown in the diagram. Curves ① and ② are in the Clear Zone and Buffer Zone respectively, and therefore are not marked as faults. Curve ③ drops below 0.9 pu at time A, and is therefore judged as a fault crossover. Curve ④ enters the fault zone at time B and is marked; even though the voltage recovers to the Buffer Zone value at time C, the fault state remains. Curve ⑤ experiences a fault crossover at time D and recovers to the Clear Zone at time E, completing fault clearance.

[0109] In the embodiments of this example, as Figure 15 To determine the state machine model for the fault region, the overcurrent limit for the outer power loop in the overcurrent point setting includes: (1) Under power overload conditions, when the apparent current exceedsi Pmax The energy storage VSG should lower its power reference to ensure no overcurrent occurs. The control strategy adopted in this disclosure is a reactive power priority control strategy, meaning that reactive current output is guaranteed first, followed by limiting active power output. Active power correction. As shown in equation (24): (twenty four) In the formula H prev To maintain the state from the previous moment, i.e. without switching the active power reference, this design can be achieved by setting the hysteresis comparator in software.

[0110] (2) In the case of fault ride-through, the active and reactive power reference values ​​need to be adjusted twice. When the power grid is faulty, the reactive current required to be provided is calculated by the GC0137 power grid standard. i qcmp (25) Vs is the apparent voltage, vn is the rated voltage, and vd is the d-axis voltage. K This is the compensation gain during a grid fault. From equation X, the reactive power reference correction required at this time can be obtained as: (26) Simultaneously, based on the reactive current, the maximum value of the active current can be estimated as follows: (27) The active power secondary reference correction is obtained from formula X as follows: (28) The power outer loop limiting flowchart is shown in Figure 16.

[0111] In this example embodiment, the internal rate limiting strategy includes: The current strategy disclosed herein combines transient virtual impedance with direct current limiting strategy, and in order to make it fully compatible, a corresponding state machine is designed to switch in real time according to the overcurrent state.

[0112] In this example embodiment, the transient virtual impedance current limiting control includes: Although virtual impedance is effective in current limiting, it is generally used to regulate power distribution in microgrid construction and to adapt to grid impedance over a wide range in grid connection. Therefore, the transient virtual impedance strategy adopted in this disclosure aims to preserve the proper function of virtual impedance during grid connection / connection. The transient virtual impedance structure adopted in this disclosure is as follows: Figure 17 As shown, the transient virtual impedance only takes effect when the apparent current exceeds the limit.

[0113] Figure 17The transient virtual impedance control framework shown mainly consists of three parts: an overcurrent detection module, a virtual impedance calculation module, and a voltage drop calculation module. First, the overcurrent detection module determines whether an overcurrent has occurred by comparing the instantaneous current is with a set threshold (1.2pu). When... i s When the set value is exceeded, the hysteresis comparator (hysteresis range ±0.01) outputs a high-level signal to avoid frequent switching of control modes and ensure the stability of the control system as much as possible. Subsequently, this signal enters the virtual impedance calculation module, where the amplification factor... k pRvi Used to calculate dynamic virtual resistance R vi To accommodate different current levels. And through settings X / R The coefficients are then used to calculate the virtual reactance value. Finally, based on the calculated virtual reactance and virtual resistance values, the voltage drop calculation module introduces the voltage drop compensation amount into the voltage controller, thereby adjusting the output voltage and limiting the current peak.

[0114] The formulas for calculating the dynamic virtual resistance and reactance are as follows: (29) make , Figure 17 The mathematical description is as follows: (30) In this example embodiment, the apparent current limiting control includes: This disclosure does not directly limit the amplitude of the voltage loop output (current reference signal). Instead, it ensures that the final current amplitude does not exceed a set saturation value by normalizing and scaling the dq-axis current. The specific structure is as follows: Figure 18 As shown. In fact, the maximum value of the dq axis current is calculated as shown in equation (31): (31) In this example embodiment, the current-limiting state machine design includes: To achieve rapid response and graded current limiting adjustment to current disturbances of different amplitudes, this disclosure designs as follows: Figure 18 The state machine shown represents the current limiting state determination. This state machine consists of four operating states: (1) Unlimited state: When the system is in normal operating range, the output current is less than 1.0 pu and no current limiting operation is performed.

[0115] (2) TVI current limiting state: When the output current is greater than 1.0pu, the transient virtual impedance TVI control mechanism is triggered, and the current rise trend is suppressed by adjusting the virtual impedance.

[0116] (3) Level 1 current limiting state: If the current rises further and exceeds the level 1 limit of 1.4pu during TVI operation, the system immediately switches to the level 1 current limiting link and enables fast current limiting control to ensure hardware safety margin.

[0117] (4) Second-level current limiting state: After the first-level current limiting link is maintained for 1ms, the system automatically enters the second-level current limiting link, the current limiting threshold is reduced to 1.1pu, the current convergence control is realized, and the stable operation recovery process is guaranteed.

[0118] The state machine design fully considers the speed and phased accuracy of the current limiting response, ensuring both current suppression and avoiding control oscillations caused by frequent switching.

[0119] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0120] Furthermore, in this example embodiment, a VSG stability assessment and graded current limiting device based on fault power angle characteristics is also provided. (Refer to...) Figure 19 As shown, the VSG stability assessment and graded current limiting device 200 based on fault power angle characteristics may include: an optimization design module 210, a power grid fault determination module 220, an outer loop overcurrent limiting module 230, an internal current limiting module 240, and a current limiting state machine generation module 250. Wherein: The optimization design module 210 is used to conduct transient stability quantitative evaluation of the current limiting control CL and the transient virtual impedance TVI based on the equal area criterion EAC, analyze the dynamic response characteristics and stability differences under fault disturbances, and generate optimization design suggestions for the current limiting controller and the transient virtual impedance. The power grid fault determination module 220 is used to generate power grid fault determination logic that includes a buffer as an intermediate state based on the optimized design suggestions. The outer loop overcurrent limiting module 230 is used to generate power outer loop overcurrent limiting strategies under power overload and fault ride-through conditions, respectively. Internal current limiting module 240 is used to generate internal current limiting strategies that include transient virtual impedance current limiting control and apparent current limiting control, respectively. The current limiting state machine generation module 250 is used to design and generate a current limiting state machine based on the power grid fault judgment logic, the power outer loop overcurrent limiting strategy and the internal current limiting strategy to achieve graded current limiting.

[0121] The specific details of each of the VSG stability assessment and graded current limiting device modules based on fault power angle characteristics mentioned above have been described in detail in the corresponding VSG stability assessment and graded current limiting method based on fault power angle characteristics, so they will not be repeated here.

[0122] It should be noted that although several modules or units of a VSG stability assessment and graded current limiting device 200 based on fault power angle characteristics have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0123] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0124] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0125] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for VSG stability assessment and graded current limiting based on fault power angle characteristics, characterized in that, The method includes: Based on the equal area criterion EAC, a transient stability quantitative evaluation of the current limiting control CL and the transient virtual impedance TVI is carried out. The dynamic response characteristics and stability differences under fault disturbances are analyzed, and optimization design suggestions for the current limiting controller and the transient virtual impedance are generated. Based on the aforementioned optimization design recommendations, a power grid fault determination logic is generated that includes a buffer as an intermediate state. Generate power outer loop overcurrent limiting strategies for power overload and fault ride-through conditions respectively; Generate internal current limiting strategies that include transient virtual impedance current limiting control and apparent current limiting control respectively; Based on the aforementioned power grid fault determination logic, power outer loop overcurrent limiting strategy, and internal current limiting strategy, a current limiting state machine is designed and generated to achieve graded current limiting.

2. The method as described in claim 1, characterized in that, The method further includes: Based on the equal area criterion EAC, a transient stability quantitative assessment of current limiting control CL is carried out, and a stability criterion under the equal area criterion EAC is generated. The maximum power angle under the current limiting control (CL) is obtained based on the stability criterion. Based on the maximum power angle result under the current limiting control CL, optimization design suggestions for the current limiting controller are generated.

3. The method as described in claim 1, characterized in that, The method further includes: After performing time-domain analysis on the transient virtual impedance TVI, the transient stability of the transient virtual impedance TVI is quantitatively evaluated based on the equal area criterion EAC. The maximum power angle of the system under the transient virtual impedance TVI current limiting strategy is obtained based on the equal area criterion EAC. Based on the system's maximum power angle result of the transient virtual impedance TVI, optimization design suggestions for the transient virtual impedance are generated.

4. The method as described in claim 1, characterized in that, The method further includes dividing the power grid fault area into a clearing zone, a buffer zone, and a fault zone based on the dynamic response of the apparent voltage at the common coupling point (PPC) at different times, wherein: The voltage in the clearing zone is maintained above 0.95 pu, the system operates stably, and no fault handling measures are required; The buffer voltage is between 0.9 and 0.95 pu, and there is a possibility of slight disturbance, but it is not immediately identified as a fault. When the voltage in the fault zone is below 0.9 pu, the system enters a fault state and requires low voltage ride-through (LVRT) strategy control. Wherein, pu stands for per unit, or per unit value.

5. The method as described in claim 1, characterized in that, The method further includes: Under power overload conditions, when the apparent current exceeds the outer loop current limit threshold, a reactive power priority control strategy is adopted, and the active power is corrected based on the hysteresis comparator.

6. The method as described in claim 1, characterized in that, The method further includes: In fault ride-through scenarios, the active and reactive power reference values ​​are adjusted a second time based on preset power grid specifications to achieve power outer loop limiting.

7. The method as described in claim 1, characterized in that, The transient virtual impedance current limiting control in the method also includes: When the overcurrent detection module determines that the instantaneous current exceeds the set value, the hysteresis comparator outputs a high-level signal to avoid frequent switching of control modes; The dynamic virtual resistance is calculated based on the virtual impedance calculation module, and the virtual reactance value is then calculated by setting the X / R coefficient. The voltage drop calculation module uses virtual reactance and virtual resistance values ​​to introduce voltage drop compensation into the voltage controller to adjust the output voltage and limit the peak current.

8. The method as described in claim 1, characterized in that, The apparent current limiting control in the method further includes: By normalizing and scaling the dq-axis current, the current amplitude is ensured to not exceed the preset saturation value.

9. The method as described in claim 1, characterized in that, The current-limiting state machine in the method consists of four operating states: In the unrestricted state, the system operates within its normal operating range, with an output current below 1.0 pu and no current limiting operation is performed. In TVI current limiting mode, when the output current is greater than 1.0pu, the transient virtual impedance TVI control mechanism is triggered, which suppresses the current rising trend by adjusting the virtual impedance. In the first-level current limiting state, if the current further increases and exceeds the first-level limit of 1.4 pu during TVI operation, the system switches to the first-level current limiting stage and enables fast current limiting control to ensure hardware safety margin. In the second-level current limiting state, after the first-level current limiting stage is maintained for 1ms, the system enters the second-level current limiting stage, and the current limiting threshold is reduced to 1.1pu, realizing the convergence control of the current and ensuring the stable operation recovery process; Wherein, pu stands for per unit, or per unit value.

10. A VSG stability assessment and graded current limiting device based on fault power angle characteristics, characterized in that, The device includes: The optimization design module is used to conduct transient stability quantitative evaluation of the current limiting control CL and transient virtual impedance TVI based on the equal area criterion EAC, analyze the dynamic response characteristics and stability differences under fault disturbances, and generate optimization design suggestions for the current limiting controller and transient virtual impedance. A power grid fault determination module is used to generate power grid fault determination logic that includes a buffer as an intermediate state based on the optimized design suggestions. The outer loop overcurrent limiting module is used to generate power outer loop overcurrent limiting strategies under power overload and fault ride-through conditions, respectively. An internal current limiting module is used to generate internal current limiting strategies that include transient virtual impedance current limiting control and apparent current limiting control, respectively. The current limiting state machine generation module is used to design and generate a current limiting state machine based on the power grid fault judgment logic, the power outer loop overcurrent limiting strategy and the internal current limiting strategy to achieve graded current limiting.

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