A bus holding circuit

Abstract

The application relates to the field of integrated circuits, in particular to a bus holding circuit which comprises a main inverter module and a feedback loop module, the main inverter module comprises an inverter unit and a Schmitt unit, the feedback loop module comprises an internal control signal locking unit, a double-loop feedback unit, a power protection unit and a self-adaptive substrate bias unit; the double-loop feedback unit comprises an NMOS feedback branch and a PMOS feedback branch; the internal control signal locking unit automatically locks the level of a Z node to a high level, avoids the metastable state problem, guarantees that the bus state is predictable when the system starts, the NMOS feedback branch and the PMOS feedback branch are used to pull down and pull up the level of an input node A, ensure that the input signal A level switching is complete, and the problems of oscillation or too long delay are avoided.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a bus hold circuit. Background Technology

[0002] In integrated circuits, numerous functional circuit modules rely on buses for data transmission and interaction. The stability of the bus voltage directly affects the normal and reliable operation of the entire system. Bus holding circuits can accurately monitor changes in the bus voltage. Through their sophisticated internal circuit structure and control mechanisms, they provide a stable and continuous bus voltage input to the functional circuit sections, ensuring that the functional circuits receive the required power supply under various operating scenarios. This guarantees that the entire integrated circuit system can efficiently and stably complete its preset tasks, greatly improving the performance and reliability of electronic products.

[0003] Traditional bus latching circuits, such as positive feedback latches composed of two inverters, lack an internal state locking mechanism during the power-on initialization phase due to the circuit's symmetry. This can cause the latch to fall into a metastable state, resulting in uncertain output states. Furthermore, they typically employ fixed feedback paths, which remain identical regardless of the bus state. This lack of adaptability and effective control mechanisms can lead to oscillations during switching or incomplete state transitions when the external drive strength is close to the holding circuit strength. Summary of the Invention

[0004] The purpose of this invention is to provide a bus hold circuit, which aims to improve the existing bus hold circuits that lack an internal state locking mechanism, resulting in uncertainty in the output state, and that when using a fixed feedback path, the external drive strength may be close to the hold circuit strength, leading to oscillations during the switching process or incomplete state switching.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A bus hold circuit includes a main inverter module and a feedback loop module. The main inverter module includes an inverter unit and a Schmitt trigger unit. The feedback loop module includes an internal control signal lock-in unit, a dual-loop feedback unit, a power supply protection unit, and an adaptive substrate bias unit. The dual-loop feedback unit includes an NMOS feedback branch and a PMOS feedback branch.

[0007] External power supply VDD is input to the main inverter module and the feedback loop module;

[0008] Input signal A is input to the inverter unit, the internal control signal lockout unit, and the power protection unit. The output terminal of the inverter unit is electrically connected to the control terminal of the Schmitt trigger and the PMOS feedback branch, and outputs signal Y. The first output terminal of the internal control signal lockout unit is electrically connected to the control terminal of the NMOS feedback branch, and outputs a constant high level to the NMOS feedback branch. The output terminals of the NMOS feedback branch and the PMOS feedback branch are both electrically connected to the input node of input signal A.

[0009] The second output terminal of the internal control signal locking unit is electrically connected to the control terminal of the adaptive substrate biasing unit. The adaptive substrate biasing unit is electrically connected to the substrate of the PMOS transistor of the dual-loop feedback unit and the power protection unit, and controls the driving capability of the PMOS transistor. The power protection unit is electrically connected to the internal control signal locking unit and the dual-loop feedback unit, and controls the connection and disconnection between the input node of the input signal A and the external power supply VDD.

[0010] Furthermore, the internal control signal locking unit includes MOSFET P9, MOSFET P10, MOSFET N5 and MOSFET N6;

[0011] The external power supply VDD is electrically connected to the source of MOSFET P9 and the source of MOSFET P10, and the input signal A is input to the gate of MOSFET P9.

[0012] The drain of MOS transistor P9 is electrically connected to the drain of MOS transistor P10, the drain of MOS transistor N5, and the gate of MOS transistor N6, and is electrically connected to the control terminal of the NMOS feedback branch as the first output terminal; the gate of MOS transistor P10 and the gate of MOS transistor N5 are both electrically connected to the drain of MOS transistor N6 and the power protection unit, and are electrically connected to the control terminal of the adaptive substrate bias unit as the second output terminal.

[0013] The sources of both MOS transistor N5 and MOS transistor N6 are grounded.

[0014] Furthermore, the NMOS feedback branch includes MOSFET N3 and MOSFET P6; the PMOS feedback branch includes MOSFET P8 and MOSFET N4.

[0015] The external power supply VDD is electrically connected to the source of MOSFET P6, the first output terminal of the internal control signal locking unit is electrically connected to the gate of MOSFET N3, and the output terminal of the inverter unit is electrically connected to the gate of MOSFET N4.

[0016] The drain of MOSFET N3 is electrically connected to the source of MOSFET P8, the gate of MOSFET P6, and the power protection unit. The source of MOSFET N3 is electrically connected to the drain of MOSFET P8 and the gate of MOSFET N4. The drain of MOSFET P6, the drain of MOSFET N4, and the gate of MOSFET P8 are all electrically connected to the input node of input signal A.

[0017] The substrates of MOS transistor P6 and P8 are electrically connected to the adaptive substrate biasing unit, and the source of MOS transistor N4 and the substrate of MOS transistor N3 are grounded.

[0018] Furthermore, the power protection unit includes MOSFET P5, MOSFET P7 and MOSFET P11;

[0019] The external power supply VDD is electrically connected to the gate of MOSFET P5, the gate of MOSFET P7, and the gate of MOSFET P11. The input signal A is input to the source of MOSFET P7, the drain of MOSFET P5, and the source of MOSFET P11. The source of MOSFET P5, the substrate of MOSFET P7, and the substrate of MOSFET P11 are all electrically connected to the adaptive substrate biasing unit.

[0020] The drain of MOS transistor P7 is electrically connected to the gate of MOS transistor P6, and the drain of MOS transistor P11 is electrically connected to the gate of MOS transistor P10 and the gate of MOS transistor N5.

[0021] Furthermore, the adaptive substrate biasing unit includes a MOS transistor P4;

[0022] The external power supply VDD is electrically connected to the source of MOSFET P4. The gates of MOSFET P10 and MOSFET N5 are both electrically connected to the gate of MOSFET P4. The substrate and gate of MOSFET P4 are electrically connected to the source of MOSFET P5, the substrate of MOSFET P6, the substrate of MOSFET P7, the substrate of MOSFET P8, and the substrate of MOSFET P11.

[0023] Furthermore, the inverter unit includes MOS transistor P1 and MOS transistor N1;

[0024] An external power supply VDD is input to the source of MOSFET P1, and an input signal A is input to the gate of MOSFET P1 and the gate of MOSFET N1. The drains of MOSFET P1 and MOSFET N1 are both used as output terminals and electrically connected to the control terminals of the Schmitt trigger cell and the PMOS feedback branch, and output signal Y.

[0025] The source of the MOS transistor N1 is grounded.

[0026] Furthermore, the Schmitt trigger unit includes MOS transistors P2, P3, and N2;

[0027] An external power supply VDD is input to the source of MOSFET P2 and the source of MOSFET P3. The drain of MOSFET P1 and the drain of MOSFET N1 are electrically connected to the drain of MOSFET P3, the gate of MOSFET P2 and the gate of MOSFET N2. The gate of MOSFET P3 is electrically connected to the drain of MOSFET P2 and the drain of MOSFET N2.

[0028] The source of the MOS transistor N2 is grounded.

[0029] By adopting the above technical solution, the present invention has the following advantages compared with the prior art:

[0030] 1. The inverter unit forms the main communication path between the input signal A and the output signal Y. The Schmitt trigger unit locks the output state of the output signal Y, enhancing output stability and preventing false flipping caused by noise.

[0031] 2. The internal control signal locking unit automatically locks the level of node Z to a high level to avoid metastability issues and ensure that the bus state is predictable when the system starts up. The NMOS feedback branch and PMOS feedback branch are used to pull the level of input node A low and high to ensure that the level switching of input signal A is complete and to avoid oscillation or excessive delay.

[0032] 3. When the voltage of input signal A exceeds VDD, the power supply protection unit isolates input signal A from the power supply voltage VDD to protect the power supply and prevent damage from overvoltage. The adaptive substrate bias unit provides adaptive substrate bias for the substrates of the PMOS transistors in the dual-loop feedback unit and the power supply protection unit.

[0033] 4. When the input signal A is high, it makes it easier for the PMOS transistor to turn on, improving the driving capability. When the input signal A is low, it makes it more difficult for the PMOS transistor to turn on, reducing leakage current. Attached Figure Description

[0034] Figure 1 This is a circuit diagram of the bus holding circuit described in this invention;

[0035] Figure 2 This is a simulation diagram of the bus holding circuit described in this invention.

[0036] Explanation of reference numerals in the attached figures:

[0037] 1. Inverter unit; 2. Schmitt trigger unit; 3. Internal control signal lock-in unit; 4. Dual-loop feedback unit; 5. Power supply protection unit; 6. Adaptive substrate bias unit. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0039] Additionally, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are all based on the orientation or positional relationship shown in the accompanying drawings. They are merely for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element of the present invention must have a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0040] When an element is referred to as being "fixed to," "set on," or "contained on" another element, it can be directly on or indirectly on that other element. When an element is referred to as being "connected to," it can be directly connected to or indirectly connected to that other element.

[0041] Unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Example

[0042] Please refer to Figure 1 and Figure 2 As shown, this embodiment provides a bus hold circuit, including a main inverter module and a feedback loop module. The main inverter module includes an inverter unit 1 and a Schmitt trigger unit 2. The feedback loop module includes an internal control signal locking unit 3, a dual-loop feedback unit 4, a power supply protection unit 5, and an adaptive substrate bias unit 6. The dual-loop feedback unit 4 includes an NMOS feedback branch and a PMOS feedback branch. An external power supply VDD is input to the main inverter module and the feedback loop module.

[0043] Input signal A is input to the inverter unit, the internal control signal lockout unit 3, and the power protection unit 5. The output terminal of inverter unit 1 is electrically connected to the control terminal of Schmitt trigger unit 2 and the PMOS feedback branch, and outputs signal Y. The first output terminal of the internal control signal lockout unit 3 is electrically connected to the control terminal of the NMOS feedback branch, and outputs a constant high level to the NMOS feedback branch. The output terminals of both the NMOS and PMOS feedback branches are electrically connected to the input node of input signal A.

[0044] The second output terminal of the internal control signal locking unit 3 is electrically connected to the control terminal of the adaptive substrate biasing unit 6. The adaptive substrate biasing unit 6 is electrically connected to the substrate of the PMOS transistor in the dual-loop feedback unit 4 and the power protection unit 5, controlling the driving capability of the PMOS transistor. The power protection unit 5 is electrically connected to the internal control signal locking unit 3 and the dual-loop feedback unit 4, controlling the connection and disconnection between the input node of the input signal A and the external power supply VDD.

[0045] Inverter unit 1 forms the main communication path between input signal A and output signal Y. Schmitt trigger unit 2 locks the output state of output signal Y, enhancing output stability and preventing false flipping caused by noise. Internal control signal locking unit 3 automatically locks the level of node Z to a high level to avoid metastability issues and ensures predictable bus state during system startup. NMOS and PMOS feedback branches are used to pull the level of input node A low and high, ensuring complete switching of input signal A and avoiding oscillation or excessive delay. When the voltage of input signal A exceeds VDD, power protection unit 5 isolates input signal A from the power supply voltage VDD to protect the power supply and prevent damage from overvoltage. Adaptive substrate bias unit 6 provides adaptive substrate bias for the substrates of the PMOS transistors in dual-loop feedback unit 4 and power protection unit 5. When input signal A is high, it makes it easier for the PMOS transistor to conduct, improving drive capability; when input signal A is low, it makes it more difficult for the PMOS transistor to conduct, reducing leakage current.

[0046] Please refer to Figure 1 As shown, the inverter unit includes MOSFET P1 and MOSFET N1.

[0047] An external power supply VDD is input to the source of MOSFET P1. Input signal A is input to the gates of MOSFET P1 and MOSFET N1. The drains of MOSFET P1 and MOSFET N1 are both connected as output terminals to the control terminals of Schmitt trigger cell 2 and the PMOS feedback branch, and output signal Y. The source of MOSFET N1 is grounded.

[0048] Schmitt cell 2 includes MOSFETs P2, P3, and N2. An external power supply VDD is input to the source of MOSFET P2 and the source of MOSFET P3. The drains of MOSFET P1 and N1 are electrically connected to the drain of MOSFET P3, the gate of MOSFET P2, and the gate of MOSFET N2. The gate of MOSFET P3 is electrically connected to the drain of MOSFET P2 and the drain of MOSFET N2.

[0049] The source of MOSFET N2 is grounded.

[0050] When Y is high, MOSFET P2 is off, MOSFET N2 is on, and the inverter formed by MOSFETs P2 and N2 outputs low. MOSFET P3 is on, pulling Y to VCC and amplifying Y to a high level. When Y is low, MOSFET P2 is on, MOSFET N2 is off, and the inverter formed by MOSFETs P2 and N2 outputs high. MOSFET P3 is off.

[0051] Please refer to Figure 1 As shown, the internal control signal locking unit 3 includes MOSFET P9, MOSFET P10, MOSFET N5 and MOSFET N6.

[0052] The external power supply VDD is electrically connected to the source of MOSFET P9 and the source of MOSFET P10. The input signal A is input to the gate of MOSFET P9. The drain of MOSFET P9 is electrically connected to the drain of MOSFET P10, the drain of MOSFET N5, and the gate of MOSFET N6, and serves as the first output terminal electrically connected to the control terminal of the NMOS feedback branch. The gates of MOSFET P10 and MOSFET N5 are both electrically connected to the drain of MOSFET N6 and the power protection unit 5, and serve as the second output terminal electrically connected to the control terminal of the adaptive substrate bias unit 6.

[0053] The sources of MOSFET N5 and MOSFET N6 are both grounded.

[0054] During power-on initialization, the power supply voltage VDD rises from 0, at which point all nodes are initially approximately 0V, and all MOSFETs are in the cutoff region. This is because PMOS transistors have gate-source capacitance C. gs When VDD rises, the capacitor C passes through MOSFETs P1, P9, and P11. gs Coupling will cause the voltage at node A to rise.

[0055] Suppose that the power supply voltage VDD rises with a slope of k, i.e., VDD(t) = k*t, where t is time and * is the multiplication operator.

[0056] According to Kirchhoff's current law, the sum of all currents flowing into and out of node A is zero, that is,

[0057] I Cgs +I Cothers +I Rleak =0;

[0058] Among them, the change in VDD is mainly coupled to node A through the capacitance from node A to VDD. The voltage change rates of other nodes are relatively small, so other parasitic capacitances to ground are combined into C. others During the slow rise of VDD, all transistors are in subthreshold or off state, and the channel current is much smaller than the capacitor current, so the channel current can be ignored. Cgs To pass through the gate-source capacitance C gs The current, I Cothers R is the current flowing through other parasitic capacitances. leak For the equivalent leakage resistance, I Rleak This is the leakage current.

[0059] Therefore, the differential equation is as follows, where C total =C gs +C others ;

[0060] ;

[0061] ;

[0062] Therefore, it can be seen that during the power-on initialization process, if node A is left floating, the voltage of node A will rise with VDD, but with a slight lag.

[0063] When VDD > Vthn + |Vthp|, where Vthn is the threshold voltage of the NMOS transistor and Vthp is the threshold voltage of the PMOS transistor. When voltage A is high, MOS transistor P9 is off, so the voltage at node X is approximately 0. MOS transistor P10 pulls the voltage at node Z up to VDD, and the voltage at node Z is fed back to MOS transistor N6, pulling the voltage at node X down to 0. When voltage A is low, MOS transistor P9 is strongly turned on, pulling the voltage at node Z up to VDD. Therefore, regardless of the state of node A, the voltage at node Z is always strongly pulled up to a high level.

[0064] Please refer to Figure 1 As shown, the NMOS feedback branch includes MOSFET N3 and MOSFET P6; the PMOS feedback branch includes MOSFET P8 and MOSFET N4.

[0065] The external power supply VDD is electrically connected to the source of MOSFET P6, the first output terminal of the internal control signal locking unit 3 is electrically connected to the gate of MOSFET N3, and the output terminal of the inverter unit 1 is electrically connected to the gate of MOSFET N4; that is, the drain of MOSFET P9 is electrically connected to the gate of MOSFET N3, and the drains of MOSFET P1 and MOSFET N1 are electrically connected to the gate of MOSFET N4.

[0066] The drain of MOSFET N3 is electrically connected to the source of MOSFET P8, the gate of MOSFET P6, and power protection unit 5. The source of MOSFET N3 is electrically connected to the drain of MOSFET P8 and the gate of MOSFET N4. The drains of MOSFET P6, N4, and P8 are all electrically connected to the input node of input signal A.

[0067] The substrates of MOSFET P6 and MOSFET P8 are electrically connected to the adaptive substrate biasing unit 6, and the source of MOSFET N4 and the substrate of MOSFET N3 are grounded.

[0068] Dual-loop feedback unit 4 is used for feedback and maintaining the bus state; that is, when node A is floating, it maintains the state it was in before it was floating, thus achieving the bus hold function. The NMOS feedback branch and PMOS feedback branch select the feedback path as either PMOS pull-up or NMOS pull-down based on the state of node A.

[0069] When A=1 and Y=0, MOSFET N4 is off. Since the voltage at node Z is locked high, MOSFET N3 is turned on. The gate voltage of MOSFET P6 is pulled down to low by MOSFET N3, and MOSFET P6 is turned on, pulling node A up to keep it equal to 1.

[0070] When A=0 and Y=1, MOSFET N4 is turned on, node A is pulled down to keep it equal to 0, MOSFET P8 is turned on, the gate voltage of MOSFET P6 is pulled high, and MOSFET P6 is turned off.

[0071] Bus low-level holding current I holdlow The pull-down capability of MOSFET N4 determines the following:

[0072] ;

[0073] Where u n C represents the electron mobility of an NMOS transistor. OX V is the gate oxide capacitance of the MOSFET. GSN4 The gate-source voltage difference of MOSFET N4 is expressed in W / L. N4 This represents the width-to-length ratio of MOSFET N4.

[0074] Bus high-level holding current I holdhigh This is determined by the pull-up capability of MOSFET P6, therefore,

[0075] ;

[0076] Where u p V represents the hole mobility of a PMOS transistor. GSP6 This represents the gate-source voltage difference of MOSFET P6.

[0077] Please refer to Figure 1 As shown, the power protection unit 5 includes MOSFET P5, MOSFET P7 and MOSFET P11.

[0078] The external power supply VDD is electrically connected to the gate of MOSFET P5, the gate of MOSFET P7, and the gate of MOSFET P11. The input signal A is input to the source of MOSFET P7, the drain of MOSFET P5, and the source of MOSFET P11. The source of MOSFET P5, the substrate of MOSFET P7, and the substrate of MOSFET P11 are all electrically connected to the adaptive substrate biasing unit 6.

[0079] The drain of MOSFET P7 is electrically connected to the gate of MOSFET P6, and the drain of MOSFET P11 is electrically connected to the gate of MOSFET P10 and the gate of MOSFET N5.

[0080] When the voltage at node A is higher than VDD, MOSFET P11 will conduct, and the potential at node Z will decrease. At this time, MOSFETs P8 and N3 will both be turned off. Simultaneously, MOSFET P7 will turn on, pulling the gate voltage of MOSFET P6 up to the node A voltage, thus turning off MOSFET P6. This protects the power supply by blocking the path between node A and the power supply. The gate of MOSFET P5 is fixed at a high level VDD, and it only conducts when the input voltage at node A is greater than VDD. At this time, the substrate potential K is pulled up to the node A voltage to prevent leakage.

[0081] Please refer to Figure 1 As shown, the adaptive substrate bias unit 6 includes a MOSFET P4. The external power supply VDD is electrically connected to the source of the MOSFET P4. The gates of MOSFET P10 and MOSFET N5 are both electrically connected to the gate of the MOSFET P4. The substrate and gate of the MOSFET P4 are electrically connected to the source of the MOSFET P5, the substrate of the MOSFET P6, the substrate of the MOSFET P7, the substrate of the MOSFET P8, and the substrate of the MOSFET P11.

[0082] The substrate of MOSFET P4 is connected to the drain, serving as a pull-up switch for the substrate potential K.

[0083] According to the body effect formula for the threshold voltage of a MOSFET:

[0084] ;

[0085] Where Vbs is the substrate source voltage, V thp0为 The zero-bias threshold voltage, γ is the body effect coefficient, and ψF is the Fermi potential.

[0086] When the MOS transistor P4 is turned on and the voltage at node K is pulled to VDD by the MOS transistor P4: For each PMOS whose substrate is connected to node K, its body potential is approximately equal to VDD. If the source voltage Vs of this PMOS is < VDD, then V bs > 0. At this time, Vthp decreases, the body effect weakens, the MOS transistor is easier to turn on, and the driving ability increases. When the MOS transistor P4 is turned off and the voltage at node K drops: If the voltage at node K is lower than the source voltage of a certain PMOS transistor, then V bs < 0. At this time, Vthp increases, the body effect strengthens, the MOS transistor is more difficult to turn on, and the leakage current decreases. In this embodiment, the bus holding circuit is made of a pure CMOS process, effectively reducing the process cost.

[0087] Please refer to the appendix Figure 2 , appendix Figure 2 is the simulation diagram under the conditions of Vthp = -0.9V, Vthn = 0.8V, input A floating, and VDD powered on from 0V to 5V within 1us. The voltage at node A rises with the voltage through the gate-source capacitance coupling. The voltage at node Z is pulled up. The potential at node X initially rises with node Z due to the gate-drain coupling of the MOS transistor N6. After VDD > Vthn + |Vthp| and continues to rise, the internal latching mechanism is triggered to pull it down to low. It can be seen that the bus holding circuit disclosed in this embodiment can ensure that the internal node is automatically locked to the predetermined state after power-on.

[0088] As mentioned above, it is only the preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any change or replacement that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A bus holding circuit, characterized in that, It includes a main inverter module and a feedback loop module. The main inverter module includes an inverter unit and a Schmitt trigger unit. The feedback loop module includes an internal control signal lock-in unit, a dual-loop feedback unit, a power supply protection unit, and an adaptive substrate bias unit. The dual-loop feedback unit includes an NMOS feedback branch and a PMOS feedback branch. External power supply VDD is input to the main inverter module and the feedback loop module; Input signal A is input to the inverter unit, the internal control signal lockout unit, and the power protection unit. The output terminal of the inverter unit is electrically connected to the control terminal of the Schmitt trigger and the PMOS feedback branch, and outputs signal Y. The first output terminal of the internal control signal lockout unit is electrically connected to the control terminal of the NMOS feedback branch, and outputs a constant high level to the NMOS feedback branch. The output terminals of the NMOS feedback branch and the PMOS feedback branch are both electrically connected to the input node of input signal A. The second output terminal of the internal control signal locking unit is electrically connected to the control terminal of the adaptive substrate biasing unit. The adaptive substrate biasing unit is electrically connected to the substrate of the PMOS transistor of the dual-loop feedback unit and the power protection unit, and controls the driving capability of the PMOS transistor. The power protection unit is electrically connected to the internal control signal locking unit and the dual-loop feedback unit, and controls the connection and disconnection between the input node of the input signal A and the external power supply VDD.

2. The bus holding circuit according to claim 1, characterized in that: The internal control signal locking unit includes MOSFET P9, MOSFET P10, MOSFET N5 and MOSFET N6; The external power supply VDD is electrically connected to the source of MOSFET P9 and the source of MOSFET P10, and the input signal A is input to the gate of MOSFET P9. The drain of MOS transistor P9 is electrically connected to the drain of MOS transistor P10, the drain of MOS transistor N5, and the gate of MOS transistor N6, and is electrically connected to the control terminal of the NMOS feedback branch as the first output terminal; the gate of MOS transistor P10 and the gate of MOS transistor N5 are both electrically connected to the drain of MOS transistor N6 and the power protection unit, and are electrically connected to the control terminal of the adaptive substrate bias unit as the second output terminal. The sources of both MOS transistor N5 and MOS transistor N6 are grounded.

3. The bus holding circuit according to claim 2, characterized in that: The NMOS feedback branch includes MOS transistor N3 and MOS transistor P6; the PMOS feedback branch includes MOS transistor P8 and MOS transistor N4; The external power supply VDD is electrically connected to the source of MOSFET P6, the first output terminal of the internal control signal locking unit is electrically connected to the gate of MOSFET N3, and the output terminal of the inverter unit is electrically connected to the gate of MOSFET N4. The drain of MOSFET N3 is electrically connected to the source of MOSFET P8, the gate of MOSFET P6, and the power protection unit. The source of MOSFET N3 is electrically connected to the drain of MOSFET P8 and the gate of MOSFET N4. The drain of MOSFET P6, the drain of MOSFET N4, and the gate of MOSFET P8 are all electrically connected to the input node of input signal A. The substrates of MOS transistor P6 and P8 are electrically connected to the adaptive substrate biasing unit, and the source of MOS transistor N4 and the substrate of MOS transistor N3 are grounded.

4. The bus holding circuit according to claim 3, characterized in that: The power protection unit includes MOSFET P5, MOSFET P7 and MOSFET P11; The external power supply VDD is electrically connected to the gate of MOSFET P5, the gate of MOSFET P7, and the gate of MOSFET P11. The input signal A is input to the source of MOSFET P7, the drain of MOSFET P5, and the source of MOSFET P11. The source of MOSFET P5, the substrate of MOSFET P7, and the substrate of MOSFET P11 are all electrically connected to the adaptive substrate biasing unit. The drain of MOS transistor P7 is electrically connected to the gate of MOS transistor P6, and the drain of MOS transistor P11 is electrically connected to the gate of MOS transistor P10 and the gate of MOS transistor N5.

5. The bus holding circuit according to claim 4, characterized in that: The adaptive substrate biasing unit includes a MOS transistor P4; The external power supply VDD is electrically connected to the source of MOSFET P4. The gates of MOSFET P10 and MOSFET N5 are both electrically connected to the gate of MOSFET P4. The substrate and gate of MOSFET P4 are electrically connected to the source of MOSFET P5, the substrate of MOSFET P6, the substrate of MOSFET P7, the substrate of MOSFET P8, and the substrate of MOSFET P11.

6. The bus holding circuit according to claim 5, characterized in that: The inverter unit includes MOS transistor P1 and MOS transistor N1; An external power supply VDD is input to the source of MOSFET P1, and an input signal A is input to the gate of MOSFET P1 and the gate of MOSFET N1. The drains of MOSFET P1 and MOSFET N1 are both used as output terminals and electrically connected to the control terminals of the Schmitt trigger cell and the PMOS feedback branch, and output signal Y. The source of the MOS transistor N1 is grounded.

7. The bus holding circuit according to claim 6, characterized in that: The Schmitt cell includes MOSFET P2, MOSFET P3 and MOSFET N2; An external power supply VDD is input to the source of MOSFET P2 and the source of MOSFET P3. The drain of MOSFET P1 and the drain of MOSFET N1 are electrically connected to the drain of MOSFET P3, the gate of MOSFET P2 and the gate of MOSFET N2. The gate of MOSFET P3 is electrically connected to the drain of MOSFET P2 and the drain of MOSFET N2. The source of the MOS transistor N2 is grounded.

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