Electronic control circuit

Abstract

Provided is an electronic control circuit. The circuit comprises an oscillator circuit for generating a periodic output signal, the output frequency of which is equal to the input frequency multiplied by the dividing ratio of the fractional frequency divider; the feedback circuit comprises an integer type frequency divider and is used for dividing the periodic output signal by a positive integer and providing the output of the integer type frequency divider as a feedback signal to the input of the oscillator circuit; wherein the integer frequency divider outputs as an input periodic signal fed to a time-to-digital converter of the oscillator circuit; wherein the time-to-digital converter is configured to output a digital signal based on an input reference signal having an input frequency and an input periodic signal.

Description

Technical Field

[0001] This invention relates to an electronic control circuit. More particularly, but not limited to, this invention relates to a fractional phase-locked loop control system. Background Technology

[0002] A phase-locked loop (PLL) is an electronic feedback control system used in a variety of applications involving signal synchronization, clock generation, frequency synthesis, and frequency modulation / demodulation. It is designed to track and align the phase and frequency of an input signal with that of a reference signal.

[0003] A PLL can generate an output signal whose phase is aligned with the input signal, and can be selected to have a different frequency than the input signal, such as a clock signal. PLLs are useful in a variety of applications, such as clock synchronization in digital circuits, frequency synthesis for generating stable frequencies, demodulation in communication systems, and signal recovery from noisy channels. Summary of the Invention

[0004] According to a first aspect of the present invention, an electronic control circuit is provided, comprising: an oscillator circuit for generating a periodic output signal LO, the output frequency of which is equal to an input frequency fref multiplied by a fractional frequency divider FCW; and a feedback circuit including an integer frequency divider for dividing the periodic output signal LO by a positive integer and providing the output of the integer frequency divider as a feedback signal to the input of the oscillator circuit; wherein the output of the integer frequency divider is fed as an input periodic signal DIV to a time-to-digital converter (TDC) of the oscillator circuit; wherein the TDC is configured to output a digital signal T based on an input reference signal REF having the input frequency fref and the input periodic signal DIV.

[0005] According to a first aspect of the invention, the electronic control circuit is a fractional-type fully digital phase-locked loop (PLL) control system.

[0006] According to a first aspect of the invention, the oscillator circuit includes the TDC for receiving the input reference signal REF, an oscillator for generating the periodic output signal LO, and a loop filter between them.

[0007] According to a first aspect of the invention, the division ratio FCW of the fractional frequency divider is a combination of the integer part FCW[int] and the fractional part FCW[frac].

[0008] According to a first aspect of the invention, the division ratio FCW of the fractional frequency divider is a rational number greater than or equal to 1.

[0009] According to a first aspect of the invention, the circuit further includes a clock correction stage for converting the digital signal T output by the time-to-digital converter (TDC) based on the input reference signal REF having an input frequency fref and the input periodic signal DIV into a corrected digital signal TC, wherein the input periodic signal DIV is equal to the integer part FCW[int] of the division ratio FCW of a fractional frequency divider, and the TC represents the output of the TDC based on the input frequency and the sum of the integer part FCW[int] and the fractional part FCW[frac] of the division ratio FCW of the fractional frequency divider; wherein the T is related to a first time difference Δt1 between the rising edges of the input signals REF and DIV; wherein the corrected digital signal TC is further provided to the oscillator in the oscillator circuit for generating the periodic output signal LO.

[0010] According to a first aspect of the invention, the integer frequency divider is configured to process the periodic output signal LO using the integer portion FCW[int] of the division ratio FCW of the fractional frequency divider, wherein the integer portion FCW[int] is equal to the floor function of FCW, i.e., rounded down to the nearest integer less than or equal to the division ratio of the fractional frequency divider.

[0011] According to a first aspect of the invention, the clock correction stage includes an adder and a clock correction calculation module, the clock correction calculation module being configured to determine a clock correction digital signal C related to a second time difference Δt2 between a virtual reference clock signal and the input periodic signal DIV, wherein the adder is configured to output the corrected digital signal TC = T + C.

[0012] According to a first aspect of the invention, the first rising edge of the virtual reference clock signal is aligned with the rising edge of the input reference signal REF, and the virtual reference clock signal includes the target frequency f of the input periodic signal DIV after the electronic control circuit is reset. divt .

[0013] According to a first aspect of the invention, the circuit further includes a main reset configured to be activated by a low-level digital reset signal.

[0014] According to a first aspect of the invention, the clock correction calculation module is further configured to determine the clock correction digital signal C based on an integer REC, wherein REC is equal to the rising edge count of DIV between the current rising edge of REF output by the TDC and the previous rising edge of REF.

[0015] According to a first aspect of the invention, wherein:

[0016] The value of C is equal to C[i] on the i-th rising edge of REF after reset, where i is a positive integer index. C[i] is generated as follows:

[0017] For i = 1, C[1] is 0; and

[0018] For i>1,

[0019] (1) If REC equals 1,

[0020]

[0021] (2) If REC equals 0,

[0022]

[0023] (3) If REC is greater than 1,

[0024]

[0025] Where u is the unit time used for TDC quantization, and Δt 1 =T xu and Δt 2 =TC xu;

[0026] Where T divt =FCW[int]x T DCOt f DCOt =FCW[int]xf divt T ref =FCW x T DCOt f DCOt =FCWx f divt f DCOt T represents the target frequency of the periodic output signal LO. DCOt f DCOt The corresponding period, f divt T represents the target frequency of DIV. divt f divt The corresponding period, f ref T represents the target frequency of REF. ref f ref The corresponding cycle.

[0027] According to a first aspect of the invention, the circuit further includes a coarse tuning module for providing a coarse tuning output signal DCT to control the switching of the capacitor of the oscillator in the oscillator circuit, thereby coarsely tuning the periodic output signal LO.

[0028] According to a first aspect of the invention, the coarse adjustment output signal DCT is an accumulation of the input CCT provided by the clock correction calculation module.

[0029] According to a first aspect of the invention, the corrected digital signal TC is filtered by a loop filter before being further provided to the oscillator.

[0030] According to a first aspect of the invention, the oscillator includes a digitally controlled oscillator. Attached Figure Description

[0031] Embodiments of the invention will now be described by way of example with reference to the accompanying drawings, wherein:

[0032] Figure 1 This is a block diagram of an example PLL containing a ΣΔ(sigma-delta) fractional N divider.

[0033] Figure 2 This is a block diagram of an electronic control circuit according to an embodiment of the present invention.

[0034] Figure 3 This is an explanation Figure 2 The diagram shows the waveforms of the clock signal, virtual reference clock signal, and master reset signal involved in the operation of the example electronic control circuit.

[0035] Figure 4 This is a block diagram of an electronic control circuit according to another embodiment of the present invention. Detailed Implementation

[0036] The inventors, through experimentation and design, developed an All Digital Phase-Locked Loop (ADPLL), a type of PLL that utilizes digital signal processing technology to implement various components using digital circuits. Compared to analog components such as voltage-controlled oscillators and analog phase detectors, ADPLLs preferentially rely on digital signal processing modules such as digital phase detectors, digital filters, and digitally controlled oscillators (DCOs) to achieve the required functions. Compared to analog PLLs, ADPLLs offer advantages such as flexibility, reconfigurability, and better noise performance. They can be used in wireless communication systems, frequency synthesis applications, and clock recovery circuits.

[0037] Implementing fractional frequency synthesis (or fractional-N frequency synthesis) techniques in ADPLL, where one does not wish to be bound by theory, involves using digital or fractional frequency dividers to divide the output frequency. Fractional-N dividers / fractional frequency dividers allow for fractional division ratios, thus enabling the generation of fractional output frequencies.

[0038] refer to Figure 1The illustration shows an example embodiment of PLL 100, which includes some key components such as an oscillator circuit 102 including a phase detector (or phase / frequency detector (PFD)) 106, a loop filter 108, a digitally controlled oscillator (DCO) 110, and a feedback circuit 104 for providing feedback signals to the phase detector.

[0039] The PLL operates as follows: First, a stable reference signal or clock signal is provided to PFD 106. The PFD compares the phase and frequency of the reference signal with the phase-divided DCO output signal DIV and generates an error signal based on the phase difference. Then, the error signal may be converted into a current, which may be further filtered by loop filter 108 (such as a low-pass or band-pass filter) to generate a control voltage. Finally, the control voltage adjusts the DCO frequency output by DCO 110. The DCO output is divided by a ΣΔ fractional-N divider in the feedback loop 104. The ΣΔ modulator dynamically changes the division ratio to achieve fractional division, thus allowing for finer frequency resolution.

[0040] In this example, the fractional ADPLL includes a ΣΔ fractional-N divider 112 in the feedback loop 104, where the division ratio is FCW. The input signal of this ΣΔ fractional-N divider is LO0, and the output signal is DIV0.

[0041] For non-integer FCW, this can be achieved by switching the division ratio between at least two integers. This causes the period of the divider's output signal DIV0 to change continuously, which may introduce a significant amount of noise into the time-to-digital converter (TDC) that acts as a PLL phase / frequency detector.

[0042] For example, this electronic control circuit can be used to generate a 2.55 GHz clock signal from a 100 MHz reference clock. Using an integer N (or integer-N) PLL may be limited to integer multiples of the reference frequency, such as 2 GHz or 3 GHz. However, using a fractional (N) PLL, the desired 2.55 GHz can be generated with the following parameters:

[0043] • Clock / Reference Frequency CLK / REF: 100MHz

[0044] • Required output frequency LO / F DCOt 2.55GHz

[0045] • Frequency division ratio (N): 25.5 (fractional)

[0046] In one example operation, the ΣΔ modulator in the feedback loop might alternate between a division ratio of 25 and 26, resulting in an average division ratio of 25.5, thus yielding the desired output frequency. Therefore, fractional division allows for non-integer division ratios, providing the flexibility to achieve precisely the desired frequency. This facilitates the generation of fine-resolution signals that are not integer multiples of the reference clock, making them suitable for applications requiring precise frequency synthesis, such as wireless communication systems.

[0047] For a PLL using an integer N divider, frequency division can only be done in integer proportions. However, a fractional N divider allows for non-integer division ratios, providing finer frequency resolution. This is achieved by periodically switching between different integer division ratios, resulting in a fractional division ratio when averaged over time. To control the switching between integer division ratios, a Sigma-Delta modulator is used, making the frequency divider a fractional divider. It converts the fractional division ratio into a series of integers that, when averaged, approximate the desired fractional value.

[0048] Fractional PLLs are useful in a variety of applications, such as in wireless communications where they are used as frequency dividers to generate precise carrier frequencies. They can also be used for clock generation, providing high-resolution clock signals to digital circuits. In some alternative examples, fractional PLLs can be used in signal processing, which is helpful for applications requiring precise frequency control and low phase noise.

[0049] refer to Figure 2 and Figure 3 An embodiment of an electronic control circuit is shown, comprising: an oscillator circuit for generating a periodic output signal LO, the output frequency of which is equal to the input frequency f. ref The frequency is multiplied by the division ratio FCW of the fractional frequency divider; and a feedback circuit, including an integer frequency divider, for dividing the periodic output signal LO by a positive integer and providing the output of the integer frequency divider as a feedback signal to the input of the oscillator circuit; wherein the output of the integer frequency divider is fed as an input periodic signal DIV to the time-to-digital converter (TDC) of the oscillator circuit; wherein the TDC is configured to output a digital signal T based on an input reference signal REF having the input frequency fref and the input periodic signal DIV.

[0050] In this embodiment, the electronic control circuit is a fractional-digital phase-locked loop (PLL) control system. The circuit comprises three main parts: an oscillator circuit for generating a periodic output signal LO based on an input clock signal or reference signal and a frequency divider signal; a feedback loop that feeds back the output LO to the input, i.e., the TDC, after some processing of the output signal, which helps the system tune or optimize the frequency of the LO when necessary; and a clock correction module for providing the correct voltage control signal to the voltage-controlled oscillator (VCO) or digitally controlled oscillator (DCO), as shown in the figure. The signal conversion in the oscillator circuit will be explained further in a later section of this disclosure.

[0051] For example, using a fractional (-N) PLL, the desired 2.55 GHz can be generated with the following parameters:

[0052] • Clock / Reference Frequency CLK / REF: 100MHz

[0053] • Required output frequency LO / F DCOt 2.55GHz

[0054] • Frequency division ratio (N): 25.5 (fractional)

[0055] Unlike the ΣΔ modulator used in the feedback loop, which may alternate between a division ratio of 25 and 26 to achieve an average division ratio of 25.5 to obtain the desired output frequency, here an integer (type) divider with a fixed division ratio of 25 is used to divide the oscillator's output signal LO. A fixed division ratio of 25.5 is input into the register to generate the desired 2.55GHz output signal.

[0056] The terminology used herein is for describing particular embodiments only and is not intended to limit the invention. Unless the context clearly indicates otherwise, the word "and / or" as used herein includes any and all combinations of one or more of the associated listed items. Unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" as used herein are intended to also include the plural forms. It should also be understood that, when used in this specification, the terms "comprising" and / or "including" specify the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art and this disclosure, and not as having an idealized or overly formal meaning, unless expressly defined herein.

[0058] According to the embodiments disclosed herein, functional units and modules of electronic control circuits, such as integer dividers and clock correction calculation modules, can be implemented using computing devices, computer processors, or electronic circuits, including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, and other programmable logic devices configured or programmed according to the teachings of this disclosure. The computer instructions or software code running in the computing device, computer processor, or programmable logic device can be easily prepared by a skilled practitioner in the software or electronics field based on the teachings of this disclosure.

[0059] refer to Figure 2 This illustrates a first preferred embodiment of the invention. In this example, the electronic control circuit 200 includes a TDC 206 for receiving the input reference signal REF, a digitally controlled oscillator (DCO) 210 for generating a periodic output signal LO, and a loop filter 208 between them in the oscillator circuit 202. DCO is an abbreviation for digitally controlled oscillator. The frequency of its periodic output signal LO is digitally controlled by a digital signal called D. The loop filter 208 is a low-pass digital filter. Its input signal is a digital signal called TC. Its output signal is a digital signal called D. Preferably, its gain for the DC input signal is infinite. The loop filter 208 can use REF as a clock, so its output signal is updated on the rising edge of CLK.

[0060] In this example, the time-to-digital converter (TDC) 206 is the input to the oscillator circuit 202. Its input signals are a reference clock, named REF in this disclosure, and a periodic signal named DIV obtained from a frequency division of LO. Its function is to detect the phase difference between REF and DIV, for example, by quantizing the time difference (denoted by Δt1) between the rising edges of the input signals, and converting the difference / error into a digital signal T. Preferably, the TDC 206 quantizes Δt1 between the rising edge of REF and the last rising edge of DIV preceding that rising edge of REF.

[0061] Preferably, the relationship between Δt1 and T may be T = Δt1 / u, where u is the unit time used for quantization. In this disclosure, T represents a digital signal, but also the numerical value of the signal. Although T may have various formats, such as signed floating-point numbers, signed integers, and some custom number formats, we ignore the format and only focus on its mathematical value. This principle applies to any digital signal in this disclosure.

[0062] Furthermore, T is a signed / negative value; it may be assigned a negative sign when the rising edge of DIV precedes the corresponding rising edge of REF, and a positive sign otherwise. If the unit time u is chosen appropriately, T is a signed integer that is easy to store in a register.

[0063] Similar to TDC 206, loop filters 208 can also use REF as a clock. Their output signals are updated on the rising edge of REF. As mentioned earlier, loop filters 208 can be low-pass or band-pass filters, filtering out unwanted frequency signals from TDC 206 before being used as control signals to control the operation of DCO210 or VCO at the output of oscillator circuit 202. Figure 2 TC in the illustrated embodiment.

[0064] Preferably, the feedback loop 204 includes an integer divider 212 for processing the periodic output signal LO using the integer part FCW[int] of the division ratio FCW of the fractional-N divider, wherein the integer part FCW[int] is equal to the nearest integer less than or equal to the division ratio FCW of the fractional-N divider rounded down. Preferably, the division ratio FCW of the fractional-N divider is a combination of the integer part FCW[int] and the fractional part FCW[frac], and is a rational number greater than or equal to 1. For example, if FCW = 2.5, FCW[int] = 2, FCW[frac] = 0.5, such that FCW = FCW[int] + FCW[frac].

[0065] In this preferred embodiment, the electronic control circuit 200 further includes a clock correction stage for converting or compensating the digital signal T output by the time-to-digital converter (TDC) to TC. The TC is then further filtered and fed to the DCO 210 to generate LO. (Refer to...) Figure 2 In this example, the error signal T is based on an input frequency f. refThe input reference signal REF and the input periodic signal DIV are used to generate a corrected digital signal TC, which is converted into the output representing the TDC 206. This corrected digital signal TC is based on the input frequency and the sum of the integer part FCW[int] and the fractional part FCW[frac] of the division ratio FCW of the fractional N divider. T is related to the first time difference Δt1 between the rising edges of the input signals REF and DIV. The corrected digital signal TC is further provided to the oscillator 210 in the oscillator circuit to generate the periodic output signal LO.

[0066] Preferably, the clock correction stage includes an adder 216 and a clock correction calculator module 214 for determining a clock correction digital signal C related to a second time difference Δt2 between the virtual reference clock (VRC) and the reference clock signal, wherein the adder is arranged to output a corrected digital signal TC = T + C.

[0067] In this example, ADD is an adder 216 that performs the logical / mathematical operation of addition. It uses REF as its clock. Its output signal is updated on the rising edge of REF.

[0068] Preferably, f can be DCOt Defined as the target frequency of LO, f ref Defined as the frequency of the reference clock, where FCW is the frequency ratio of them, therefore And f DCOt =FCW xf ref For a fraction N ADPLL, FCW is a positive rational number greater than or equal to 1.

[0069] In this preferred embodiment, an integer divider 212 is used instead of a ΣΔ fractional N divider. The input signal of this integer divider 212 is LO, and the output signal is DIV. A clock correction calculator module 214 is provided to make the division ratio of LO and REF equivalent to a fractional FCW.

[0070] For the integer frequency divider 212, the division ratio is FCW[int], which is the integer part of FCW, mathematically also known as the floor function of FCW. By defining fdivt as the target frequency of DIV, And f DCOt =FCW[int]xf divt .

[0071] Preferably, the reference clock signal is a virtual reference clock signal, whose first rising edge is aligned with the rising edge of the input reference signal REF, and the virtual reference clock signal includes the target frequency f of the input periodic signal DIV after the electronic control circuit is reset. divt .

[0072] Because f divt with f ref Unlike REF, the rising edge of DIV cannot lock with the rising edge of REF, therefore the frequency of DIV may differ from the target frequency, and the frequency of LO may also differ from the target frequency. To solve this problem, a virtual reference clock (VRC) is introduced. Figure 4 Preferably, the virtual reference clock is a fictitious signal in the mathematical process. The virtual reference clock can be utilized by calculating the position of its rising edge if it were real.

[0073] refer to Figure 4 The virtual reference clock is defined as follows: First, after reset, its first rising edge is aligned with the first rising edge of ref; second, its frequency is equal to f. divt The signal nrst is a digital reset signal activated by a low level of the ADPLL. If the rising edge of DIV is locked to the rising edge of the virtual reference clock, the frequency of DIV will be exactly equal to the target frequency, and the same applies to LO.

[0074] As mentioned earlier, signal T is quantized from the time difference Δt1 between the rising edges of REF and DIV. To give LO the target frequency, the signal TC fed into the loop filter is likely quantized from the time difference Δt2 between the rising edges of the virtual reference clock and the input periodic signal DIV. The clock correction calculator module is configured to calculate TC using T. The output signal of the clock correction calculator is a digital signal named C.

[0075] In addition, the TDC 206 has an extra function—counting the rising edges / edges of the DIV between the current rising edge and the previous rising edge of the REF, and outputting the count result as an integer named REC. TC can be calculated by TC = T + C.

[0076] Preferably, the clock correction calculator module 214 calculates C based on the input FCW[frac] and the REC value provided by TDC 206. C[i] is defined as the value of C at the i-th rising edge of the ref after reset, where i is a positive integer sequence number. C[i] is generated as follows:

[0077] For i = 1, C[1] is 0;

[0078] At any rising edge of the ref other than the first one, i.e., for i>1,

[0079] (1) If REC equals 1,

[0080] Where FCW[frac] is the fractional part of FCW, defined as FCW[frac] = FCW - FCW[int];

[0081] (2) If REC equals 0,

[0082]

[0083] (3) If REC is greater than 1,

[0084]

[0085] refer to Figure 4 This illustrates a second embodiment of the electronic control circuit 200' of the present invention. In this embodiment, the ADPLL 200' further includes a coarse tuning module 218 for providing a coarse tuning output signal DCT to control the switching of capacitors in oscillator 210 of oscillator circuit 202 to coarsely tune the periodic output signal LO, wherein the coarse tuning output signal DCT is an accumulation of the input CCT provided by clock correction calculator module 214'.

[0086] The ADPLL 200' in this second embodiment is similar to the first embodiment, except that all modules are the same, except for the clock correction calculator 214' and the coarse adjustment 218. In this clock correction calculator 214', C is calculated as described above and further divided into two parts, namely CF and CCT, where C = CF + CCT. These two parts are also digital signals, with CF used as the input to the loop filter and CCT used as the input to the coarse adjustment 218.

[0087] Preferably, a positive numerical threshold named TH is selected, for example... Then the calculations for CF and CCT are as follows:

[0088] CCT = TH xk; and

[0089] CF = C – CCT, where k is The floor function, which is to round down. Round down to the nearest integer less than or equal to it.

[0090] Preferably, the coarse adjustment module 218 accumulates its input signal and uses the result as its output signal DCT, which can be used to control the switching of the capacitor in the DCO 210 to coarsely tune the frequency of the DCO.

[0091] These embodiments may have the advantage of enabling fractional PLLs with a fixed division ratio by including an integer divider in the feedback loop to process the fixed integer division and further processing the error signal through a correction module to embed the fractional part. This allows for precise frequency synthesis, which is crucial in applications such as wireless communications or applications that require generating frequencies that are integer multiples of a non-reference frequency.

[0092] Advantageously, this electronic control circuit is not intuitive and differs significantly from traditional PLLs. Furthermore, unlike digital PLLs that use ΣΔ modulators (required in ΣΔ fractional-N dividers), the noise introduced by the divider is greatly reduced, as is the noise at the TDC (time-to-digital converter) output node. Therefore, the overall noise of the ADPLL is reduced.

[0093] Those skilled in the art will understand that numerous variations and / or modifications can be made to the specific embodiments shown without departing from the spirit or scope of the broad description of the invention. Therefore, these embodiments should be considered illustrative rather than restrictive in all respects.

[0094] Unless otherwise stated, any reference to prior art contained herein shall not be construed as an admission that the information is ordinary general knowledge.

Claims

1. An electronic control circuit, characterized by Comprising: an oscillator circuit for generating a periodic output signal LO whose output frequency is equal to the input frequency fref multiplied by a fractional frequency divider's division ratio FCW; and a feedback circuit comprising an integer frequency divider for dividing the periodic output signal LO by a positive integer and providing the integer frequency divider's output as a feedback signal to the input of the oscillator circuit; wherein the integer frequency divider's output is fed as an input periodic signal DIV to a time-to-digital converter (TDC) of the oscillator circuit; wherein the TDC is configured to output a digital signal T based on an input reference signal REF having the input frequency fref and the input periodic signal DIV.

2. The electronic control circuit of claim 1, wherein, wherein the electronic control circuit is a fractional all-digital phase-locked loop (PLL) control system.

3. The electronic control circuit of claim 2, wherein, wherein the oscillator circuit comprises the TDC for receiving an input reference signal REF, an oscillator for generating the periodic output signal LO, and a loop filter therebetween.

4. The electronic control circuit of claim 3, wherein, wherein the fractional frequency divider's division ratio FCW is a combination of an integer part FCW[int] and a fractional part FCW[frac].

5. The electronic control circuit of claim 4, wherein, wherein the fractional frequency divider's division ratio FCW is a rational number greater than or equal to 1.

6. The electronic control circuit of claim 4, wherein, further comprising a clock correction stage for converting the digital signal T output by the time-to-digital converter (TDC) based on the input reference signal REF having the input frequency fref and the input periodic signal DIV into a corrected digital signal TC, wherein the input periodic signal DIV is equal to the integer part FCW[int] of the fractional frequency divider's division ratio FCW, which TC represents the output of the TDC based on the input frequency and the sum of the integer part FCW[int] and the fractional part FCW[frac] of the fractional frequency divider's division ratio FCW; wherein this T is related to a first time difference Ati between rising edges of the input signals REF and DIV; wherein the corrected digital signal TC is further provided to the oscillator in the oscillator circuit for generating the periodic output signal LO.

7. The electronic control circuit of claim 6, wherein, wherein the integer frequency divider is configured to process the periodic output signal LO with the integer part FCW[int] of the fractional frequency divider's division ratio FCW, wherein the integer part FCW[int] is equal to the floor of FCW, i.e. rounded down to the nearest integer smaller than or equal to the fractional frequency divider's division ratio.

8. The electronic control circuit of claim 6, wherein, wherein the clock correction stage comprises an adder and a clock correction calculation module configured to determine a clock correction digital signal C related to a second time difference At2 between a virtual reference clock signal and the input periodic signal DIV, wherein the adder is configured to output the corrected digital signal TC = T + C.

9. The electronic control circuit of claim 8, wherein, wherein a first rising edge of the virtual reference clock signal is aligned with a rising edge of the input reference signal REF, and the virtual reference clock signal comprises a target frequency f of the input periodic signal DIV after reset of the electronic control circuit divt .

10. The electronic control circuit of claim 9, wherein, further comprising a master reset configured to be activated by a digital reset signal activated by a low level.

11. The electronic control circuit of claim 9, wherein, wherein the clock correction calculation module is further configured to determine the clock correction digital signal C based on an integer REC, wherein REC is equal to a rising edge count of DIV between a current REF rising edge and a previous REF rising edge output by the TDC.

12. The electronic control circuit of claim 11, wherein, wherein: a value of C at an i-th rising edge of REF after reset is equal to C[i], where i is a positive integer index, and C[i] is generated as follows: for i = 1, C[1] is 0; and for i > 1, (1) if REC is equal to 1, (2) if REC is equal to 0, (3) if REC is greater than 1, where u is a unit time used by the TDC quantization, Δti = T x u and Δt2 = TC x u; where T divt = FCW [int] x T DCOt , f DCOt = FCW [int] x f divt , T ref = FCW x T DCOt , f DCOt = FCW x f divt , f DCOt denotes the target frequency of the periodic output signal LO, T DCOt denotes the corresponding period of f DCOt , f divt denotes the target frequency of DIV, T divt denotes the corresponding period of f divt , f ref denotes the target frequency of REF, T ref denotes the corresponding period of f ref .

13. The electronic control circuit of claim 11, wherein, further comprising a coarse tuning module for providing a coarse tuning output signal DCT to control a switch of a capacitance of an oscillator in the oscillator circuit, so as to coarsely tune the periodic output signal LO.

14. The electronic control circuit of claim 13, wherein, wherein the coarse tuning output signal DCT is a cumulation of an input CCT provided by the clock correction calculation module.

15. The electronic control circuit of claim 6, wherein, wherein the modified digital signal TC is filtered by a loop filter before being further provided to the oscillator.

16. The electronic control circuit of claim 3, wherein, wherein the oscillator comprises a digitally controlled oscillator.

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