High-precision delta-sigma modulator based on time-sharing chopping

Abstract

The invention provides a high-precision delta-sigma modulator based on time-sharing chopping. The high-precision delta-sigma modulator comprises a first-stage integrator, a second-stage integrator, a third-stage integrator, an adder, a comparator, two pairs of chopper circuits and an analog-to-digital converter, according to the invention, two pairs of chopper circuits are arranged, a time-sharing clock control technology is adopted, and a virtual device layout matching design is combined, so that accurate suppression of multi-source low-frequency interference is realized. The modulator adopts a three-order CIFF architecture, internal noise and imbalance of an operational amplifier are eliminated through a time-sharing controlled chopper 1, input charge injection, switching nonlinearity and DAC feedback errors are eliminated through a system-level chopper 2, and the stability of the sampling and integration process is ensured in cooperation with an optimized clock delay design. Under the sampling frequency of 1.024 MHz, the signal-to-noise distortion ratio reaches 106.7 dB, the noise suppression capability is improved by 68.1 dB, and the total power consumption is only 504 mu W.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-precision delta-sigma modulator based on time-division chopping. Background Technology

[0002] Low-frequency signal monitoring plays an increasingly crucial role in fields such as industrial inspection, biomedicine, environmental monitoring, and aerospace. These fields all require low-frequency signal monitoring, and high-precision low-frequency signal acquisition technology provides key support for these advanced applications.

[0003] In addition to preamplifiers and anti-aliasing filters, low-frequency signal readout circuits require analog-to-digital converters (ADCs) with bandwidths ranging from DC to several kilohertz. These ADCs convert analog signals into digital representations through high-precision quantization for subsequent analysis and processing. However, current ADC modulators have poor resistance to noise in the low-frequency band, and low-frequency signals are easily submerged in complex low-frequency noise and cannot be distinguished. This leads to problems such as low accuracy in the low-frequency domain for common ADC modulators, making accurate analog-to-digital conversion impossible and failing to meet the high-precision analog-to-digital conversion requirements for low-frequency signals. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a high-precision delta-sigma modulator based on time-division chopping. By optimizing the chopping circuit configuration and clock timing design, this invention effectively suppresses low-frequency noise and DC deviation from multiple sources, including the input signal, DAC feedback, and operational amplifier, thereby improving the accuracy and stability of low-frequency signal analog-to-digital conversion.

[0005] The technical solution of the present invention is: a high-precision delta-sigma modulator based on time-division chopper, including a first-stage integrator INT1, a second-stage integrator INT2, a third-stage integrator INT3, an adder, a comparator Quantizer, two pairs of chopper circuits chopper1 and chopper2, and an analog-to-digital converter DAC.

[0006] The input terminal of the first chopper circuit, chopper1, is connected to the differential input signal input terminals VIP and VIN;

[0007] The input terminal of the second chopper circuit, chopper1, is connected to the output terminal of the analog-to-digital converter (DAC).

[0008] The output terminals of the two chopper circuits 1 are connected to the signal input terminal of the operational amplifier AMP1 of the first-stage integrator INT1 via a switched capacitor sampling circuit.

[0009] The output of the operational amplifier AMP1 of the first-stage integrator INT1 is directly connected to the input of the first chopper circuit chopper2. The output of the operational amplifier is modulated by the first chopper circuit chopper2 and then reaches the output of the first-stage integrator INT1.

[0010] The output of the first-stage integrator INT1 is split into two paths, one of which passes through a feedback capacitor. and One path is connected to the input of the second chopper circuit, chopper2, and the other path is connected to the first input of the adder as a feedforward signal.

[0011] The output of the second chopper circuit, chopper2, is connected to the input of the operational amplifier AMP1 of the first-stage integrator INT1;

[0012] The output of the first chopper circuit, chopper2, is connected to the input of the second-stage integrator, INT2. The output of the second-stage integrator, INT2, is split into two paths: one path serves as a feedforward signal connected to the second input of the adder, and the other path is connected to the input of the third-stage integrator, INT3.

[0013] The output of the third-stage integrator INT3 is used as the third feedforward signal and connected to the third input of the adder. The output of the adder is connected to the input of the comparator Quantizer through a single-ended signal line.

[0014] The output of the comparator Quantizer is divided into two paths: one path serves as the final quantization level output DOUT of the modulator, and the other path is connected to the input of the analog-to-digital converter (DAC).

[0015] Preferably, the first-stage integrator INT1, the second-stage integrator INT2, the third-stage integrator INT3, and the two pairs of chopper circuits chopper1 and chopper2 are all connected to a switch control signal generator, which provides a non-overlapping clock signal. , , , and time-division chopper clock signals CH1, CH2, CH3; the non-overlapping clock signals and Phase difference 180°; and , and There is a latency of 388ps in all cases.

[0016] Preferably, the chopper circuit 1 is controlled by clock signals CH2 and CH3; the chopper circuit 2 is controlled by clock signal CH1.

[0017] Preferably, a non-overlapping clock signal is used. , , , Control the sampling switches and integral switch control terminals of the first-stage integrator INT1, the second-stage integrator INT2, and the third-stage integrator INT3.

[0018] Preferably, the first-stage integrator INT1, the second-stage integrator INT2, and the third-stage integrator INT3 are all composed of an operational amplifier AMP, a sampling capacitor Cs, and a feedback capacitor. composition.

[0019] Preferably, the chopper circuit chopper1 consists of two symmetrical MOS transistor switch arrays. The control terminal of each MOS transistor switch array is connected to clock signals CH2 and CH3 respectively. Clock signal CH2 controls the on and off of the first MOS transistor switch array, and clock signal CH3 controls the on and off of the second MOS transistor switch array.

[0020] Preferably, the two symmetrical MOS transistor switch arrays of the chopper circuit 2 are both connected to the clock signal CH1, and the clock signal CH1 synchronously controls the state flipping of the two MOS transistor switch arrays.

[0021] Preferably, the switch control signal generator includes a D flip-flop, logic gates, an inverter chain, and an input non-overlapping clock signal. The aforementioned switch control signal generator uses internal logic circuitry to... Converted to CH1, CH2, CH3;

[0022] The input non-overlapping clock signal First, connect the input terminals of the inverter chain. Then, connect the output terminals of the inverter chain to the clock input terminal of the D flip-flop and the first input terminal of the logic gate, respectively.

[0023] The data input terminal D of the D flip-flop is connected to its own output terminal Q via a feedback line. The reset terminal of the D flip-flop is connected to a high level, and the output terminal Q is connected to the second input terminal of the logic gate.

[0024] The logic gate adopts a NAND gate structure. Its two input terminals receive the output signals of the inverter chain and the output signals of the D flip-flop, respectively. The output terminals of the logic gate are divided into two paths: one path is directly used as the CH1 clock signal output, and the other path is divided into CH2 and CH3 clock signal outputs after passing through two stages of inverters.

[0025] The inverter chain consists of four inverters connected in series. Each inverter's power supply terminal is connected to a 3.3V DC power supply, and its ground terminal is grounded. This chain is used to achieve signal delay and phase adjustment, ensuring that CH1, CH2, and CH3 are synchronized with each other. Delayed matching requirements.

[0026] As a preferred option, virtual device layout technology is used to achieve a high degree of matching between the chopper switches in chopper1 and chopper2, thereby further suppressing low-frequency component interference.

[0027] Preferably, the adder adopts a resistor network weighted structure, and after weighted summing of the feedforward signals of the first-stage integrator INT1, the second-stage integrator INT2, and the third-stage integrator INT3, it outputs the sum to the input of the comparator Quantizer through a single-ended signal line; the comparator quantizes the analog signal into a single-bit quantization level.

[0028] The beneficial effects of this invention are as follows:

[0029] 1. This invention achieves precise suppression of multi-source low-frequency interference by setting up two pairs of chopper circuits and adopting time-division clock control technology, combined with virtual device layout matching design;

[0030] 2. The modulator of this invention adopts a third-order CIFF architecture. The time-division controlled chopper1 eliminates the internal noise and offset of the operational amplifier, and the system-level chopper2 eliminates input charge injection, switching nonlinearity and DAC feedback error. With the optimized clock delay design, the stability of the sampling and integration process is ensured. The two-stage chopper circuit realizes the full-path suppression of operational amplifier noise, input signal noise, DAC feedback noise and switching nonlinearity noise, and the noise suppression capability is improved by 68.1dB compared with the traditional solution.

[0031] 3. This invention ensures that CH1, CH2, CH3 and , The delay matching avoids transient interference from switching and chopping operations, ensures accurate storage and transfer of the sample capacitor charge, and improves the reliability of the modulator.

[0032] 4. Under the conditions of 625Hz input signal and 1.024MHz sampling frequency, the present invention achieves a signal-to-noise ratio of 106.7dB and a quality factor of approximately 172.7dB, meeting the high-precision analog-to-digital conversion requirements for low-frequency signals. Attached Figure Description

[0033] Figure 1 This is a circuit diagram of the regulator of the present invention;

[0034] Figure 2The circuit diagrams for the chopper circuits chopper1 and chopper2 of this invention are shown below.

[0035] Figure 3 This is a circuit diagram of the time-division clock control signal generation circuit of the present invention;

[0036] Figure 4 This is the clock timing diagram for the time-division chopping of the present invention;

[0037] Figure 5 The simulation diagram of the power spectral density after the addition of offset in this invention;

[0038] Figure 6 This is a power spectral density test diagram of the input signal in this invention;

[0039] Figure 7 This is a DC noise floor test diagram for the present invention. Detailed Implementation

[0040] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings:

[0041] Example 1

[0042] like Figure 1 As shown, this embodiment provides a high-precision delta-sigma modulator based on time-division chopping, including a first-stage integrator INT1, a second-stage integrator INT2, a third-stage integrator INT3, an adder, a comparator quantizer, two pairs of chopper circuits chopper1 and chopper2, and an analog-to-digital converter DAC.

[0043] The input terminal of the first chopper circuit, chopper1, is connected to the differential input signal input terminals VIP and VIN;

[0044] The input terminal of the second chopper circuit, chopper1, is connected to the output terminal of the analog-to-digital converter (DAC).

[0045] The output terminals of the two chopper circuits 1 are connected to the signal input terminal of the operational amplifier AMP1 of the first-stage integrator INT1 via a switched capacitor sampling circuit.

[0046] The output of the operational amplifier AMP1 of the first-stage integrator INT1 is directly connected to the input of the first chopper circuit chopper2. The output of the operational amplifier is modulated by the first chopper circuit chopper2 and then reaches the output of the first-stage integrator INT1.

[0047] The output of the first-stage integrator INT1 is split into two paths, one of which passes through a feedback capacitor. and One path is connected to the input of the second chopper circuit, chopper2, and the other path is connected to the first input of the adder as a feedforward signal.

[0048] The output of the second chopper circuit, chopper2, is connected to the input of the operational amplifier AMP1 of the first-stage integrator INT1;

[0049] The output of the first chopper circuit, chopper2, is connected to the input of the second-stage integrator, INT2. The output of the second-stage integrator, INT2, is split into two paths: one path serves as a feedforward signal connected to the second input of the adder, and the other path is connected to the input of the third-stage integrator, INT3.

[0050] The output of the third-stage integrator INT3 is used as the third feedforward signal and connected to the third input of the adder. The output of the adder is connected to the input of the comparator Quantizer through a single-ended signal line.

[0051] The output of the comparator Quantizer is divided into two paths: one path serves as the final quantization level output DOUT of the modulator, and the other path is connected to the input of the analog-to-digital converter (DAC).

[0052] In this embodiment, the first-stage integrator INT1, the second-stage integrator INT2, the third-stage integrator INT3, and the two pairs of chopper circuits chopper1 and chopper2 are all connected to a switch control signal generator, which provides a non-overlapping clock signal. , , , and time-division chopper clock signals CH1, CH2, CH3; the non-overlapping clock signals and Phase difference 180°; and , and Both have a 388ps delay; CH1 has a frequency of 512kHz and a duty cycle of 50%, and its falling edge is the same as the original... There is a delay of approximately 63 ns at the falling edge of the signal. The frequencies of CH2 and CH3 are the same as those of CH1, but their duty cycles are 25%, and the falling edges of CH2 and CH3 are delayed compared to the original signals. There is a delay of approximately 525 ps at the falling edge of the signal.

[0053] In this embodiment, the chopper circuit 1 is controlled by clock signals CH2 and CH3; the chopper circuit 2 is controlled by clock signal CH1.

[0054] In this embodiment, a non-overlapping clock signal is used. , , , Control the sampling switches and integral switch control terminals of the first-stage integrator INT1, the second-stage integrator INT2, and the third-stage integrator INT3.

[0055] In this embodiment, the first-stage integrator INT1 consists of an operational amplifier AMP1 and a sampling capacitor. , , and Feedback capacitor and The second-stage integrator INT2 consists of an operational amplifier AMP2 and a sampling capacitor. and Feedback capacitor and The third-stage integrator INT3 consists of operational amplifier AMP2 and sampling capacitors. and Feedback capacitor and composition.

[0056] In this embodiment, as Figure 2 As shown, the chopper circuit 1 consists of two symmetrical MOSFET switch arrays, each array comprising four NMOS transistors. The control terminals of each MOSFET switch array are connected to clock signals CH2 and CH3, respectively. Clock signal CH2 controls the on / off state of the first MOSFET switch array, and clock signal CH3 controls the on / off state of the second MOSFET switch array. By alternately turning the two symmetrical MOSFET switch arrays on and off, the internal noise and offset of the operational amplifier AMP1 are eliminated.

[0057] In this embodiment, as Figure 2 As shown, the two symmetrical MOSFET switch arrays of the chopper circuit 2 are both connected to the clock signal CH1. The clock signal CH1 synchronously controls the state switching of the two MOSFET switch arrays. By synchronously switching the switch states, errors introduced by input charge injection, switching nonlinearity, and DAC feedback are eliminated.

[0058] In this embodiment, as Figure 3 As shown, the switch control signal generator includes D flip-flops, logic gates, an inverter chain, and an input non-overlapping clock signal. ;in, This is a clock signal with a frequency of 1.024MHz and a duty cycle of 50%. The aforementioned switch control signal generator uses internal logic circuitry to... Converted to CH1, CH2, CH3.

[0059] The input non-overlapping clock signal First, connect the input terminals of the inverter chain. Then, connect the output terminals of the inverter chain to the clock input terminal of the D flip-flop and the first input terminal of the logic gate, respectively.

[0060] The D flip-flop adopts a rising edge triggering structure. The data input terminal D and the output terminal Q of the D flip-flop are connected through a feedback line to form a frequency divider circuit. The reset terminal (RST terminal) of the D flip-flop is connected to a high level of 3.3V to ensure stable operation of the flip-flop. The output terminal Q is connected to the second input terminal of the logic gate. The output is the frequency divider signal.

[0061] The logic gate adopts a NAND gate structure. Its two input terminals receive the output signals of the inverter chain and the D flip-flop, respectively. Its power supply terminal VDD is connected to a 3.3V DC power supply, and GND is grounded. The output terminal of the logic gate is divided into two paths: one path is directly used as the CH1 clock signal output, which is output to the control terminal of chopper2 through the clock control line; the other path is divided into CH2 and CH3 clock signals after passing through two stages of CMOS inverters. The output is output to the two sets of switch control terminals of chopper1 through two independent clock control lines. The two stages of inverters are used to adjust the signal phase and driving capability to ensure that the timing of CH2, CH3 and CH1 is matched.

[0062] The inverter chain consists of four CMOS inverters connected in series. Each CMOS inverter has a 3.3V DC power supply at its power terminal and its GND terminal grounded. This chain is used to achieve signal delay and phase adjustment, ensuring that CH1, CH2, and CH3 are synchronized with each other. To meet the delay matching requirements, the output of the inverter chain is connected to the clock input (CLK) of the D flip-flop and the first input of the logic gate (NAND gate) via two signal lines.

[0063] In this embodiment, the switch control signal generator controls the signal by... The signal is inverted and delayed to generate , , Signal; The signal is directly transmitted through the inverter. Inverting the phase yields the result; The signal passes through A 388ps delay is achieved by connecting three inverters in series along the path. The signal passes through A delay of 388ps is achieved by connecting three inverters in series along the path; , , , The clock control lines are output to the sampling switch and integral switch control terminals of the three-stage integrator, respectively.

[0064] The switch control signal generator generates, for example Figure 4 The chopper circuits CH1, CH2, and CH3 shown are time-division clock control signals. CH1 has a frequency of 512kHz and a duty cycle of 50%, and its falling edge coincides with the original... There is a delay of approximately 63 ns at the falling edge of the signal. The frequencies of CH2 and CH3 are the same as those of CH1, but their duty cycles are 25%, and the falling edges of CH2 and CH3 are delayed compared to the original signals. There is a delay of approximately 525 ps at the falling edge of the signal.

[0065] In this embodiment, a complete working cycle of the modulator is divided into four stages, namely:

[0066] Phase 1: S1 transitions to a high level on the rising edge, while S... 1D CH1 and CH2 transition to high level on the rising edge after delays of 388ps, 63ns, and 525ps respectively. Simultaneously, S2 transitions to low level on the falling edge. 2D Similarly, after a 388ps delay, CH3 transitions to a low level on a falling edge, remaining low throughout this phase. At this time, the switch controlled by S1 is closed, and the switch controlled by S2 is open. The chopper circuit 1, controlled by CH2 and CH3, is in a direct-on state. The input signal Vin and the DAC feedback signal are sampled by the chopper circuit 1 to the sampling capacitor C of the first-stage integrator. S1 C S2 ;

[0067] For CH1, the transition occurs 63ns after S1 completes its transition. During this 63ns delay, S1 remains closed, and CH remains in its previous state (low level) before the transition causes the chopper circuit 2 to flip its state. Because S1 and S2 control the switching between the sampling and integration states in the circuit, if S1 and CH1 transition at the same time, the transient caused by S1 closing will directly interfere with the chopper circuit 2 controlled by CH1. After the 63ns delay, the circuit has stabilized, and at this point, the transition of CH1 causes the chopper circuit 2 to change from a cross-output state to a direct-output state. This ensures that the transient response during the transitions of S1 and S2 and the transient response in the chopper circuit caused by the transition of CH1 do not occur simultaneously, resulting in a more stable sampling and integration setup process for the operational amplifier AMP1, thus achieving higher conversion accuracy.

[0068] Phase 2: S1 transitions to low level via a falling edge, S1D CH2 transitions to low level via a falling edge after delays of 388ps and 525ps, while S2 transitions to high level via a rising edge. 2D After a 388ps delay, the signal transitions to a high level. During this phase, CH1 remains high and CH3 remains low. The switch controlled by S1 is open, stopping sampling; the switch controlled by S2 is closed, initiating integration; chopper circuits 1 controlled by CH2 and CH3 are both off. Chopper circuit 2 controlled by CH1 is in a pass-through state. At this time, the input signal arrives at the input node of the first-stage op-amp from the sampling capacitor for integration. As Phase 1 is about to end, S2 and S... 2D All are at low level. At the start of Phase 2, the switch controlled by S2 closes first, setting the sampling capacitor C... S1 and C S2 The right electrode is connected to the input of operational amplifier AMP1. After a delay of 388 ps, the signal is then transmitted by S... 2D The control switch closing will sample capacitor C S1 C S2 The left plate is connected to the common-mode voltage V. CM This delay ensures that the virtual ground of the operational amplifier AMP1's input stabilizes after the transient response of S2, and the sampling capacitor C... S1 C S2 The left electrode plate is connected to V. CM The common-mode voltage allows the charge stored on the sampling capacitor to be input into the operational amplifier. This ensures that the charge transfer process and the transient process of the switch controlled by S2 (charge injection, clock feedthrough) do not occur simultaneously, making the charge transfer more accurate.

[0069] Phase 3: At this time, S1 transitions to a high level via a rising edge. 1D CH3 and CH4 transition to high level via rising edge after delays of 388ps and 525ps respectively. CH1 transitions to low level via falling edge after a delay of 63ns. Simultaneously, S2 transitions to low level via falling edge, while S... 2D Similarly, after a 388ps delay, it transitions to a low level on a falling edge. CH2 remains low throughout this stage.

[0070] The switch controlled by S1 closes, and the switch controlled by S2 opens, initiating the sampling process. Meanwhile, the chopper circuit 1, controlled by CH2 and CH3, is in a cross-output state. The input signal Vin is sampled onto the sampling capacitor through the cross-output chopper circuit 1. As Phase 2 of the previous stage is about to end, S2 and S... 2DBoth are at high level. At this time, S2 first completes the transition to low level, and then after a 388ps delay, S... 2D The transition to low level marks the complete end of the integration phase. After 525 ps, CH3 transitions, initiating the chopper circuit (chopper1) to operate. After 63 ns, CH1 transitions, similar to the purpose in Phase 1, to ensure that the transient response of this clock transition and the chopper transient response do not interfere with each other.

[0071] Phase 4: At this point, S1 transitions to a low level via a falling edge. 1D CH3 and S2 transition to low level on their falling edges after delays of 388ps and 525ps, respectively. S2 transitions to high level on its rising edge. 2D After a 388ps delay, the signal transitions to a high level, while CH1 and CH2 remain low. At this point, the circuit re-enters integration mode, and the chopper circuit 2, controlled by CH1, is in cross-output mode. The signal charge sampled in Phase 3 is integrated via the cross-output chopper circuit 2. Similar to Phase 2, S1 / S2 and S... 1D / S 2D The time delay is used to ensure conversion accuracy.

[0072] In this embodiment, virtual device layout technology is used to achieve a high matching degree of chopper switches in chopper circuits chopper1 and chopper circuits chopper2, thereby further suppressing low-frequency component interference.

[0073] The time-division chopping technique in this embodiment enables the delta-sigma modulator to suppress low-frequency noise. The invented delta-sigma modulator is designed and manufactured using a standard 180nm CMOS process, with a total chip area of ​​1660μm*1400μm.

[0074] Figure 5 The image shows the sampling capacitor C. S1 The power spectral density simulation results show the left electrode and DOUTP connected in series with 10mV DC voltage sources (to simulate their DC offset and low-frequency noise respectively); when time-division chopping technology is not used, the DC offset of DOUP (blue) is larger than the DC offset of sampling capacitor CS1 (black). Figure 5 As shown, when using time-division chopping technology, the DC offset of DOUP (green) and the DC offset of sampling capacitor CS1 (red) are approximately the same and greatly reduced. Therefore, time-division chopping technology can better suppress low-frequency offset and noise.

[0075] Figure 6The image shows the signal-to-noise ratio (SNDR) test results of the delta-sigma modulator in this embodiment. Under the conditions of an input sinusoidal signal frequency of 625Hz, a sampling frequency of 1.024MHz, and a bandwidth of 0.6Hz~2kHz, the SNDR reaches 106.7dB. At this time, the chip is powered by a 3.3V DC power supply, with a total power consumption of approximately 504μW. The calculated quality factor is approximately 172.7dB.

[0076] like Figure 7 The results show the DC noise floor test results of the modulator with and without time-division chopping technology. Using time-division chopping technology can reduce the noise by about 68.1 dB.

[0077] The embodiments and descriptions above are merely illustrative of the principles and preferred embodiments of the present invention. Various changes and modifications may be made to the present invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed.

Claims

1. A high-precision delta-sigma modulator based on time-division chopping, characterized by, The first level integrator INT1, the second level integrator INT2, the third level integrator INT3, the adder, the comparator Quantizer, two pairs of chopper circuits chopper1, chopper2, the analog-to-digital converter DAC; The input end of the first chopper circuit chopper1 is connected with the differential input signal input end VIP, VIN; The input end of the second chopper circuit chopper1 is connected with the output end of the analog-to-digital converter DAC; The output end of the two chopper circuits chopper1 is connected with the signal input end of the operational amplifier AMP1 of the first level integrator INT1 through the switched capacitor sampling circuit; The output end of the operational amplifier AMP1 of the first level integrator INT1 is directly connected with the input end of the first chopper circuit chopper2, and the operational amplifier output reaches the output end of the first level integrator INT1 after being modulated by the first chopper circuit chopper2; The output of the first integrator INT1 is split into two paths, one path via a feedback capacitor and connected to the input of a second chopper chopper2, the other path being connected as a feedforward signal to a first input of a summer The output end of the second chopper circuit chopper2 is connected with the input end of the operational amplifier AMP1 of the first level integrator INT1; The output end of the first chopper circuit chopper2 is connected with the input end of the second level integrator INT2, and the output end of the second level integrator INT2 is divided into two paths; one path is connected with the second input end of the adder as a feedforward signal, and the other path is connected with the input end of the third level integrator INT3; The output end of the third level integrator INT3 is connected with the third input end of the adder as a third feedforward signal, and the output end of the adder is connected with the input end of the comparator Quantizer through a single-ended signal line; The output end of the comparator Quantizer is divided into two paths, one path is connected with the input end of the analog-to-digital converter DAC as the final quantization level output DOUT, and the other path is connected with the input end of the analog-to-digital converter DAC.

2. A high precision delta-sigma modulator based on time-sharing chopping according to claim 1, characterized in that: The first integrator INT1, the second integrator INT2, the third integrator INT3 and the two pairs of chopper circuits chopper1, chopper2 are connected with the switch control signal generator, and the non-overlapping clock signals are provided by the switch control signal generator 、 、 、 and the time-sharing chopper clock signals CH1, CH2, CH3.

3. A high precision delta-sigma modulator based on time-sharing chopping according to claim 2, characterized in that: The chopper circuit chopper1 is controlled by clock signals CH2 and CH3; the chopper circuit chopper2 is controlled by clock signal CH1; the non-overlapping clock signals 、 、 、 control the sampling switch and the integration switch control end of the first-stage integrator INT1, the second-stage integrator INT2 and the third-stage integrator INT3.

4. A high precision delta-sigma modulator based on time-sharing chopping according to claim 3, characterized in that: The non-overlapping clock signals With a phase difference of 180°; With , With A 388 ps delay is present at the falling edge of both The frequency of CH1 is 512 kHz, the duty cycle is 50%, and the rising edge thereof is synchronized with There is a delay of about 63 ns at the falling edge of the signal; The frequencies of CH2 and CH3 are the same as CH1, the duty cycle is 25%, and the falling edges of CH2 and CH3 are the same as There is a delay of about 525 ps at the falling edge of the signal.

5. A high precision delta-sigma modulator based on time-sharing chopping according to claim 3, characterized in that: The first-stage integrator INT1, the second-stage integrator INT2, and the third-stage integrator INT3 are each composed of an operational amplifier AMP, a sampling capacitor Cs, and a feedback capacitor compositions.

6. A high precision delta-sigma modulator based on time-sharing chopping according to claim 3, characterized in that: The chopper circuit chopper1 is composed of two groups of symmetrical MOS switch arrays, the control ends of each group of MOS switch arrays are respectively connected with clock signals CH2, CH3, the clock signal CH2 controls the conduction and shutdown of the first group of MOS switch arrays, and the clock signal CH3 controls the conduction and shutdown of the second group of MOS switch arrays; The two groups of symmetrical MOS switch arrays of the chopper circuit chopper2 are connected with the clock signal CH1, and the clock signal CH1 synchronously controls the state flip of the two groups of MOS switch arrays.

7. A high precision delta-sigma modulator based on time-sharing chopping according to claim 2, characterized in that: The switch control signal generator comprises a D flip-flop, a logic gate, an inverter chain and an input non-overlapping clock signal The switch control signal generator converts the internal logic circuit into CH1, CH2 and CH3 through internal logic circuit. The switch control signal generator converts the internal logic circuit into CH1, CH2 and CH3 through internal logic circuit.

8. A high precision delta-sigma modulator based on time-sharing chopping according to claim 7, characterized in that: The input non-overlapping clock signal The input end of the inverter chain is firstly accessed, and the output end of the inverter chain is connected to the clock input end of the D flip-flop and the first input end of the logic gate respectively. The data input end D end of the D flip-flop is connected with the output end Q end through a feedback line; the reset end of the D flip-flop is connected with a high level, and the output end Q end is connected with the second input end of the logic gate; The logic gate adopts an NAND gate structure, two input ends of the logic gate respectively receive the output signal of the inverter chain and the output signal of the D flip-flop, and the output end of the logic gate is divided into two paths: one path is directly connected with the CH1 clock signal output, and the other path is divided into the CH2, CH3 clock signal output after passing through two inverters; The inverter chain is composed of four CMOS inverters in series, the power supply end of each CMOS inverter is connected with a 3.3V direct current power supply, and the ground end is connected with the ground.

9. A high precision delta-sigma modulator based on time-sharing chopping according to claim 6, characterized in that: The matching degree of the chopping switches in the chopper 1 and the chopper 2 is realized by using a virtual device layout technology, and low-frequency component interference is further suppressed.

10. A high precision delta-sigma modulator based on time-sharing chopping according to claim 1, characterized in that: The adder adopts a resistance network weighting structure, and after weighting and summing the feedforward signals of the first integrator INT1, the second integrator INT2 and the third integrator INT3, the signals are output to the input end of the comparator Quantizer through a single-end signal line; the comparator quantizes the analog signals into single-bit quantization levels.

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