IGBT device and preparation method thereof

Abstract

The invention provides an IGBT device and a preparation method thereof, the prepared IGBT device is of a parallel structure of a positive NMOS and a positive PMOS, and during turn-off and short circuit periods of the IGBT device, a channel of a negative voltage gate is controlled through the negative voltage gate, so that a hole stored in a drift region flows along a path from an emitter of a PMOS transistor to the channel and then to a collector to flow out from the front. A hole is directly discharged to an emitting electrode of the IGBT after passing through a drain electrode, a channel and a source electrode of the PMOS, and under the large-current working conditions such as short circuit and the like, an NPN transistor formed by an N base region, an IGBT P body region and an N-drift region can be triggered to be conducted through control voltage adjustment of a negative-voltage grid electrode, so that a current low-resistance discharge path is formed, and the short-circuit peak current of the IGBT device is increased. In the turn-off and short-circuit processes of the IGBT, the negative voltage is applied through the PMOS grid, and the PMOS channel is conducted, so that the hole extraction speed in the turn-off process is accelerated, the turn-off speed of the IGBT device in the switching process is accelerated, and the short-circuit peak current of the device can be improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to an IGBT device and its fabrication method. Background Technology

[0002] IGBTs (Insulated Gate Bipolar Transistors), as voltage-controlled power semiconductor devices, are widely used in new energy vehicles, smart grids, and industrial drives due to their advantages such as high input impedance, low conduction loss, and high switching speed. Their working principle is based on the gate voltage control of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and the conductivity modulation effect of bipolar transistors, achieving high-current conduction through a dual-carrier conduction mechanism of electrons and holes.

[0003] refer to Figure 1 , Figure 1 The related technology describes an IGBT where, in the on-state, a large number of electrons and holes are injected into the drift region, creating a conductivity modulation effect that results in a lower on-resistance than a MOSFET. During the turn-off process, due to the storage effect of minority carriers (holes), the holes in the drift region need to recombine with electrons to disappear, leading to current flow between the collector and emitter, generating a turn-off tail current. This not only affects the switching speed of the IGBT but may also cause system instability or even damage. The related technology also describes an IGBT structure with a Schottky diode connected in parallel between the emitter and collector to provide a reverse discharge path for holes during turn-off. However, this approach increases the device's conduction losses and has a larger leakage current, affecting device reliability. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this application provides an IGBT device and its fabrication method. The technical problem to be solved by this application is achieved through the following technical solution: In a first aspect, this application provides an IGBT device comprising, from bottom to top, an N-type doped substrate 100, an interlayer dielectric layer 400, a front metal layer 600, a field stop layer 700, and a back metal layer 800. The N-type doped substrate 100 comprises, from top to bottom, an N-type doped carrier storage layer 110, a P-type body region 300, and three gate trenches 200 extending from the P-type body region 300 through the N-type doped carrier storage layer 110. The inner walls of the three gate trenches 200 are provided with gate oxide layers 210, and the interiors are filled with polysilicon layers 220. The three gate trenches are respectively an active gate trench, a dummy gate trench, and a negative voltage gate trench. A PMOS N-base region 301 is disposed within the P-type body region 300 and between the negative voltage gate trench and the dummy gate trench. Contact holes 500 are provided on both sides of the ports of the three gate trenches. The contact hole 500 between the dummy gate trench and the active gate trench is disposed within the PMOS N-base region 301. A PMOS transistor is disposed near the contact hole 500 on one side of the negative voltage gate trench port. The P+ emitter 310 has IGBT N+ emitters 320 on both sides of the port of the active gate trench and the virtual gate trench. Except for the contact hole 500 in the PMOS N-base region 301, the bottom of each contact hole 500 has a contact hole P+ injection layer 510. The interlayer dielectric layer 400 covers the front side except for the contact holes 500. The front metal layer 600 is disposed on the interlayer dielectric layer 400, and the contact holes 500 are electrically connected to the PMOS P+ emitters 310. The field cutoff layer 700 is disposed on the back side of the substrate 100, the collector layer 710 is disposed on the back side of the field cutoff layer 700, and the back metal layer 800 is disposed on the back side of the collector layer 710.

[0005] Secondly, this application provides a method for fabricating an IGBT device, wherein the IGBT device as described in the first aspect is fabricated, the method comprising: S100, obtain an N-type doped substrate 100, and form an N-type doped carrier storage layer 110 on the upper surface of the N-type doped substrate 100 by ion implantation; S200: Using an etching process, three gate trenches 200 are etched in the substrate 100 from top to bottom through the carrier storage layer 110. A gate oxide layer 210 is thermally grown on the inner wall of the gate trenches 200 and the surface of the substrate 100. Polysilicon is deposited in the gate trenches 200 and the surface gate oxide layer until the trench structure is completely filled. Then, it is etched back to a predetermined position below the substrate 100 to form a polysilicon layer 220. S300, the device surface obtained after S200 is formed by implanting P-type impurities into the N-type doped substrate 100 to form P-type body regions 300 on both sides of the three gate trenches 200. S400, within the P-type body region 300 between the virtual gate trench and the negative gate trench, a PMOS N-base region 301 is formed by ion implantation of N-type impurities, and a PMOS P+ emitter 310 is formed by ion implantation of heavily doped P-type impurities at the port position near the negative gate trench within the PMOS N-base region 301. S500, an IGBT N+ emitter 320 is formed by ion implantation and heavy doping of N-type impurities in the P-type body region 300 on both sides of the virtual gate trench and the active gate trench near the trench port. S600, an interlayer dielectric layer 400 is deposited on the front side of the N-type doped substrate 100 by chemical vapor deposition, and a contact hole 500 is opened in the interlayer dielectric layer 400 by photolithography and etching to expose the underlying P-type body region 300 and P+ emitter 310. S700, P-type impurities are injected into the bottom of the contact hole 500 to form a contact hole P+ injection layer 510, and a front metal layer 600 is deposited on the front side of the interlayer dielectric layer 400 to fill the contact hole 500 and form an electrical connection with the emitter. In S800, the device formed in S700 is flipped over, and a back field cutoff layer 700 is formed on the back side of the device by ion implantation. A P+ back collector layer 710 is formed on the back side of the back field cutoff layer 700 by ion implantation. A back metal layer 800 is deposited on the back side of the P+ back collector layer 710.

[0006] Optionally, the resistivity of the N-type doped substrate 100 is 20~30 Ω·cm.

[0007] Optionally, in S100, forming an N-type doped carrier storage layer 110 on the upper surface of the N-type doped substrate 100 by ion implantation includes: An N-type doped carrier storage layer 110 is formed on the upper surface of the N-type doped substrate 100 by phosphorus ion implantation, wherein the phosphorus ion doping concentration is 1e17~1e18.

[0008] Optionally, the predetermined position in S200 is 0.1~0.2um below the substrate 100.

[0009] Optionally, in S300, implanting a P-type impurity into the N-type doped substrate 100 includes: By implanting boron ions into the N-type doped substrate 100, P-type body regions 300 are formed on both sides of the three gate trenches 200, wherein the boron ion doping concentration is 8e15~2e17.

[0010] Optionally, the formation of the PMOS N-base region 301 in S400 through ion implantation of N-type impurities includes: The PMOS N-base region 301 is formed by implanting phosphorus ions, wherein the phosphorus ion doping concentration is 1e17~1e18. The S400 PMOS P+ emitter 310 is formed by ion implantation to heavily dope P-type impurities, including: The PMOS P+ emitter 310 is formed by implanting boron ions, wherein the boron ion doping concentration is 5e19~8e20.

[0011] Optionally, the formation of the IGBT N+ emitter 320 in the S500 through ion implantation and heavy doping of N-type impurities includes: An IGBT N+ emitter 320 is formed by implanting phosphorus ions, wherein the phosphorus ion doping concentration is 5e19~1e21.

[0012] Optionally, in S700, injecting a P-type impurity into the bottom of the contact hole 500 to form a contact hole P+ injection layer 510 includes: BF2 ions are implanted at the bottom of the contact hole 500 to form a contact hole P+ implantation layer 510, wherein the doping concentration of BF2 ions is 5e19~5e20.

[0013] Optionally, in S800, a back field stop layer 700 is formed on the back side of the device by ion implantation, and a P+ back collector layer 710 is formed on the back side of the back field stop layer 700 by ion implantation, including: A back field cutoff layer 700 is formed on the back side of the device by multiple proton implantation, wherein the proton implantation is 2 to 4 times and the proton doping concentration is 5e14~5e16; and a P+ back collector layer 710 is formed on the back side of the back field cutoff layer 700 by implanting boron ions, wherein the boron ion doping concentration is 8e18~6e19.

[0014] Beneficial effects: This application provides an IGBT device and its fabrication method. The fabricated IGBT device is a parallel structure of front-side NMOS and PMOS. During the IGBT device's turn-off and short-circuit periods, the channel of the negative gate is controlled by a negative gate, allowing holes stored in the drift region to flow out from the front side along the path from the emitter to the channel and then to the collector of the PMOS transistor. The holes are directly discharged to the IGBT emitter through the drain, channel, and source of the PMOS. Under high current conditions such as short circuit, the NPN transistor formed by the N-base region, the P-body region of the IGBT, and the N-drift region can be triggered to conduct by adjusting the control voltage of the negative gate, forming a low-resistance discharge path and increasing the short-circuit peak current of the IGBT device. In this application, a negative voltage is applied to the PMOS gate during the IGBT turn-off and short-circuit processes, causing the PMOS channel to conduct, thereby accelerating the hole extraction speed during turn-off, accelerating the turn-off speed of the IGBT device during switching, and increasing the short-circuit peak current of the device.

[0015] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of an IGBT device disclosed in the relevant technology; Figure 2 This is a schematic diagram of the structure of the IGBT device provided in this application; Figure 3 This is a schematic diagram of the fabrication method of the IGBT device provided in this application; Figures 4a-4o This is a schematic diagram of the fabrication process of the IGBT device provided in this application. Detailed Implementation

[0017] The present application will be described in further detail below with reference to specific embodiments, but the implementation of the present application is not limited thereto.

[0018] Firstly, such as Figure 2 As shown, this application provides an IGBT device comprising, from bottom to top, an N-type doped substrate 100, an interlayer dielectric layer 400, a front metal layer 600, a field stop layer 700, and a back metal layer 800; refer to Figure 2An N-type doped carrier storage layer 110, a P-type body region 300, and three gate trenches 200 extending from the P-type body region 300 through the N-type doped carrier storage layer 110 are disposed from top to bottom within the N-type doped substrate 100. A gate oxide layer 210 is disposed on the inner wall of each of the three gate trenches 200, and a polysilicon layer 220 is filled inside each trench. The three gate trenches are respectively an active gate trench, a dummy gate trench, and a negative voltage gate trench. A PMOS N-base region 301 is disposed within the P-type body region 300 and between the negative voltage gate trench and the dummy gate trench. Contact holes 500 are disposed on both sides of the ports of the three gate trenches. The contact hole 500 between the dummy gate trench and the active gate trench is disposed within the PMOS N-base region 301. A PMOS transistor is disposed near the contact hole 500 on one side of the negative voltage gate trench port. The P+ emitter 310 has IGBT N+ emitters 320 on both sides of the port of the active gate trench and the virtual gate trench. Except for the contact hole 500 in the PMOS N-base region 301, the bottom of each contact hole 500 has a contact hole P+ injection layer 510. The interlayer dielectric layer 400 covers the front side except for the contact holes 500. The front metal layer 600 is disposed on the interlayer dielectric layer 400, and the contact holes 500 are electrically connected to the PMOS P+ emitters 310. The field cutoff layer 700 is disposed on the back side of the substrate 100, the collector layer 710 is disposed on the back side of the field cutoff layer 700, and the back metal layer 800 is disposed on the back side of the collector layer 710.

[0019] The IGBT device of this application integrates a vertical PMOS transistor in the active region of each cell. During the device turn-off process, a hole channel is formed on the negative gate of the PMOS through the negative gate voltage, which increases the hole extraction path. Compared with the conventional IGBT structure, holes can only be eliminated by reverse extraction and recombination through the PN junction. This invention improves the hole extraction path and increases the hole extraction speed.

[0020] During a short circuit, the PMOS structure forms an electron channel in the negative gate structure through positive voltage formation. The peak short-circuit current of the IGBT can be increased through the NPN / NMOS structure composed of the N-base region, the IGBT P-body region, and the N-drift region.

[0021] like Figure 3 This application provides a method for fabricating an IGBT device, wherein the IGBT device as described in the first aspect is fabricated, the method comprising: S100, obtain an N-type doped substrate 100, and form an N-type doped carrier storage layer 110 on the upper surface of the N-type doped substrate 100 by high-energy P-ion implantation. Typically, the peak concentration of the carrier storage layer is between 1e15 and 1e17. (Reference) Figures 4a-4b .

[0022] In this application, an N-type doped carrier storage layer 110 is formed on the upper surface of the N-type doped substrate 100 by phosphorus ion implantation, wherein the phosphorus ion doping concentration is 1e17~1e18.

[0023] S200: Using an etching process, three gate trenches 200 extending from top to bottom through the carrier storage layer 110 are etched into the substrate 100. A gate oxide layer 210 is thermally grown on the inner wall of the gate trenches 200 and the surface of the substrate 100. Polysilicon is then deposited within the gate trenches 200 and on the surface gate oxide layer using a deposition process until the trench structure is completely filled. The process is then etched back to a predetermined position below the substrate 100 to form a polysilicon layer 220. (Refer to...) Figures 4c-4f The predetermined position is 0.1~0.2um below the substrate 100.

[0024] S300, the device surface obtained after S200, is used to form P-type body regions 300 on both sides of the three gate trenches 200 by ion implantation of P-type impurities into the N-type doped substrate 100. (Refer to...) Figure 4g .

[0025] This application creates a P-type body region 300 on both sides of the three gate trenches 200 by implanting boron ions into the N-type doped substrate 100, wherein the boron ion doping concentration is 8e15~2e17.

[0026] S400, within the P-type body region 300 between the virtual gate trench and the negative gate trench, a PMOS N-base region 301 is formed by ion implantation of N-type impurities. Furthermore, within the PMOS N-base region 301, near the port position of the negative gate trench, a PMOS P+ emitter 310 is formed by ion implantation of heavily doped P-type impurities. (Reference) Figures 4h to 4i .

[0027] This application forms a PMOS N-base region 301 by implanting phosphorus ions, wherein the phosphorus ion doping concentration is 1e17~1e18; and forms a PMOS P+ emitter 310 by implanting boron ions, wherein the boron ion doping concentration is 5e19~8e20.

[0028] S500, near the trench port within the P-type body region 300 on both sides of the virtual gate trench and the active gate trench, an IGBT N+ emitter 320 is formed by ion implantation and heavy doping with N-type impurities. (Reference) Figure 4j .

[0029] This application forms the IGBT N+ emitter 320 by implanting phosphorus ions, wherein the phosphorus ion doping concentration is 5e19~1e21.

[0030] In S600, an interlayer dielectric layer 400 is deposited on the front side of an N-type doped substrate 100 via chemical vapor deposition. Contact holes 500 are then formed in the interlayer dielectric layer 400 through photolithography and etching, exposing the underlying P-type body region 300 and P+ emitter 310. (Reference) Figures 4k to 4l .

[0031] S700, a P-type impurity is injected into the bottom of the contact hole 500 to form a contact hole P+ injection layer 510. A front-side metal layer 600 is deposited on the front side of the interlayer dielectric layer 400 to fill the contact hole 500 and form an electrical connection with the emitter. Reference Figure 4m .

[0032] In this application, BF2 ions are implanted at the bottom of the contact hole 500 to form a contact hole P+ implantation layer 510, wherein the doping concentration of BF2 ions is 5e19~5e20.

[0033] In step S800, the device formed in step S700 is flipped over, and a back field cutoff layer 700 is formed on the back side of the device by ion implantation. A P+ back collector layer 710 is then formed on the back side of the back field cutoff layer 700 by ion implantation. A back metal layer 800 is deposited on the back side of the P+ back collector layer 710. (Refer to...) Figures 4n to 4o .

[0034] In this application, a back field cutoff layer 700 is formed on the back side of the device by multiple proton implantations, wherein the proton implantation is 2 to 4 times and the proton doping concentration is 5e14~5e16; and a P+ back collector layer 710 is formed on the back side of the back field cutoff layer 700 by implanting boron ions, wherein the boron ion doping concentration is 8e18~6e19.

[0035] It is worth noting that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0036] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. An IGBT device, characterized in that, It includes an N-type doped substrate (100), an interlayer dielectric layer (400), a front metal layer (600), a field stop layer (700), and a back metal layer (800) arranged from bottom to top. The N-type doped substrate (100) contains, from top to bottom, an N-type doped carrier storage layer (110), a P-type body region (300), and three gate trenches (200) extending from the P-type body region (300) through the N-type doped carrier storage layer (110). The inner walls of the three gate trenches (200) are provided with gate oxide layers (210), and the interiors are filled with polysilicon layers (220). The three gate trenches are respectively an active gate trench, a dummy gate trench, and a negative voltage gate trench. A PMOS N-base region (301) is disposed within the P-type body region (300) and between the negative voltage gate trench and the dummy gate trench. Contact holes (500) are provided on both sides of the ports of the three gate trenches. The contact hole (500) between the dummy gate trench and the active gate trench is disposed within the PMOS N-base region (301). A PMOS is disposed near the contact hole (500) on one side of the negative voltage gate trench port. The P+ emitter (310) is provided with IGBT N+ emitters (320) on both sides of the port of the active gate trench and the virtual gate trench; except for the contact hole (500) in the PMOS N base region (301), the bottom of the other contact holes (500) is provided with a contact hole P+ injection layer (510); the interlayer dielectric layer (400) covers the front side except for the contact hole (500), the front metal layer (600) is disposed on the interlayer dielectric layer (400), and the contact hole (500) is electrically connected to the PMOS P+ emitter (310); the field cut-off layer (700) is disposed on the back side of the substrate (100), the collector layer (710) is disposed on the back side of the field cut-off layer (700), and the back metal layer (800) is disposed on the back side of the collector layer (710).

2. A method for fabricating an IGBT device, characterized in that, The method for fabricating the IGBT device as described in claim 1 includes: S100, obtain an N-type doped substrate (100), and form an N-type doped carrier storage layer (110) on the upper surface of the N-type doped substrate (100) by ion implantation. S200, using an etching process, three gate trenches (200) are etched in the substrate (100) from top to bottom through the carrier storage layer (110), and a gate oxide layer (210) is thermally grown on the inner wall of the gate trenches (200) and the surface of the substrate (100). Polysilicon is deposited in the gate trenches (200) and the surface gate oxide layer until the trench structure is completely filled. Then, it is etched back to a predetermined position below the substrate (100) to form a polysilicon layer (220). S300, the device surface obtained after S200 is formed by ion implantation of P-type impurities into the N-type doped substrate (100) to form P-type body regions (300) on both sides of the three gate trenches (200). S400, within the P-type body region (300) between the virtual gate trench and the negative gate trench, a PMOS N-base region (301) is formed by ion implantation of N-type impurities, and within the PMOS N-base region (301) near the port position of the negative gate trench, a PMOS P+ emitter (310) is formed by ion implantation of heavily doped P-type impurities. S500, an IGBT N+ emitter (320) is formed near the trench port in the P-type body region (300) on both sides of the virtual gate trench and the active gate trench by ion implantation and heavy doping of N-type impurities. S600, an interlayer dielectric layer (400) is deposited on the front side of an N-type doped substrate (100) by chemical vapor deposition, and a contact hole (500) is opened in the interlayer dielectric layer (400) by photolithography and etching to expose the underlying P-type body region (300) and P+ emitter (310). S700, P-type impurities are injected into the bottom of the contact hole (500) to form a contact hole P+ injection layer (510), and a front metal layer (600) is deposited on the front side of the interlayer dielectric layer (400) to fill the contact hole (500) and form an electrical connection with the emitter. In S800, the device formed in S700 is flipped over, and a back field cutoff layer (700) is formed on the back side of the device by ion implantation, and a P+ back field collector layer (710) is formed on the back side of the back field cutoff layer (700) by ion implantation; a back metal layer (800) is deposited on the back side of the P+ back field collector layer (710).

3. The method for fabricating an IGBT device according to claim 2, characterized in that, The resistivity of the substrate (100) is 20~30 Ω·cm.

4. The method for fabricating an IGBT device according to claim 2, characterized in that, In S100, the formation of an N-type doped carrier storage layer (110) on the upper surface of the N-type doped substrate (100) by ion implantation includes: An N-type doped carrier storage layer (110) is formed on the upper surface of the N-type doped substrate (100) by phosphorus ion implantation, wherein the phosphorus ion doping concentration is 1e17~1e18.

5. The method for fabricating an IGBT device according to claim 2, characterized in that, The predetermined position in S200 is 0.1~0.2um below the substrate (100).

6. The method for fabricating an IGBT device according to claim 2, characterized in that, In S300, implanting P-type impurities into the N-type doped substrate (100) includes: By implanting boron ions into the N-type doped substrate (100), P-type body regions (300) are formed on both sides of the three gate trenches (200), wherein the doping concentration of boron ions is 8e15~2e17.

7. The method for fabricating an IGBT device according to claim 2, characterized in that, The formation of the PMOS N-base region (301) in S400 by ion implantation of N-type impurities includes: A PMOS N-base region (301) is formed by implanting phosphorus ions, wherein the phosphorus ion doping concentration is 1e17~1e18. The formation of the PMOS P+ emitter (310) in S400 by ion implantation and heavy doping of P-type impurities includes: A PMOS P+ emitter (310) is formed by implanting boron ions, wherein the boron ion doping concentration is 5e19~8e20.

8. The method for fabricating an IGBT device according to claim 2, characterized in that, The S500 IGBT N+ emitter (320) formed by ion implantation and heavy doping with N-type impurities includes: An IGBT N+ emitter (320) is formed by implanting phosphorus ions, wherein the phosphorus ion doping concentration is 5e19~1e21.

9. The method for fabricating an IGBT device according to claim 2, characterized in that, In S700, a P-type impurity is injected into the bottom of the contact hole (500) to form a contact hole P+ injection layer (510), including: BF2 ions are injected into the bottom of the contact hole (500) to form a contact hole P+ implantation layer (510), wherein the doping concentration of BF2 ions is 5e19~5e20.

10. The method for fabricating an IGBT device according to claim 2, characterized in that, In S800, a back field stop layer (700) is formed on the back side of the device by ion implantation, and a P+ back collector layer (710) is formed on the back side of the back field stop layer (700) by ion implantation, including: A back field cutoff layer (700) is formed on the back side of the device by multiple proton implantation, wherein the proton implantation is 2 to 4 times and the proton doping concentration is 5e14~5e16; and a P+ back collector layer (710) is formed on the back side of the back field cutoff layer (700) by implanting boron ions, wherein the boron ion doping concentration is 8e18~6e19.

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