Semiconductor structure and semiconductor device

Abstract

The invention provides a semiconductor structure and a semiconductor device. The semiconductor structure comprises a substrate and an epitaxial layer which are stacked in sequence; the at least two first doped regions are arranged at intervals in the first direction and located in the epitaxial layer, and the doping types of the first doped regions and the epitaxial layer are different; wherein one first doped region comprises a second doped region, a third doped region and a fourth doped region which are sequentially arranged in the first direction, the other first doped region comprises a third doped region, a fifth doped region and a second doped region which are sequentially arranged in the first direction, and the doping type of the second doped region is the same as that of the first doped region; the doping type of the third doped region, the fourth doped region and the fifth doped region is different from the doping type of the first doped region. The MOS device solves the problem that in the prior art, a parasitic triode in an MOS device is easy to conduct, so that the reliability of the device is low.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a semiconductor device. Background Technology

[0002] Silicon-based IGBTs dominate high-voltage, high-current applications, but they cannot withstand high-frequency operation and have high power consumption. SiC, on the other hand, with its high voltage and high temperature resistance, allows it to achieve the same voltage withstand capability as silicon-based IGBTs using simpler MOSFET devices, while avoiding their high energy consumption. Under the same conditions, silicon carbide MOSFETs reduce energy loss by 66% compared to silicon-based IGBTs of the same specifications, primarily due to a significant reduction in switching losses. In the new energy vehicle industry, SiC can be used in inverters for driving and controlling motors, on-board chargers, and fast-charging stations. In photovoltaic power generation, leading photovoltaic inverter companies have already adopted SiC power devices to replace silicon devices.

[0003] In the N+ source region structure of traditional SiC MOS, the parasitic transistor formed by the N+ source region, P-base body region and epitaxial layer has a high emitter injection efficiency due to the high doping of the N+ source region, which can easily lead to the parasitic transistor turning on, reducing the device's UIS capability and affecting device reliability. Summary of the Invention

[0004] The main objective of this application is to provide a semiconductor structure and semiconductor device to solve the problem of low device reliability caused by the easy conduction of parasitic transistors in existing MOS devices.

[0005] To achieve the above objectives, according to one aspect of this application, a semiconductor structure is provided, comprising: a substrate; an epitaxial layer located on one side surface of the substrate; at least two first doped regions spaced apart in a first direction, located in the epitaxial layer, wherein the doping type of the first doped regions is different from the doping type of the epitaxial layer, and the first direction intersects the thickness direction of the substrate; wherein one of the first doped regions includes a second doped region, a third doped region, and a fourth doped region implanted in a stepped manner along the first direction; and the other first doped region includes the third doped region, a fifth doped region implanted in a stepped manner along the first direction, and the second doped region, wherein the doping type of the second doped region is the same as the doping type of the first doped region, and the doping types of the third, fourth, and fifth doped regions are different from the doping type of the first doped region.

[0006] Optionally, the fourth doped region, which is implanted in a stepped manner, includes at least two layers of doped regions with different doping concentrations, and the fifth doped region, which is implanted in a stepped manner, includes at least two layers of doped regions with different doping concentrations.

[0007] Optionally, the fourth doped region includes a first sub-doped region and a second sub-doped region disposed along a second direction, the doping concentration of the second sub-doped region being greater than the doping concentration of the first sub-doped region, the surface of the second sub-doped region facing away from the substrate being flush with the surface of one of the first doped regions facing away from the substrate, and the second direction being parallel to the thickness direction of the substrate; the fifth doped region includes a third sub-doped region and a fourth sub-doped region disposed along the second direction, the doping concentration of the fourth sub-doped region being greater than the doping concentration of the third sub-doped region, the surface of the fourth sub-doped region facing away from the substrate being flush with the surface of the other first doped region facing away from the substrate, and the doping concentration of the third sub-doped region being less than the doping concentration of the first sub-doped region.

[0008] Optionally, the fourth doped region includes three layers of doped regions with different doping concentrations, the fifth doped region includes three layers of doped regions with different doping concentrations, the fourth doped region further includes a fifth sub-doped region located between the first sub-doped region and the second sub-doped region, the doping concentration of the fifth sub-doped region being greater than the doping concentration of the first sub-doped region and less than the doping concentration of the second sub-doped region; the fifth doped region further includes a sixth sub-doped region located between the third sub-doped region and the fourth sub-doped region, the doping concentration of the sixth sub-doped region being greater than the doping concentration of the third sub-doped region and less than the doping concentration of the fourth sub-doped region.

[0009] Optionally, the doping concentration of the second sub-doped region is equal to the doping concentration of the fourth sub-doped region, and the doping concentration of the sixth sub-doped region is less than the doping concentration of the fifth sub-doped region.

[0010] Optionally, the doping depth of the second sub-doped region is less than the doping depth of the fourth sub-doped region, the doping depth of the first sub-doped region is less than the doping depth of the third sub-doped region, and the doping depth of the fifth sub-doped region is less than the doping depth of the sixth sub-doped region.

[0011] Optionally, the doping concentration of the first sub-doped region is 3.0e17cm. -3 -4.0e17cm -3 The doping concentration of both the second sub-doped region and the fourth sub-doped region is 1.0e20cm. -3 -5.0e20cm -3 The doping concentration of the fifth sub-doped region is 7.0e17cm. -3-8.0e17cm -3 The doping concentration of the third sub-doped region is 1.0e17cm. -3 -2.0e17cm -3 The doping concentration of the sixth sub-doped region is 4.0e17cm. -3 -5.0e17cm -3 .

[0012] Optionally, the doping depth of the first sub-doped region is 0.3 μm-0.4 μm, the doping depth of the second sub-doped region is 0.04 μm-0.06 μm, the doping depth of the fifth sub-doped region is 0.08 μm-0.12 μm, the doping depth of the third sub-doped region is 0.25 μm-0.35 μm, the doping depth of the fourth sub-doped region is 0.08 μm-0.12 μm, and the doping depth of the sixth sub-doped region is 0.15 μm-0.25 μm.

[0013] Optionally, the semiconductor structure further includes: a JFET region located between the two first doped regions; a gate structure located on a portion of the JFET region facing away from the substrate, a portion of the two first doped regions facing away from the substrate, a portion of the fourth doped region facing away from the substrate, and a portion of the third doped region in the other first doped region facing away from the substrate; an interlayer dielectric layer covering the gate structure; a first electrode located on a portion of the second doped region facing away from the substrate, a portion of the third doped region facing away from the substrate, a portion of the fourth doped region facing away from the substrate, and a portion of the fifth doped region facing away from the substrate, the interlayer dielectric layer being located between the first electrode and the gate structure; and a second electrode located on a surface of the substrate facing away from the epitaxial layer.

[0014] According to another aspect of this application, a semiconductor device is provided, comprising: any of the semiconductor structures described herein.

[0015] Using the technical solution of this application, the semiconductor structure includes a substrate, an epitaxial layer located on one side surface of the substrate, and at least two first doped regions located in the epitaxial layer and spaced apart along a first direction. One of the first doped regions includes a second doped region, a third doped region, and a fourth doped region arranged sequentially along the first direction, and the other first doped region includes a third doped region, a fifth doped region, and a second doped region arranged sequentially along the first direction. The doping types of the epitaxial layer, the third doped region, the fourth doped region, and the fifth doped region are all the same, while the doping types of the first doped region and the second doped region are different from those of the epitaxial layer. Compared with the problem of low device reliability caused by the easy conduction of parasitic transistors in existing MOS devices, this application sets a second, third, and fourth doped region arranged sequentially along a first direction in the source region of one half-cell, and sets a third, fifth, and second doped region arranged sequentially along the first direction in the source region of the other half-cell. By setting the fourth and fifth doped regions in the first doped region on different sides with different positional relationships with the second and third doped regions, an asymmetrical distribution is formed, which makes the overall resistance of the two half-cells different. This makes the current carried by the two half-cells different when the device is normally turned on, and disperses the current path. By creating paths with completely different conductivity on the left and right sides, intelligent current shunting is achieved, the current distribution is improved, local current concentration is avoided, the UIS failure threshold of the device is increased, the conduction probability of parasitic transistors is effectively reduced, and the reliability of the device is improved. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A cross-sectional schematic diagram of a semiconductor structure provided according to an embodiment of this application is shown;

[0018] Figures 2 to 7 The diagrams show cross-sectional structural schematics during the fabrication process of a semiconductor structure according to embodiments of this application.

[0019] The above figures include the following reference numerals:

[0020] 10. Substrate; 11. Epitaxial layer; 12. First doped region; 13. First sub-doped region; 14. Second sub-doped region; 15. Third sub-doped region; 16. Fourth sub-doped region; 17. Fifth sub-doped region; 18. Sixth sub-doped region; 19. Third doped region; 20. Second doped region; 21. JFET region; 22. Gate structure; 23. Interlayer dielectric layer; 24. First electrode; 25. Second electrode; 26. Fourth doped region; 27. Fifth doped region; 221. Gate oxide layer; 222. Gate. Detailed Implementation

[0021] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0022] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0025] As described in the background section, in the prior art, parasitic transistors in MOS devices are prone to conduction, resulting in low device reliability. To solve the above problems, embodiments of this application provide a semiconductor structure and a semiconductor device.

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] This application provides a semiconductor structure, such as... Figure 1 As shown, it includes:

[0028] Substrate 10;

[0029] Specifically, the resistivity of the substrate can be 0.02 ± 20% Ωcm, and the doping concentration of the substrate can be 1E15~1E16cm. -3 .

[0030] Epitaxial layer 11 is located on one side surface of the substrate 10;

[0031] Specifically, the doping type of the epitaxial layer is the same as that of the substrate. The doping type of the epitaxial layer can be N-type or P-type, and this application does not impose a specific limitation on this. In the embodiments of this application, the doping type of the epitaxial layer is N-type.

[0032] At least two first doped regions 12 are spaced apart in a first direction and located in the epitaxial layer 11. The doping type of the first doped region 12 is different from the doping type of the epitaxial layer. The first direction intersects the thickness direction of the substrate 10.

[0033] Specifically, the doping depth of the first doped region is 0.7 μm to 0.9 μm, and the doping concentration is 1E17 ± 50% cm⁻¹. -3 In this embodiment, the first doped region is p-type, and the doping element can be Al.

[0034] One of the aforementioned first doped regions 12 includes a second doped region 20, a third doped region 19, and a fourth doped region 26 arranged sequentially along the first direction. The other of the aforementioned first doped regions 12 includes the third doped region 19, a fifth doped region 27, and the second doped region 20 arranged sequentially along the first direction. The doping type of the second doped region 20 is the same as that of the first doped region 12, while the doping types of the third doped region 19, the fourth doped region 26, and the fifth doped region 27 are different from those of the first doped region 12.

[0035] Specifically, the doping concentration of the third doped region is 1.0e19cm. -3 -9.0e19cm -3 The doping depth of the second doped region is 0.2 μm to 0.3 μm, and the doping concentration is 1E19 ± 50% cm⁻¹. -3In this embodiment, the second doped region is p-type, and the doping element can be Al; the third, fourth, and fifth doped regions are all n-type.

[0036] In the above embodiments, the semiconductor structure includes a substrate, an epitaxial layer located on one side surface of the substrate, and at least two first doped regions located in the epitaxial layer and spaced apart along a first direction. One of the first doped regions includes a second doped region, a third doped region, and a fourth doped region arranged sequentially along the first direction. The other first doped region includes a third doped region, a fifth doped region, and a second doped region arranged sequentially along the first direction. The doping types of the epitaxial layer, the third doped region, the fourth doped region, and the fifth doped region are all the same, while the doping types of the first doped region and the second doped region are different from those of the epitaxial layer. Compared with the problem of low device reliability caused by the easy conduction of parasitic transistors in existing MOS devices, this application sets a second, third, and fourth doped region arranged sequentially along a first direction in the source region of one half-cell, and sets a third, fifth, and second doped region arranged sequentially along the first direction in the source region of the other half-cell. By setting the fourth and fifth doped regions in the first doped region on different sides with different positional relationships with the second and third doped regions, an asymmetrical distribution is formed, which makes the overall resistance of the two half-cells different. This makes the current carried by the two half-cells different when the device is normally turned on, and disperses the current path. By creating paths with completely different conductivity on the left and right sides, intelligent current shunting is achieved, the current distribution is improved, local current concentration is avoided, the UIS failure threshold of the device is increased, the conduction probability of parasitic transistors is effectively reduced, and the reliability of the device is improved.

[0037] In one alternative embodiment, the fourth doped region, implanted in a stepped manner, comprises at least two layers of doped regions with different doping concentrations, and the fifth doped region, implanted in a stepped manner, comprises at least two layers of doped regions with different doping concentrations. In this embodiment, the stepped implantation improves the robustness of the device under various operating conditions and further disperses the current into different conductive paths, thus preventing rapid thermal failure caused by excessive current concentration in a particular area.

[0038] In other embodiments, such as Figure 1As shown, the fourth doped region 26 includes a first sub-doped region 13 and a second sub-doped region 14 disposed along a second direction. The doping concentration of the second sub-doped region 14 is greater than that of the first sub-doped region 13. The surface of the second sub-doped region 14 facing away from the substrate 10 is flush with the surface of one of the first doped regions 12 facing away from the substrate. The second direction is parallel to the thickness direction of the substrate 10. The fifth doped region 27 includes a third sub-doped region 15 and a fourth sub-doped region 16 disposed along the second direction. The doping concentration of the fourth sub-doped region 16 is greater than that of the third sub-doped region 15. The surface of the fourth sub-doped region 16 facing away from the substrate 10 is flush with the surface of the other first doped region 12 facing away from the substrate 10. The doping concentration of the third sub-doped region 15 is less than that of the first sub-doped region 13. In this embodiment, the present application sets a first sub-doped region and a second sub-doped region with gradient doping in the fourth doped region on one side, and sets a fourth sub-doped region with gradient doping in the fifth doped region on the other side, and sets the concentration of the third sub-doped region to be less than the concentration of the first sub-doped region, further forming asymmetric source region doping, so that the overall resistance of the half cell on one side is less than the overall resistance of the half cell on the other side, so that the half cell on the other side carries a small amount of current when the device is normally turned on, further dispersing the current path and further improving the UIS failure threshold of the device.

[0039] In another alternative, such as Figure 1 As shown, the fourth doped region 26 comprises three layers of doped regions with different doping concentrations, and the fifth doped region 27 comprises three layers of doped regions with different doping concentrations. The fourth doped region 26 further comprises a fifth sub-doped region 17, located between the first sub-doped region 13 and the second sub-doped region 14. The doping concentration of the fifth sub-doped region 17 is greater than that of the first sub-doped region 13 and less than that of the second sub-doped region 14. The fifth doped region 27 further comprises a sixth sub-doped region 18, located between the third sub-doped region 15 and the fourth sub-doped region 16. The doping concentration of the sixth sub-doped region 18 is greater than that of the third sub-doped region 15 and less than that of the fourth sub-doped region 16. In this embodiment, the fifth and sixth sub-doped regions serve as transition layers, mitigating the abrupt change from high to low concentration and helping to optimize the electric field distribution.

[0040] According to some exemplary embodiments of this application, the doping concentration of the second sub-doped region is equal to the doping concentration of the fourth sub-doped region, and the doping concentration of the sixth sub-doped region is less than the doping concentration of the fifth sub-doped region. In this embodiment, since the doping concentration of the sixth sub-doped region is lower than that of the fifth sub-doped region, the resistance of the right path is further higher than that of the left path, which further effectively guides most of the current to preferentially pass through the left path, while the right path carries less current. This helps to further suppress the conduction of parasitic BJTs and further improve the UIS robustness of the device.

[0041] According to some other exemplary embodiments of this application, the doping depth of the second sub-doped region is less than the doping depth of the fourth sub-doped region, the doping depth of the first sub-doped region is less than the doping depth of the third sub-doped region, and the doping depth of the fifth sub-doped region is less than the doping depth of the sixth sub-doped region. In this embodiment, by setting the doping depths of the second, first, and fifth sub-doped regions to be less than the doping depths of the fourth, third, and sixth sub-doped regions, respectively, that is, by setting the doping depths of the left and right cells to be different, asymmetric doping is further formed, which further disperses the current path and further reduces the conduction probability of the parasitic transistor.

[0042] Specifically, the doping concentration of the third doped region is 1.0e19cm. -3 -9.0e19cm -3 In this embodiment, the doping type of the third doped region is N-type.

[0043] Specifically, the left half-cell (low-resistance main path): N+ region (i.e., the third doped region in one of the first doped regions mentioned above): This is the "entry" of the main current path on the left, forming a low-resistance ohmic contact with the source metal to ensure smooth electron flow; The overall function of the gradient layers N1+ (i.e., the second sub-doped region), N1 (i.e., the fifth sub-doped region), and N1- (i.e., the first sub-doped region): Together they form a low-resistance vertical channel, guiding most of the current to pass through preferentially; N1+ layer: Highly doped, providing extremely low vertical resistance, which is the key to the low-resistance path; N1 layer: Medium doped, serving as a transition layer, mitigating the abrupt change from high concentration to low concentration, which helps to optimize the electric field distribution; N1- layer: Low doped, connecting with the JFET region, its easily depleted characteristics help to modulate the electric field, reduce the IFET effect under high field, and make current transport smoother.

[0044] Specifically, the overall function of the gradient layers of the right half-cell (high-resistance auxiliary path): N2+ (i.e., the fourth sub-doped region), N2 (i.e., the sixth sub-doped region), and N2- (i.e., the third sub-doped region): By deliberately designing a lower doping concentration than the left side, a high-resistance path is formed. It shares a small amount of current during normal operation, but generates a self-limiting current effect under extreme conditions; N2+ layer: ensures contact with the source, but its overall path resistance is high; N2 layer: its doping concentration is usually designed to be lower than that of the N1 layer on the left, which can create a resistance difference; N2- layer: the region with the lowest concentration, usually lighter doped than N1-, will be completely depleted under high field, the resistance increases sharply, and a strong self-limiting current effect is generated; N+ region (i.e., the third doped region in the other first doped region mentioned above): as the exit of the right channel, it ensures that electrons from the right channel can be injected into the gradient layer. It is low-resistance itself, but because it is connected in series in the entire high-resistance path, it does not change the overall high-resistance property of the right side.

[0045] According to some other exemplary embodiments of this application, the doping concentration of the first sub-doped region is 3.0e17cm. -3 -4.0e17cm -3 The doping concentration of both the second and fourth sub-doped regions is 1.0e20cm. -3 -5.0e20cm -3 The doping concentration of the fifth sub-doped region is 7.0e17cm. -3 -8.0e17cm -3 The doping concentration of the aforementioned third sub-doped region is 1.0e17cm. -3 -2.0e17cm -3 The doping concentration of the sixth sub-doped region is 4.0e17cm. -3 -5.0e17cm -3 In this embodiment, this specific concentration distribution aims to establish an asymmetric structure of a low-resistivity main path on the left and a high-resistivity auxiliary path on the right. The left path, composed of the second sub-doped region, the fifth sub-doped region, and the first sub-doped region, provides a fast channel for electrons to move from the source region to the drift region. It has a low resistivity, ensuring efficient current transmission. The right path, through the different concentration designs of the fourth, sixth, and third sub-doped regions, forms a natural current limiter, effectively preventing current concentration even under extreme conditions. In addition, the high doping treatment of the second and fourth sub-doped regions on both sides ensures good contact with the metal.

[0046] According to some other exemplary embodiments of this application, the doping depth of the first sub-doped region is 0.3 μm-0.4 μm, the doping depth of the second sub-doped region is 0.04 μm-0.06 μm, the doping depth of the fifth sub-doped region is 0.08 μm-0.12 μm, the doping depth of the third sub-doped region is 0.25 μm-0.35 μm, the doping depth of the fourth sub-doped region is 0.08 μm-0.12 μm, and the doping depth of the sixth sub-doped region is 0.15 μm-0.25 μm. In this embodiment, by precisely controlling the doping depth of each layer, the current flow path can be further effectively adjusted, thereby further improving the reliability of the device.

[0047] In other embodiments, such as Figure 1 As shown, the semiconductor structure further includes: a JFET region 21 located between the two first doped regions 12; a gate structure 22 located on the surface of the JFET region 21 facing away from the substrate 10, the surface of the two first doped regions 12 facing away from the substrate, the surface of the fourth doped region 26 facing away from the substrate 10, and the surface of the third doped region 19 in the other first doped region 12 facing away from the substrate 10; an interlayer dielectric layer 23 covering the gate structure 22; a first electrode 24 located on the surface of the second doped region 20 facing away from the substrate 10, the surface of the third doped region 19 facing away from the substrate 10, the surface of the fourth doped region 26 facing away from the substrate 10, and the surface of the fifth doped region 27 facing away from the substrate 10, the interlayer dielectric layer 23 being located between the first electrode 24 and the gate structure 22; and a second electrode 25 located on the surface of the substrate 10 facing away from the epitaxial layer 11. In this embodiment, by introducing a JFET region and setting a gate structure on top of it, the current flowing through the device can be controlled more precisely. The presence of the JFET region allows its conductivity to be modulated by changes in the gate voltage, thereby avoiding uncontrolled current flow to a certain extent, especially preventing overcurrent phenomena under high voltage. Two electrodes are used for current input and output, and the gate structure is used to control the current switching. The presence of the interlayer dielectric layer isolates the gate structure and the electrodes, avoiding short circuits.

[0048] Specifically, such as Figure 1As shown, the gate structure 22 includes a gate oxide layer 221 and a gate 222. The gate oxide layer 221 is located on the partial surface of the JFET region 21 away from the substrate 10, the partial surfaces of the two first doped regions 12 away from the substrate, the partial surface of the fourth doped region 26 away from the substrate 10, and the partial surface of the third doped region 19 in the other first doped region 12 away from the substrate 10. The gate 222 is located on the surface of the gate oxide layer 221 away from the substrate 10.

[0049] Specifically, the first electrode serves as the source electrode of the device, and the second electrode serves as the drain electrode of the device.

[0050] Specifically, the doping type of the JFET region is the same as that of the epitaxial layer, and the doping concentration of the JFET region is 1E18±50%cm³. -3 The doping depth of the JFET region is 0.8 μm to 0.9 μm. In this embodiment, the JFET is N-type doped, and the doping element can be nitrogen.

[0051] Specifically, the material of the interlayer dielectric layer can be SiO2 or other materials, and this application does not impose specific restrictions on it; the thickness of the interlayer dielectric layer is 600nm-1000nm.

[0052] In summary, this application utilizes asymmetric source region doping, where the depth or concentration of the three-layer doped structure in the source region differs near the cell center and near the gate channel, creating asymmetry and dispersing the current path. This reduces parasitic transistor conduction while improving UIS robustness, enhancing current distribution, avoiding local current concentration, and raising the UIS failure threshold. In traditional symmetric cell structures, all regions have consistent conductivity, causing current to flow uniformly and concentratedly through the same path in each cell during conduction. However, in the asymmetric structure of this application, intelligent current shunting is achieved by creating paths with drastically different conductivity on the left and right sides.

[0053] In this application, the left path is a low-resistance main path. The left half-cell is designed with gradient doping from the surface N1+ to the deep N1-. N1+, N1, and N1- form a gradient structure with gradually decreasing doping concentration. This makes the overall resistance of the entire left path very low. According to the "principle of minimum resistance" of current, when the device is turned on, most electrons will preferentially choose this "highway" as the main path. The right path is a high-resistance auxiliary path. By designing the doping concentration of the N2- and N2 layers to be lower than that of the corresponding N1- and N1 layers on the left, the overall resistance of this path is higher than that of the left. It carries a small amount of current when normally turned on, and its more important role is reflected in extreme operating conditions.

[0054] This application can significantly improve short-circuit withstand capability: In extreme cases such as short circuits, the instantaneous current is huge. In traditional symmetrical structures, the huge current will concentrate through the JFET region, generating local hot spots, causing the device to fail thermally within microseconds. In asymmetrical structures, the current is actively dispersed to the left and right paths, significantly reducing the peak current density of the JFET region. According to Joule's law, the heat generated is proportional to the square of the current density. Therefore, even a slight dispersion of the current density can lead to a significant reduction in heat, thereby greatly extending the short-circuit withstand time. This application can effectively suppress parasitic BJT conduction: SiCMOSFETs have inherent parasitic NPN transistors. When a large current flows through the lateral resistance of the first doped region, the resulting voltage drop exceeds about 0.7V, which will trigger the parasitic BJT to conduct, causing current latch-up and burning out the device. The asymmetrical structure guides the main current path to the left, which greatly reduces the current density flowing through the first doped region on the right side. As a result, the lateral voltage drop generated on the resistance of the first doped region is also significantly reduced, increasing the turn-on threshold of the parasitic BJT and enhancing the reliability of the device.

[0055] Specifically, the process steps of the semiconductor structure fabrication method of this application include: 1) as follows Figure 2 As shown, firstly, an EPI layer (i.e., epitaxial layer 11) is grown on an N+ type substrate 10, including SiC (with a resistivity of 0.02 ± 20% Ωcm), to serve as the drift region and bear the main breakdown layer. The doping concentration of epitaxial layer 11 is 1E15cm. -3 ~1E16cm -3 The thickness is set according to product requirements (e.g., the EPI layer thickness of a 1200V MOS is 9~11μm, and the EPI layer thickness of a 650V MOS is 5~7μm); 2) such as Figure 3 As shown, a P+ layer (i.e., the second doped region 20) was grown, with Al as the implanted element and an implantation dose of 1E19±50%cm. -3 The injection depth is 0.2μm~0.3μm; 3) such as Figure 3 As shown, a P-base layer (i.e., the first doped region 12) is grown, with Al as the implanted element and an implantation dose of 1E17±50%cm. -3 The injection depth is 0.7μm~0.9μm; 4) such as Figure 4 As shown, an N-source region layer is grown using implantation or epitaxy techniques. On the left side of the cell (near the gate channel (not shown)), N1+ regions (i.e., the second sub-doped region 14), N1 regions (i.e., the fifth sub-doped region 17), and N1- regions (i.e., the first sub-doped region 13) are formed, wherein the doping concentration of the N1+ region is 1.0e20cm⁻¹. -3 -5.0e20cm -3The doping depth is 0.04 μm-0.06 μm, and the doping concentration in the N1 region is 7.0-8.0e17 cm⁻¹. -3 The doping depth is 0.08-0.12 μm, and the doping concentration in the N1- region is 3.0-4.0e17cm. -3 The doping depth is 0.3-0.4 μm; N2+ regions (i.e., the fourth sub-doped region 16), N2 regions (i.e., the sixth sub-doped region 18), and N2- regions (i.e., the third sub-doped region 15) are generated on the right side of the cell (away from the channel), wherein the doping concentration of the N2+ region is 1.0e20cm. -3 -5.0e20cm -3 The doping depth is 0.08-0.12 μm, and the doping concentration in the N2 region is 4.0-5.0e17cm. -3 The doping depth is 0.15-0.25 μm, and the doping concentration in the N2- region is 1.0-2.0e17cm. -3 The doping depth is 0.25-0.35 μm; two N+ regions (i.e., the third doped region 19) are generated, with a doping concentration of 1.0-9.0e19cm⁻¹. -3 The two N+ regions have the same size; this asymmetric source region doping disperses the current path, reducing parasitic transistor conduction while improving UIS robustness, improving current distribution, avoiding local current concentration, and raising the UIS failure threshold; 5) such as Figure 5 As shown, JFET region 21 was grown, and the implanted element was nitrogen, with an implantation dose of 1E18 ± 50% cm⁻¹. -3 The implantation depth is 0.8~0.9μm, and the activation of the implanted region and the formation and etching of the active region are completed; 6) such as Figure 6 As shown, a pre-gate oxide layer (not shown) with a thickness of 300-800 Å is grown, followed by the growth of a polysilicon pre-gate layer (not shown) with a thickness of 2000-8000 Å. Excess pre-gate oxide layer and pre-gate layer are then etched away to obtain a gate structure 22 including a gate oxide layer 221 and a gate 222; 7) as shown Figure 7 As shown, a preliminary interlayer dielectric layer (not shown) is deposited, and excess preliminary interlayer dielectric layer is etched away to obtain interlayer dielectric layer 23, which can be made of SiO2 or other dielectric materials, with a thickness of 600-1000 nm; 8) As shown Figure 1 As shown, the source electrode (i.e., the first electrode 24) and the back drain electrode (i.e., the second electrode 25) are generated sequentially.

[0056] This application also provides a semiconductor device, including any of the above-described semiconductor structures.

[0057] Specifically, the semiconductor device in this application may be a SiC MOS device.

[0058] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0060] In the semiconductor structure of this application, the semiconductor structure includes a substrate, an epitaxial layer located on one side surface of the substrate, and at least two first doped regions located in the epitaxial layer and spaced apart along a first direction. One of the first doped regions includes a second doped region, a third doped region, and a fourth doped region arranged sequentially along the first direction. The other first doped region includes a third doped region, a fifth doped region, and a second doped region arranged sequentially along the first direction. The doping types of the epitaxial layer, the third doped region, the fourth doped region, and the fifth doped region are all the same. The doping types of the first doped region and the second doped region are different from those of the epitaxial layer. Compared with the problem of low device reliability caused by the easy conduction of parasitic transistors in existing MOS devices, this application sets a second, third, and fourth doped region arranged sequentially along a first direction in the source region of one half-cell, and sets a third, fifth, and second doped region arranged sequentially along the first direction in the source region of the other half-cell. By setting the fourth and fifth doped regions in the first doped region on different sides with different positional relationships with the second and third doped regions, an asymmetrical distribution is formed, which makes the overall resistance of the two half-cells different. This makes the current carried by the two half-cells different when the device is normally turned on, and disperses the current path. By creating paths with completely different conductivity on the left and right sides, intelligent current shunting is achieved, the current distribution is improved, local current concentration is avoided, the UIS failure threshold of the device is increased, the conduction probability of parasitic transistors is effectively reduced, and the reliability of the device is improved.

[0061] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized by, Comprising: a substrate; an epitaxial layer on one side surface of the substrate; at least two first doped regions arranged in a first direction on the epitaxial layer, the first doped regions having a different doping type from the epitaxial layer, the first direction being perpendicular to the thickness direction of the substrate; one of the first doped regions comprises a second doped region, a third doped region and a fourth doped region with a stepwise layered doping concentration arranged in the first direction, and the other of the first doped regions comprises the third doped region, a fifth doped region with a stepwise layered doping concentration and the second doped region arranged in the first direction, the second doped region having the same doping type as the first doped region, and the third doped region, the fourth doped region and the fifth doped region having a different doping type from the first doped region.

2. The semiconductor structure of claim 1, wherein, The fourth doped region with a stepwise layered doping concentration comprises at least two doped regions with different doping concentrations, and the fifth doped region with a stepwise layered doping concentration comprises at least two doped regions with different doping concentrations.

3. The semiconductor structure of claim 2, wherein: the fourth doped region comprises a first sub-doped region and a second sub-doped region arranged in a second direction, the second sub-doped region having a higher doping concentration than the first sub-doped region, and a surface of the second sub-doped region away from the substrate being flush with a surface of the one of the first doped regions away from the substrate, the second direction being parallel to the thickness direction of the substrate; the fifth doped region comprises a third sub-doped region and a fourth sub-doped region arranged in the second direction, the fourth sub-doped region having a higher doping concentration than the third sub-doped region, and a surface of the fourth sub-doped region away from the substrate being flush with a surface of the other of the first doped regions away from the substrate, and the third sub-doped region having a lower doping concentration than the first sub-doped region.

4. The semiconductor structure of claim 3, wherein, the fourth doped region comprises three doped regions with different doping concentrations, and the fifth doped region comprises three doped regions with different doping concentrations, the fourth doped region further comprises a fifth sub-doped region between the first sub-doped region and the second sub-doped region, the fifth sub-doped region having a higher doping concentration than the first sub-doped region and a lower doping concentration than the second sub-doped region; the fifth doped region further comprises a sixth sub-doped region between the third sub-doped region and the fourth sub-doped region, the sixth sub-doped region having a higher doping concentration than the third sub-doped region and a lower doping concentration than the fourth sub-doped region.

5. The semiconductor structure of claim 4, wherein, the doping concentration of the second sub-doped region is equal to the doping concentration of the fourth sub-doped region, and the doping concentration of the sixth sub-doped region is lower than the doping concentration of the fifth sub-doped region.

6. The semiconductor structure of claim 4, wherein, the doping depth of the second sub-doped region is lower than the doping depth of the fourth sub-doped region, the doping depth of the first sub-doped region is lower than the doping depth of the third sub-doped region, and the doping depth of the fifth sub-doped region is lower than the doping depth of the sixth sub-doped region.

7. The semiconductor structure of claim 4, wherein, a doping concentration of the first sub-doped region is 3.0e17 cm -3 -4.0e17 cm -3 a doping concentration of the second sub-doped region and the fourth sub-doped region is 1.0e20 cm -3 -5.0e20 cm -3 a doping concentration of the fifth sub-doped region is 7.0e17 cm -3 -8.0e17 cm -3 a doping concentration of the third sub-doped region is 1.0e17 cm -3 -2.0e17 cm -3 a doping concentration of the sixth sub-doped region is 4.0e17 cm -3 -5.0e17 cm -3 .

8. The semiconductor structure of claim 4, wherein, The first sub-doped region has a doping depth of 0.3-0.4 μm, the second sub-doped region has a doping depth of 0.04-0.06 μm, the fifth sub-doped region has a doping depth of 0.08-0.12 μm, the third sub-doped region has a doping depth of 0.25-0.35 μm, the fourth sub-doped region has a doping depth of 0.08-0.12 μm, and the sixth sub-doped region has a doping depth of 0.15-0.25 μm.

9. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a JFET region between the two first doped regions; a gate structure on a part of the surface of the JFET region facing away from the substrate, on a part of the surface of the two first doped regions facing away from the substrate, on a part of the surface of the fourth doped region facing away from the substrate, and on a part of the surface of the third doped region in the other first doped region facing away from the substrate; an interlayer dielectric layer covering the gate structure; a first electrode on a surface of the second doped region facing away from the substrate, on a surface of the third doped region facing away from the substrate, on a part of the surface of the fourth doped region facing away from the substrate, and on a part of the surface of the fifth doped region facing away from the substrate, the interlayer dielectric layer being between the first electrode and the gate structure; a second electrode on a surface of the substrate facing away from the epitaxial layer.

10. A semiconductor device, characterized by comprising: The semiconductor structure comprises: the semiconductor structure of any one of claims 1-9. the semiconductor structure of any one of claims 1-9.

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