Semiconductor structure with metal bonding interface and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure, a memory device and a manufacturing method thereof. The method includes providing a first structure including a first substrate and a wiring layer over the first substrate. The method includes providing a second structure including a second substrate. The method includes forming a first metal bonding layer on the first structure, and forming a second metal bonding layer on the first surface of the second substrate. The method includes bonding the first metal bonding layer and the second metal bonding layer to form a bonded metal layer.

Description

[0001] Background of the invention

[0002] Related applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 63 / 517,113, filed August 1, 2023, entitled “Semiconductor Structure Having Metal-Metal Bonds and Method of Manufacturing Thereof,” the entire contents of which are incorporated herein by reference.

[0004] Field of invention

[0005] This disclosure relates to semiconductor structures, memory devices, and methods of manufacturing the same. Specifically, some embodiments of this disclosure relate to semiconductor structures having vertical devices in contact with contact structures, memory devices using the vertical devices as selectors, and methods of manufacturing the same.

[0006] Description of related technologies

[0007] The semiconductor industry has a continuous need to increase the integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. This increase in integration density stems from the iterative reduction of the minimum feature size, allowing more components to be integrated into a given chip area. However, photolithography processes have physical limitations. On the other hand, as the size of semiconductor devices shrinks and integration density increases, the spacing between these devices also decreases. The spacing between devices is critical to their performance; when the spacing is too small, these devices may interfere with each other. Therefore, trade-offs must be made to balance feature size and device spacing, and it may be necessary to optimize the performance of each individual device.

[0008] As the lateral dimensions of semiconductor devices shrink with each generation of technology, further increasing integration density faces bottlenecks. One solution is to integrate devices through vertical stacking and interconnects. One approach to this is to form vertical electrical interconnects between stacked wafers using a wafer-to-wafer bonding process. Specifically, a first metal contact in a first wafer is aligned with a corresponding second metal contact in a second wafer, and then subsequent wafer-to-wafer bonding is performed to bond the first and second wafers. However, when the feature size of the metal contacts is small, alignment misalignment issues can occur during wafer-to-wafer bonding, and electrical interconnects between stacked wafers may fail. Further improvements to manufacturing processes are needed to achieve higher integration density and better device performance. Summary of the Invention

[0009] According to this disclosure, a method for manufacturing a semiconductor structure is provided. The method includes providing a first structure, the first structure including a first substrate and a wiring layer located above the first substrate (step (a)). The method includes providing a second structure, the second structure including a second substrate (step (b)). The method includes forming a first metal bonding layer on the first structure and forming a second metal bonding layer on a first surface of the second substrate (step (c)). The method includes bonding the first metal bonding layer and the second metal bonding layer to form a bonding metal layer (step (d)). The method includes removing a portion of the second structure and forming a second surface of the second substrate (step (e)). The method includes patterning the second substrate to form a plurality of vertical devices (step (f)). The method includes patterning the bonding metal layer to form a plurality of contact structures for the plurality of vertical devices (step (g)).

[0010] According to this disclosure, a semiconductor structure is provided. The semiconductor structure includes a wiring layer, a first contact structure, a second contact structure, a first vertical device, a second vertical device, and a second dielectric layer. The wiring layer is located within the first dielectric layer. The first contact structure lands on the wiring layer. The second contact structure lands on the wiring layer. The first vertical device is located above and in contact with the first contact structure. The second vertical device is located above and in contact with the second contact structure. The first vertical device and the second vertical device are located at the same horizontal level. The second dielectric layer is located above the first dielectric layer. The second dielectric layer surrounds each of the first vertical device, the second vertical device, the first contact structure, and the second contact structure. Each of the first contact structure and the second contact structure includes a first metal layer, a second metal layer located above the first metal layer, and a metal bonding interface located between the first metal layer and the second metal layer.

[0011] According to this disclosure, a memory device is provided. The memory device includes a first wiring layer, a first contact structure, a first vertical device, a first memory cell, and a second wiring layer. The first wiring layer is located above a first substrate and electrically connected to functional devices in the first substrate. The first contact structure is landed on the first wiring layer. The first contact structure includes a first metal layer and a second metal layer located above and directly bonded to the first metal layer. The first vertical device is located above the first contact structure and contacts the first contact structure at a first end. The first memory cell is located above the first vertical device and has a first end and a second end. The first vertical device is electrically connected from the second end of the first vertical device to the second end of the first memory cell. The second wiring layer is electrically connected to the first end of the first memory cell. The first metal layer contacts the first wiring layer, and the second metal layer contacts the first vertical device.

[0012] Through the technical solution described in this disclosure, multiple vertical devices (e.g.) Figure 1H , 2E The vertical PN diodes 54a, 55a, 56a and / or 57a shown in 3E, 4F, 5G, 12E, 13E and 14 Figure 6F and 7 The vertical Schottky diodes 54b and / or 55b shown are as follows Figure 8F , 9 The vertical transistors 54c, 54d, 55c and / or 55d shown in figures 10 and 11, the metal contact structures (e.g., metal contact structures 40a, 40b, 40c and / or 40d shown in the figures above), and the wiring layer (e.g., wiring layer 31 shown in the figures above) can be easily aligned, and the metal bonding interfaces therein may have ideal characteristics, which allows for better electrical connection between the vertical devices and the wiring layer through the corresponding metal contact structures. The conductive characteristics in the wiring layer can be linear (e.g., Figure 1F The first wiring layer 31 shown) or island-shaped (e.g.) Figure 5E The first wiring layer 31 shown here depends on the circuit design.

[0013] By employing the technical solution described in this disclosure, multiple metal contact structures can be formed from unpatterned bonding metal layers according to alignment marks, thus avoiding the alignment misalignment problem of wafer-to-wafer bonding. In some embodiments, each metal contact structure can be formed by patterning a bonding metal layer, which is formed by bonding a first metal bonding layer and a second metal bonding layer. Therefore, the second metal layer of the contact structure can be directly bonded to the corresponding first metal layer of the same contact structure, thereby forming a metal bonding interface between the first metal layer and the second metal layer.

[0014] Through the present disclosure described herein, even at small feature sizes, the metal bonding layer (e.g.) can be ensured. Figure 1B , 2B The connection between the metal bonding layers 41 and / or 42 shown in 3B, 4B, 5B, 6B and 8B can avoid alignment misalignment problems in wafer-to-wafer bonding. For example, refer to Figure 1C , 2C Materials such as 3C, 4C, 5C, 6C, 8C, and 13D, when both the first metal bonding layer 41 and the second metal bonding layer 42 are unpatterned metal layers, can form metal bonds with ideal bond strength, and these bonds can be "self-aligned". In some embodiments, at least one of the first and second metal bonding layers can be patterned. This also avoids thermal mismatch at the metal-dielectric interface, which can reduce the bond strength and reliability.

[0015] Through the present disclosure described herein, multiple storage units (e.g.) Figure 1H , 2E The memory cells 100a and / or 100b shown in 3E, 4F, 5G, 6F and 7 may include phase change materials or variable resistance materials, and Figure 8F , 9 The memory cells 100a and / or 100b shown in 12E, 13E, and 14 may include a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material, and are formed together with multiple vertical devices, metal contact structures, and wiring layers as described above, and collectively function as a memory device (e.g., Figure 1H , 2E Phase-change random access memory (PCRAM) devices or resistive random access memory (RRAM) devices shown in 3E, 4F, 5G, 6F, 7, 8F and 9 Figure 8F , 9 The spin-transfer torque magnetic random access memory (STT-MRAM) devices shown in 12E and 14, and Figure 13E The spin-orbit torque magnetic random access memory (SOT-MRAM) device shown is illustrated. In some embodiments, the semiconductor structure can be used as a storage device without additional storage cells (e.g., Figure 10 The ring-gate transistor non-volatile memory device shown is... Figure 11 The zero-capacitance random access memory (ZRAM) device shown.

[0016] As described herein, the second structure to be bonded may include a second substrate having a hydrogen-implanted layer (e.g., Figure 1AThe second structure 100B shown) or a second substrate having an embedded etch stop layer (e.g., Figure 3A The second structure 300B shown is illustrated. In some embodiments, a silicon-on-insulator (SOI) substrate (e.g., Figure 2A The second structure 200B shown) or silicon-on-insulator etch-stop layer (SEOI) substrate (e.g.) Figure 4A The second structure 400B shown is used to replace the hydrogen-implanted layer to mitigate the problem of large amounts of particles and contamination generated during the removal of a portion of the second structure, and can provide additional options for the fabrication of vertical devices. Attached Figure Description

[0017] Figures 1A to 1I This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0018] Figures 2A to 2E This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0019] Figures 3A to 3E This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0020] Figures 4A to 4F This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0021] Figures 5A to 5H This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0022] Figures 6A to 6F This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0023] Figure 7 This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0024] Figures 8A to 8F This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0025] Figure 9 This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0026] Figure 10 This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0027] Figure 11This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0028] Figures 12A to 12E This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0029] Figures 13A to 13E This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0030] Figure 14 This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure.

[0031] Figures 15A to 15B This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0032] The terminology used in the following description is intended to be interpreted in its broadest and most reasonable manner, even when used in conjunction with a detailed description of certain specific embodiments of the technology. Certain terms may be emphasized below; however, any term intended to be interpreted in any limiting manner will be clearly defined in this detailed description section. Components and implementations of semiconductor structures or memory devices according to this disclosure can be illustrated in the following figures and embodiments. However, the dimensions and shapes of the semiconductor structures or memory devices shown in the figures do not limit the features of this disclosure.

[0033] The term "on" as used herein can mean directly on or indirectly on, with an intervening element or layer present. Spatially relative terms, such as "below," "below," "lower than," "above," etc., are used herein for ease of description to describe the relationship of one element or feature to another element or feature shown in the accompanying drawings. Spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as "below" or "below" of another element or feature will subsequently be oriented "above" the other element or feature. Thus, the exemplary term "below" can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0034] Figures 1A to 1I This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Figure 1AAs shown, a first structure 100A (step (a)) is provided. The first structure 100A includes a first substrate 10 and a first wiring layer 31. The first substrate 10 may include a semiconductor material layer. In some embodiments, the first substrate 10 may include a single-crystal semiconductor material, such as silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In some embodiments, the first substrate 10 may include glass, polycrystalline silicon, or ceramic. The first substrate 10 may include semiconductor devices, including but not limited to transistors or diodes. In some embodiments, the first substrate 10 may include functional devices (e.g., Figure 1G The functional device 11 shown is shown. A first wiring layer 31 may be located above the first substrate 10. The first wiring layer 31 may include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), other suitable materials, or combinations thereof. The first wiring layer 31 may be fabricated by any suitable process (e.g., photolithography and etching, damascus process, double damascus process, etc.). For example, the first wiring layer 31 may be formed in the first dielectric layer 21 located on the first substrate 10 using a damascus process, a double damascus process, or any suitable method. In some embodiments, the first wiring layer 31 may include multiple conductive lines (e.g., a first word line WL1 and a second word line WL2). In some embodiments, the first structure 100A may further include an alignment mark 90 located on the first substrate 10. The alignment mark 90 may be manufactured by any suitable method. The fabrication of semiconductor devices in the first wiring layer 31 and the first substrate 10, as well as the subsequent fabrication of semiconductor devices and / or conductive features in and / or above the second substrate 50, may be performed according to the alignment mark 90 (see below). Figure 1E (For a more detailed description). In some embodiments, alignment marks 90 may include multiple mark layers. For the sake of brevity, the accompanying drawings show only a portion of the alignment marks.

[0035] like Figure 1AAs shown, a second structure 100B is provided (step (b)). The second structure 100B includes a second substrate 50. The second substrate 50 may include a semiconductor material layer. In some embodiments, the second substrate 50 may include a single-crystal semiconductor material, such as silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In some embodiments, the second substrate 50 includes a first semiconductor material layer 51 and a second semiconductor material layer 52. The second semiconductor material layer 52 may be located on the first semiconductor material layer 51. In some embodiments, the first semiconductor material layer 51 may be doped with a first type of dopant. For example, p-type dopant, such as boron, aluminum, gallium, indium, etc., or combinations thereof, or n-type dopant, such as phosphorus, arsenic, antimony, bismuth, etc., or combinations thereof. In some embodiments, the second semiconductor material layer 52 may be doped with a second type of dopant, different from the first type. For example, the p-type dopant or n-type dopant described above. In some embodiments, the doping concentration of the first semiconductor material layer 51 and / or the second semiconductor material layer 52 may be about 1.0 × 10⁻⁶. atoms / cm³ to approximately 5.0 × 10⁻⁶ Within the range of atoms / cm³. In one embodiment, the thickness of the second substrate 50 can be in the range of about 100 nm to about 1 mm. These values ​​are merely examples and are not intended to be limiting.

[0036] like Figure 1A As shown, the first semiconductor material layer 51 may further include a first heavily doped layer 46. In one embodiment, the first heavily doped layer 46 may be formed by ion implantation or epitaxial growth. In some embodiments, the first heavily doped layer 46 may be doped with the same first type of dopant as the first semiconductor material layer 51 described above. In some embodiments, the first heavily doped layer 46 may have a higher doping concentration than the first semiconductor material layer 51. In some embodiments, the doping concentration of the first heavily doped layer 46 may be approximately 1.0 × 10⁻⁶. Atoms / cm³ to approximately 3.0 × 10⁻⁶ Within the range of atoms / cm³. In one embodiment, the thickness of the first heavily doped layer 46 can range from about 5 nm to about 100 nm. These values ​​are merely examples and are not intended to be limiting.

[0037] like Figure 1AAs shown, the second semiconductor material layer 52 may further include a second heavily doped layer 47 extending from the first surface 50a of the second substrate 50. In one embodiment, the second heavily doped layer 47 may be formed by ion implantation or epitaxial growth. In some embodiments, the second heavily doped layer 47 may be doped with the same second type of dopant as the second semiconductor material layer 52 described above. In some embodiments, the second heavily doped layer 47 may have a higher doping concentration than the second semiconductor material layer 52. In some embodiments, the doping concentration of the second heavily doped layer 47 may be approximately 1.0 × 10⁻⁶. Atoms / cm³ to approximately 3.0 × 10⁻⁶ Within the range of atoms / cm³. In one embodiment, the thickness of the second doped layer 47 can range from about 5 nm to about 100 nm. These values ​​are merely examples and are not intended to be limiting.

[0038] exist Figure 1A In the illustrated embodiment, the second substrate 50 further includes a hydrogen implantation layer 58 located within the second substrate 50. The hydrogen implantation layer 58 is implanted to a specific depth within the second substrate 50 before the bonding of the first structure 100A and the second structure 100B. Implantation can be performed before or after the formation of the first semiconductor material layer 51 and / or the second semiconductor material layer 52, as long as the hydrogen implantation layer 58 is not damaged by subsequent processes. For example, if the formation of the first semiconductor material layer 51 and / or the second semiconductor material layer 52 requires high temperatures (e.g., annealing processes), hydrogen implantation may need to be performed after the formation of the first semiconductor material layer 51 and / or the second semiconductor material layer 52. In some embodiments, a metal layer (e.g., hereinafter) can be formed. Figure 1B Implantation is performed before the second metal bonding layer 42 described herein. In one embodiment, 1×10⁻⁶ is used. ions / cm² up to 2×10 A dose of ions / cm² and an implantation energy of 50 keV to 150 keV are used to implant hydrogen ions into the second substrate 50. For larger substrates, a higher dose can be used. A hydrogen implantation layer 58 can be formed approximately 4 × 10¹⁴ kiloelectron volts (keV) from the first surface 50a of the second substrate 50. inch to 8×1 At a depth of inches (1 to 2 micrometers). These values ​​are merely examples and are not intended to be limiting. In one embodiment, since the thicknesses of the first semiconductor material layer 51 and the second semiconductor material layer 52 are known, an appropriate injection voltage can be selected such that the peak of injected hydrogen occurs at a desired depth below the first surface 50a.

[0039] like Figure 1BAs shown, before bonding the first structure 100A and the second structure 100B, a first metal bonding layer 41 is formed on the first structure 100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). In some embodiments, the first metal bonding layer 41 may be formed to contact the wiring layer 31. In some embodiments, the second metal bonding layer 42 may be formed to contact the first surface 50a of the second substrate 50. In some embodiments, the second metal bonding layer 42 may be formed to contact the second semiconductor material layer 52. In some embodiments, the second metal bonding layer 42 may be formed to contact the second heavily doped layer 47 of the second semiconductor material layer 52. In some embodiments, the second heavily doped layer 47 is formed before the second metal bonding layer 42 is formed. In some embodiments, each of the first metal bonding layer 41 and the second metal bonding layer 42 may include a suitable metal, a conductive metal compound (e.g., a metal silicide, a metal nitride), or a metal alloy, such as aluminum (Al), gold (Au), indium (In), palladium (Pd), germanium (Ge), copper (Cu), aluminum-silicon alloy (Al-Si), titanium nitride (TiN), nickel (Ni) silicide, cobalt (Co) silicide, tungsten (W) silicide, chromium (Cr) silicide, platinum (Pt) silicide, titanium (Ti) silicide, molybdenum (Mo) silicide, palladium (Pd) silicide, lead-tin alloy (Pb-Sn), aluminum-tin alloy (Al-Sn), gold-tin alloy (Au-Sn), indium-palladium alloy (In-Pd), indium-tin alloy (In-Sn), silver-tin alloy (Ag-Sn), gold-indium alloy (Au-In), copper-tin alloy (Cu-Sn), or combinations thereof. In one embodiment, the thickness of each of the first metal bonding layer 41 and the second metal bonding layer 42 may be in the range of about 5 nm to about 500 nm. These values ​​are merely examples and are not intended to be limiting. In some embodiments, the first metal bonding layer 41 and / or the second metal bonding layer 42 may be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the first metal bonding layer 41 and / or the second metal bonding layer 42 may be formed by sputtering, evaporation, or electroplating.

[0040] In some embodiments, the first metal bonding layer 41 and the second metal bonding layer 42 may have the same composition; however, in some other embodiments, the first metal bonding layer 41 and the second metal bonding layer 42 may have different compositions, as long as subsequent bonding processes can be performed between the first metal bonding layer 41 and the second metal bonding layer 42. In some embodiments, each of the first metal bonding layer 41 and the second metal bonding layer 42 may have a multilayer structure. The composition and structure of the first metal bonding layer 41 and the second metal bonding layer 42 can be adjusted according to the desired bonding strength and / or device characteristics.

[0041] like Figure 1C As shown, a first metal bonding layer 41 and a second metal bonding layer 42 are bonded to form a bonded metal layer 40 (step (d)). The second structure 100B is flipped and bonded to the first structure 100A through the bonded metal layer 40 to form a bonded structure 100C. The first metal bonding layer 41 and the second metal bonding layer 42 can be bonded by hot-press bonding, eutectic bonding, or reactive bonding. In some embodiments, the bonding of the first metal bonding layer 41 and the second metal bonding layer 42 can be direct bonding. For example, the first metal bonding layer 41 and the second metal bonding layer 42 can be bonded by a hot-press bonding process (such as diffusion bonding). In one embodiment, both the first metal bonding layer 41 and the second metal bonding layer 42 are cleaned by conventional cleaning techniques (such as dry etching and plasma surface treatment). The cleaning process removes surface impurities and particles from the surfaces of the metal bonding layers 41 and 42. In one embodiment, during a thermal process, external pressure is applied to the stacked first structure 100A, first metal bonding layer 41, second metal bonding layer 42, and second structure 100B. In some embodiments, atoms on the surfaces of the first metal bonding layer 41 and the second metal bonding layer 42 can diffuse into each other, allowing metal bonds to form at the metal bonding interface 43, thereby forming a bonded metal layer 40. In one embodiment, the thickness of the bonded metal layer 40 can be in the range of 5 nm to 1000 nm. These values ​​are merely examples and are not intended to be limiting.

[0042] In some embodiments, the first metal bonding layer 41 and / or the second metal bonding layer 42 may comprise a stack of conductive sublayers comprising the aforementioned metal, conductive metal compound, or metal alloy. In some embodiments, the first metal bonding layer 41 may be electrically coupled to a semiconductor device formed in the first substrate 10. In some embodiments, the first metal bonding layer 41 and / or the second metal bonding layer 42 may comprise a diffusion barrier layer (not shown), which may comprise titanium, tungsten, tantalum, and their nitrides. The diffusion barrier layer may contact the second substrate 50 to prevent metal from diffusing from the metal bonding layer into the second substrate 50.

[0043] At least one of the first metal bonding layer 41 and the second metal bonding layer is an unpatterned metal layer. In this document, an unpatterned layer refers to a material layer that extends continuously from at least one point to another in a given region and will be separated in a subsequent patterning process by removing a portion of that material layer. Figure 1CIn the illustrated embodiment, both the first metal bonding layer 41 and the second metal bonding layer 42 are unpatterned metal layers, such that the metal bonding interface 43 between the first metal bonding layer 41 and the second metal bonding layer 42 extends continuously from the point overlapping with the first word line WL1 to the point overlapping with the second word line WL2, and there is no metal-dielectric interface in between. However, in some other embodiments, one of the first metal bonding layer and the second metal bonding layer may be patterned. The process described herein ensures connectivity between metal bonding layers even at small feature sizes and avoids alignment misalignment issues in wafer-to-wafer bonding. With both the first metal bonding layer 41 and the second metal bonding layer 42 being unpatterned metal layers, metal bonds with ideal bonding strength can be formed, and these bonds can be “self-aligned.” This also avoids thermal mismatch at the metal-dielectric interface, which reduces the bonding strength and reliability of the bond. Furthermore, since the coefficient of thermal expansion (CTE) of the first wiring layer 31 is greater than that of the first dielectric layer 21, when the first metal bonding layer 41 and the second metal bonding layer 42 are bonded, the portion abutting the metal feature of the first wiring layer 31 may withstand relatively greater pressure than the portion abutting the dielectric material of the first dielectric layer 21. This can result in greater bonding strength in the portion above the metal feature of the first wiring layer 31. Therefore, the portion of the bonding metal layer 40 retained after subsequent patterning processes can include a metal bonding interface with greater bonding strength.

[0044] like Figure 1D As shown, a portion of the second structure 100B is removed, and the second surface 50b of the second substrate 50 is formed (step (e)). In Figure 1D In the illustrated embodiment, a portion of the second substrate 50 is removed from approximately the hydrogen-implanted layer 58. This portion of the second substrate 50 can be removed by heating the bonding structure 100C at a first temperature. The first temperature is typically below 400°C to avoid damaging the semiconductor devices (if any) fabricated in the first structure 100A and / or the second structure 100B. In some embodiments, this portion of the second substrate 50 can be removed by other methods, provided that this portion of the second substrate 50 has been sufficiently weakened by the previous hydrogen implantation and some subsequent annealing. For example, the bonding structure 100C can be cleaved by applying mechanical pressure to the second substrate 50 or by immersing the bonding structure 100C in liquid nitrogen and quenching it.

[0045] The portion of the second substrate 50 remaining on the bonding structure 100C can be based on an implantation depth of less than 3 μm for the hydrogen implantation layer 58. The thickness of the remaining portion of the second substrate 50 can also depend on the semiconductor manufacturing technology node applied to various semiconductor device fabrications. After removal, a second surface 50b of the second substrate 50 is formed. The second surface 50b of the second substrate 50 typically has a roughness on the order of several hundred angstroms. The second surface 50b of the second substrate 50 can be polished by chemical mechanical polishing (CMP) to planarize and minimize non-uniformity. Other methods such as etching can be used to achieve the same purpose. When using etching to planarize and minimize the non-uniformity of the second surface 50b of the second substrate 50, it may be necessary to pre-deposit an etch stop layer (not shown).

[0046] exist Figure 1D In the illustrated embodiment, the first heavily doped layer 46 is exposed after a portion of the second structure 100B (e.g., a portion of the second substrate 50) is removed. In some other embodiments, the first heavily doped layer 46 extending from the second surface 50b of the second substrate 50 can be formed (step (j2)) after a portion of the second structure 100B is removed and the second surface 50b of the second substrate 50 is formed (step (e)). In this case, the layer can be similar to the one described above. Figure 1A Similar materials and methods are described to form the first doped layer 46.

[0047] like Figure 1E As shown, the second substrate 50 is patterned to form a plurality of vertical devices including a first vertical device 54a and a second vertical device 55a (step (f)). Figure 1E In the illustrated embodiment, each of the first vertical device 54a and the second vertical device 55a is a vertical PN diode. This disclosure is not limited thereto. In some embodiments, patterning the second substrate 50 to form a plurality of vertical devices (step (f)) may be performed after bonding the first metal bonding layer 41 and the second metal bonding layer 42 (step (d)). The second substrate 50 may be patterned by any suitable process, such as photolithography and etching. In some embodiments, the patterning process of the second substrate 50 may be performed according to the alignment mark 90 of the first structure 100A. In some embodiments, the bonding metal layer 40 may be used as an etch stop layer in the etching process for patterning the second substrate 50.

[0048] like Figure 1EAs shown, the bonding metal layer 40 is patterned to form a plurality of contact structures, including a first contact structure 40a and a second contact structure 40b, for the first vertical device 54a and the second vertical device 55a (step (g)). In some embodiments, the patterning of the bonding metal layer 40 to form a plurality of contact structures (step (g)) may be performed after bonding the first metal bonding layer 41 and the second metal bonding layer 42 (step (d)). The bonding metal layer 40 can be patterned by any suitable process, such as photolithography and etching processes. For example, the bonding metal layer 40 can be patterned using dry etching processes, such as reactive ion etching and inductively coupled plasma etching. In one embodiment, when the bonding metal layer 40 comprises aluminum (e.g., an aluminum alloy), boron trichloride (BC) can be used. ), chlorine (C ) and ammonia (N A mixture of gases is used as the etching gas to pattern the bonding metal layer 40 by dry etching. In some embodiments, when the bonding metal layer 40 comprises titanium nitride (TiN), carbon tetrafluoride (C4F) can be used. Boron trichloride (BC) ) and nitrogen ( A mixture of gases, or argon (Ar) and chlorine (C). The bonding metal layer 40 is patterned by dry etching using a mixture of gases as etching gases. This disclosure is not limited thereto. In some embodiments, the patterning process of the bonding metal layer 40 can be performed according to the alignment mark 90 of the first structure 100A. In some embodiments, the first dielectric layer 21 can be used as an etch stop layer in the etching process for patterning the bonding metal layer 40.

[0049] Figure 1F yes Figure 1E A schematic top view of the semiconductor structure shown, and Figure 1G yes Figure 1E Another cross-sectional view of the semiconductor structure is shown. Specifically, Figure 1E It is along Figure 1F A cross-sectional view of the semiconductor structure along line A-A', and Figure 1G It is along Figure 1F A cross-sectional view of the semiconductor structure along line B-B'. (See diagram below.) Figures 1E to 1G As shown, a trench 59 passing through the second substrate 50 and the bonding metal layer 40 can be formed through one or more of the above-described etching processes, thereby separating the first vertical device 54a from the second vertical device 55a, and separating the first contact structure 40a from the second contact structure 40b. Figures 1E to 1G As shown, the vertical stacking of the first contact structure 40a and the first vertical device 54a is island-shaped, and the vertical stacking of the second contact structure 40b and the second vertical device 55a is also island-shaped. Figure 1GAs shown, a third vertical device 55a' similar to the second vertical device 55a and a third contact structure 40b' similar to the second contact structure 40b can also be formed. Figures 1E to 1G As shown, the first substrate 10 may include functional devices 11, and the first wiring layer 31 is electrically connected to the functional devices 11. In some embodiments, the functional devices 11 may be peripheral devices, such as control devices, word line select devices, and bit line select devices. The first substrate 10 may include a plurality of functional devices 11. In some embodiments, the first substrate 10 may include a device layer or a device stack including a plurality of functional devices 11, wherein the device layer or the device stack may include a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), or the like. In some embodiments, the first wiring layer 31 is electrically connected to the functional devices 11 through a first interconnect structure 35. The first interconnect structure 35 may include titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, some other suitable material or a combination thereof, and may be formed in the first dielectric layer 21 using a damask process or a double damask process or any suitable method prior to the formation of the first metal bonding layer 41.

[0050] The methods disclosed herein enable the formation of vertical devices comprising single-crystal semiconductor materials, thus allowing for superior performance compared to vertical devices made from polycrystalline and / or amorphous semiconductor materials. Furthermore, in some embodiments, the semiconductor material layer can be annealed prior to the formation of the metal contact layer, avoiding high-temperature processes in subsequent stages. Moreover, as discussed above, the methods disclosed herein facilitate the easy alignment of multiple vertical devices, metal contact structures, and wiring layers, and the metal bonding interfaces may possess desirable characteristics, enabling better electrical connections between the vertical devices and wiring layers through appropriate metal contact structures. Specifically, since multiple metal contact structures can be formed from unpatterned bonding metal layers based on alignment marks, wafer-to-wafer bonding alignment misalignment issues are avoided.

[0051] like Figure 1H and Figure 1IAs shown, after patterning the bonding metal layer 40 (step (g)), a second dielectric layer 22 is formed (step (h)). The second dielectric layer 22 may surround the vertical devices 54a and 55a and the contact structures 40a and 40b. The second dielectric layer 22 may include one or more stacked dielectric layers. The second dielectric layer 22 may include dielectric materials such as silicon oxide, silicon oxynitride, low dielectric constant (low k) materials, combinations thereof, and / or other suitable materials, and may be formed by deposition (such as CVD, PVD, or ALD), spin coating, or any suitable method. The second dielectric layer 22 may fill trenches 59 such that the first vertical device 54a and the second vertical device 55a are laterally isolated by the second dielectric layer 22, and the first contact structure 40a and the second contact structure 40b are laterally isolated by the second dielectric layer 22.

[0052] In some embodiments, a conformal diffusion barrier layer (not shown) may be formed around the vertical device and contact structure prior to the formation of the second dielectric layer 22. The conformal diffusion barrier layer may include titanium, tungsten, tantalum, and their nitrides. (Due to the above...) Figures 1A to 1G In the discussed "self-aligned" process, the sidewalls of the first vertical device 54a and the first contact structure 40a can be vertically aligned without alignment deviation, and the sidewalls of the second vertical device 55a and the second contact structure 40b can also be vertically aligned without alignment deviation. Therefore, a conformal diffusion barrier layer can be formed on the sidewalls of the vertical devices and the contact structures, such that the conformal diffusion barrier layer can be substantially flat on the sidewalls of the vertical devices and the contact structures.

[0053] like Figure 1H and Figure 1IAs shown, a first memory cell 100a and a second memory cell 100b are formed above vertical devices 54a and 55a (step (i)). The first memory cell 100a is formed above the first vertical device 54a, and the second memory cell 100b is formed above the second vertical device 55a. The first memory cell 100a may have a first end 101a and a second end 102a. In some embodiments, the first memory cell 100a extends from the first end 101a to the second end 102a. The second memory cell 100b may have a first end 101b and a second end 102b. In some embodiments, the second memory cell 100b extends from the first end 101b to the second end 102b. Each of the first memory cell 100a and the second memory cell 100b may include a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material. In some embodiments, the first memory cell 100a and the second memory cell 100b can be formed by using suitable materials and processes, such as deposition, photolithography, and etching techniques. For example, they can be formed by deposition or by methods similar to those described above. Figures 1A to 1C The described metal bonding process forms a stack of memory material layers on the first vertical device 54a and the second vertical device 55a, and the stack of memory material layers can be defined to form a plurality of memory cells. The formation of the first memory cell 100a and the second memory cell 100b can be performed according to alignment marks 90 located on the first substrate 10. Figure 1I As shown, a third storage cell 100b', similar to the second storage cell 100b, can be formed above the third vertical device 55a'. The third storage cell 100b' may have a first end 101b' and a second end 102b'. In some embodiments, the third storage cell 100b' extends from the first end 101b' of the third storage cell 100b' to the second end 102b' of the third storage cell 100b'.

[0054] exist Figure 1H and Figure 1I In the illustrated embodiment, memory cells 100a and 100b are formed after the second substrate 50 is patterned. However, in some other embodiments, memory cells can be formed by defining a stack of memory material layers on the second substrate 50 before patterning the second substrate 50, wherein the stack of memory material layers can be formed on the second substrate 50 by deposition or any suitable method, or by a method similar to the one described above. Figures 1A to 1C The described metal bonding process bonds the stacked storage material layers to the second substrate 50.

[0055] like Figure 1H and Figure 1IAs shown, a second wiring layer 32 is formed above the first memory cell 100a and the second memory cell 100b. The second wiring layer 32 may include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), other suitable materials, or combinations thereof. The second wiring layer 32 can be fabricated using any suitable process (e.g., photolithography and etching, damascus etching, double damascus etching, etc.). For example, the second wiring layer 32 can be formed in the second dielectric layer 22 using a damascus etching process, a double damascus etching process, or any suitable method.

[0056] refer to Figure 1H and Figure 1I A semiconductor structure 110 is provided, comprising a first wiring layer 31, a first contact structure 40a, a second contact structure 40b, a first vertical device 54a, a second vertical device 55a, and a second dielectric layer 22. The first wiring layer 31 is located above a first substrate 10. In some embodiments, the first wiring layer 31 is located within the first dielectric layer 21. In some embodiments, the first wiring layer 31 is electrically connected to a functional device 11. In some embodiments, the functional device 11 is located within the first substrate 10.

[0057] In some embodiments, both the first contact structure 40a and the second contact structure 40b land on the first wiring layer 31. Specifically, the first wiring layer 31 may include conductive features such as vias and wires. Figure 1H and Figure 1I In the illustrated embodiment, the first contact structure 40a and the second contact structure 40b land on the first word line WL1 and the second word line WL2, respectively. In another embodiment, the first contact structure 40a and the second contact structure 40b may land on corresponding vias or conductors of the first wiring layer 31, respectively. The first contact structure 40a includes a first metal layer 41a, a second metal layer 42a, and a metal bonding interface 43a, wherein the second metal layer 42a is located above the first metal layer 41a, and the metal bonding interface 43a is located between the first metal layer 41a and the second metal layer 42a. The second contact structure 40b includes a first metal layer 41b, a second metal layer 42b, and a metal bonding interface 43b, wherein the second metal layer 42b is located above the first metal layer 41b, and the metal bonding interface 43b is located between the first metal layer 41b and the second metal layer 42b.

[0058] In some embodiments, each of the first contact structure 40a and the second contact structure 40b can be formed by patterning a bonding metal layer 40, the bonding metal layer 40 being bonded to the aforementioned reference. Figures 1C to 1EThe first metal bonding layer 41 and the second metal bonding layer 42 are formed. Therefore, the second metal layer 42a of the first contact structure 40a can be directly bonded to the first metal layer 41a of the first contact structure 40a, such that a metal bonding interface 43a is formed between the first metal layer 41a and the second metal layer 42a; and the second metal layer 42b of the second contact structure 40b can be directly bonded to the first metal layer 41b of the second contact structure 40b, such that a metal bonding interface 43b is formed between the first metal layer 41b and the second metal layer 42b. As discussed above, each of the first metal layers 41a and 41b and the second metal layers 42a and 42b may include a multilayer structure. However, this disclosure is not limited thereto. The first metal layer 41a of the first contact structure 40a can contact the first wiring layer 31, and the second metal layer 42a of the first contact structure 40a can contact the first vertical device 54a. The first metal layer 41b of the second contact structure 40b can contact the first wiring layer 31, and the second metal layer 42b of the second contact structure 40b can contact the second vertical device 55a. In this way, the first vertical device 54a and the second vertical device 55a can be electrically connected to the first wiring layer 31 through the first contact structure 40a and the second contact structure 40b, respectively.

[0059] like Figure 1H and Figure 1I As shown, in some embodiments, the width W1 of the first metal layer 41a of the first contact structure 40a is substantially equal to the width W2 of the second metal layer 42a of the first contact structure 40a, and the width W1' of the first metal layer 41b of the second contact structure 40b is substantially equal to the width W2' of the second metal layer 42b of the second contact structure 40b. In some embodiments, the metal bonding interface 43a of the first contact structure 40a and the metal bonding interface 43b of the second contact structure 40b are substantially flush. In some embodiments, due to the above regarding Figures 1A to 1G In the discussed "self-aligned" process, the first metal layer 41a and the second metal layer 42a of the first contact structure 40a can be vertically aligned without alignment deviation, and the first metal layer 41b and the second metal layer 42b of the second contact structure 40b can also be vertically aligned without alignment deviation. Figure 1H and Figure 1I As shown, the sidewalls of the first metal layer 41a and the second metal layer 42a of the first contact structure 40a can be substantially aligned, and the sidewalls of the first metal layer 41b and the second metal layer 42b of the second contact structure 40b can be substantially aligned. This can reduce the overall width of the first contact structure 40a and the second contact structure 40b, and thus reduce the size of the memory cell made from the semiconductor structure disclosed herein. However, this disclosure is not limited thereto.

[0060] like Figure 1H and Figure 1I As shown, a first vertical device 54a extends from a first end 54g to a second end 54h, wherein the first vertical device 54a is located above and in contact with the first contact structure 40a. In some embodiments, the first vertical device 54a contacts the first contact structure 40a at its first end 54g. In some embodiments, the height H1 of the first vertical device 54a (e.g., the height between the first end 54g and the second end 54h) can be in the range of about 10 nm to about 300 nm. In some embodiments, the width W3 of the first vertical device 54a is substantially equal to the width W2 of the second metal layer 42a of the first contact structure 40a. A second vertical device 55a extends from a first end 55g to a second end 55h, wherein the second vertical device 55a is located above and in contact with the second contact structure 40b. In some embodiments, the second vertical device 55a contacts the second contact structure 40b at its first end 55g. In some embodiments, the width W3' of the second vertical device 55a is substantially equal to the width W2' of the second metal layer 42b of the second contact structure 40b. In some embodiments, the first vertical device 54a and the second vertical device 55a are located at the same horizontal position. In other words, the top end (e.g., the second end 54h) of the first vertical device 54a may be substantially flush with the top end (e.g., the second end 55h) of the second vertical device 55a, and the bottom end (e.g., the first end 54g) of the first vertical device 54a may be substantially flush with the bottom end (e.g., the first end 55g) of the second vertical device 55a. In some embodiments, the height H1 of the first vertical device 54a is substantially equal to the height H2 of the second vertical device 55a (e.g., the height between the first end 55g and the second end 55h of the second vertical device 55a). In some embodiments, each of the first vertical device 54a and the second vertical device 55a may include a single-crystal semiconductor material, such as silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN).

[0061] For ease of description, spatially relative terms (such as “top” and “bottom”) throughout this document describe the relationship of one element or feature to another element or feature shown in the accompanying drawings. It should be understood that these terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the accompanying drawings. For example, if the device in the accompanying drawings were flipped, the feature described by “top” would subsequently be at the “bottom,” and vice versa. The structure may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0062] exist Figure 1H and Figure 1I In the illustrated embodiment, each of the first vertical device 54a and the second vertical device 55a is a vertical PN diode. This disclosure is not limited thereto. The first vertical device 54a may be arranged in the same orientation as the second vertical device 55a, such as... Figure 1H and Figure 1I As shown, the first current I1 allowed by the first vertical device 54a (e.g., from the first end 54g to the second end 54h of the first vertical device 54a) has the same direction as the second current I2 allowed by the second vertical device 55a under similar conditions (e.g., from the first end 55g to the second end 55h of the second vertical device 55a).

[0063] like Figure 1H and Figure 1I As shown, the second dielectric layer 22 may be located above the first dielectric layer 21 and surrounding each of the first vertical device 54a, the second vertical device 55a, the first contact structure 40a, and the second contact structure 40b. In some embodiments, as described above, the second dielectric layer 22 is formed by depositing dielectric material on the uppermost surface 21a of the first dielectric layer 21 surrounding the first metal layers 41a and 41b and the second metal layers 42a and 42b of the first and second contact structures 40a and 40b. Thus, the second dielectric layer 22 can extend continuously from the uppermost surface 21a of the first dielectric layer 21, without a bonding interface located between the first contact structure 40a and the second contact structure 40b and substantially at the same horizontal level as the metal bonding interface 43a of the first contact structure 40a and the metal bonding interface 43b of the second contact structure 40b. In other words, the bonding interfaces (e.g., metal bonding interface 43a) between the first metal layer 41a and the second metal layer 42a of the first contact structure 40a and the bonding interfaces (e.g., metal bonding interface 43b) between the first metal layer 41b and the second metal layer 42b of the second contact structure 40b can be laterally separated by the deposition layer of the second dielectric layer 22, in which there are no bonding interfaces (e.g., dielectric-dielectric bonding interfaces and / or metal-metal bonding interfaces).

[0064] refer to Figure 1H and Figure 1I A storage device 200 is provided. The storage device 200 includes a first wiring layer 31, a first contact structure 40a, a first vertical device 54a, a first storage cell 100a, and a second wiring layer 32. The first wiring layer 31 may include multiple word lines extending in a first direction 103a. Figure 1H and Figure 1IIn the illustrated embodiment, the multiple word lines include a first word line WL1 and a second word line WL2. The storage device 200 may further include a second contact structure 40b, wherein a first contact structure 40a may land on the first word line WL1, and a second contact structure 40b may land on the second word line WL2. In some embodiments, both the first contact structure 40a and the third contact structure 40b' (the second contact structure) land on the first word line WL1.

[0065] exist Figure 1H and Figure 1I In the illustrated embodiment, the first vertical device 54a is electrically connected from its second end 54h to the second end 102a of the first storage cell 100a. Figure 1H and Figure 1I In the illustrated embodiment, the second vertical device 55a is electrically connected from its second end 55h to the second end 102b of the second memory cell 100b. The second wiring layer 32 may be electrically connected to the first end 101a of the first memory cell 100a. The second wiring layer 32 may also be electrically connected to the first end 101b of the second memory cell 100b. The second wiring layer 32 may include multiple bit lines extending in a second direction 103b, different from the first direction 103a. Figure 1H and Figure 1I In the illustrated embodiment, the multiple bit lines include a first bit line BL1 and a second bit line BL2, and the first terminal 101a of the first memory cell 100a is electrically connected to the first bit line BL1. Figure 1I In the illustrated embodiment, the third vertical device 55a' is electrically connected to the second end 102b' of the third memory cell 100b', and the first end 101b' of the third memory cell 100b' is electrically connected to the second bit line BL2. In some embodiments, the memory device 200 further includes alignment marks 90 located on the first substrate 10. Relevant details of the features of the memory device 200 have been described above and will not be repeated here.

[0066] In the illustrated embodiment, storage device 200 includes storage cells arranged in rows and columns to form a storage array. Storage device 200 may include any suitable number of rows and columns. For example, storage device 200 includes R rows and C columns, where R is an integer greater than or equal to 1, and C is an integer greater than or equal to 2. Specifically, Figure 1H and Figure 1I The storage device 200 shown may be a resistive random access memory (RRAM) device or a phase change random access memory (PcRAM) device.

[0067] Figures 2A to 2E This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Figure 2A As shown, a first structure 100A is provided (step (a)). The first structure 100A can be connected with... Figure 1A The first structure 100A shown is substantially similar, with the same reference numerals indicating the same components. (Previous reference...) Figure 1A The manufacturing and related details of the first structure 100A described herein can be applied here.

[0068] like Figure 2A As shown, a second structure 200B is provided (step (b)). The second structure 200B can be used with... Figure 1A The second structure 100B shown is substantially similar, with the same reference numerals denoteing the same elements. The second structure 200B, including the second substrate 50, further includes a third substrate 60 and a bonding layer 70. The bonding layer 70 may be located between the second substrate 50 and the third substrate 60. In some embodiments, the bonding layer 70 may include an oxide, such as silicon oxide. In one embodiment, the third substrate 60 is a wafer with a diameter of 6, 8, 12, or 18 inches. The third substrate 60 may be a support wafer. In some embodiments, the third substrate 60 may include glass, polycrystalline silicon, or ceramic. In some other embodiments, the third substrate 60 may include a single-crystal semiconductor material, such as silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In one embodiment, the thickness of the third substrate 60 may range from 20 μm to 700 μm. These values ​​are merely examples and are not intended to be limiting. Figure 2A The second substrate 50 in the middle can be with Figure 1A The second substrate 50 is substantially similar, wherein the same reference numerals denote the same elements. (Previous reference...) Figure 1A The fabrication and related details of the second substrate 50 described herein may be applied here. In one embodiment, the second structure 200B may be fabricated by bonding a third substrate 60 and a substrate (not shown) through a bonding layer 70, removing a portion of the substrate after bonding, and retaining the second substrate 50 in the second structure 200B.

[0069] like Figure 2B As shown, before bonding the first structure 100A and the second structure 200B, a first metal bonding layer 41 is formed on the first structure 100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). (See previous reference) Figure 1B The described formation process and related details are applicable here.

[0070] like Figure 2CAs shown, a first metal bonding layer 41 and a second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 200B is flipped and bonded to the first structure 100A through the bonding metal layer 40 to form a bonding structure 200C. (See previous reference...) Figure 1C The bonding process and related details described are applicable here.

[0071] like Figure 2D As shown, a portion of the second structure 200B is removed, and the second surface 50b of the second substrate 50 is formed (step (e)). In Figure 2D In the illustrated embodiment, removing this portion of the second structure 200B includes removing the third substrate 60 and the bonding layer 70. The third substrate 60 and the bonding layer 70 can be removed by performing suitable processes such as grinding, chemical mechanical polishing (CMP), and etching. In one embodiment, the third substrate 60 is removed by grinding and / or chemical mechanical polishing (CMP) processes, and can be removed by applying a first etchant (e.g., dilute hydrofluoric acid (HF) or water). The bonding layer 70 is removed by using a mixture of O and hydrofluoric acid (HF) in a weight ratio of approximately 100:1. This disclosure is not limited thereto. Following removal and an optional polishing process, a second surface 50b of the second substrate 50 is formed.

[0072] exist Figure 2D In the illustrated embodiment, the first heavily doped layer 46 is exposed after a portion of the second structure 200B (e.g., bonding layer 70) is removed. (See previous reference...) Figure 1D The formation process and related details of the first doped layer 46 described herein can be applied here.

[0073] like Figure 2E As shown, a semiconductor structure 110 and a memory device 200 are provided. The processes for manufacturing the semiconductor structure 110 and the memory device 200 can be the same as those described above. Figures 1E to 1I The described processes are basically similar, and for the sake of brevity, relevant descriptions are omitted.

[0074] Figures 3A to 3E This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Figure 3A As shown, a first structure 100A is provided (step (a)). The first structure 100A can be connected with... Figure 1A The first structure 100A shown is substantially similar, with the same reference numerals indicating the same components. (Previous reference...) Figure 1A The manufacturing and related details of the first structure 100A described herein can be applied here.

[0075] like Figure 3A As shown, a second structure 300B is provided (step (b)). The second structure 300B can be used with... Figure 2A The second structure 200B shown is substantially similar, with the same reference numerals denoteing the same elements. The second structure 300B, including the second substrate 50, further includes a third substrate 60 and an etch stop layer 80. The etch stop layer 80 may be located between the second substrate 50 and the third substrate 60. The etch stop layer 80 may have high etch selectivity relative to the third substrate 60. In other words, under the same etch conditions, the etch rate of the third substrate 60 is significantly faster than the etch rate of the etch stop layer 80. In some embodiments, the etch stop layer 80 may include silicon nitride, silicon oxynitride, a doped semiconductor material, an undoped semiconductor material, a metal, a conductive metal compound, or a combination thereof. The doped semiconductor material may be a semiconductor material doped with the aforementioned p-type or n-type dopant. The undoped semiconductor material may be amorphous silicon, polycrystalline silicon, silicon-germanium, etc., or a combination thereof. The metal may be aluminum, gold, copper, tungsten, etc., or alloys thereof. The conductive metal compound can be a metal silicide, a metal carbide, a metal nitride, or a combination thereof, such as tungsten nitride (WN), tantalum nitride (TaN), tantalum silicide (TaSi), titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), molybdenum nitride (MoN), iridium oxide (IrOx), ruthenium oxide (RuOx), or ruthenium titanium nitride (RuTiN). Figure 3A The second substrate 50 and the third substrate 60 can be with Figure 2A The second substrate 50 and the third substrate 60 are substantially similar, with the same reference numerals denoteing the same elements. (Previous reference...) Figure 2A The fabrication and related details of the second substrate 50 and the third substrate 60 described herein are applicable here.

[0076] like Figure 3B As shown, before bonding the first structure 100A and the second structure 300B, a first metal bonding layer 41 is formed on the first structure 100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). (See previous reference) Figure 1B The described formation process and related details are applicable here.

[0077] like Figure 3C As shown, a first metal bonding layer 41 and a second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 300B is flipped and bonded to the first structure 100A through the bonding metal layer 40 to form a bonding structure 300C. (See previous reference...) Figure 1C The bonding process and related details described are applicable here.

[0078] like Figure 3DAs shown, a portion of the second structure 300B is removed, and the second surface 50b of the second substrate 50 is formed (step (e)). In Figure 3D In the illustrated embodiment, removing this portion of the second structure 300B includes removing the etch stop layer 80. The third substrate 60 and the etch stop layer 80 can be removed by performing suitable processes such as grinding, chemical mechanical polishing (CMP), and etching processes. In one embodiment, the third substrate 60 is removed by an etching process under suitable etching conditions. The etch stop layer 80 can be removed by oxide etching, plasma etching, hydrogen peroxide etching, or any suitable method. In one embodiment, the etch stop layer 80, comprising silicon nitride, can be removed by applying a second etchant (e.g., hot phosphoric acid). However, this disclosure is not limited thereto. After removing the etch stop layer 80, a second surface 50b of the second substrate 50 can be formed. The introduction of the etch stop layer 80 ensures the flatness of the formed second surface 50b of the second substrate 50, and the etch stop layer 80 can be used to monitor the etching endpoint.

[0079] exist Figure 3D In the illustrated embodiment, the first heavily doped layer 46 is exposed after a portion of the second structure 300B (e.g., etch stop layer 80) is removed. (See previous reference...) Figure 1D The formation process and related details of the first doped layer 46 described herein can be applied here.

[0080] like Figure 3E As shown, a semiconductor structure 110 and a memory device 200 are provided. The processes for manufacturing the semiconductor structure 110 and the memory device 200 can be the same as those described above. Figures 1E to 1I The described processes are basically similar, and for the sake of brevity, relevant descriptions are omitted.

[0081] Figures 4A to 4F This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Figure 4A As shown, a first structure 100A is provided (step (a)). The first structure 100A can be connected with... Figure 1A The first structure 100A shown is substantially similar, with the same reference numerals indicating the same components. (Previous reference...) Figure 1A The manufacturing and related details of the first structure 100A described herein can be applied here.

[0082] like Figure 4A As shown, a second structure 400B is provided (step (b)). The second structure 400B can be used with... Figure 3AThe second structure 300B shown is substantially similar, wherein the same reference numerals denote the same elements. The second structure 400B, including the second substrate 50, further includes a third substrate 60, a bonding layer 70, and an etch stop layer 80. The bonding layer 70 may be located between the second substrate 50 and the third substrate 60, and the etch stop layer 80 may be located between the bonding layer 70 and the second substrate 50. Figure 4A The second substrate 50, the third substrate 60, and the bonding layer 70 can be with Figure 2A The second substrate 50, third substrate 60, and bonding layer 70 are substantially similar, with the same reference numerals denoteing the same components. The etch stop layer 80 may have high etch selectivity relative to the bonding layer 70. In other words, under the same etch conditions, the etch rate of the bonding layer 70 is significantly faster than the etch rate of the etch stop layer 80. In some embodiments, the etch stop layer 80 may comprise silicon nitride, silicon oxynitride, a doped semiconductor material, an undoped semiconductor material, a metal, a conductive metal compound, or a combination thereof. The doped semiconductor material may be a semiconductor material doped with the aforementioned p-type or n-type dopants. The undoped semiconductor material may be amorphous silicon, polycrystalline silicon, silicon-germanium, or a combination thereof. The metal may be aluminum, gold, copper, tungsten, or alloys thereof. The conductive metal compound can be a metal silicide, metal carbide, metal nitride, or a combination thereof, such as tungsten nitride (WN), tantalum nitride (TaN), tantalum silicide (TaSi), titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), molybdenum nitride (MoN), iridium oxide (IrOx), ruthenium oxide (RuOx), or ruthenium titanium nitride (RuTiN). (Previous reference) Figure 2A and Figure 3A The fabrication and related details of the second substrate 50, the third substrate 60, and the bonding layer 70 described herein are applicable. In one embodiment, an etch stop layer 80 may be formed on a substrate (not shown) by epitaxial growth or by deposition (such as CVD, PVD, or ALD), and then the substrate may be bonded to the third substrate 60 via the bonding layer 70. In some embodiments, a portion of the substrate may be removed after bonding, and the second substrate 50 may be retained in the second structure 400B. A semiconductor substrate including an etch stop layer may be fabricated by bonding two substrates after forming the etch stop layer, as described in application PCT / US23 / 69597, the contents of which are incorporated herein by reference.

[0083] like Figure 4B As shown, before bonding the first structure 100A and the second structure 400B, a first metal bonding layer 41 is formed on the first structure 100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). (See previous reference) Figure 1BThe described formation process and related details are applicable here.

[0084] like Figure 4C As shown, a first metal bonding layer 41 and a second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 400B is flipped and bonded to the first structure 100A through the bonding metal layer 40 to form a bonding structure 400C. (See previous reference...) Figure 1C The bonding process and related details described are applicable here.

[0085] like Figure 4D and Figure 4E As shown, a portion of the second structure 400B is removed, and the second surface 50b of the second substrate 50 is formed (step (e)). In Figure 4D In the illustrated embodiment, removing this portion of the second structure 400B includes removing the third substrate 60 and bonding layer 70 to expose the etch stop layer 80. The third substrate 60 and bonding layer 70 can be removed by performing suitable processes such as grinding, chemical mechanical polishing (CMP), and etching. In one embodiment, the third substrate 60 is removed by grinding and / or chemical mechanical polishing (CMP) processes, and can be removed by applying a first etchant (e.g., dilute hydrofluoric acid (HF) or water). The bonding layer 70 is removed by using a mixture of O and hydrofluoric acid (HF) in a weight ratio of approximately 100:1. This disclosure is not limited thereto. Figure 4E In the illustrated embodiment, removing this portion of the second structure 400B includes removing the etch stop layer 80. The etch stop layer 80 can be removed by oxide etching, plasma etching, hydrogen peroxide etching, or any suitable method. In one embodiment, the etch stop layer 80, comprising silicon nitride, can be removed by applying a second etchant (e.g., hot phosphoric acid). However, this disclosure is not limited thereto. After removing the etch stop layer 80, a second surface 50b of the second substrate 50 can be formed.

[0086] exist Figure 4E In the illustrated embodiment, the first heavily doped layer 46 is exposed after a portion of the second structure 400B (e.g., bonding layer 70 and etch stop layer 80) is removed. (See previous reference...) Figure 1D The formation process and related details of the first doped layer 46 described herein can be applied here.

[0087] like Figure 4F As shown, a semiconductor structure 110 and a memory device 200 are provided. The processes for manufacturing the semiconductor structure 110 and the memory device 200 can be the same as those described above. Figures 1E to 1I The described processes are basically similar, and for the sake of brevity, relevant descriptions are omitted.

[0088] The above Figures 2A to 2E , Figures 3A to 3E as well as Figures 4A to 4F The methods disclosed in the illustrated embodiments can mitigate the problems of large amounts of particles and contamination generated during the removal of a portion of the second structure, and can provide additional options for the fabrication of vertical devices.

[0089] Figures 5A to 5H This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Figure 5A As shown, a first structure 500A is provided (step (a)). The first structure 500A can be connected with... Figure 1A The first structure 500A shown is substantially similar to the first structure 100A, wherein the same reference numerals denote the same elements. The first structure 500A, including a first substrate 10 and a first wiring layer 31, further includes a first memory cell 100a and a second memory cell 100b located between the first wiring layer 31 and the first substrate 10. In some embodiments, the first substrate 10 may include functional devices (e.g., Figure 5F The functional device 11 shown. The first storage cell 100a may have a first end 101a and a second end 102a. In some embodiments, the first storage cell 100a extends from the first end 101a to the second end 102a. The second storage cell 100b may have a first end 101b and a second end 102b. In some embodiments, the second storage cell 100b extends from the first end 101b to the second end 102b. Each of the first storage cell 100a and the second storage cell 100b may include a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material. Figure 5A In the illustrated embodiment, the first wiring layer 31 can be electrically connected to the second terminal 102a of the first storage cell 100a. The first wiring layer 31 can also be electrically connected to the second terminal 102b of the second storage cell 100b (as described below). Figures 5D to 5F (More detailed description). Previous reference Figure 1H and Figure 1I The fabrication processes and related details of the described memory cells 100a and 100b are applicable here. In some embodiments, the first structure 500A may further include a third memory cell 100b', similar to the second memory cell 100b, located between the first wiring layer 31 and the first substrate 10 (e.g., Figure 5F and Figure 5H (As shown). The third storage cell 100b' may have a first end 101b' and a second end 102b'. In some embodiments, the third storage cell 100b' extends from the first end 101b' of the third storage cell 100b' to the second end 102b' of the third storage cell 100b'.

[0090] like Figure 5A As shown, the first structure 500A may include multiple bit lines, including a first bit line BL1 and a second bit line BL2. In some embodiments, each of the first bit line BL1 and the second bit line BL2 may include platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), copper (Cu), tungsten (W), other suitable materials, or combinations thereof. The multiple bit lines can be fabricated by any suitable process (e.g., photolithography and etching, damascus etching, double damascus etching, etc.). For example, the first bit line BL1 and the second bit line BL2 can be formed in the first dielectric layer 21 using a damascus etching process, a double damascus etching process, or any suitable method. In some embodiments, the first end 101a of the first memory cell 100a may be electrically connected to the first bit line BL1, and the first end 101b of the second memory cell 100b may be electrically connected to the second bit line BL2. (See previous reference...) Figure 1A The manufacturing and related details of the first structure 100A described herein can be applied here.

[0091] like Figure 5A As shown, a second structure 200B is provided (step (b)). The second structure 200B can be used with... Figure 2A The second structure 200B shown is substantially similar, with the same reference numerals indicating the same components. (Previous reference...) Figure 2A The manufacturing and related details of the second structure 200B described herein can be applied here.

[0092] like Figure 5B As shown, before bonding the first structure 500A and the second structure 200B, a first metal bonding layer 41 is formed on the first structure 500A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). (See previous reference) Figure 1B The described formation process and related details are applicable here.

[0093] like Figure 5C As shown, a first metal bonding layer 41 and a second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). The second structure 200B is flipped and bonded to the first structure 500A through the bonding metal layer 40 to form a bonding structure 500C. (See previous reference...) Figure 1C The bonding process and related details described are applicable here.

[0094] like Figure 5DAs shown, a portion of the second structure 200B is removed, and a second surface 50b of the second substrate 50 is formed (step (e)). The second substrate 50 is patterned to form a first vertical device 54a and a second vertical device 55a extending from a first end 55g of the second vertical device 55a to a second end 55h of the second vertical device 55a, wherein the second vertical device 55a is located above and in contact with the second contact structure 40b. In some embodiments, the second vertical device 55a contacts the second contact structure 40b at the first end 55g of the second vertical device 55a.

[0095] refer to Figure 12E A storage device 260 is provided. The storage device 260 includes a first wiring layer 31, a first contact structure 40a, a first vertical device 54a, a first memory cell 100a, and a second wiring layer 32. The first wiring layer 31 may include a plurality of word lines extending in a first direction 103a. Figure 12E In the illustrated embodiment, the multiple word lines include a first word line WL1. The storage device 260 may further include a second contact structure 40b, wherein the first contact structure 40a may land on the first word line WL1, and the second contact structure 40b may land on an island feature of the first wiring layer 31.

[0096] exist Figure 12E In the illustrated embodiment, the first vertical device 54a is electrically connected from its second end 54h to the second end 102a of the first storage cell 100a. Figure 12E In the illustrated embodiment, the second vertical device 55a is electrically connected from its first end 55g to the second end 102a of the first memory cell 100a. In some embodiments, the second vertical device 55a is electrically connected to the second end 102a of the first memory cell 100a via a via 30. The second wiring layer 32 may be electrically connected to the first end 101a of the first memory cell 100a. The second wiring layer 32 may include multiple bit lines extending in a second direction 103b, different from the first direction 103a. Figure 12E In the illustrated embodiment, the multiple bit lines include a first bit line BL1, and a first terminal 101a of the first memory cell 100a is electrically connected to the first bit line BL1. A fourth wiring layer 34 may be electrically connected to a second terminal 102a of the first memory cell 100a. The fourth wiring layer 34 may include multiple word lines extending in a first direction 103a. Figure 12E In the embodiment shown, the multiple word lines include the second word line WL2.

[0097] When the first memory cell 100a includes a magnetic tunnel junction (MTJ) structure, Figure 12EThe illustrated memory device 260 can be a spin-transfer torque type magnetic random access memory (STT-MRAM) device. For example, to perform a data write process in the first memory cell 100a, the programming current can flow along a first current path from the first word line WL1 through the first vertical device 54a and the memory cell 100a to the first bit line BL1; or, the programming current can flow along a second current path from the first bit line BL1 through the memory cell 100a and the second vertical device 55a to the second word line WL2. The flow and direction of the programming current can be controlled by the voltage applied to the word line and the bit line. Although in Figures 12A to 12E Only one memory cell is shown in the document, but multiple memory cells or memory cell arrays can be fabricated simultaneously using the methods disclosed herein.

[0098] exist Figures 12A to 12E In the illustrated embodiment, a memory device comprising two PN diodes as selectors can be manufactured using the methods disclosed herein. In some embodiments, each of the first vertical device 54a and the second vertical device 55a of the memory device 260 may be replaced with... Figure 6F or Figure 7 The first vertical device 54b and the second vertical device 55b shown are substantially similar vertical Schottky diodes to provide a memory device comprising two Schottky diodes as selectors.

[0099] Figures 13A to 13E This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Figure 13A As shown, this semiconductor structure can be used with Figure 1D , Figure 2D , Figure 3D , Figure 4E or Figure 15B The semiconductor structures shown are substantially similar, with the same reference numerals denoteing the same elements. In some embodiments, Figure 13A The semiconductor structure shown can be obtained from the above reference. Figures 1A to 1D , Figures 2A to 2D , Figures 3A to 3D , Figures 4A to 4E or Figures 15A to 15B The process described is used for manufacturing, and for the sake of brevity, related descriptions are omitted.

[0100] like Figure 13B As shown, the second substrate 50 is patterned to form a plurality of vertical devices including a first vertical device 54a and a second vertical device 55a (step (f)), and the bonding metal layer 40 is patterned to form a plurality of contact structures including a first contact structure 40a and a second contact structure 40b for the first vertical device 54a and the second vertical device 55a (step (g)). This patterning process can be compared with the above-mentioned reference. Figure 1EThe described processes are basically similar, and for the sake of brevity, relevant descriptions are omitted.

[0101] like Figure 13C As shown, after patterning and bonding the metal layer 40 (step (g)), a second dielectric layer 22 is formed (step (h)). The second dielectric layer 22 may fill the trench 59 such that the first vertical device 54a and the second vertical device 55a are laterally isolated through the second dielectric layer 22, and the first contact structure 40a and the second contact structure 40b are laterally isolated through the second dielectric layer 22. (See previous reference...) Figure 1H The described formation process and related details are applicable here.

[0102] like Figure 13C As shown, electrodes 105 are formed above the first vertical device 54a and the second vertical device 55a. Electrode 105 can be electrically connected to the first vertical device 54a from its second end 54h. Electrode 105 can be electrically connected to the second vertical device 55a from its second end 55h. In some embodiments, electrode 105 may comprise a material with a high spin Hall effect, such as β-tantalum (β-Ta), β-tungsten (β-W), tantalum (Ta), tungsten (W), platinum (Pt), copper (Cu) doped with elements such as iridium (Ir), bismuth (Bi), or any other suitable material or combination thereof that may exhibit high spin-orbit coupling. Electrode 105 can be fabricated by any suitable process, such as photolithography and etching processes, damascus processes, double damascus processes, etc.

[0103] like Figure 13C As shown, a first memory cell 100a is formed above a first vertical device 54a (step (i)). The first memory cell 100a is formed above the first vertical device 54a. In some embodiments, the first memory cell 100a is formed above an electrode 105. The electrode 105 can extend laterally from a first side 104a of the first memory cell 100a to a second side 104b of the first memory cell 100a. The first memory cell 100a may have a first end 101a and a second end 102a. In some embodiments, the first memory cell 100a extends from the first end 101a of the first memory cell 100a to the second end 102a of the first memory cell 100a. The electrode 105 can be electrically connected to the second end 102a of the first memory cell 100a. The first memory cell 100a may include a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material. (Previous reference) Figure 1H The materials and processes used to form the first storage cell 100a described herein are applicable here, and for the sake of brevity, related descriptions are omitted.

[0104] like Figure 13CAs shown, a second wiring layer 32 is formed above the first memory cell 100a. (See previous reference...) Figure 1H The materials and processes used to form the second wiring layer 32 described herein are applicable here, and for the sake of brevity, related descriptions are omitted.

[0105] like Figure 13C As shown, a plurality of vias, including a first via 30a and a second via 30b, are formed. The first via 30a can be formed above the first vertical device 54a. The first via 30a can be formed at a first side 104a of the first memory cell 100a. The second via 30b can be formed above the second vertical device 55a. The second via 30b can be formed at a second side 104b of the first memory cell 100a. Figure 13C In the illustrated embodiment, a first via 30a can be electrically connected to the first vertical device 54a from the second end 54h, and a second via 30b can be electrically connected to the second vertical device 55a from the second end 55h. In some embodiments, vias 30a and 30b can be electrically connected to the vertical devices 54a and 55a via electrode 105. In some embodiments, the first via 30a is electrically connected to electrode 105 at the first side 104a of the first storage cell 100a, and the second via 30b is electrically connected to electrode 105 at the second side 104b of the first storage cell 100a. The materials and processes used to form vias 30a and 30b can be the same as those described above. Figure 12E The materials and processes used to form the described via 30 are similar.

[0106] like Figure 13D As shown, Figure 2A The second structure 200B shown is flipped and bonded to the bonding metal layer 40. Figure 13C A bonding structure 1100C is formed on the first structure 1100A shown. Specifically, before bonding the first structure 1100A and the second structure 200B, a first metal bonding layer 41 is formed on the first structure 1100A, and a second metal bonding layer 42 is formed on the first surface 50a of the second substrate 50 (step (c)). The first metal bonding layer 41 and the second metal bonding layer 42 are bonded to form a bonding metal layer 40 (step (d)). (See previous reference...) Figure 2B and Figure 2C The described process and related details apply here.

[0107] like Figure 13EAs shown, a portion of the second structure 200B is removed, and a second surface (not shown) of the second substrate 50 is formed (step (e)). Then, the second substrate 50 is patterned to form a plurality of vertical devices including a third vertical device 56a and a fourth vertical device 57a (step (f)). The bonding metal layer 40 is patterned to form a plurality of contact structures, including a third contact structure 40c and a fourth contact structure 40d, for the third vertical device 56a and the fourth vertical device 57a (step (g)). The third contact structure 40c and the fourth contact structure 40d can be referenced above. Figure 1E The process described is similar to that used for the first contact structure 40a and the second contact structure 40b, and the relevant details previously described with reference to the first contact structure 40a and the second contact structure 40b (if applicable) may also be applied here.

[0108] like Figure 13E As shown, after patterning the bonding metal layer 40 (step (g)), a third dielectric layer 23 is formed (step (h)). The third dielectric layer 23 may surround the vertical devices 56a and 57a and the contact structures 40c and 40d. The third dielectric layer 23 may include one or more stacked dielectric layers. The third dielectric layer 23 may fill the trench (not shown) between the third vertical device 56a and the fourth vertical device 57a, such that the third vertical device 56a and the fourth vertical device 57a are laterally isolated by the third dielectric layer 23, and the third contact structure 40c and the fourth contact structure 40d are laterally isolated by the third dielectric layer 23. The forming materials and processes of the third dielectric layer 23 may be the same as those described above. Figure 1H The materials and processes used to form the second dielectric layer 22 are similar.

[0109] like Figure 13E As shown, a third wiring layer 33 is formed above the third vertical device 56a and the fourth vertical device 57a. The material and process for forming the third wiring layer 33 can be the same as those described above. Figure 1H The materials and processes used to form the second wiring layer 32 are similar. For example, the third wiring layer 33 can be formed in the third dielectric layer 23 using a damascus process, a double damascus process, or any suitable method.

[0110] like Figure 13E As shown, a semiconductor structure 180 is provided, which includes a first wiring layer 31, a first contact structure 40a, a second contact structure 40b, a first vertical device 54a, a second vertical device 55a, and a second dielectric layer 22. The first wiring layer 31 is located above a first substrate 10. The fabrication and related details of the first wiring layer 31, the first contact structure 40a, the second contact structure 40b, the first vertical device 54a, the second vertical device 55a, and the second dielectric layer 22 can be found in the above references. Figures 1A to 1I , Figures 2A to 2E, Figures 3A to 3E or Figures 4A to 4F The descriptions are similar, and will not be repeated here.

[0111] like Figure 13E As shown, the semiconductor structure 180 may further include a third contact structure 40c, a fourth contact structure 40d, a third vertical device 56a, a fourth vertical device 57a, and a third dielectric layer 23. The third contact structure 40c includes a first metal layer 41c, a second metal layer 42c, and a metal bonding interface 43c, wherein the second metal layer 42c is located above the first metal layer 41c, and the metal bonding interface 43c is located between the first metal layer 41c and the second metal layer 42c. The fourth contact structure 40d includes a first metal layer 41d, a second metal layer 42d, and a metal bonding interface 43d, wherein the second metal layer 42d is located above the first metal layer 41d, and the metal bonding interface 43d is located between the first metal layer 41d and the second metal layer 42d.

[0112] In some embodiments, each of the third contact structure 40c and the fourth contact structure 40d may be formed by patterning a bonding metal layer, which is formed by bonding a first metal bonding layer and a second metal bonding layer (see reference). Figures 13D to 13E Therefore, the second metal layer 42c of the third contact structure 40c can be directly bonded to the first metal layer 41c of the third contact structure 40c, such that a metal bonding interface 43c is formed between the first metal layer 41c and the second metal layer 42c; and the second metal layer 42d of the fourth contact structure 40d can be directly bonded to the first metal layer 41d of the fourth contact structure 40d, such that a metal bonding interface 43d is formed between the first metal layer 41d and the second metal layer 42d. Each of the first metal layers 41c and 41d and the second metal layers 42c and 42d may include a multilayer structure. However, this disclosure is not limited thereto. The first metal layer 41c of the third contact structure 40c can contact the first via 30a, and the second metal layer 42c of the third contact structure 40c can contact the third vertical device 56a. The first metal layer 41d of the fourth contact structure 40d can contact the second via 30b, and the second metal layer 42d of the fourth contact structure 40d can contact the fourth vertical device 57a. In this way, the third vertical device 56a and the fourth vertical device 57a can be electrically connected to the first via 30a and the second via 30b through the third contact structure 40c and the fourth contact structure 40d, respectively.

[0113] The third vertical device 56a and the fourth vertical device 57a can be substantially similar to the first vertical device 54a and the second vertical device 55a, and can be referenced as described above. Figure 1EThe process is similar to that described above. Relevant details previously described with reference to the first vertical device 54a and the second vertical device 55a (if applicable) may be applied here. However, this disclosure is not limited thereto. Figure 13E As shown, a third vertical device 56a extends from a first end 56g to a second end 56h, wherein the third vertical device 56a is located above and in contact with the third contact structure 40c. In some embodiments, the third vertical device 56a contacts the third contact structure 40c at its first end 56g. In some embodiments, the height H3 of the third vertical device 56a (e.g., the height between the first end 56g and the second end 56h) can be in the range of about 10 nm to about 300 nm. A fourth vertical device 57a extends from a first end 57g to a second end 57h, wherein the fourth vertical device 57a is located above and in contact with the fourth contact structure 40d. In some embodiments, the fourth vertical device 57a contacts the fourth contact structure 40d at its first end 57g.

[0114] In some embodiments, the third vertical device 56a and the fourth vertical device 57a are located at the same horizontal level. In other words, the top end (e.g., the second end 56h) of the third vertical device 56a may be substantially flush with the top end (e.g., the second end 57h) of the fourth vertical device 57a, and the bottom end (e.g., the first end 56g) of the third vertical device 56a may be substantially flush with the bottom end (e.g., the first end 57g) of the fourth vertical device 57a. In some embodiments, both the third vertical device 56a and the fourth vertical device 57a are located above the first vertical device 54a. In some embodiments, the height H3 of the third vertical device 56a is substantially equal to the height H4 of the fourth vertical device 57a (e.g., the height between the first end 57g and the second end 57h of the fourth vertical device 57a). In some embodiments, each of the third vertical device 56a and the fourth vertical device 57a may comprise a single-crystal semiconductor material, such as silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN).

[0115] exist Figure 13E In the illustrated embodiment, each of the first vertical device 54a, the second vertical device 55a, the third vertical device 56a, and the fourth vertical device 57a is a vertical PN diode. This disclosure is not limited thereto. The first vertical device 54a may be arranged in the same orientation as the second vertical device 55a, such as... Figure 13EAs shown, the first current I1 allowed by the first vertical device 54a (e.g., from the first end 54g to the second end 54h of the first vertical device 54a) and the second current I2 allowed by the second vertical device 55a under similar conditions (e.g., from the first end 55g to the second end 55h of the second vertical device 55a) have the same direction. The third vertical device 56a can be arranged in the same direction as the fourth vertical device 57a, as shown. Figure 13E As shown, the third current I3 allowed by the third vertical device 56a (e.g., from the first end 56g to the second end 56h of the third vertical device 56a) has the same direction as the fourth current I4 allowed by the fourth vertical device 57a under similar conditions (e.g., from the first end 57g to the second end 57h of the fourth vertical device 57a). Figure 13E As shown, the first vertical device 54a can be arranged in the same direction as the third vertical device 56a, so that the first current I1 and the third current I3 have the same direction; the second vertical device 55a can be arranged in the same direction as the fourth vertical device 57a, so that the second current I2 and the fourth current I4 have the same direction.

[0116] refer to Figure 13E A storage device 270 is provided. The storage device 270 includes a first wiring layer 31, a first contact structure 40a, a first vertical device 54a, an electrode 105, a first storage cell 100a, a second wiring layer 32, a second contact structure 40b, a second vertical device 55a, a third contact structure 40c, a third vertical device 56a, a fourth contact structure 40d, and a fourth vertical device 54a. The first wiring layer 31 may include multiple word lines. Figure 13E In the illustrated embodiment, the multiple word lines include a first word line WL1 and a second word line WL2. For example... Figure 13E As shown, the first character line WL1 extends in the first direction 103a, and the second character line WL2 may extend in the second direction 103b, which is different from the first direction 103a. The first contact structure 40a may land on the first character line WL1, and the second contact structure 40b may land on the second character line WL2.

[0117] exist Figure 13E In the illustrated embodiment, the first vertical device 54a is electrically connected from its second end 54h to the second end 102a of the first storage cell 100a. Figure 13E In the illustrated embodiment, the second vertical device 55a is electrically connected from its second end 55h to the second end 102a of the first storage cell 100a. Figure 13E In the illustrated embodiment, the third vertical device 56a is electrically connected from its first end 56g to the second end 102a of the first storage cell 100a. Figure 13EIn the embodiment shown, the fourth vertical device 57a is electrically connected from the first end 57g of the fourth vertical device 57a to the second end 102a of the first storage unit 100a.

[0118] exist Figure 13E In the illustrated embodiment, a first via 30a can be electrically connected to the third vertical device 56a from its first end 56g, and a second via 30b can be electrically connected to the fourth vertical device 57a from its first end 57g. Thus, the third vertical device 56a and the fourth vertical device 57a can be electrically connected to the electrode 105 through the first via 30a and the second via 30b, respectively. The electrode 105 can be electrically connected to the third vertical device 56a from its first end 56g. The electrode 105 can be electrically connected to the fourth vertical device 57a from its first end 57g. In some embodiments, both the first vertical device 54a and the third vertical device 56a are electrically connected to the electrode 105 at the first side 104a of the first storage cell 100a, and both the second vertical device 55a and the fourth vertical device 57a are electrically connected to the electrode 105 at the second side 104b of the first storage cell 100a.

[0119] exist Figure 13E In the illustrated embodiment, the second wiring layer 32 may be electrically connected to a first terminal 101a of the first memory cell 100a. The second wiring layer 32 may include multiple bit lines extending in a second direction 103b. Figure 13E In the illustrated embodiment, the multiple bit lines include a first bit line BL1, and the first terminal 101a of the first memory cell 100a is electrically connected to the first bit line BL1.

[0120] exist Figure 13E In the illustrated embodiment, the memory device 270 further includes a third wiring layer 33. A third vertical device 56a can be electrically connected to the third wiring layer 33 from its second end 56h. A fourth vertical device 57a can be electrically connected to the third wiring layer 33 from its second end 57h. The third wiring layer 33 may include multiple word lines. Figure 13E In the illustrated embodiment, the multiple word lines include a third word line WL3 and a fourth word line WL4. For example... Figure 13E As shown, the third word line WL3 extends in the first direction 103a, and the fourth word line WL4 extends in the second direction 103b. The third word line WL3 can be electrically connected to the third vertical device 56a from the second end 56h. The fourth word line WL4 can be electrically connected to the fourth vertical device 57a from the second end 57h.

[0121] Each of the vertical devices 54a-57a has a length of 1F and a width of 1F, where F represents half of the minimum feature size or minimum feature pitch typically associated with a particular photolithography process. For example... Figure 13E As shown, the storage device 270 has cell sizes of 6F and 2F in the first direction 103a and the second direction 103b, respectively, providing a cell size of 12 feature squares (F²).

[0122] When the first memory cell 100a includes a magnetic tunnel junction (MTJ) structure, Figure 13E The storage device 270 shown can be a spin-orbit torque type magnetic random access memory (SOT-MRAM) device. When a programming current flows through electrode 105, the spin Hall effect (SHE) of electrode 105 generates spin injection into the free magnetic layer of the MTJ structure. A large spin Hall effect provides sufficient spin injection to switch the magnetization direction of the free magnetic layer. A large spin Hall effect can be achieved by using a suitable material with a high spin Hall effect (high spin injection efficiency) for electrode 105 or by flowing a large programming current through electrode 105. To reduce energy consumption, it is more feasible to select a suitable material with a high spin Hall effect, and some materials are mentioned in the above references. Figure 13C It is described in the text.

[0123] For example, to perform a data write process in the first memory cell 100a, the programming current can flow along a first current path from the first word line WL1 through the first vertical device 54a, electrode 105, and fourth vertical device 57a to the fourth word line WL4; or, the programming current can flow along a second current path from the second word line WL2 through the second vertical device 55a, electrode 105, and third vertical device 56a to the third word line WL3. The flow and direction of the programming current can be controlled by the voltage applied to the word lines. Although in Figures 13A to 13E Only one memory cell is shown in the document, but multiple memory cells or memory cell arrays can be fabricated simultaneously using the methods disclosed herein.

[0124] exist Figures 13A to 13E In the illustrated embodiment, a memory device comprising four PN diodes as selectors can be fabricated using the methods disclosed herein. In some embodiments, each of the vertical devices 54a-57a of the memory device 270 may be replaced with... Figure 6F or Figure 7 The vertical devices 54b and 55b shown are substantially similar vertical Schottky diodes to provide a memory device comprising four Schottky diodes as selectors.

[0125] Figure 14 This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Figure 14As shown, a semiconductor structure 181 and a memory device 271 are provided. The semiconductor structure 181 and the memory device 271 can be used with... Figure 13E The semiconductor structure 180 and memory device 270 shown are substantially similar, except that the semiconductor structure 181 and memory device 271 do not include, for example, Figure 13E Apart from the second contact structure 40b, the second vertical device 55a, the second via 30b, the fourth contact structure 40d, and the fourth vertical device 57a connected to the electrode 105, as shown, and for the sake of brevity, related descriptions are omitted.

[0126] When the first memory cell 100a includes a magnetic tunnel junction (MTJ) structure, Figure 14 The storage device 271 shown may be a spin-transfer torque type magnetic random access memory (STT-MRAM) device. For example, to perform a data write process in the first storage cell 100a, the programming current can be made to flow along a first current path from the first word line WL1 through the first vertical device 54a and the storage cell 100a to the first bit line BL1; or, the programming current can be made to flow along a second current path from the first bit line BL1 through the storage cell 100a and the third vertical device 56a to the third word line WL3. The flow and direction of the programming current can be controlled by the voltage applied to the word line and the bit line. Although in Figure 14 Only one memory cell is shown in the document, but multiple memory cells or memory cell arrays can be fabricated simultaneously using the methods disclosed herein.

[0127] and Figure 12E Compared to the storage device 260 shown, Figure 14 The arrangement shown can further reduce the storage cell size from 12F² to 8F². Figure 14 The structure shown has a 4F element size in the first direction 103a and a 2F element size in the second direction 103b, providing an element size of 8 characteristic squares (F²); while Figure 12E The storage device 260 shown is in Figure 12E The second direction 103b shown has a cell size of 6F, in Figure 12E The first direction 103a shown has a cell size of 2F, providing a cell size of 12 feature squares (F²). Different architectures will further reduce the memory cell size.

[0128] exist Figure 14 In the illustrated embodiment, a memory device comprising two PN diodes as selectors can be fabricated using the methods disclosed herein. In some embodiments, each of the first vertical device 54a and the third vertical device 56a of the memory device 271 may be replaced with... Figure 6F or Figure 7The first vertical device 54b and the second vertical device 55b shown are substantially similar vertical Schottky diodes to provide a memory device comprising two Schottky diodes as selectors.

[0129] Figures 15A to 15B This is a schematic diagram illustrating an intermediate stage in the fabrication of a semiconductor structure according to an embodiment of the present disclosure. Figure 15A As shown, a bonding structure 100C' is provided. The bonding structure 100C' can be coupled with... Figure 1C The bonding structure 100C shown is basically similar, except that the bonding structure 100C' does not include bonding with... Figure 1C The hydrogen-injected layer 58 shown is similar to other hydrogen-injected layers, with the same reference numerals indicating the same elements. Figure 15A The bonding structure 100C' shown can be used with the above reference Figures 1A to 1C The process described is similar to manufacturing, and for the sake of brevity, related descriptions are omitted. Figures 15A to 15B In the illustrated embodiment, the upper layer 50p of the second substrate 50 may include silicon, and each of the first semiconductor material layer 51 and the second semiconductor material layer 52 may include germanium (Ge) or silicon-germanium (SixGey). This disclosure is not limited thereto. Semiconductor material layers 51 and 52 may have high etch selectivity relative to the upper layer 50p of the second substrate 50. In other words, under the same etch conditions, the etch rate of the upper layer 50p of the second substrate 50 is significantly faster than the etch rates of the semiconductor material layers 51 and 52. (See previous reference...) Figure 1A The relevant details of the second substrate 50 described herein (if applicable) may be applied here.

[0130] like Figure 15B As shown, a portion of the second structure is removed, and the second surface 50b of the second substrate 50 is formed (step (e)). In Figure 15B In the illustrated embodiment, removing the portion of the second structure includes removing the upper layer 50p of the second substrate 50. The upper layer 50p of the second substrate 50 can be removed by an etching process under suitable etching conditions. In some embodiments, a first semiconductor material layer 51 (e.g., Ge or SixGey) can be used as an etch stop layer in the etching process used to remove the portion of the second structure (e.g., silicon). After removal, a second surface 50b of the second substrate 50 is formed. Subsequent processes can be performed in accordance with the above-described references. Figures 1E to 1H The described processes are basically similar, and for the sake of brevity, relevant descriptions are omitted.

[0131] The processes disclosed herein can provide additional options for the fabrication of vertical devices and can reduce process steps and process time. For example, the hydrogen implantation process can be omitted. Furthermore, the processes disclosed herein can also provide vertical devices, including germanium (Ge) or silicon germanium (SixGey), for high-frequency and high-power applications.

[0132] The foregoing description of the embodiments is intended to enable those skilled in the art to make and use the disclosed subject matter. Various modifications to these embodiments will readily be apparent to those skilled in the art, and the novel principles and subject matter disclosed herein can be applied to other embodiments without the use of inventive ability. Therefore, the claimed subject matter is not limited to the embodiments shown herein, but should be given the widest scope consistent with the principles and novel features disclosed herein. It is conceivable that additional embodiments are within the spirit and true scope of the disclosed subject matter. Therefore, it is intended that the invention cover modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A method of fabricating a semiconductor structure, comprising: (a) providing a first structure, the first structure comprising a first substrate and a wiring layer located above the first substrate; (b) providing a second structure, the second structure comprising a second substrate; (c) forming a first metal bonding layer on the first structure and a second metal bonding layer on a first surface of the second substrate; (d) bonding the first metal bonding layer and the second metal bonding layer to form a bonding metal layer; (e) removing a portion of the second structure and forming a second surface of the second substrate; (f) patterning the second substrate to form a plurality of vertical devices; and (g) patterning the bonding metal layer to form a plurality of contact structures for the plurality of vertical devices. Patterning the second substrate to form a plurality of vertical devices (step (f)) is performed after step (d).

2. The method of claim 1, wherein, Patterning the bonding metal layer to form a plurality of contact structures (step (g)) is performed after step (d).

3. The method of claim 1, wherein, In step (d), at least one of the first metal bonding layer and the second metal bonding layer is an unpatterned metal layer.

4. The method of claim 1, wherein, Step (d) comprises bonding the first metal bonding layer and the second metal bonding layer by thermocompression bonding, eutectic bonding, or reactive bonding.

5. The method of claim 1, wherein, Each of the first metal bonding layer and the second metal bonding layer comprises aluminum (Al), gold (Au), indium (In), palladium (Pd), germanium (Ge), copper (Cu), aluminum-silicon alloy (Al-Si), titanium nitride (TiN), lead-tin alloy (Pb-Sn), aluminum-tin alloy (Al-Sn), gold-tin alloy (Au-Sn), indium-palladium alloy (In-Pd), indium-tin alloy (In-Sn), silver-tin alloy (Ag-Sn), gold-indium alloy (Au-In), or copper-tin alloy (Cu-Sn).

6. The method of claim 1, wherein, The first structure further comprises alignment marks, and step (f) comprises patterning the second substrate according to the alignment marks, and step (g) comprises patterning the bonding metal layer according to the alignment marks.

7. The method of claim 1, wherein, 8. The method of claim 1, further comprising (h) forming a dielectric layer around the vertical devices and the contact structures after step (g).

9. The method of claim 1, further comprising (i) forming a plurality of memory cells above the vertical devices. The first substrate comprises functional devices, and the wiring layer is electrically connected to the functional devices.

10. The method of claim 1, wherein, The first structure further comprises a plurality of memory cells between the wiring layer and the first substrate.

11. The method of claim 1, wherein, Each of the vertical devices is a vertical PN diode, a vertical Schottky diode, a vertical bipolar transistor, or a vertical field effect transistor.

12. The method of claim 1, wherein, The wiring layer comprises a plurality of conductive lines.

13. The method of claim 1, wherein, The second substrate comprises a single-crystalline semiconductor material.

14. The method of claim 1, wherein, ​ 15. The method of claim 1, wherein, the second substrate includes a first semiconductor material layer and a second semiconductor material layer on the first semiconductor material layer, the first semiconductor material layer is doped with a first type of dopant, and the second semiconductor material layer is doped with a second type of dopant; and after step (c), the second metal bonding layer is in contact with the second semiconductor material layer.

16. The method of claim 15, wherein, the second semiconductor material layer includes a second heavily doped layer extending from a first surface of the second substrate.

17. The method of claim 1, wherein, the second substrate includes a first semiconductor material layer, a second semiconductor material layer on the first semiconductor material layer, and a third semiconductor material layer between the first semiconductor material layer and the second semiconductor material layer; the first semiconductor material layer and the second semiconductor material layer are doped with a first type of dopant, and the third semiconductor material layer is doped with a second type of dopant; and after step (c), the second metal bonding layer is in contact with the second semiconductor material layer.

18. The method of claim 1, wherein, the second substrate includes a semiconductor material layer and a first metal material layer on the semiconductor material layer, and after step (c), the second metal bonding layer is in contact with the first metal material layer.

19. The method of claim 1, further comprising (j1) forming a second metal material layer on a second surface of the second substrate after step (e).

20. The method of claim 1, further comprising (j2) forming a first heavily doped layer extending from a second surface of the second substrate after step (e).

21. The method of claim 1, wherein, the second substrate further includes a first heavily doped layer, and after step (e), the first heavily doped layer is exposed.

22. The method of claim 1, wherein, the second substrate further includes a hydrogen implant layer, and step (e) includes removing a portion of the second substrate from about the hydrogen implant layer.

23. The method of claim 1, wherein, the second structure further includes a third substrate and an etch stop layer between the second substrate and the third substrate, and step (e) includes removing the etch stop layer.

24. The method of claim 1, wherein, the second structure further includes a third substrate and a bonding layer between the second substrate and the third substrate, and step (e) includes removing the bonding layer.

25. The method of claim 24, wherein, the second structure further includes an etch stop layer between the bonding layer and the second substrate, and step (e) includes removing the bonding layer to expose the etch stop layer.

26. The method of claim 1, wherein, each of the first metal bonding layer and the second metal bonding layer includes a metal, a conductive metal compound, or a metal alloy.

27. The method of claim 1, wherein, each of the first metal bonding layer and the second metal bonding layer includes a metal silicide or a metal nitride.

28. A semiconductor structure, comprising: a wiring layer in a first dielectric layer; a first contact structure landing on the wiring layer; a second contact structure landing on the wiring layer; a first vertical device over and in contact with the first contact structure; a second vertical device over and in contact with the second contact structure. a second vertical device over and in contact with the second contact structure, and the first vertical device is at a same horizontal location as the second vertical device; and a second dielectric layer over the first dielectric layer and surrounding each of the first vertical device, the second vertical device, the first contact structure, and the second contact structure; wherein each of the first contact structure and the second contact structure includes a first metal layer, a second metal layer over the first metal layer, and a metal bonding interface between the first metal layer and the second metal layer.

29. The semiconductor structure of claim 28, wherein, The height of the first vertical device is substantially equal to the height of the second vertical device.

30. The semiconductor structure of claim 28, wherein, The height of the first vertical device is in a range from about 10 nm to about 300 nm.

31. The semiconductor structure of claim 28, wherein, Each of the first vertical device and the second vertical device is a vertical PN diode, a vertical Schottky diode, a vertical bipolar transistor, or a vertical field effect transistor.

32. The semiconductor structure of claim 28, wherein, The first vertical device and the second vertical device are arranged in a same direction.

33. The semiconductor structure of claim 28, wherein, Each of the first vertical device and the second vertical device includes a single crystalline semiconductor material.

34. The semiconductor structure of claim 28, further comprising a first memory cell over the first vertical device.

35. The semiconductor structure of claim 34, wherein, The first memory cell includes a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material.

36. The semiconductor structure of claim 28, wherein, The first metal layer and the second metal layer of the first contact structure are vertically aligned without alignment deviation, and the first metal layer and the second metal layer of the second contact structure are vertically aligned without alignment deviation.

37. The semiconductor structure of claim 28, wherein, The wiring layer is electrically connected with the functional device.

38. The semiconductor structure of claim 28, wherein, The second dielectric layer continuously extends from the uppermost surface of the first dielectric layer and there is no bonding interface between the first contact structure and the second contact structure and substantially at a same horizontal location as the metal bonding interfaces of the first contact structure and the second contact structure.

39. The semiconductor structure of claim 28, wherein, The second dielectric layer is formed by depositing a dielectric material on the uppermost surface of the first dielectric layer surrounding the first metal layer and the second metal layer of the first contact structure and the second contact structure.

40. The semiconductor structure of claim 28, wherein, Each of the first contact structure and the second contact structure is formed by patterning a bonding metal layer formed by bonding a first metal bonding layer and a second metal bonding layer.

41. A memory device, comprising: a first wiring layer over and electrically connected with a functional device in a first substrate; a first contact structure landing on the first wiring layer, and the first contact structure including a first metal layer and a second metal layer over and directly bonded with the first metal layer; a first vertical device over and in contact with the first contact structure at a first end of the first vertical device; a first storage unit over the first vertical device and having a first end and a second end, the first vertical device electrically connected from a second end of the first vertical device to a second end of the first storage unit; and a second wiring layer electrically connected to the first end of the first storage unit; wherein the first metal layer is in contact with the first wiring layer and the second metal layer is in contact with the first vertical device.

42. The memory device of claim 41, wherein, The width of the first metal layer is substantially equal to the width of the second metal layer.

43. The memory device of claim 41, wherein, The width of the first vertical device is substantially equal to the width of the second metal layer.

44. The memory device of claim 41, wherein, The first storage unit comprises a magnetic tunnel junction (MTJ) structure, a phase change material, or a variable resistance material.

45. The memory device of claim 41, wherein, The first vertical device is a vertical PN diode, a vertical Schottky diode, a vertical bipolar transistor, or a vertical field effect transistor.

46. The memory device of claim 41, wherein, The first vertical device comprises a single crystalline semiconductor material.

47. The memory device of claim 41, further comprising an alignment mark on the first substrate.

48. The memory device of claim 41, wherein, The second wiring layer is over the first storage unit.

49. The memory device of claim 41, further comprising: a second contact structure landing on the first wiring layer, the second contact structure comprising a first metal layer and a second metal layer over the first metal layer and directly bonded to the first metal layer; and a second vertical device over the second contact structure and in contact with the second contact structure at a first end of the second vertical device.

50. The memory device of claim 49, wherein, The first vertical device is in the same horizontal position as the second vertical device.

51. The memory device of claim 49, wherein, The first vertical device is arranged in the same direction as the second vertical device.

52. The memory device of claim 49, wherein, The second vertical device is electrically connected from a first end of the second vertical device to a second end of the first storage unit.

53. The memory device of claim 49, further comprising a second storage unit having a first end and a second end, wherein, The second storage unit is over the second vertical device and the second vertical device is electrically connected from a second end of the second vertical device to a second end of the second storage unit.

54. The memory device of claim 49, wherein, The first wiring layer comprises a plurality of word lines extending in a first direction, the first contact structure lands on a first word line, and the second contact structure lands on a second word line.

55. The memory device of claim 49, wherein, The first wiring layer comprises a plurality of word lines extending in a first direction, the first contact structure and the second contact structure both land on a first word line.

56. The memory device of claim 54, wherein, The second wiring layer comprises a plurality of bit lines extending in a second direction different from the first direction, and the first end of the first storage unit is electrically connected to a first bit line.

57. The memory device of claim 41, further comprising: a second contact structure landing on the first wiring layer; a second vertical device over the second contact structure and in contact with the second contact structure at a first end of the second vertical device, the second vertical device electrically connected from a second end of the second vertical device to a second end of the first storage unit; an electrode extending laterally from a first side of the first memory cell to a second side of the first memory cell, the electrode in contact with the first memory cell at a second end of the first memory cell; a third contact structure; a third vertical device over the third contact structure and in contact with the third contact structure at a first end of the third vertical device; and a fourth contact structure; and a fourth vertical device over the fourth contact structure and in contact with the fourth contact structure at a first end of the fourth vertical device; wherein the first vertical device and the third vertical device are each electrically connected to the electrode at the first side of the first memory cell, and the second vertical device and the fourth vertical device are each electrically connected to the electrode at the second side of the first memory cell; and wherein each of the second contact structure, the third contact structure, and the fourth contact structure includes a first metal layer and a second metal layer over the first metal layer and directly bonded to the first metal layer.

58. The memory device of claim 57, wherein, The first vertical device and the second vertical device are in the same horizontal location.

59. The memory device of claim 57, wherein, The third vertical device and the fourth vertical device are in the same horizontal location.

60. The memory device of claim 57, wherein, The third vertical device and the fourth vertical device are each over the first vertical device.

61. The memory device of claim 57, wherein, A height of the first vertical device is substantially equal to a height of the second vertical device.

62. The memory device of claim 57, wherein, A height of the third vertical device is substantially equal to a height of the fourth vertical device.

63. The memory device of claim 57, wherein, The first vertical device and the second vertical device are arranged in the same direction.

64. The memory device of claim 57, wherein, The third vertical device and the fourth vertical device are arranged in the same direction.

65. The memory device of claim 57, wherein, The first vertical device and the third vertical device are arranged in the same direction, and the second vertical device and the fourth vertical device are arranged in the same direction.

66. The memory device of claim 57, further comprising a third wiring layer, the third vertical device is electrically connected to the third wiring layer from a second end of the third vertical device, and the fourth vertical device is electrically connected to the third wiring layer from a second end of the fourth vertical device.

67. The memory device of claim 57, wherein, The memory device has a cell size of about 12 features squared (F2).

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