Display panel and display terminal
By introducing a voltage divider module and gradient electric field technology into the liquid crystal display panel, the problem of alignment dark patterns was solved, the display effect was improved, and stable deflection of liquid crystal molecules was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-22
- Publication Date
- 2026-04-03
AI Technical Summary
Existing liquid crystal display panels are prone to alignment dark lines during the alignment process, which affects the display effect. This is mainly due to the disordered deflection of liquid crystal molecules in two electric fields.
By introducing a voltage divider module into the display panel and connecting it to the pixel electrode via a data line, the external high voltage is divided into a medium voltage to form a gradient electric field, thereby improving the deflection disorder of liquid crystal molecules. Multiple transistors or resistors are used for voltage division to ensure voltage stability and uniformity.
It effectively improves alignment dark patterns, enhances the display effect of LCD panels, reduces the risk of liquid crystal molecule deflection disorder, and improves display quality.
Smart Images
Figure CN121785017A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to a display panel and a display terminal. Background Technology
[0002] Liquid crystal display (LCD) panels are the mainstream display products. The liquid crystal layer in an LCD panel needs to be aligned using alignment technology to form a micro-alignment structure on the substrate surface, allowing the liquid crystal molecules to exhibit a specific pretilt angle when there is no electric field, thereby improving the display effect.
[0003] In the alignment process, an electric field is needed to position the liquid crystal molecules at a specific pretilt angle. However, existing equipment can only provide two voltages. When the liquid crystal display panel is deflected in the electric fields formed by the two voltages, disorder occurs, which easily leads to alignment dark lines after the alignment process. Alignment dark lines affect the display effect of the display panel. Summary of the Invention
[0004] This application provides a display panel and a display terminal to improve the technical problem of alignment dark patterns that easily appear in liquid crystal display panels.
[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, including a display area and a non-display area disposed around the periphery of the display area, the display panel comprising: First substrate; A driving circuit layer is disposed on one side of the first substrate. The driving circuit layer includes a voltage divider module disposed in the non-display area and a data line disposed in the display area. The data line extends along a first direction. An electrode layer is disposed on the side of the driving circuit layer away from the first substrate. The electrode layer includes a first electrode line, a second electrode line, and a pixel electrode. The first electrode line and the second electrode line both extend along the first direction. Each column of pixel electrodes is located between the first electrode line and the second electrode line. The first electrode line or the second electrode line is disposed between any two adjacent columns of pixel electrodes. The voltage divider module is electrically connected to the pixel electrode via the data line.
[0006] Optionally, the voltage divider module includes at least one first transistor, the first transistor including a first source, a first drain and a first gate, the first source of the first transistor being shorted to the first gate of the same first transistor, and the first drain of the first transistor in the voltage divider module near the data line being electrically connected to the data line.
[0007] Optionally, the driving circuit layer includes a first metal layer and a second metal layer located on the side of the first metal layer away from the first substrate; The first gate is located in the first metal layer, the first source and the first drain are located in the second metal layer, and the display panel further includes a first connection trace located in the first metal layer. The first connection trace is electrically connected to the first drain at one end near the first transistor, and electrically connected to the data line at one end near the data line. The data line is located in the second metal layer.
[0008] Optionally, the display panel further includes a second connection trace located in the first metal layer. The end of the second connection trace near the first transistor is connected to the first gate, and the end of the second connection trace away from the first transistor extends to the edge of the first substrate.
[0009] Optionally, the voltage divider module includes at least two of the first transistors, with two adjacent first transistors connected in series.
[0010] Optionally, the electrode layer further includes a connection block located in the non-display area, the connection block being connected to the first source of the first transistor through at least one via, and the connection block being connected to the first gate of the same first transistor through another via.
[0011] Optionally, the non-display area includes a binding area, the voltage divider module and the binding area are located on the same side of the display area, and the voltage divider module is located on the side of the binding area away from the display area.
[0012] Optionally, the first electrode line overlaps with the odd-numbered data lines in the thickness direction of the display panel, and the second electrode line overlaps with the even-numbered data lines in the thickness direction of the display panel.
[0013] Optionally, the electrode layer includes a third connection trace and a fourth connection trace, wherein each of the first electrode lines is connected to the third connection trace, and each of the second electrode lines is connected to the fourth connection trace.
[0014] Optionally, both the third and fourth connection traces are located in the non-display area, and the third and fourth connection traces are disposed on opposite sides of the display area, with one of the third and fourth connection traces located on the same side of the display area as the voltage divider module.
[0015] Optionally, both the third and fourth connection traces extend to the edge of the first substrate.
[0016] Optionally, the driving circuit layer further includes a second transistor located in the display area, the second transistor including a second source and a second drain, the second source being electrically connected to the data line and the second drain being electrically connected to the pixel electrode.
[0017] According to a second aspect of this application, a display terminal is provided, including the display panel described above.
[0018] In the display panel of this application embodiment, an external high voltage can be input to the first electrode line, and an external low voltage can be input to the second electrode line. The voltage divider module is electrically connected to the pixel electrode through the data line. The voltage divider module can divide the external high voltage to form a medium voltage lower than the high voltage. The medium voltage is input to the pixel electrode, which is located between the first electrode line and the second electrode line. This allows the first electrode line, the second electrode line, and the pixel electrode to form a gradient electric field under the three voltages. The gradient electric field can reduce the risk of liquid crystal deflection disorder in the alignment process, thereby improving alignment dark lines.
[0019] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0022] Figure 1 These are photos of alignment patterns appearing on display panels in related technologies; Figure 2 This is a top view of the display panel provided in an exemplary embodiment of this disclosure; Figure 3 yes Figure 2 Schematic diagram of the cross-sectional structure at point CC; Figure 4 yes Figure 2 A magnified structural diagram at point B in the diagram; Figure 5 yes Figure 4 A magnified structural diagram at point E in the diagram; Figure 6 yes Figure 5 The equivalent circuit diagram of the voltage divider module in the diagram; Figure 7 This is a cross-sectional structural diagram of the display panel; Figure 8 This is a schematic diagram of the structure of a display terminal provided in an exemplary embodiment of this disclosure.
[0023] Explanation of reference numerals in the attached figures: 1-Display panel; AA-Display area; NA-Non-display area; BA-Binding area; 11-Subpixel; 10 - First substrate; 20 - Driver circuit layer; 21 - Voltage divider module; 211 - First transistor; 2111 - First source; 2112 - First drain; 2113 - First gate; 2114 - First active part; 22 - First metal layer; 221 - First connection trace; 222 - Second connection trace; 223 - Scan line; 23 - Second metal layer; 231 - Data line; 212 - Second transistor; 2121 - Second source; 2122 - Second drain; 2123 - Second gate; 2124 - Second active part; 213 - Bonding terminal; 30 - Electrode layer; 31 - First electrode line; 32 - Second electrode line; 33 - Pixel electrode; 34 - Connector block; 35 - Third connection trace; 36 - Fourth connection trace; 40 - Second substrate; 41 - Common electrode layer; 50-Liquid Crystal Layer; 61-Chip-on-chip film; 62 - Printed Circuit Board; D1 - First direction; D2 - Second direction; 2-Display terminal; 3-Backlight module. Detailed Implementation
[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0025] like Figure 1 As shown, Figure 1 This is a photograph of the alignment dark pattern appearing on display panel 1 in the related technology. Figure 1 The diagram shows a sub-pixel 11. Sub-pixel 11 has a two-domain structure arranged vertically. As indicated by arrow A in the diagram, a black shadow is formed in the middle area of the first domain of sub-pixel 11, and a black shadow is also formed in the middle area of the second domain of sub-pixel 11, which is called alignment dark pattern. The alignment dark pattern will affect the display effect of display panel 1.
[0026] According to the first aspect of this application, Figures 2 to 7 As shown, a display panel 1 is provided, including a display area AA and a non-display area NA disposed around the display area AA. The display panel 1 includes a first substrate 10, a driving circuit layer 20, and an electrode layer 30. The driving circuit layer 20 is disposed on one side of the first substrate 10 and includes a voltage divider module 21 disposed in the non-display area NA and a data line 231 disposed in the display area AA. The data line 231 extends along a first direction D1. The electrode layer 30 is disposed on the side of the driving circuit layer 20 away from the first substrate 10 and includes a first electrode line 31, a second electrode line 32, and a pixel electrode 33. The first electrode line 31 and the second electrode line 32 both extend along the first direction D1. Any column of pixel electrodes 33 is located between the first electrode line 31 and the second electrode line 32. A first electrode line 31 or a second electrode line 32 is disposed between any two adjacent columns of pixel electrodes 33. The voltage divider module 21 is electrically connected to the pixel electrode 33 through the data line 231.
[0027] like Figure 2 As shown, the display panel 1 includes a display area AA and a non-display area NA disposed around the display area AA. The display area AA may have multiple sub-pixels 11, which may include a first sub-pixel 11, a second sub-pixel 11, and a third sub-pixel 11 of different emitting colors. The first sub-pixel 11, the second sub-pixel 11, and the third sub-pixel 11 may be one of a red sub-pixel 11, a green sub-pixel 11, and a blue sub-pixel 11, respectively, thereby achieving color display. The display area AA is provided with a pixel driving circuit, which drives the sub-pixels 11 for display. The non-display area NA may have a gate driving circuit, etc., which provides driving signals to the sub-pixels 11.
[0028] In some embodiments, the display panel 1 may adopt a 2-domain design to increase the aperture ratio of the display panel 1.
[0029] In some embodiments, the display panel may be a vertical alignment (VA) type panel, but is not limited thereto.
[0030] The first substrate 10 can be a rigid material or a flexible material. The rigid material can be glass, quartz, or silicon wafer. The flexible material can be one of polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET).
[0031] The driving circuit layer 20 is provided with driving circuits, such as gate driving circuits and pixel driving circuits, and the driving circuit layer 20 is used to provide driving signals for sub-pixels 11.
[0032] like Figures 2 to 7 As shown, the driving circuit layer 20 includes a voltage divider module 21, which converts a first voltage into a second voltage, the value of which is less than the value of the first voltage. The voltage divider module 21 can be a thin-film transistor, a resistor, etc. The resistor can be formed using semiconductor materials, etc.
[0033] Combination Figure 2 and Figure 7 The driving circuit layer 20 also includes a data line 231, which is disposed in the display area AA and extends along the first direction D1 of the display panel 1. The extension direction of the data line 231 is the column direction of the display panel 1.
[0034] Combination Figure 2 and Figure 7 The driving circuit layer 20 also includes scan lines 223, which are disposed in the display area AA. The scan lines 223 extend along the second direction D2 of the display panel 1, and the extension direction of the scan lines 223 is the row direction of the display panel 1. Multiple scan lines 223 intersect with multiple data lines 231 to form an opening, which roughly corresponds to the light-transmitting area of the display panel 1.
[0035] like Figure 7 As shown, the electrode layer 30 is located on the side of the driving circuit layer 20 away from the first substrate 10. The electrode layer 30 can be a transparent conductive material, such as ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), etc.
[0036] like Figure 7 As shown, the electrode layer 30 includes pixel electrodes 33, which are located in the light-transmitting area. The voltage divider module 21 is electrically connected to the pixel electrodes 33 via a data line 231, meaning that the data line 231 is electrically connected to each pixel electrode 33, thereby inputting a signal to the pixel electrode 33.
[0037] like Figure 2 and Figure 3 As shown, both the first electrode line 31 and the second electrode line 32 extend along the first direction D1. Each column of pixel electrodes 33 is located between the first electrode line 31 and the second electrode line 32, and either a first electrode line 31 or a second electrode line 32 is provided between any two adjacent columns of pixel electrodes 33. That is, each pixel electrode 33 has a first electrode line 31 on one side and a second electrode line 32 on the other side. Both the first electrode line 31 and the second electrode line 32 can input signals. For example, the first electrode line 31 can input a first voltage, and the second electrode line 32 can input a third voltage. The first voltage is greater than the second voltage, and the second voltage is greater than the third voltage.
[0038] like Figure 3As shown, the display panel 1 further includes a second substrate 40, which is disposed opposite to and spaced apart from the first substrate 10. The display panel 1 also includes a liquid crystal layer 50, which is located between the first substrate 10 and the second substrate 40. One pixel electrode 33 corresponds to one sub-pixel 11.
[0039] The display panel 1 also includes a common electrode layer 41, which can be disposed on the side of the second substrate 40 near the liquid crystal layer 50. When the display panel 1 displays an image, the common electrode layer 41 and the pixel electrode 33 form an electric field, driving the liquid crystal molecules in the liquid crystal layer 50 to deflect. Liquid crystal molecules with different deflection angles correspond to different light transmittances, thereby controlling the light transmittance of the display panel 1 and realizing the brightness control of the displayed image.
[0040] It should be noted that the display panel 1 is an LCD panel. The LCD panel itself does not emit light and needs to be backlit by the backlight module 3.
[0041] In the alignment process of display panel 1, an external device provides two voltages, namely a first voltage and a third voltage, wherein the first voltage is greater than the third voltage. For example, the first voltage can be 23 volts and the third voltage can be 0 volts, but it is not limited to these.
[0042] A first voltage is input to the first electrode line 31, and a third voltage is input to the second electrode line 32. The first voltage is simultaneously input to a voltage divider module 21. The voltage divider module 21 divides the first voltage and outputs a second voltage, which is less than the first voltage and greater than the third voltage. For example, the second voltage can be 10 volts. The first electrode line 31, the pixel electrode 33, and the second electrode line 32 form a gradient electric field under the three voltages.
[0043] Specifically, such as Figure 3 As shown, Figure 3 The middle arrow indicates the direction of the electric field. The first voltage of the first electrode line 31 and the second voltage of the pixel electrode 33 form a first electric field. Liquid crystal molecules in the first electric field deflect in one direction. The second voltage of the pixel electrode 33 and the third voltage of the second electrode line 32 form a second electric field, and liquid crystal molecules in the second electric field deflect in the same direction. That is, the first electric field and the second electric field constitute a gradient electric field. In the gradient electric field, liquid crystal molecules in the liquid crystal layer 50 corresponding to the same pixel electrode 33 deflect in the same direction, thereby reducing the risk of liquid crystal molecule deflection disorder in the alignment process and improving alignment dark lines.
[0044] Figure 3The diagram shows two sub-pixels 11, one of which corresponds to a pixel electrode 33. The liquid crystal molecules in the first sub-pixel 11 are all tilted to the right, while the liquid crystal molecules in the second sub-pixel 11 are all tilted to the left. This means that the liquid crystal molecules in the same sub-pixel 11 have the same deflection direction, thereby reducing the risk of liquid crystal molecule deflection disorder during the alignment process and improving alignment dark lines.
[0045] Optionally, such as Figures 4 to 6 As shown, the voltage divider module 21 includes at least one first transistor 211. The first transistor 211 includes a first source 2111, a first drain 2112, and a first gate 2113. The first source 2111 of the first transistor 211 is shorted to the first gate 2113 of the same first transistor 211. The first drain 2112 of the first transistor 211 located near the data line 231 in the voltage divider module 21 is electrically connected to the data line 231.
[0046] The first transistor 211 also includes a first active portion 2114, one end of which is connected to the first source 2111, and the other end of which is connected to the first drain 2112.
[0047] In some embodiments, the material of the first active part 2114 is a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, metal oxide, etc.
[0048] In some embodiments, such as Figure 5 and Figure 6 As shown, the voltage divider module 21 includes at least one first transistor 211. For example, the voltage divider module 21 may include one, two, three, four, or other numbers of first transistors 211.
[0049] In some embodiments, the first transistor 211 can be an N-type transistor. By adjusting the channel length of the first transistor 211, the conduction performance of the first transistor 211 can be adjusted. Since there is voltage loss when the first transistor 211 is turned on, the first transistor 211 acts like a resistor, thus playing a voltage divider role.
[0050] In other embodiments, the voltage divider module 21 may also be a resistor, which may be a semiconductor material, such as monocrystalline silicon or polycrystalline silicon.
[0051] like Figure 5 and Figure 6 As shown, the first source 2111 of the first transistor 211 is shorted to the first gate 2113 of the same first transistor 211. This means that for any given first transistor 211, the potential of the first gate 2113 is the same as the potential of the first source 2111, i.e., V0. GSThe value is 0. Through the above settings, the V of the first transistor 211 can be set to 0. GS The conductivity of the first transistor 211 remains unchanged regardless of fluctuations in the input voltage of the circuit, ensuring that its channel conduction capability is determined solely by its own structural parameters. This gives the first transistor 211 a resistor-like function with stable impedance. Structural parameters include the channel aspect ratio and carrier mobility, among others.
[0052] In some embodiments, the structural parameters of any one of the first transistors 211 are the same, so that the voltage can be evenly distributed among the multiple first transistors 211.
[0053] like Figure 6 As shown, Figure 6 yes Figure 5 The equivalent circuit diagram of voltage divider module 21 in the diagram. Figure 6 The following explanation uses two first transistors 211 as an example. The first first transistor 211 is named TFT1, and the second first transistor 211 is named TFT2. The first source 2111 of TFT1 is named S1, the first gate 2113 of TFT1 is named G1, and the first drain 2112 of TFT1 is named D1. The first source 2111 of TFT2 is named S2, the first gate 2113 of TFT2 is named G2, and the first drain 2112 of TFT2 is named D2.
[0054] like Figure 6 As shown, the first voltage is divided into the second voltage by TFT1 and TFT2. In TFT1, G1 and S1 are shorted, and both G1 and S1 are the first voltage. The voltage output by D1 of TFT1 is used as the voltage between S2 and G2 of TFT2. After being output by D2 of TFT2, it becomes the second voltage. The second voltage is transmitted to the pixel electrode 33 by D2 via data line 231. In other words, the voltage divider module 21 converts the original first voltage into the second voltage and then transmits it to the pixel electrode 33.
[0055] It should be noted that when the voltage divider module 21 has only one first transistor 211, D1 is connected to the data line 231. When the voltage divider module 21 has multiple first transistors 211, only the first drain 2112 of the last first transistor 211 is connected to the data line 231. In the other two adjacent first transistors 211, the first drain 2112 of the preceding first transistor 211 is connected to the first source 2111 of the following first transistor 211. "Previous" and "following" refer to the order in which current flows through the voltage divider module 21. For example, TFT1 is the preceding first transistor 211, and TFT2 is the following first transistor 211.
[0056] Optionally, such as Figure 7As shown, the driving circuit layer 20 includes a first metal layer 22 and a second metal layer 23 located on the side of the first metal layer 22 away from the first substrate 10; wherein, the first gate 2113 is located in the first metal layer 22, the first source 2111 and the first drain 2112 are located in the second metal layer 23, and the display panel 1 also includes a first connection trace 221, which is located in the first metal layer 22. The first connection trace 221 is electrically connected to the first drain 2112 at one end near the first transistor 211, and the first connection trace 221 is electrically connected to the data line 231 at one end near the data line 231. The data line 231 is located in the second metal layer 23.
[0057] In some embodiments, the first metal layer 22 and the second metal layer 23 are both conductive materials, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.
[0058] In some embodiments, such as Figure 7 As shown, the first source 2111 and the first drain 2112 are both located in the second metal layer 23, and the data line 231 is also located in the second metal layer 23, that is, the first source 2111, the first drain 2112 and the data line 231 are all arranged in the same layer.
[0059] The first connection trace 221 is located on the first metal layer 22, meaning that the first source 2111, the first drain 2112, and the data line 231 are all on different layers from the first connection trace 221. Since there is an insulating layer between the first metal layer 22 and the second metal layer 23, and the side of the second metal layer 23 furthest from the first substrate 10 also has an insulating layer, this arrangement allows the first connection trace 221 to be closer to the first substrate 10 in the thickness direction of the display panel 1. This results in a greater number of insulating film layers above the first connection trace 221, reducing the risk of corrosion to the first connection trace 221.
[0060] In some embodiments, the insulating layer may be made of silicon oxide, silicon nitride, silicon oxynitride, etc.
[0061] The first connection trace 221 is electrically connected to the first drain 2112 at one end near the first transistor 211, and electrically connected to the data line 231 at the other end. The data line 231 is located in the second metal layer 23. This means that one end of the first connection trace 221 is used to connect to the first drain 2112 of the last first transistor 211 in the voltage divider module 21, and the other end of the first connection trace 221 is used to connect to the data line 231.
[0062] Optionally, such as Figure 7As shown, the display panel 1 also includes a second connection trace 222, which is located in the first metal layer 22. One end of the second connection trace 222 near the first transistor 211 is connected to the first gate 2113, and the other end of the second connection trace 222 away from the first transistor 211 extends to the edge of the first substrate 10.
[0063] In some embodiments, the second connection trace 222 is located on the first metal layer 22. With the above arrangement, the number of insulating film layers above the second connection trace 222 can be increased, which can reduce the risk of corrosion of the second connection trace 222.
[0064] It should be understood that when two conductive materials of different layers are connected, the conductive materials of the upper and lower layers can be made conductive through a via, thereby achieving an electrical connection.
[0065] In some embodiments, the end of the second connection trace 222 near the first transistor 211 is connected to the first gate 2113, and the end of the second connection trace 222 away from the first transistor 211 extends to the edge of the first substrate 10. It should be noted that during the manufacturing process, the display panel 1 is not fabricated individually, but rather multiple display panels 1 are grouped together on a motherboard. Circuitry is disposed on the motherboard to provide each display panel 1 with the first and third voltages required for the alignment process. After the manufacturing process is completed, each display panel 1 is cut off from the motherboard to form an independent display panel 1. Since the second connection trace 222 needs to be connected to the circuitry in the motherboard to input the first voltage to the display panel 1, the second connection trace 222 needs to extend to the edge of the first substrate 10. That is to say, the end of the second connection trace 222 away from the first transistor 211 is approximately flush with the sidewall of the first substrate 10.
[0066] Optionally, such as Figure 5 and Figure 6 As shown, the voltage divider module 21 includes at least two first transistors 211, with two adjacent first transistors 211 connected in series.
[0067] In some embodiments, the number of first transistors 211 in the voltage divider module 21 can be adjusted according to the magnitude of the voltage to be shared. Each first transistor 211 can share the same voltage, achieving voltage equalization.
[0068] It should be noted that the first transistor 211 being connected in series means that in two adjacent first transistors 211, the first drain 2112 of the first first transistor 211 is connected to the first source 2111 of the second first transistor 211.
[0069] Optionally, such as Figure 5 and Figure 7As shown, the electrode layer 30 also includes a connection block 34 located in the non-display area NA. The connection block 34 is connected to the first source 2111 of the first transistor 211 through at least one via, and the connection block 34 is connected to the first gate 2113 of the same first transistor 211 through another via. The connection block 34 can achieve a short circuit between the first gate 2113 and the first source 2111 of the same first transistor 211.
[0070] In some embodiments, such as Figure 7 As shown, the connector 34 can be located on the electrode layer 30, meaning the connector 34 can be disposed on the same layer as the pixel electrode 33. The material of the electrode layer 30 is usually a transparent metal oxide. Transparent metal oxides have better corrosion resistance than metals, which can reduce the risk of corrosion of the connector 34.
[0071] Optionally, such as Figure 2 and Figure 4 As shown, the non-display area NA includes the bonding area BA. The voltage divider module 21 and the bonding area BA are located on the same side of the display area AA, and the voltage divider module 21 is located on the side of the bonding area BA away from the display area AA.
[0072] In some embodiments, such as Figure 2 As shown, the non-display area NA includes a bonding area BA, which can be used to connect to a bonding component. The bonding area BA includes multiple bonding terminals 213, which may include multiple layers of conductive layers. For example, the conductive layers may be formed by stacking at least two of a first metal layer 22, a second metal layer 23, and an electrode layer 30. Adjacent conductive layers are in direct contact and conductive. Specifically, a groove can be cut in the insulating layer between adjacent conductive layers to allow direct contact between the adjacent conductive layers.
[0073] It should be noted that, as Figure 4 As shown, a segment of the first connection trace 221 can be reused as a conductive layer, meaning that the bonding terminal 213 is electrically connected to the first connection trace 221. After the manufacturing process is completed, the display panel 1 is independent, and the voltage divider module 21 is no longer used for the alignment process. The bonding component is connected to the data line 231 through the first connection trace 221, thereby providing pixel drive signals to the pixel electrode 33.
[0074] In some embodiments, such as Figure 2 As shown, the bonding components include a flip-chip film 61 and a printed circuit board 62. The end of the flip-chip film 61 closest to the display panel 1 is connected to the bonding terminal 213, and the end of the flip-chip film 61 furthest from the display panel 1 is connected to the printed circuit board 62. The number of flip-chip films 61 can be set as needed.
[0075] like Figure 4As shown, the voltage divider module 21 is located on the side of the bonding terminal 213 away from the display area AA. This arrangement prevents the voltage divider module 21 from affecting the signal transmission between the bonding area BA and the display area AA after the display panel 1 is separated from the motherboard. After the manufacturing process is completed, the display panel 1 is independent, and the drive signal in the bonding component is provided to the pixel electrode 33 via the data line 231, providing pixel voltage to the pixel electrode 33.
[0076] Optionally, combined Figure 2 and Figure 3 The first electrode line 31 overlaps with the odd-numbered data lines 231 in the thickness direction of the display panel 1, and the second electrode line 32 overlaps with the even-numbered data lines 231 in the thickness direction of the display panel 1.
[0077] It should be noted that, Figure 2 To facilitate the distinction between the first electrode line 31 and the second electrode line 32, the first electrode line 31 is shown as a thick solid line, and the second electrode line 32 is shown as a thin solid line. The thick and thin solid lines are for illustrative purposes only and are unrelated to the actual width of the traces.
[0078] In some embodiments, combined with Figure 2 , Figure 3 and Figure 7 A data line 231 can correspond to a column of pixel electrodes 33. A data line 231 can provide a signal to the pixel electrodes 33 in the same column.
[0079] In some embodiments, the first electrode line 31 overlaps with the odd-numbered data lines 231 in the thickness direction of the display panel 1, and the second electrode line 32 overlaps with the even-numbered data lines 231 in the thickness direction of the display panel 1. That is to say, the first electrode line 31 can correspond to the odd-numbered data lines 231, and the second electrode line 32 can correspond to the even-numbered data lines 231.
[0080] It should be noted that the first electrode line 31 and its corresponding data line 231 may completely overlap or partially overlap. The second electrode line 32 and its corresponding data line 231 may completely overlap or partially overlap.
[0081] In some embodiments, the width of the first electrode line 31 may be greater than or equal to the width of the data line 231. The first electrode line 31 may cover the data line 231 in the width direction, thereby multiplexing the first electrode line 31 as a DBS (Data BM Less, data line 231 without black matrix) line. The width of the first electrode line 31 refers to the size of the first electrode line 31 in the direction perpendicular to the first direction D1, and the width of the data line 231 refers to the size of the data line 231 in the direction perpendicular to the first direction D1.
[0082] In some embodiments, the width of the second electrode line 32 may be greater than or equal to the width of the data line 231, and the second electrode line 32 may cover the data line 231 in the width direction, thereby multiplexing the second electrode line 32 as a DBS line. The width of the second electrode line 32 refers to the dimension of the second electrode line 32 in the direction perpendicular to the first direction D1.
[0083] Optionally, the electrode layer 30 includes a third connection trace 35 and a fourth connection trace 36, wherein any first electrode line 31 is connected to the third connection trace 35, and any second electrode line 32 is connected to the fourth connection trace 36.
[0084] like Figure 2 As shown, the third connecting trace 35 can extend along the second direction D2, the fourth connecting trace 36 can extend along the fourth direction, and the second direction D2 can be perpendicular to the first direction D1.
[0085] By connecting any of the first electrode lines 31 to the third connection trace 35, the uniformity of the voltage on the first electrode lines 31 can be improved, and excessive voltage drop across multiple first electrode lines 31 can be avoided.
[0086] By connecting any of the second electrode lines 32 to the fourth connection trace 36, the uniformity of the voltage on the second electrode lines 32 can be improved, and excessive voltage drop across multiple second electrode lines 32 can be avoided.
[0087] Optionally, such as Figure 2 As shown, the third connection trace 35 and the fourth connection trace 36 are both located in the non-display area NA, and the third connection trace 35 and the fourth connection trace 36 are located on opposite sides of the display area AA. One of the third connection trace 35 and the fourth connection trace 36 is located on the same side of the display area AA as the voltage divider module 21.
[0088] In some embodiments, the third connection trace 35 and the fourth connection trace 36 may be located in the non-display area NA, thereby avoiding the third connection trace 35 and the fourth connection trace 36 occupying the area of the display area AA.
[0089] In some embodiments, the third connection trace 35 may be located on the same side of the display area AA as the voltage divider module 21, that is, the third connection trace 35 is located on the lower edge of the display panel 1, and the fourth connection trace 36 is located on the upper edge of the display panel 1.
[0090] In some embodiments, such as Figure 2 As shown, the fourth connection trace 36 can be located on the same side of the display area AA as the voltage divider module 21, that is, the fourth connection trace 36 is located on the lower edge of the display panel 1, and the third connection trace 35 is located on the upper edge of the display panel 1.
[0091] Optionally, such as Figure 2As shown, both the third connection trace 35 and the fourth connection trace 36 extend to the edge of the first substrate 10. With this configuration, the third connection trace 35 can be connected to the circuitry on the motherboard, and the fourth connection trace 36 can be connected to the circuitry on the motherboard. Thus, in the alignment process, a first voltage is input to the first electrode line 31 through the third connection trace 35, and a third voltage is input to the second electrode line 32 through the fourth connection trace 36, thereby creating a gradient electric field between the first electrode line 31, the pixel electrode 33, and the second electrode line 32.
[0092] Optionally, such as Figure 7 As shown, the driving circuit layer 20 also includes a second transistor 212 located in the display area AA. The second transistor 212 includes a second source 2121 and a second drain 2122. The second source 2121 is electrically connected to the data line 231, and the second drain 2122 is electrically connected to the pixel electrode 33.
[0093] The second transistor 212 further includes a second active portion 2124, one end of which is connected to the second source 2121, and the other end of which is connected to the second drain 2122. The material of the second active portion 2124 is a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, or metal oxide. The second active portion 2124 can be disposed on the same layer as the first active portion 2114. The second transistor 212 also includes a second gate 2123, which can be disposed on the same layer as the first gate 2113, thereby simplifying the manufacturing process of the display panel 1.
[0094] In some embodiments, the second transistor 212 may be a transistor in a pixel driving circuit. The second source 2121 is connected to the data line 231, and the second drain 2122 is electrically connected to the pixel electrode 33, thereby inputting a second voltage to the pixel electrode 33 during the alignment process.
[0095] According to the second aspect of this application, such as Figure 8 As shown, a display terminal 2 is provided, including the display panel 1 described above.
[0096] In this embodiment, as Figure 8 As shown, the display terminal 2 includes a display panel 1 and a backlight module 3, which are combined into one unit.
[0097] In this embodiment, the display terminal 2 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.
[0098] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0099] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0100] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0101] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A display panel, characterized in that, The display panel includes a display area and a non-display area disposed around the periphery of the display area. First substrate; A driving circuit layer is disposed on one side of the first substrate. The driving circuit layer includes a voltage divider module disposed in the non-display area and a data line disposed in the display area. The data line extends along a first direction. An electrode layer is disposed on the side of the driving circuit layer away from the first substrate. The electrode layer includes a first electrode line, a second electrode line, and a pixel electrode. The first electrode line and the second electrode line both extend along the first direction. Each column of pixel electrodes is located between the first electrode line and the second electrode line. The first electrode line or the second electrode line is disposed between any two adjacent columns of pixel electrodes. The voltage divider module is electrically connected to the pixel electrode via the data line.
2. The display panel according to claim 1, characterized in that, The voltage divider module includes at least one first transistor, the first transistor including a first source, a first drain and a first gate, the first source of the first transistor being shorted to the first gate of the same first transistor, and the first drain of the first transistor in the voltage divider module near the data line being electrically connected to the data line.
3. The display panel according to claim 2, characterized in that, The driving circuit layer includes a first metal layer and a second metal layer located on the side of the first metal layer away from the first substrate; The first gate is located in the first metal layer, the first source and the first drain are located in the second metal layer, and the display panel further includes a first connection trace located in the first metal layer. The first connection trace is electrically connected to the first drain at one end near the first transistor, and electrically connected to the data line at one end near the data line. The data line is located in the second metal layer.
4. The display panel according to claim 3, characterized in that, The display panel further includes a second connection trace located in the first metal layer. The end of the second connection trace near the first transistor is connected to the first gate, and the end of the second connection trace away from the first transistor extends to the edge of the first substrate.
5. The display panel according to claim 2, characterized in that, The voltage divider module includes at least two of the first transistors, with two adjacent first transistors connected in series.
6. The display panel according to claim 2, characterized in that, The electrode layer further includes a connection block located in the non-display area, the connection block being connected to the first source of the first transistor through at least one via, and the connection block being connected to the first gate of the same first transistor through another via.
7. The display panel according to claim 1, characterized in that, The non-display area includes a binding area, the voltage divider module and the binding area are located on the same side of the display area, and the voltage divider module is located on the side of the binding area away from the display area.
8. The display panel according to any one of claims 1 to 7, characterized in that, The first electrode line overlaps with the odd-numbered data lines in the thickness direction of the display panel, and the second electrode line overlaps with the even-numbered data lines in the thickness direction of the display panel.
9. The display panel according to any one of claims 1 to 7, characterized in that, The electrode layer includes a third connection trace and a fourth connection trace, wherein each of the first electrode lines is connected to the third connection trace, and each of the second electrode lines is connected to the fourth connection trace.
10. The display panel according to claim 9, characterized in that, Both the third and fourth connection traces are located in the non-display area, and the third and fourth connection traces are arranged on opposite sides of the display area. One of the third and fourth connection traces is located on the same side of the display area as the voltage divider module.
11. The display panel according to claim 9, characterized in that, Both the third and fourth connection traces extend to the edge of the first substrate.
12. The display panel according to claim 1, characterized in that, The driving circuit layer further includes a second transistor located in the display area. The second transistor includes a second source and a second drain. The second source is electrically connected to the data line, and the second drain is electrically connected to the pixel electrode.
13. A display terminal, characterized in that, Includes the display panel as described in any one of claims 1 to 12.