Data storage device and method for avoiding return of zero to host

Abstract

A data storage device and method for avoiding returning zero to a host are provided. In one embodiment, a data storage device is provided that includes a memory and one or more processors. The one or more processors, individually or in combination, are configured to: receive a command from a host to read data stored in a logical address of the memory; determining whether the data includes all zeros; and in response to determining that the data includes all zero, providing an indication to the host that the data includes all zero, rather than sending the data to the host. Other embodiments are disclosed.

Description

Background Technology

[0001] The Non-Volatile Memory Fast (NVMe) specification defines the "Write Zeros" command. When a host sends a Write Zeros command to a data storage device, the data storage device marks the logical address range specified in the command as zero, rather than actually writing zeros into the data storage device's memory. If the host later sends a read command to the data storage device specifying a logical address within that range, the data storage device abandons the read from memory and simply returns zeros to the host, as if those zeros were actually read from memory. Attached Figure Description

[0002] Figure 1A This is a block diagram of the data storage device in the implementation scheme.

[0003] Figure 1B This is a block diagram illustrating the storage module of an example implementation.

[0004] Figure 1C This is a block diagram illustrating a hierarchical storage system for an example implementation.

[0005] Figure 2A This is an example based on the implementation plan. Figure 1A The diagram shows a block diagram of the controller components of the data storage device.

[0006] Figure 2B This is an example based on the implementation plan. Figure 1A The diagram shows the components of the data storage device.

[0007] Figure 3 This is a block diagram of the host and data storage devices in the implementation scheme.

[0008] Figure 4 This is an example of the architecture of the implementation plan.

[0009] Figure 5 This is a flowchart of the implementation method.

[0010] Figure 6 It is a graph of the implementation plan. Detailed Implementation

[0011] The following embodiments generally relate to a data storage device and method for avoiding returning zeros to a host. In one embodiment, a data storage device including memory and one or more processors is provided. The one or more processors are configured individually or in combination to: receive from a host a command to read data stored at a logical address in the memory; determine whether the data includes all zeros; and, in response to determining that the data includes all zeros, provide an indication to the host that the data includes all zeros, instead of sending the data to the host.

[0012] In some implementations, the one or more processors are further configured individually or in combination to send the data to the host in response to determining that the data does not contain all zeros.

[0013] In some implementations, providing the instruction to the host includes writing a status code to a completion queue.

[0014] In some implementations, the host is configured to interpret the status code to generate zero that was not sent to the host by the data storage device.

[0015] In some implementations, providing the instruction to the host includes using a compressed form that indicates the location of the zero.

[0016] In some implementations, determining whether the data includes all zeros involves reading the physical location in the memory mapped to the logical address and determining whether the physical location stores all zeros.

[0017] In some implementations, determining whether the data includes all zeros includes determining whether the logical address is mapped to a physical location in the memory.

[0018] In some implementations, this data is associated with a large language model.

[0019] In some implementations, the data includes all data stored at that logical address.

[0020] In some implementations, the data includes data segments stored in the logical address.

[0021] In some implementations, the one or more processors are further configured individually or in combination to receive the size of the data segment from the host.

[0022] In some implementations, the memory includes a three-dimensional memory.

[0023] In another embodiment, a method is provided to be performed in a data storage device including memory. The method includes: receiving from a host a command for reading data stored at a logical address in the memory; determining whether the data includes all zeros; in response to determining that the data does not include all zeros, sending the data to the host; and in response to determining that the data includes all zeros, abandoning the sending of the data to the host.

[0024] In some implementations, the method further includes: in response to determining that the data includes all zeros, providing the host with an indication that the data includes all zeros.

[0025] In some implementations, providing the instruction to the host includes writing a status code into a completion queue, and wherein the host is configured to interpret the status code to generate zeros not sent to the host by the data storage device.

[0026] In some implementations, the host is configured to allocate a buffer initialized with zero values ​​to the data storage device, thus abandoning the transmission of the data to the host, which would generate an indication that the data includes all zeros.

[0027] In some implementations, the method further includes determining whether the data includes all zeros by reading the physical location in the memory mapped to the logical address and determining whether the physical location stores all zeros.

[0028] In some implementations, determining whether the data includes all zeros includes determining whether the logical address is mapped to a physical location in the memory.

[0029] In some implementations, the method further includes sending the host a bitmap of which Physical Region Page (PRP) list entries to skip or a bitmap of which Distributed Cluster List (SGL) ranges to skip.

[0030] In another embodiment, a data storage device is provided, comprising: a memory; and means for: receiving from a host a request for data stored in the memory; determining whether all data includes the same value; and, in response to determining that all data includes the same value, providing the host with an indication that all data includes the same value, instead of sending the data to the host.

[0031] Other implementations are possible, and each implementation can be used alone or in combination. Therefore, various implementations will now be described with reference to the accompanying drawings.

[0032] Implementation Plan

[0033] The following implementation relates to a data storage device (DSD). As used herein, a "data storage device" refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid-state drives (SSDs), tape drives, hybrid drives, etc. Details of example DSDs are provided below.

[0034] Figures 1A to 1C Examples of data storage devices suitable for implementing these implementation schemes are shown below. It should be noted that these are merely examples and other specific implementations may be used. Figure 1A This is a block diagram illustrating a data storage device 100 according to an implementation scheme. (See reference) Figure 1A In this example, the data storage device 100 includes a controller 102 coupled to non-volatile memory, which may consist of one or more non-volatile memory dies 104. As used herein, the term die refers to a collection of non-volatile memory cells formed on a single semiconductor substrate and associated circuitry for managing the physical operations of those non-volatile memory cells. The controller 102 interfaces with a host system and transmits sequences of commands to the non-volatile memory die 104 for read, program, and erase operations. Furthermore, as used herein, the phrases “communicating with” or “coupled with” may mean directly communicating / coupling with or indirectly communicating / coupling with (or through) one or more components, which may or may not be shown or described herein. The communication / coupling may be wired or wireless.

[0035] Controller 102 (which may be a non-volatile memory controller (e.g., flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM) controller)) may include one or more components that are individually or in combination configured to perform certain functions, including but not limited to the functions described herein and illustrated in the flowcharts. For example, such as Figure 2A As shown, controller 102 may include one or more processors 138, which are individually or in combination configured to perform functions, such as, but not limited to, the functions described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-transitory memories 139 internal to controller 102 and / or external to controller 102 (e.g., in random access memory (RAM) 116 or read-only memory (ROM) 118). Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0036] In one example implementation, a nonvolatile memory controller 102 is a device that manages data stored on nonvolatile memory and communicates with a host (such as a computer or electronic device) having any suitable operating system. The nonvolatile memory controller 102 may have various functionalities beyond those described herein. For example, the nonvolatile memory controller may format the nonvolatile memory to ensure proper operation, map faulty nonvolatile memory cells, and allocate spare cells to replace future failed cells. A portion of the spare cells may be used to maintain firmware (and / or other metadata for housekeeping and tracking) to operate the nonvolatile memory controller and implement other features. In operation, the host may communicate with the nonvolatile memory controller when it needs to read data from or write data to the nonvolatile memory. If the host provides a logical address for reading / writing data, the nonvolatile memory controller may translate the logical address received from the host into a physical address in the nonvolatile memory. The non-volatile memory controller can also perform a variety of memory management functions, such as, but not limited to, wear leveling (spreading writes to avoid exhausting specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (moving only valid data pages to new blocks after a block is full, so that the full block can be erased and reused).

[0037] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may be in the form of solid-state (e.g., flash memory) memory cells and may be one-time programmable, few-time programmable, or multiple-time programmable. The memory cells may also be single-level cells (SLC), multi-level cells (MLC) (e.g., two-level cells, three-level cells (TLC), four-level cells (QLC), etc.) or may use other memory cell hierarchy technologies now known or developed hereafter. Furthermore, the memory cells may be fabricated in two or three dimensions.

[0038] The interface between controller 102 and non-volatile memory die 104 can be any suitable flash memory interface, such as Toggle Mode 200, 400, or 800. In one embodiment, data storage device 100 can be a card-based system, such as a Secure Digital (SD) or Micro-Secure Digital (micro-SD) card. In another embodiment, data storage device 100 can be part of an embedded data storage device.

[0039] Despite Figure 1AIn the illustrated example, data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between controller 102 and non-volatile memory die 104, but the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as...) Figure 1B and Figure 1C In the architecture shown, depending on the controller's capabilities, there may be two, four, eight, or more memory channels between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the figure, there may be more than a single channel between the controller and the memory die.

[0040] Figure 1B An example is illustrated of a storage module 200 comprising multiple non-volatile data storage devices 100. Therefore, the storage module 200 may include a storage controller 202 that interfaces with a host and with a data storage device 204 comprising the multiple data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Interconnect Fast (PCIe) interface, a Double Data Rate (DDR) interface, or a Serial Attached Small Scale Computing Interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptops and tablets.

[0041] Figure 1C This is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes multiple storage controllers 202, each controlling a corresponding data storage device 204. A host system 252 can access the memory within the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Fast (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, Figure 1C The illustrated system may be a rack accessible to multiple host computers that can house a massive storage system, such as in a data center or other location requiring massive storage devices.

[0042] Refer again Figure 2AThe controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, such as, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls the internal bus arbitration of controller 102. Modules may include one or more processors or components, as discussed above. ROM 118 may store system boot code. Although in Figure 2A The RAM 116 is illustrated as being located separately from the controller 102, but in other embodiments, one or both of the RAM 116 and ROM 118 may be located within the controller 102. In still other embodiments, portions of the RAM 116 and ROM 118 may be located both inside and outside the controller 102.

[0043] Front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface to the host or next-layer storage controller. The type of host interface 120 may be selected depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Fast, Serial Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. Host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0044] Backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and corrects errors in data bytes read from the non-volatile memory. Command sequencer 126 generates a sequence of commands, such as programming and erasing command sequences, to be transferred to the non-volatile memory die 104. RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of faulty data. RAID parity can be used as an additional level of integrity protection for data being written to memory device 104. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, memory interface 130 may be a Double Data Rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. The controller 102 in this example also includes a media management layer 137 and a flash control layer 132, which controls the overall operation of the back-end module 110.

[0045] The data storage device 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer area management / bus controller are optional components that are not necessary in the controller 102.

[0046] Figure 2B This is a block diagram illustrating the components of a non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells and / or NOR flash memory cells arranged in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 also includes a data cache 156 that caches data and address decoders 148, 150. In this example, the peripheral circuitry 141 includes a state machine 152 that provides state information to the controller 102. The peripheral circuitry 141 may also include one or more components that are individually or in combination configured to perform certain functions, including but not limited to the functions described herein and illustrated in the flowchart. For example, as... Figure 2B As shown, the memory die 104 may include one or more processors 168, which are individually or in combination configured to execute computer-readable program code stored in one or more non-transitory memories 169, in the memory array 142, or external to the memory die 104. Alternatively, the one or more components may include circuitry, such as, but not limited to, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0047] In addition to or replacing one or more processors 138 (or more generally, components) in controller 102 and one or more processors 168 (or more generally, components) in memory die 104, data storage device 100 may include another set of one or more processors (or more generally, components). Generally, regardless of their location or number, one or more processors (or more generally, components) in data storage device 100 may be configured individually or in combination to perform various functions, including but not limited to those described herein and illustrated in the flowcharts. For example, one or more processors (or components) may be located in other locations within controller 102, memory device 104, and / or data storage device 100. Furthermore, different processors (or components) or combinations of processors (or components) may be used to perform different functions. Additionally, means for performing functions may be implemented using a controller that includes one or more components (e.g., processors or other components described above).

[0048] Return to reference Figure 2A The flash control layer 132 (which will be referred to herein as the flash translation layer (FTL)) handles flash errors and interfaces with the host. Specifically, the FTL (which may be an algorithm in the firmware) is responsible for the internal organization of memory management and translates writes from the host into writes to memory 104. An FTL may be necessary because memory 104 may have limited endurance, may only be written in multi-page format, and / or may be unwritable unless it is erased as a block. The FTL understands these potential limitations of memory 104, which may be invisible to the host. Therefore, the FTL attempts to translate writes from the host into writes to memory 104.

[0049] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses (“LBA”) from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-off recovery (enabling the recovery of the FTL’s data structures in the event of a sudden power failure) and wear leveling (ensuring uniform wear across memory blocks to prevent certain blocks from becoming excessively worn, which would lead to a greater chance of failure).

[0050] Turning back to the attached image, Figure 3This is a block diagram of a host 300 and a data storage device 100 according to an embodiment. The host 300 can take any suitable form, including but not limited to a computer, mobile phone, tablet device, wearable device, digital video recorder, surveillance system, etc. In this embodiment, the host 300 (here, a computing device) includes one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform actions described herein as being performed by the host 300. Therefore, actions performed by the host 300 are sometimes referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0051] PCIe / NVMe commands from the host typically use a series of queues (e.g., commit and complete queues) for commit and completion. When an input / output (I / O) command is executed, the data storage device's controller may perform a direct memory access (DMA) transfer across the PCIe bus and then complete the command by writing to a complete queue in the host's memory. The NVMe command "Write Zeros" can be used to set a logical block range to zero. After successful completion of the command, subsequent reads of logical blocks within that range will clear all bytes to 0h until a write to that range occurs.

[0052] If the Write-Zeros-Size-Limit (WZSL) field in the identifier controller data structure is set to a non-zero value, and if bit 3 of the Optional NVMe Command Support (ONCS) field in the identifier controller data structure is set to "1", the WZSL field indicates the recommended maximum data size for Write Zeros commands, and any Write Zeros command whose data size exceeds this recommended maximum value for a specified logical block range may encounter delays in processing. Additionally, if the Write-Zeros-Size-Limit (WZSL) field in the identifier controller data structure is set to a non-zero value, and if bit 3 of the ONCS field is cleared to "0", the WZSL field indicates a data size limit for Write Zeros commands, and the controller will use the status of invalid fields in the command to abort any Write Zeros command whose data size exceeds this limit for a specified logical block range.

[0053] When the host sends a Write Zeros command to the data storage device, it implies that the data storage device's controller does not actually write zeros to the data storage device's memory, but rather marks the range. Therefore, when the host requests to read a logical block address range containing zeros, the controller will not actually read from memory, but will return zeros as if they were read from memory. In this way, the data storage device's controller will send zeros to the host as if it were sending balanced data (0s and 1s) that would actually be read from memory.

[0054] The following implementation presents the Reverse-Write-Zeros (RWZ) command. Using this command, when a zero (not pre-marked by the host 300) is read from the memory 104 of the data storage device 100, the controller 102 of the data storage device 100 can simply indicate this to the host 300 and avoid actually transferring the zero to the host 300, thus saving latency and power. This is particularly useful in machine learning-based workloads, such as when loading Large Language Model (LLM) inference and Feedforward Network (FFN) models from memory 104.

[0055] In one example operation of the RWZ command, after a read from memory 104 is completed by the controller 102 of data storage device 100, an indication for a zero batch is sent to host 300, which avoids the actual data transfer of the zero to host 300. This indication can be sent to host 300 in any suitable manner, such as, but not limited to, a status code via the NVMe interface or using a compressed form indicating the location of the zero.

[0056] Turning back to the attached image, Figure 4 This is an example of the architecture of the implementation plan. For example... Figure 4 As shown, in this embodiment, a completion message is stored in a completion queue 400 (which may be stored in the host 300 or the data storage device 100) after the controller 102 of the data storage device 100 executes a command stored in a submission queue (not shown). The controller 102 of the data storage device 100 includes a write-to-zero control module 410, and the host 300 includes a completion queue interpretation module 430. One or more processors 138 of the data storage device may be used individually or in combination to implement the write-to-zero control module 410 by executing computer-readable program code / instructions stored in the memory of the data storage device 100. Similarly, one or more processors 330 of the host may be used individually or in combination to implement the completion queue interpretation module 430 by executing computer-readable program code / instructions stored in one or more memories 340 of the host 300.

[0057] In operation, host 300 sends a read command to data storage device 100, and controller 102 of data storage device 100 determines whether the requested data is all zeros. Controller 102 can determine this by actually reading data from the location in memory 104 associated with the logical block address (LBA) in the read command. Alternatively, controller 102 can make this determination without actually reading memory 104, such as when zero pages are not marked differently in the logical-to-physical address mapping (e.g., in the flash translation layer (FTL) and not mapped to a physical location in non-volatile memory 104). Reverse write zero control module 410 can determine which transfers are unnecessary and skip such unnecessary transfers. New status codes can be added to command completion to indicate that some ranges are skipped in the transfer and should be zeroed by host 300. Furthermore, a bitmap of which Physical Region Page (PRP) list entries or Scattered Cluster List (SGL) ranges are skipped can be returned as part of the metadata transfer or via additional fields in the complete queue entry. Completion queue interpretation module 430 can be used to interpret such entries.

[0058] Figure 5 This is flowchart 500 illustrating the method of operation for this example implementation scheme. For example... Figure 5 As shown, the reverse write-zero control module 410, implemented by controller 102, analyzes the data read from memory 104 (510) and determines for each data segment whether the segment can be RWZ compressed because it contains all zeros (520). If the data segment is a mixed load of one and zero, controller 102 sends the data segment to the memory indicated by host 300 (e.g., host memory 340) (530). However, if the data segment contains all zeros, the reverse write-zero control module 410 writes a special status code indicating that the data segment contains all zeros to completion queue 420 (540). Completion queue interpretation module 430 in host 300 can interpret the special status code to load zeros instead of missing data segments (550).

[0059] Several advantages exist associated with these implementations, such as reduced transfers to host 300 to reduce power consumption and read latency. One such use case is loading large language models (LLMs) from memory 104 (which can be relatively large in size, e.g., tens of gigabytes). For example, the Open Pre-trained (OPT) 6.7B model exhibits a significant 97% sparsity (weight values ​​equal to 0). Other popular models also exhibit similar high sparsity values. Figure 6 As shown in the graph, the Corrected Linear Unit (ReLU) activation function has input values ​​less than zero. This causes many weights to go to zero, thus boosting the values ​​of these implementations, since more sectors going to zero are expected when using this popular activation function in a model. Figure 6It is also shown that the Gaussian error linear unit (GELU) also has input values ​​less than zero.

[0060] Several alternatives can be used with these implementations. For example, in one alternative, the host 300 can control the fragment size via an interface to allow flexibility between potential transfer savings and additional overhead in post-processing. In another alternative, when the host 300 allocates buffers to the data storage device 100, the host 300 can initialize them with zero values. Subsequently, when the controller 102 of the data storage device 100 detects that the data should be “0”, the controller 102 can simply ignore those transactions, assuming the initial value is indeed “0”. This method eliminates the need for changes in the completion phase while effectively reducing unnecessary traffic. Moreover, although these implementations are described in the context of data requested from the host having all zeros, similar methods can be used when all data includes one or some other value. Other alternatives can be used.

[0061] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices (such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices), non-volatile memory devices (such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which is considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”)) and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either NAND or NOR configurations.

[0062] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements that, in some embodiments, include resistivity-switching storage elements such as antifuses, phase-change materials, and optionally, manipulation elements such as diodes. Further, as a non-limiting example, active semiconductor memory elements include elements that, in some embodiments, include charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials used in EEPROM and flash memory device elements.

[0063] Multiple memory elements can be configured such that they are connected in series or such that each element is individually accessible. As a non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically comprises memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple memory strings, each string consisting of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured such that each element is individually accessible, for example, a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0064] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as two-dimensional memory structures or three-dimensional memory structures.

[0065] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device layer. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane extending substantially parallel to the main surface of the substrate supporting such memory elements (e.g., in the xz plane). The substrate may be a wafer on which the memory element layer is formed, or the substrate may be a carrier substrate attached to the memory elements after the memory elements are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.

[0066] Memory elements can be arranged in an ordered array (e.g., by multiple rows and / or columns) within a single memory device hierarchy. However, memory elements can be arranged irregularly or non-orthogonally. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0067] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device layers, thereby forming a three-dimensional structure (i.e., in the x, y and z directions, where the y direction is substantially perpendicular to the main surface of the substrate and the x and z directions are substantially parallel to the main surface of the substrate).

[0068] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device layers. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate (i.e., in the y-direction), with multiple memory elements in each column. The columns can be arranged in a two-dimensional configuration (e.g., in the xz plane), resulting in a three-dimensional arrangement of memory elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0069] As a non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device layer. Alternatively, memory elements may be coupled together to form vertical NAND strings traversing multiple horizontal memory device layers. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory layer, while others contain memory elements spanning multiple memory layers. The three-dimensional memory array can also be designed with NOR and ReRAM configurations.

[0070] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers located at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device level of the array is typically formed on the layer of the underlying memory device level of the array. However, the layers of adjacent memory device levels in a monolithic three-dimensional memory array may be shared between memory device levels or have an interposer layer.

[0071] Similarly, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory layers on separate substrates and then stacking these memory layers on top of each other. The substrates can be thinned or removed from the memory device layers before stacking, but since the memory device layers are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0072] The operation and communication with memory elements typically require associated circuitry. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0073] Those skilled in the art will recognize that the present invention is not limited to the described two-dimensional and three-dimensional structures, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art.

[0074] The foregoing specific embodiments are intended to be understood as examples of selected forms of the invention, and not as a definition of the invention. Only the following claims (including all equivalents) are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with each other.

Claims

1. A data storage device, the data storage device comprising: Memory; and One or more processors, wherein the one or more processors are configured individually or in combination to: Receive a command from the host to read data stored at the logical address in the memory; Determine whether the data includes all zeros; as well as In response to determining that the data includes all zeros, an indication that the data includes all zeros is provided to the host, instead of sending the data to the host.

2. The data storage device of claim 1, wherein the one or more processors are further configured individually or in combination to: In response to determining that the data does not include all zeros, the data is sent to the host.

3. The data storage device of claim 1, wherein providing the indication to the host includes writing a status code into a completion queue.

4. The data storage device of claim 3, wherein the host is configured to interpret the status code to generate a zero not sent by the data storage device to the host.

5. The data storage device of claim 1, wherein providing the indication to the host includes using a compressed form that displays the position of the zero.

6. The data storage device of claim 1, wherein determining whether the data includes all zeros comprises: Read the physical location in the memory that is mapped to the logical address and determine whether the physical location stores all zeros.

7. The data storage device of claim 1, wherein determining whether the data includes all zeros comprises: Determine whether the logical address is mapped to a physical location in the memory.

8. The data storage device of claim 1, wherein the data is associated with a large language model.

9. The data storage device of claim 1, wherein the data includes all data stored at the logical address.

10. The data storage device of claim 1, wherein the data includes data segments stored in the logical address.

11. The data storage device of claim 10, wherein the one or more processors are further configured individually or in combination to: The size of the data segment received from the host.

12. The data storage device according to claim 1, wherein the memory includes a three-dimensional memory.

13. A method, the method comprising: Execute in a data storage device that includes memory: Receive a command from the host to read data stored at a logical address in the memory; Determine whether the data includes all zeros; In response to determining that the data does not include all zeros, the data is sent to the host; as well as In response to determining that the data includes all zeros, the transmission of the data to the host is abandoned.

14. The method according to claim 13, further comprising: In response to determining that the data includes all zeros, an indication that the data includes all zeros is provided to the host.

15. The method of claim 14, wherein providing the indication to the host comprises writing a status code into a completion queue, and wherein the host is configured to interpret the status code to generate a zero not sent to the host by the data storage device.

16. The method of claim 13, wherein the host is configured to allocate a buffer initialized with zero values ​​to the data storage device, thereby abandoning the transmission of the data to the host to generate an indication that the data includes all zeros.

17. The method of claim 13, wherein determining whether the data includes all zeros comprises: Read the physical location in the memory that is mapped to the logical address and determine whether the physical location stores all zeros.

18. The method of claim 13, wherein determining whether the data includes all zeros comprises: Determine whether the logical address is mapped to a physical location in the memory.

19. The method according to claim 13, further comprising: Send a bitmap to the host of which Physical Region Page (PRP) list entries to skip or which Distributed Cluster List (SGL) ranges to skip.

20. A data storage device, the data storage device comprising: Memory; and Apparatus for performing the following operations: Receive a request from the host for data stored in the memory; Determine if all data includes the same value; and In response to determining that all data includes the same value, an indication is provided to the host that all data includes the same value, instead of sending the data to the host.

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