Memory wear leveling method and electronic equipment
By monitoring the number of ECC error correction bits and setting a risk threshold based on historical erase counts, risky memory blocks are identified and processed, solving the problem of insufficient wear leveling in existing technologies and improving the data reliability and lifespan management of memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-03
AI Technical Summary
Existing wear leveling algorithms cannot promptly detect and process storage blocks that have deteriorated in condition despite low erase counts, leading to data read errors and shortened memory lifespan.
By monitoring the number of ECC error correction bits generated by read data operations, and combining historical erase counts and the maximum ECC error correction capability to dynamically set risk thresholds, risk blocks are identified and preset response operations are executed, such as reducing usage priority or data relocation.
It enables accurate early warning of storage block failure risks, avoids data loss or system crashes, optimizes memory lifespan management, and improves data reliability and lifespan utilization.
Smart Images
Figure CN121785545A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage management technology, and in particular to a wear leveling method and electronic device for a memory. Background Technology
[0002] For non-volatile memories (such as NAND Flash), existing wear leveling algorithms mainly rely on the number of erase and write operations for each memory block in the record memory.
[0003] Traditional wear leveling only focuses on the number of erases, which cannot detect and deal with memory blocks that have deteriorated rapidly despite having a low number of erases in a timely manner. This may lead to sudden data read errors and shorten the lifespan of the memory.
[0004] Therefore, improvements to existing technologies are necessary.
[0005] The above information is provided as background information only to aid in understanding this application and does not constitute an assertion or admission that any of the above content can be used as prior art relative to this application. Summary of the Invention
[0006] This application provides a wear leveling method and electronic device for memory to solve the problem of poor wear leveling in the prior art.
[0007] To achieve the above objectives, this application provides the following technical solution:
[0008] In a first aspect, embodiments of this application provide a wear leveling method for a memory, the memory comprising multiple memory blocks, including:
[0009] When performing a read operation on the current storage block, determine the number of ECC error correction bits generated by the read operation, and the number of historical erases of the current storage block;
[0010] The number of ECC error correction bits is compared with a risk threshold, which is determined based on the number of historical erases and the maximum ECC error correction capability of the memory.
[0011] If the number of ECC error correction bits is greater than the risk threshold, the current storage block is determined to be a risk block, and a preset risk response operation is performed on the risk block.
[0012] Optionally, the risk threshold shall not exceed 75% of the maximum error correction capability of ECC, and the risk threshold shall be inversely proportional to the number of historical erases.
[0013] Optionally, the method for determining the risk threshold includes:
[0014] ;
[0015] in, Risk threshold;
[0016] This represents the historical erase count for the current storage block.
[0017] This is the maximum number of erase cycles allowed.
[0018] This represents the maximum ECC error correction capability of the memory.
[0019] This is the slope coefficient, and its value range is... .
[0020] Optionally, the preset risk response operation includes: lowering the usage priority of the risk block according to a preset method, and / or, moving the data of the risk block;
[0021] The priority is used to indicate the order in which the corresponding storage blocks are selected when writing data tasks are subsequently assigned.
[0022] Optionally, the preset method includes:
[0023] The historical erase count of the aforementioned risk block is forcibly modified to the rated maximum erase count;
[0024] And / or, add a mark to the risk block, the mark being used to identify its lowest usage priority.
[0025] Optionally, the data migration process for the risk block, executed at the current time or a delayed time after the risk block is identified, includes:
[0026] Request a new free block;
[0027] Copy the valid data of the risk block to the free block;
[0028] Update the logical address to physical address mapping table to point the original mapping that pointed to the risk block to the free block;
[0029] Perform an erase operation on the risk block to clear its data;
[0030] The erased risk block is added to the free block list after the maximum number of erases.
[0031] Secondly, embodiments of this application provide an electronic device, including:
[0032] The memory includes multiple memory blocks;
[0033] The wear leveling module is used to determine the number of ECC error correction bits generated by the read data operation and the historical erase count of the current storage block when performing a read data operation on the current storage block; compare the number of ECC error correction bits with a risk threshold, which is determined based on the historical erase count and the maximum ECC error correction capability of the memory; if the number of ECC error correction bits is greater than the risk threshold, the current storage block is determined to be a risk block, and a preset risk response operation is performed on the risk block.
[0034] Optionally, the wear leveling module, in performing preset risk response operations on the risk block, is specifically used to: lower the usage priority of the risk block according to a preset method, and / or to move the data of the risk block; wherein the usage priority is used to indicate the order in which the corresponding storage blocks are selected when subsequent write data tasks are allocated.
[0035] Thirdly, embodiments of this application provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the memory wear leveling method described in any of the above claims.
[0036] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions thereon, which are executed by a computer processor to implement the memory wear leveling method described in any of the above claims.
[0037] Compared with existing technologies, this application introduces the number of ECC error correction bits as a real-time monitoring indicator of the health status of storage blocks, and dynamically sets risk thresholds by combining historical erase counts and maximum ECC error correction capability. Compared with the traditional approach that relies solely on the number of erase counts as a reference indicator, this approach achieves accurate early warning of storage block failure risks and has the following beneficial effects:
[0038] It can detect and isolate storage blocks that are deteriorating in advance, avoiding data loss or system crashes caused by sudden errors;
[0039] It can improve data reliability by eliminating storage blocks before they approach the limits of ECC error correction.
[0040] Memory lifetime management has been optimized to make it more accurate and reliable, fully utilizing the potential of each block while avoiding high-risk use.
[0041] This application has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of this application. Attached Figure Description
[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 This is a flowchart of a wear leveling method for memory provided in an embodiment of this application. Detailed Implementation
[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0045] Please refer to Figure 1 This application provides a wear leveling method for a memory, the memory comprising multiple memory blocks, including:
[0046] S1. When performing a read operation on the current storage block, determine the number of ECC error correction bits generated by the read operation, as well as the number of historical erases of the current storage block.
[0047] S2. Compare the number of ECC error correction bits with a risk threshold, which is determined based on the number of historical erases and the memory's maximum ECC error correction capability.
[0048] S3. If the number of ECC error correction bits is greater than the risk threshold, the current storage block is determined to be a risk block, and a preset risk response operation is performed on the risk block.
[0049] Currently, flash memory possesses many superior characteristics unmatched by traditional hard drives, such as small size, large capacity, non-volatility, and low power consumption. The flash memory controller must incorporate error-correcting code (ECC) circuitry to protect the data and enable data recovery within a certain error range. Data is encoded simultaneously with the data area of the flash memory, and the calculated parity bit is written to the flash memory parity area. When reading data from the flash memory, the parity bit must be read along with the data, decoded, and used to detect errors. If errors are found, they are corrected.
[0050] The inventors discovered through research that physical aging of NAND Flash (tunnel oxide layer damage, charge leakage) directly leads to an increase in the bit error rate of data storage. The number of ECC error correction bits is a direct quantitative indicator of the bit error rate; that is, the more error correction bits there are, the more severe the current data errors in the storage block and the higher the degree of physical aging. Therefore, this application introduces the number of ECC error correction bits as a real-time monitoring indicator of the storage block's health status.
[0051] Meanwhile, the risk threshold in this application embodiment is dynamically adjusted, rather than being fixed. This is because the physical aging rate of the storage block changes dynamically during repeated erasure and rewriting. Therefore, this application embodiment dynamically adjusts the risk threshold based on the historical number of erasures to adapt it to the current physical aging situation.
[0052] In summary, this application's embodiments introduce the number of ECC error correction bits as a real-time monitoring indicator of storage block health status, and dynamically set risk thresholds by combining historical erase counts and maximum ECC error correction capability. Compared with the traditional approach that relies solely on erase counts as a reference indicator, this achieves accurate early warning of storage block failure risks and has the following advantages:
[0053] It can detect and isolate storage blocks that are deteriorating in advance, avoiding data loss or system crashes caused by sudden errors;
[0054] It can improve data reliability by eliminating storage blocks before they approach the limits of ECC error correction.
[0055] Memory lifetime management has been optimized to make it more accurate and reliable, fully utilizing the potential of each block while avoiding high-risk use.
[0056] Furthermore, in some embodiments, the risk threshold does not exceed 75% of the maximum error correction capability of the ECC, and the risk threshold is inversely proportional to the number of historical erases. In other words, the more historical erases, the smaller the risk threshold; the fewer historical erases, the larger the risk threshold, and the risk threshold never exceeds 75% of the maximum error correction capability of the ECC.
[0057] This is because, on the one hand, the maximum error correction capability of ECC is the theoretical upper limit of the number of bit errors that the memory can correct. If the number of error-correcting bits reaches or approaches this upper limit, it means that the error rate of the memory block is on the verge of getting out of control. Once a sudden disturbance occurs (such as voltage fluctuations or temperature changes), ECC will be unable to complete error correction, directly leading to data loss or read / write failures. Therefore, this embodiment limits the risk threshold to a safe range of 75% to avoid the extreme situation of the error correction capability being exhausted. When a risk is identified, the system has a buffer time to execute preset risk response operations to eliminate or reduce the risk.
[0058] On the other hand, new storage blocks are theoretically in good health with a low error rate. In this case, the risk threshold is set more leniently (allowing a higher number of ECC correction bits), which avoids misjudging new healthy blocks as risky blocks and can quickly filter out inherently weak blocks (few historical erases but a high error rate). Conversely, older storage blocks have been erased more frequently, leading to accumulated damage to the tunnel oxide layer and an increased error rate due to repeated writes and erases. In this case, the risk threshold is set more strictly (allowing only a lower number of ECC correction bits), allowing for more accurate and early identification of risks caused by aging. Therefore, this embodiment, through a design where the risk threshold is inversely proportional to the number of historical erases, can dynamically adapt the risk threshold to the entire lifecycle of the storage block.
[0059] Furthermore, in some embodiments, the risk threshold can be determined by calculating it according to the following formula:
[0060] ;
[0061] in, Risk threshold;
[0062] This represents the historical erase count for the current storage block.
[0063] This is the maximum number of erase cycles allowed.
[0064] This represents the maximum ECC error correction capability of the memory.
[0065] This is the slope coefficient, and its value range is... The default value is 0.5, which can be fine-tuned based on different product models to ensure performance at the end of the product's lifespan. It will not drop to 0.
[0066] In step S3 above, the preset risk response operation may include:
[0067] One approach is to lower the usage priority of risky blocks according to a preset method. Usage priority indicates the order in which corresponding storage blocks are selected when subsequent write tasks are allocated. Based on this, in subsequent applications, the number of erases on risky blocks can be reduced, while the number of erases on healthy blocks can be increased, thereby achieving the effect of balancing the wear and tear on each storage block.
[0068] For example, the preset method may be: forcibly modifying the historical erase count of the risk block to the rated maximum erase count; and / or, adding a mark to the risk block, the mark being used to directly identify its lowest usage priority.
[0069] Another approach is to relocate the data in the risky block to reduce potential and urgent read errors and other risks associated with that block.
[0070] For example, the moving and processing operation method includes:
[0071] Request a new free block; copy the valid data of the risk block to the free block; update the mapping table from logical address to physical address so that the original mapping pointing to the risk block points to the free block; perform an erase operation on the risk block to clear its data; add the erased risk block to the free block linked list with the maximum number of erases.
[0072] It should be noted that this relocation operation can be performed either immediately upon identification of the risky block, or after a certain delay following identification. During delayed execution, the data remains within the risky block, and the relocation request is sent to a low-priority garbage collection (GC) thread, where it will be processed when the system becomes idle.
[0073] Secondly, embodiments of this application provide an electronic device, including:
[0074] The memory comprises multiple memory blocks; the memory can be various types of non-volatile memory such as NAND Flash.
[0075] The wear leveling module is used to determine the number of ECC error correction bits generated by the read operation and the historical erase count of the current storage block when performing a read operation on the current storage block; compare the number of ECC error correction bits with a risk threshold, which is determined based on the historical erase count and the maximum ECC error correction capability of the memory; if the number of ECC error correction bits is greater than the risk threshold, the current storage block is determined to be a risk block, and a preset risk response operation is performed on the risk block.
[0076] It should be noted that the electronic device can be a mobile phone, tablet computer, desktop computer, laptop computer, handheld computer, notebook computer, super mobile personal computer, netbook, as well as cellular phone, personal digital assistant, augmented reality device, virtual reality device, artificial intelligence device, wearable device, in-vehicle device, smart home device and / or smart city device. The embodiments of this application do not impose any special restrictions on the specific type of the electronic device.
[0077] The aforementioned electronic device can execute the methods provided in any embodiment of this application, and has the corresponding functional modules and beneficial effects for executing the methods. Based on the foregoing embodiments, features not explained in this embodiment are explained using the methods described in the foregoing embodiments, and will not be repeated here.
[0078] Thirdly, embodiments of this application provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the wear leveling method provided in any embodiment of this application.
[0079] Fourthly, Embodiment 4 of this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the wear leveling method provided in all embodiments of this application.
[0080] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.
[0081] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.
[0082] The program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.
[0083] Computer program code for performing the operations of this application can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, and C++, and conventional procedural programming languages such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0084] Finally, it should be noted that although the above embodiments have been described in the text and drawings of this application, this should not limit the scope of patent protection of this application. Any technical solutions that are based on the essential concept of this application and utilize the content described in the text and drawings of this application, resulting in equivalent structural or procedural substitutions or modifications, as well as the direct or indirect application of the technical solutions of the above embodiments to other related technical fields, are all included within the scope of patent protection of this application.
Claims
1. A wear leveling method for a memory, the memory comprising multiple memory blocks, characterized in that, include: When performing a read operation on the current storage block, determine the number of ECC error correction bits generated by the read operation, and the number of historical erases of the current storage block; The number of ECC error correction bits is compared with a risk threshold, which is determined based on the number of historical erases and the maximum ECC error correction capability of the memory. If the number of ECC error correction bits is greater than the risk threshold, the current storage block is determined to be a risk block, and a preset risk response operation is performed on the risk block.
2. The wear leveling method for memory according to claim 1, characterized in that, The risk threshold does not exceed 75% of the maximum error correction capability of ECC, and the risk threshold is inversely proportional to the number of historical erases.
3. The wear leveling method for a memory according to claim 2, characterized in that, The method for determining the risk threshold includes: ； in, Risk threshold; This represents the historical erase count for the current storage block. This is the maximum number of erase cycles allowed. This represents the maximum ECC error correction capability of the memory. This is the slope coefficient, and its value range is... .
4. The wear leveling method for a memory according to claim 1, characterized in that, The preset risk response operation includes: lowering the usage priority of the risk block according to a preset method, and / or, moving the data of the risk block; The priority is used to indicate the order in which the corresponding storage blocks are selected when writing data tasks are subsequently assigned.
5. The wear leveling method for a memory according to claim 4, characterized in that, The preset method includes: The historical erase count of the aforementioned risk block is forcibly modified to the rated maximum erase count; And / or, add a mark to the risk block, the mark being used to identify its lowest usage priority.
6. The wear leveling method for a memory according to claim 4, characterized in that, The data transfer process for the risk block, executed at the current time or a delayed time after the risk block is identified, includes: Request a new free block; Copy the valid data of the risk block to the free block; Update the logical address to physical address mapping table to point the original mapping that pointed to the risk block to the free block; Perform an erase operation on the risk block to clear its data; The erased risk block is added to the free block list after the maximum number of erases.
7. An electronic device, characterized in that, include: The memory includes multiple memory blocks; The wear leveling module is used to determine the number of ECC error correction bits generated by the read data operation and the historical erase count of the current storage block when performing a read data operation on the current storage block; compare the number of ECC error correction bits with a risk threshold, which is determined based on the historical erase count and the maximum ECC error correction capability of the memory; if the number of ECC error correction bits is greater than the risk threshold, the current storage block is determined to be a risk block, and a preset risk response operation is performed on the risk block.
8. The electronic device according to claim 7, characterized in that, The wear leveling module, in terms of performing preset risk response operations on the risk block, is specifically used to: lower the usage priority of the risk block according to a preset method, and / or to move the data of the risk block; wherein, the usage priority is used to indicate the order in which the corresponding storage blocks are selected when subsequent write data tasks are allocated.
9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the wear leveling method for the memory as described in any one of claims 1 to 6.
10. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that, The computer-executable instructions are executed by a computer processor to implement the wear leveling method for the memory as described in any one of claims 1 to 6.