Embedded software full-digital excitation deployment modeling method and system

Abstract

The invention relates to the technical field of embedded system development and verification, and discloses an embedded software full-digital excitation deployment modeling method and system.The method comprises the steps that virtualization modeling is conducted on a processing board card of a multi-core heterogeneous system, and a universal digital target machine is obtained; carrying out data transmission based on a real-time communication transmission technology of a data distribution service, and constructing a real-time communication link; and combining the general digital target machine with the real-time communication link to construct a full-digital excitation deployment model so as to realize digital verification of embedded software. According to the invention, a full-digital deployment verification platform consistent with the hardware function of a real embedded system can be quickly established, so that software development and testing personnel can simulate the real hardware scene to deploy and operate various embedded software in the digital environment and quickly carry out system function test and verification work.

Description

Technical Field

[0001] This invention relates to the field of embedded system development and verification technology, and in particular to a fully digital stimulus deployment modeling method and system for embedded software. Background Technology

[0002] Traditional embedded software verification heavily relies on the physical hardware environment, and the hardware in the military industry is mostly non-standard products, characterized by high customization, long development and testing cycles, and high costs. In recent years, with the comprehensive implementation of domestic production requirements, embedded system processors have largely adopted the domestically produced FT2000 series, coupled with operating systems such as Tianmai 3 and Ruihua. Existing virtual simulation technologies based on processing boards are insufficient for achieving fully digital verification and rapid hardware adaptation and porting, exhibiting significant shortcomings in the following aspects: 1) Difficulty in coordinating heterogeneous resources across multiple cores and insufficient dynamic load balancing. For example, the task allocation strategies of heterogeneous cores such as ARM, DSP and PPC are highly coupled, making it difficult to dynamically adjust task migration according to real-time load, and the efficiency of cross-core communication is low. 2) Lack of compatibility and interoperability among multiple operating systems, and contradictions in system isolation and interaction, such as differences in process scheduling and interrupt response mechanisms between Linux and real-time operating systems (such as RTEMS), which lead to uncontrollable delays in cross-system service calls; 3) Poor compatibility of peripheral communication drivers: The driver interfaces of the same peripheral (such as Ethernet / CAN controller) are not consistent under different operating systems, and the adaptation layer needs to be developed repeatedly. 4) Embedded software has poor scalability in distributed deployment, lacks dynamic adaptation capabilities for various interactive objects (software and hardware models), is too highly customized, and cannot be connected to semi-physical devices.

[0003] In summary, existing solutions have significant shortcomings in areas such as elastic management of heterogeneous resources, real-time cross-system interaction, high-precision synchronization reliability, flexible extension of communication protocols, and distributed scalable deployment. Summary of the Invention

[0004] To address the aforementioned issues, this invention proposes a fully digital incentive deployment modeling method and system for embedded software. Through innovative methods such as modeling abstraction, containerized isolation, and dynamically adapted communication middleware, it enables fully digital development and verification of embedded software, meeting the needs of a parallel R&D model that integrates hardware development, software development, and system function verification, thereby improving the efficiency of embedded software R&D.

[0005] The technical solution adopted in this invention is as follows: A fully digital incentive deployment modeling method for embedded software includes: Virtualization modeling of the processing board of a multi-core heterogeneous system yields a general-purpose digital target machine; Data transmission is performed using real-time communication transmission technology based on data distribution services to build real-time communication links; By combining the general-purpose digital target machine with the real-time communication link, a fully digital incentive deployment model is constructed, thereby realizing the digital verification of embedded software.

[0006] Furthermore, the virtualization modeling of the processing board of the multi-core heterogeneous system includes: simulating the CPU architecture, operating system, board support package, peripheral interfaces and board peripherals of the target processor, so that the general-purpose digital target machine is independent of the target processor model and operating system.

[0007] Furthermore, the CPU architecture of the target processor is simulated, including optimization of atomic operation instructions: The complete load-modify-store atomic instruction sequence is identified within the basic instruction block, and the identified atomic instruction sequence is directly mapped to the hardware instructions of the host platform; the atomic instruction sequence includes instruction combinations corresponding to addition, XOR, OR, bit clear, and swap operations; The execution status check logic of atomic instructions is optimized to directly return the execution success result in single-core simulation scenarios and utilize the implicit state of atomic instructions in multi-core simulation scenarios; the memory order semantics of the target processor are maintained to ensure the correctness of atomic operations.

[0008] Furthermore, the CPU architecture of the target processor is simulated, including vector instruction optimization: Identify the vector instructions of the target processor and merge the multiple scalar operations corresponding to the vector instructions into a single vector operation; If the host platform supports the vector instruction set corresponding to the vector instruction, then the vector instructions of the target processor will be directly mapped to the corresponding vector instructions of the host platform. All data corresponding to the vector instruction is loaded at once, and the result is stored at once after vector operation, replacing multiple single data access operations.

[0009] Furthermore, simulating the target processor's operating system includes: Initialize the processor state, define a structure containing all processor registers, distinguish between the master and slave cores, and set the boot order of the master and slave cores and the initialization state of shared resources; The device tree binary file is dynamically generated based on command-line parameters, placed in a specified location in physical memory, and its address is passed to the operating system kernel during system startup. Multiple virtual CPU instances are created using the symmetric multiprocessing option of the simulation platform. Shared cache or global memory is simulated through memory-mapped regions. Atomic operation instructions are used to implement a locking mechanism in the shared memory region to complete the synchronization of inter-core communication. Multiple boot methods are used to adapt to different types of operating systems, achieving multi-system boot compatibility.

[0010] Furthermore, the simulation of the target processor's board peripherals includes: A protocol conversion engine is built to encapsulate the raw data layer by layer according to the high-speed serial bus protocol and send it to the target device. After receiving the data packets from the target device, the engine parses them layer by layer according to the same protocol, temporarily stores the valid data payload obtained from the parsing, and reports the reception status. A message management engine is built to allocate a memory buffer for the parsed data packets. The valid data payload is temporarily stored in the buffer and then inserted into the message queue of the corresponding type. The application retrieves data from the message queue according to the first-in-first-out principle and releases the memory buffer after retrieval. A window mapping and memory management module is constructed, which uses output windows and input windows in conjunction with local window mapping to realize the mutual conversion between processor physical addresses and high-speed serial bus global addresses; Develop a driver program, which includes a device initialization management module, a message management module, and a memory management module, which respectively perform basic device configuration, message sending and receiving management, and address space management.

[0011] Furthermore, the simulation of the target processor's board peripherals includes: Configure the control register group. The host controls the enabling and disabling of fiber optic channel data transmission and reception by accessing the control register group, and works with the equipment to complete the control process and service function debugging. Build a streaming message management engine to manage the sending and receiving buffers, message identifiers and message construction of streaming messages, and provide message sending and receiving monitoring and abnormal message discarding functions; A cache management engine is built, and a dedicated internal storage area is used for data cache management. After the application completes message framing, it configures control information through the bus and updates the sending cache queue. When receiving a message, the data is copied from the cache area to the corresponding management area, and the upper layer application is notified to read and process it through an interrupt. Develop a driver program, which includes a control register management module, a stream message management module, and a cache management module, which respectively perform control register access, stream message lifecycle management, and cache resource management.

[0012] Furthermore, the data transmission technology based on the data distribution service performs data transmission, including: The data distribution service communication module is encapsulated, and a publish-subscribe pattern is used to realize data communication between nodes. The data type and name are defined by topics, and data writing operations are performed by data writers and data reading operations are performed by data readers. Communication behavior is controlled through quality of service policies; the input and output interfaces of hardware modules are digitally modeled, including functional implementation process modeling, interface type modeling, and instantiated application support, thereby enabling rapid adaptation and expansion of different embedded board peripherals.

[0013] Furthermore, the interface type modeling includes modeling of controller LAN interfaces, Ethernet interfaces, serial interfaces, high-speed serial bus interfaces, and integrated circuit bus interfaces, which can flexibly configure the communication module type of the virtual board according to requirements.

[0014] An embedded software fully digital incentive deployment modeling system includes: The general-purpose digital target machine construction module is configured to perform virtualization modeling of the processing board of a multi-core heterogeneous system to obtain a general-purpose digital target machine; The real-time communication link construction module is configured to transmit data and construct a real-time communication link based on the real-time communication transmission technology of the data distribution service. The fully digital incentive deployment model construction module is configured to combine the general digital target machine with the real-time communication link to construct a fully digital incentive deployment model, thereby realizing the digital verification of embedded software.

[0015] The beneficial effects of this invention are as follows: This invention obtains a general-purpose digital target machine by virtualizing and modeling the processing board of a multi-core heterogeneous system; it then uses real-time communication transmission technology based on data distribution services to transmit data and construct a real-time communication link; finally, it combines the general-purpose digital target machine and the real-time communication link to build a fully digital stimulus deployment model, thereby achieving digital verification of embedded software. This invention can quickly build a fully digital deployment and verification platform that is consistent with the hardware functions of a real embedded system, enabling software developers and testers to simulate real hardware scenarios in this digital environment to deploy and run various embedded software and quickly conduct system function testing and verification. Attached Figure Description

[0016] Figure 1 This is a flowchart of an embedded software fully digital stimulus deployment modeling method according to Embodiment 1 of the present invention.

[0017] Figure 2 This is a block diagram of the RapidIO hardware composition of the ARM board in Embodiment 2 of the present invention.

[0018] Figure 3 This is a logic diagram of RapidIO in Embodiment 2 of the present invention.

[0019] Figure 4 This is a block diagram of the ARM board FC hardware composition of Embodiment 2 of the present invention.

[0020] Figure 5 This is a diagram of the FC logic composition of Embodiment 2 of the present invention.

[0021] Figure 6 This is a data communication flowchart of the publish and subscribe mode in Embodiment 2 of the present invention.

[0022] Figure 7 This is a schematic diagram of the interaction between components of the fully digital incentive deployment and verification platform in Embodiment 2 of the present invention. Detailed Implementation

[0023] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments are now described. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention; that is, the described embodiments are only a part of the embodiments of the invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0024] Example 1 like Figure 1 As shown, this embodiment provides a fully digital incentive deployment modeling method for embedded software, including: virtualizing the processing board of a multi-core heterogeneous system to obtain a general-purpose digital target machine; transmitting data based on real-time communication transmission technology of data distribution service to construct a real-time communication link; and combining the general-purpose digital target machine and the real-time communication link to construct a fully digital incentive deployment model, thereby realizing the digital verification of embedded software.

[0025] It should be noted that this method realizes a fully digital transformation of embedded software verification, gets rid of dependence on physical hardware boards, reduces hardware costs and wear and tear in the verification process, and improves the flexibility and scalability of verification work, making it adaptable to the embedded software verification needs of different scenarios.

[0026] Preferably, virtualization modeling is performed on the processing board of the multi-core heterogeneous system, including simulation of the CPU architecture, operating system, board support package, peripheral interface and board peripherals of the target processor, so that the general digital target machine is independent of the target processor model and operating system.

[0027] Specifically, simulations were conducted for each core component of the target processor: for the CPU architecture, its core functions such as instruction execution and arithmetic logic were replicated; for the operating system, its key mechanisms such as process management, resource scheduling, and kernel operation were simulated; for the board support package, its hardware compatibility was reproduced; for peripheral interfaces, its data transmission protocols and interaction methods were simulated; and for board peripherals, their functional implementation and data processing flow were simulated. Through independent simulation and collaborative integration of each part, it was ensured that the general-purpose digital target machine was not limited to a specific target processor model and operating system.

[0028] It should be noted that this method achieves high compatibility and versatility of general-purpose digital target machines, eliminating the need to rebuild the target machine for different processors and operating systems, which greatly reduces modeling costs, improves modeling efficiency, and expands the applicability of the method.

[0029] Preferably, the simulation of the target processor's CPU architecture includes optimization of atomic operation instructions. Specifically, this involves identifying complete load-modify-store atomic instruction sequences within the instruction basic block and directly mapping the identified atomic instruction sequences to the host platform's hardware instructions. The atomic instruction sequences include instruction combinations corresponding to addition, XOR, OR, bit clear, and swap operations. The execution status check logic of atomic instructions is optimized, directly returning a successful execution result in a single-core simulation scenario and utilizing the implicit state of atomic instructions in a multi-core simulation scenario. The memory order semantics of the target processor are maintained to ensure the correctness of atomic operations.

[0030] Specifically, during CPU architecture simulation, the basic instruction blocks are first parsed to identify complete load-modify-store atomic instruction sequences, which cover instruction combinations corresponding to addition, XOR, OR, bit clear, and swap operations. Subsequently, the identified atomic instruction sequences are directly mapped and matched with the host platform's hardware instructions, eliminating the need for additional instruction conversion intermediates. Regarding the optimization of execution status check logic, for single-core simulation scenarios, the check process is simplified, directly returning a successful execution result. For multi-core simulation scenarios, status checks are completed using the implicit states of the atomic instructions themselves. Simultaneously, throughout the entire optimization process, the memory order semantics of the target processor are strictly maintained to ensure that the execution logic of atomic operations is consistent with that of the target processor.

[0031] It should be noted that this method significantly improves the execution efficiency of atomic instructions, reduces unnecessary state check overhead, and ensures the correctness of atomic operations in different simulation scenarios, making the simulation of CPU architecture more accurate and efficient, and providing core support for the stable operation of general-purpose digital target machines.

[0032] Preferably, the simulation of the CPU architecture of the target processor includes vector instruction optimization, specifically identifying the vector instructions of the target processor and merging multiple scalar operations corresponding to the vector instructions into a single vector operation; if the host platform supports the vector instruction set corresponding to the vector instructions, then the vector instructions of the target processor are directly mapped to the corresponding vector instructions of the host platform; all data corresponding to the vector instructions are loaded at once, and the operation results are stored at once after the vector operation is performed, replacing multiple single data access operations.

[0033] Specifically, during CPU architecture simulation, the vector instructions of the target processor are accurately located using an instruction recognition algorithm. For the identified vector instructions, the multiple scalar operations corresponding to them are analyzed, and these scattered scalar operations are integrated into a single vector operation. Then, it is determined whether the host platform supports the vector instruction set corresponding to the vector instruction. If it does, a mapping relationship between the target processor vector instructions and the corresponding vector instructions on the host platform is directly established. In the data processing stage, all the data required by the vector instruction is obtained in a one-time loading manner. After the vector operation is completed, the operation result is saved in a one-time storage operation, replacing the traditional multiple single data access mode.

[0034] It should be noted that this method reduces the number of data accesses and the overhead during data transmission. At the same time, it makes full use of the host platform's vector computing capabilities, significantly improves the execution efficiency of vector instructions, and thus optimizes the overall performance of CPU architecture simulation, effectively improving the running speed of the general-purpose digital target machine.

[0035] Preferably, simulating the operating system of the target processor includes initializing the processor state, defining a structure containing all processor registers, distinguishing between the master and slave cores, setting the boot order of the master and slave cores and the initialization state of shared resources; dynamically generating a device tree binary file based on command-line parameters, placing the file in a specified location in physical memory, and passing the file address to the operating system kernel during system startup; creating multiple virtual CPU instances using the symmetric multiprocessing option of the simulation platform, simulating shared cache or global memory through memory-mapped regions, implementing a locking mechanism in the shared memory region using atomic operation instructions, and completing the synchronization of inter-core communication; and adapting to different types of operating systems through multiple boot methods to achieve multi-system boot compatibility.

[0036] Specifically, during the operating system simulation process, the processor state is first initialized, constructing a structure containing all processor registers. Based on this structure, the master and slave cores are clearly distinguished, and the boot order of the master and slave cores and the initial state of shared resources are reasonably set. Subsequently, the parameters input from the command line are parsed, and a device tree binary file is dynamically generated based on the parameter information. This file is stored in a designated area of ​​physical memory, and during the system boot process, the file address is accurately passed to the operating system kernel, providing hardware information support for kernel operation. Next, multiple virtual CPU instances are created using the symmetric multiprocessing function of the simulation platform. Shared cache or global memory space is simulated through memory mapping technology, and a locking mechanism is implemented in the shared memory area using atomic operation instructions to ensure data synchronization and consistency in inter-core communication. Finally, multiple boot modes are configured to adapt to the boot requirements of different types of operating systems, achieving multi-system boot compatibility.

[0037] It should be noted that this method achieves accurate simulation of the operating system environment, ensures the stability of inter-core communication and data consistency, and has multi-system adaptability, thus broadening the application scenarios of general-purpose digital target machines and improving the practicality of the modeling method.

[0038] Preferably, the simulation of the target processor's board peripherals includes: building a protocol conversion engine to encapsulate raw data layer by layer according to the high-speed serial bus protocol and send it to the target device; receiving data packets from the target device and parsing them layer by layer according to the protocol; temporarily storing the parsed valid data payload and reporting the reception status; building a message management engine to allocate a memory buffer for the parsed data packets; temporarily storing the valid data payload in the buffer and inserting it into the corresponding type of message queue; the application terminal retrieving data from the message queue according to the first-in-first-out principle; and releasing the memory buffer after retrieval; building a window mapping and memory management module to realize the mutual conversion between the processor's physical address and the high-speed serial bus global address through output windows and input windows in conjunction with local window mapping; and developing a driver program, which includes a device initialization management module, a message management module, and a memory management module, which respectively execute the device's basic configuration, message sending and receiving management, and address space management.

[0039] Specifically, during the simulation of the board peripherals, a protocol conversion engine is first built. After receiving the raw data, this engine performs layer-by-layer packet processing according to the hierarchical structure of the high-speed serial bus protocol. After packetization, the data is sent to the target device. At the same time, it receives data packets from the target device, parses the data packets layer by layer according to the same protocol, extracts the valid data payload and stores it temporarily, and reports the data reception status to the upper-layer system. Next, a message management engine is built. When a parsed data packet is received, a dedicated memory buffer is allocated for it. After storing the valid data payload in the buffer, it is inserted into the corresponding message queue according to the data type. The application reads data from the message queue according to the first-in-first-out principle. After the data is read, the corresponding memory buffer is released in a timely manner to avoid resource occupation. Then, a window mapping and memory management module is built. Through the collaborative work of output window, input window and local window mapping, a mapping relationship between the processor physical address and the high-speed serial bus global address is established to realize bidirectional conversion between the two addresses. Finally, a driver program is developed. This driver program includes a device initialization management module, a message management module and a memory management module, which are responsible for executing the basic parameter configuration of the device, message sending and receiving scheduling management and address space allocation and release management, respectively.

[0040] It should be noted that this method achieves efficient data transmission and address adaptation between the board peripherals and the processor, ensuring the orderliness and accuracy of data transmission and reception. At the same time, through the modular design of the driver, it improves the stability and maintainability of peripheral simulation, ensuring the accurate simulation of related board peripherals by the general-purpose digital target machine.

[0041] Preferably, the simulation of the target processor's board peripherals includes configuring a control register group. The host accesses this control register group to control the enabling and disabling of fiber optic channel data transmission and reception, and cooperates with the equipment to complete the control flow and service function debugging; building a streaming message management engine to manage the sending and receiving buffers, message identification, and message construction of streaming messages, and providing message sending and receiving monitoring and abnormal message discarding functions; building a cache management engine, using a dedicated internal storage area for data cache management. After the application completes message framing, it configures control information through the bus and updates the sending cache queue. When receiving a message, it copies the data from the cache area to the corresponding management area and notifies the upper-layer application to read and process it through an interrupt; and developing a driver program, which includes a control register management module, a streaming message management module, and a cache management module, which respectively execute control register access, streaming message lifecycle management, and cache resource management.

[0042] Specifically, during the board peripheral simulation process, the control register group is first configured. The host can enable or disable the fiber channel data transmission and reception function by accessing this register group, thereby assisting the device in debugging the control flow and verifying the service function. Next, a streaming message management engine is built. This engine is responsible for managing the streaming message transmission and reception buffer space, assigning a unique identifier to each message, participating in the message construction process, and having the ability to monitor message transmission and reception, identify abnormal messages, and discard them. Then, a cache management engine is built, allocating a dedicated internal storage area for data caching. After the application completes message framing, it configures relevant control information through the bus and updates the sending cache queue. When receiving a message, the data is copied from the cache area to the corresponding management area, and then the upper-layer application is notified through an interrupt signal to read and process the data in a timely manner. Finally, a driver program is developed. This driver program includes a control register management module, a streaming message management module, and a cache management module, which are responsible for the access operation of the control register, the full lifecycle management of streaming messages from generation to destruction, and the allocation, release, and scheduling management of cache resources, respectively.

[0043] It should be noted that this method achieves accurate simulation of peripherals on fiber channel boards, ensuring the stability and reliability of data transmission and reception. The fault tolerance of the simulation is improved through the abnormal message handling mechanism. At the same time, the modular design of the driver facilitates maintenance and expansion, providing strong support for the debugging of related business functions.

[0044] Preferably, data transmission is performed using real-time communication transmission technology based on data distribution services. This includes encapsulating a data distribution service communication module and using a publish-subscribe model to achieve data communication between nodes; defining data types and names through topics; performing data writing operations using a data writer and data reading operations using a data reader; controlling communication behavior through quality of service policies; and digitally modeling the input and output interfaces of hardware modules, including functional implementation process modeling, interface type modeling, and instantiated application support, thereby enabling rapid adaptation and expansion of different embedded board peripherals.

[0045] Specifically, when constructing a real-time communication link, the data distribution service communication module is first encapsulated, clarifying its functional boundaries and interaction interfaces. A publish-subscribe pattern is adopted to design the module's communication logic, enabling efficient data interaction among nodes. Data types and names are uniformly defined through topics, standardizing data identification methods. A data writer is configured to perform data writing operations, writing data into the communication channel in a standardized format. A data reader is configured to perform data reading operations, accurately retrieving target data from the communication channel. Corresponding quality of service strategies are formulated to constrain and control communication behaviors such as communication latency, data reliability, and bandwidth usage. Simultaneously, digital modeling is conducted on the input and output interfaces of the hardware modules. This includes streamlining and modeling the functional implementation process of the interfaces, clarifying interface types and establishing corresponding models, and providing instantiated application support. These modeling efforts enable rapid adaptation and expansion of different embedded board peripherals.

[0046] It should be noted that this method uses a publish-subscribe model to improve the flexibility and efficiency of data communication between nodes, the quality of service strategy ensures the stability and reliability of communication, and the digital modeling of hardware interfaces enables rapid adaptation and expansion of different peripherals, reducing the difficulty of system integration and improving the universality and scalability of real-time communication links.

[0047] Preferably, the interface type modeling includes modeling of controller LAN interfaces, Ethernet interfaces, serial interfaces, high-speed serial bus interfaces, and integrated circuit bus interfaces, which can flexibly configure the communication module type of the virtual board according to requirements.

[0048] Specifically, when modeling interface types, for controller area network interfaces, the core features such as data transmission protocols, communication rate control, and frame formats are replicated and modeled; for Ethernet interfaces, the network layering architecture, data forwarding mechanism, and connection establishment and disconnection processes are simulated and modeled; for serial port interfaces, the baud rate configuration, data bit verification method, and data transmission timing are simulated and modeled; for high-speed serial bus interfaces, the high-speed data transmission logic, protocol encapsulation format, and signal processing methods are restored and modeled; for integrated circuit bus interfaces, the master-slave device communication mechanism, address addressing method, and data interaction process are simulated and modeled; at the same time, a flexible configuration mechanism is designed to select and configure the corresponding communication module type of the virtual board according to actual application requirements.

[0049] It should be noted that this method covers mainstream hardware interface types, achieves accurate modeling of multiple interfaces, and improves the adaptability of virtual board communication modules through a flexible configuration mechanism, which can meet the communication needs in different scenarios and further enhance the versatility and practicality of real-time communication links.

[0050] Accordingly, this embodiment also provides an embedded software fully digital stimulus deployment modeling system, including a general-purpose digital target machine construction module, a real-time communication link construction module, and a fully digital stimulus deployment model construction module. The general-purpose digital target machine construction module is configured to virtualize and model the processing board of a multi-core heterogeneous system to obtain a general-purpose digital target machine; the real-time communication link construction module is configured to transmit data using real-time communication transmission technology based on data distribution services to construct a real-time communication link; and the fully digital stimulus deployment model construction module is configured to combine the general-purpose digital target machine and the real-time communication link to construct a fully digital stimulus deployment model, thereby realizing the digital verification of embedded software.

[0051] Specifically, after the general-purpose digital target machine construction module starts, it performs virtualization simulation of each component of the multi-core heterogeneous system's processing board according to preset modeling rules and processes, including CPU architecture, operating system, board support package, peripheral interfaces, and board peripherals. Through the collaborative simulation of each part, a general-purpose digital target machine is formed. When the real-time communication link construction module runs, it encapsulates the data distribution service communication module, adopts a publish-subscribe model, and combines a quality of service strategy to build a stable and efficient real-time communication link. At the same time, it completes the digital modeling of the hardware module's input and output interfaces. The fully digital incentive deployment model construction module receives the general-purpose digital target machine output by the general-purpose digital target machine construction module and the real-time communication link generated by the real-time communication link construction module. It sorts out the collaborative logic and data interaction interface between the two, organically integrates them, and constructs a complete fully digital incentive deployment model. Embedded software is deployed in this model to run and complete digital verification.

[0052] It should be noted that the system achieves the division of labor and cooperation among various functions through modular design. The general digital target machine construction module ensures the universality and accuracy of the target machine, the real-time communication link construction module ensures the efficiency and scalability of communication, and the fully digital incentive deployment model construction module achieves the effective integration of the two, ultimately realizing the efficient implementation of embedded software digital verification and improving the quality and efficiency of verification work.

[0053] Example 2 This embodiment provides a fully digital stimulus deployment modeling method for embedded software, which mainly consists of two important parts: processing board modeling technology for multi-core heterogeneous systems and real-time communication and transmission technology based on DDS. The FT2000 processor is used as an example for detailed explanation.

[0054] I. Processing board modeling technology for multi-core heterogeneous systems By simulating the CPU architecture, operating system, BSP, peripheral interfaces, and board peripherals of the FT2000 processor, a general-purpose digital target machine independent of the processor model and operating system is realized, and virtualization modeling of the processor board is completed.

[0055] The FT2000 processing board excitation model in this embodiment is compatible with most commonly used domestic operating systems on the market, such as Tianmai 3 (32-bit / 64-bit) and Reworks (32-bit / 64-bit) operating systems.

[0056] 1.1 FT2000 Processor Core Modeling 1.1.1 CPU Instruction Optimization The EMU uses binary translation technology to perform heterogeneous platform simulation, masking hardware differences. Currently, the QEMU platform primarily supports the following architectures by default:

[0057] The FT2000 differs from other processors in that it integrates four Phytium-developed high-efficiency processor cores, FTC663, which are compatible with the 64-bit ARMv8 instruction set and support both ARM64 and ARM32 execution modes. It supports single-precision and double-precision floating-point arithmetic instructions and ASIMD processing instructions, and supports hardware virtualization.

[0058] In QEMU, the performance degradation of TCG (Tiny Code Generator) dynamic translation of ARMv8 instructions largely stems from the semantic mapping cost of complex instructions (such as SIMD vector operations, atomic instructions, privileged state instructions, etc.). These instructions often require the generation of a large amount of TCG intermediate code (IR) to simulate their behavior, resulting in long translation times and low execution efficiency. To improve the simulation efficiency of the ARM platform, a feasible approach is to perform targeted optimization for these types of instructions. The core idea of ​​this embodiment is to improve the execution speed of the translated code by manually writing efficient TCG IR generation logic, reducing redundant operations, or directly mapping to the native instructions of the host platform (such as using x86's AVX instructions to simulate ARMv8's NEON instructions).

[0059] 1) Atomic instruction optimization When QEMU uses TCG for dynamic translation of ARMv8 instructions, atomic operation instructions (such as LDXR / STXR) are among the instructions with the most severe performance degradation. Below is a specific optimization scheme for atomic operations.

[0060] Performance bottlenecks: LDXR (Load Exclusive Register) and STXR (Store Exclusive Register) are used to implement atomic memory operations; traditional TCG translation requires simulating complete load-modify-store atomic semantics; each operation requires entering the QEMU helper function, resulting in high context switching overhead; in multi-core simulation, a global lock needs to be maintained, leading to severe serialization.

[0061] Key optimization techniques: Instruction sequence recognition: Identifies complete LDXR-ALU-OP-STXR sequences within basic blocks; supports common atomic operations such as ADD, EOR, ORR, BIC, SWAP, etc.

[0062] State optimization: Eliminate explicit success / failure state checks; return success (0) directly in single-core simulations; use implicit states of atomic instructions in multi-core simulations.

[0063] Memory order handling: Preserve ARM memory order semantics.

[0064] The performance comparison is as follows: Original implementation optimization effect of indicators

[0065] 2) Vector instruction optimization Taking the NEON instruction set of ARMv8 as an example, the function of the VADD v0.16b, v1.16b, and v2.16b instructions is to add the 16 bytes (uint8_t) in registers v1 and v2 one by one, and store the result in v0.

[0066] This method generates 48 TCG IR instructions (16 × (load + addition + store)) and requires memory access (simulated registers) for each operation, resulting in extremely low efficiency. If the host platform is x86_64 (supporting the AVX2 instruction set), the ARMv8's 128-bit NEON addition can be directly mapped to x86's vpaddb (128-bit byte vector addition), requiring only one host instruction, significantly reducing the number of IR instructions and execution steps. Key optimization points: Avoid circular splitting: Combine 16 scalar operations into 1 128-bit vector operation, reducing the number of IRs from 48 to 4 (2 loads + 1 addition + 1 storage).

[0067] Utilize host hardware acceleration: Directly reuse x86 AVX2 instructions to complete vector calculations, avoiding the overhead of software simulation.

[0068] Reduce memory access: Load / store 128 bits of data at once, replacing 16 single-byte accesses, reducing memory interaction costs.

[0069] Integrating the above optimizations into QEMU's ARMv8 translator requires modifying the corresponding instruction decoding and generation logic: Instruction decoding: In target / arm / translate-a64.c, the encoding of VADD v0.16b, v1.16b, and v2.16b instructions is identified (by matching the opcode) and the optimized generation function is called.

[0070] TCG IR generation: Implement the gen_vadd_16b function in target / arm / tcg / neon_helper.c to generate the optimized IR as described above.

[0071] Host instruction mapping: Ensure that the QEMU TCG backend (tcg / x86 / tcg-target.c) supports mapping tcg_gen_add_i128 to the vpaddb instruction on x86 (QEMU has already mapped common SIMD operations, but can be extended for ARMv8).

[0072] The optimization results are as follows: Translation speed: The number of IRs generated is reduced by more than 90%, and the translation stage takes less time.

[0073] Execution speed: What used to require 16 scalar additions and memory accesses can now be accomplished with a single host SIMD instruction, improving execution efficiency by 5-10 times (depending on the specific scenario).

[0074] Scope of application: Similar optimizations can be extended to other NEON instructions (such as VMUL, VAND, etc.), covering high-frequency scenarios such as multimedia and signal processing.

[0075] 1.1.2 Operating System Boot Based on a general-purpose ARM emulation platform, the FT2000 platform boot code has been extended. Its core function is to initialize the FT2000 processor's boot environment and provide multi-boot path support, mainly including: 1) Processor state initialization: Define processor-related structures, such as the CPUFT2000State structure, which contains all the processor's registers (general-purpose registers, status registers, and FT2000-specific control registers, 64-bit accumulators, etc.), distinguish between master and slave cores, define the startup order of master and slave cores, the initialization state of shared resources, etc., to achieve accurate modeling and initialization of the processor chip. 2) Pre-initialization of critical peripherals: A device tree binary file (DTB) is dynamically generated based on command-line parameters and placed in a specific location in physical memory. Device tree nodes describe the memory layout, interrupt controller, and connection information, register address ranges, and interrupt signals of various other peripherals. During system startup, this DTB file is read and its addresses are passed to the booting operating system kernel. 3) Multi-core boot and inter-core communication synchronization: Use QEMU's SMP option (-smp cores=8) to create multiple virtual CPU instances to simulate the multi-core FT2000 processor. Simulate shared cache or global memory through memory mapping regions, use atomic operation instructions to implement locks in the shared memory region, and achieve synchronization of inter-core communication. 4) Boot compatibility with multiple operating systems: It can adapt to various domestic operating systems through different boot methods, such as the commonly used Tianmai 3 (32-bit / 64-bit) and Reworks (32-bit / 64-bit) operating systems; Through precise instruction-level control and multi-path design, comprehensive support for the FT2000 processor platform is achieved, ensuring compatibility with the standard ARM boot process while providing optimizations and extensions unique to domestically produced processors. Boot support for different operating systems (Tianmai, Ruihua, VxWorks) is also implemented.

[0076] 1.2 Modeling of board peripherals Based on QEMU, this model extends the capabilities of CPUs such as ARM, PowerPC, and DSP. Commonly used peripherals include DDR, EMIF, Flash, serial port, Ethernet, SRIO, RS422 / 485, and CAN. The following section uses RapidIO and FC as examples to describe peripheral modeling in detail.

[0077] 1.2.1 RapidIO Function Integration like Figure 2 and Figure 3 As shown, taking the RapidIO device on the ARM platform as an example, this illustrates the expansion of the processing board's capabilities.

[0078] The general ARM platform does not provide a RapidIO interface. Hardware boards typically implement PCIe to RapidIO modules through FPGA chips to provide RapidIO hardware capabilities for the ARM platform. This model defines a general RapidIO peripheral model. Simultaneously, based on the unified driver interface corresponding to the business software, a driver program for the processing board is developed and provided, achieving seamless switching between the virtual platform and the real platform, and between the PCIe bus and the SRIO bus.

[0079] 1.2.1.1 Model Design 1) Implementation of the protocol conversion engine After the analog device obtains the raw data through the application layer, it encapsulates the raw data layer by layer according to the SRIO protocol, and the encapsulated data is sent to the corresponding device. After receiving the SRIO data packet, the analog device parses the data layer by layer according to the SRIO protocol, temporarily stores and manages the acquired valid data payload, reports different reception statuses according to different data packet types, and notifies the application to obtain the received data.

[0080] 2) Implementation of the message management engine After parsing the data packet received by the simulation device, it allocates a memory buffer to temporarily store the payload of this data packet, and inserts it into the message queue of the specified type according to the parsed data packet type; When the application retrieves data, it takes the temporarily stored valid data payload from the specified queue based on the first-in-first-out principle, and releases the memory buffer after the data retrieval is completed.

[0081] 3) Implementation of window mapping and memory management Outbound and Inbound, together with local window mapping, enable the mapping between processor physical addresses and SRIO global addresses; Local window mapping routes the processor's local physical address to the SRIO controller; Outbound maps the local physical address to the SRIO address, and the data sent by the sending end carries the SRIO address after being converted by Outbound. Inbound maps SRIO addresses to local physical addresses. After the receiving end uses Inbound to convert SRIO addresses, it updates the data to the processor's local physical address.

[0082] 1.2.1.2 Driver Design 1) SRIO initialization management Perform basic device configuration, including node master-slave mode, interrupt handling, doorbell and message sending / receiving logic, send / receive window settings, SRIO link initialization, etc.

[0083] 2) SRIO Message Management Module It manages message sending and receiving nodes, as well as data and processing logic for doorbells, messages, etc.

[0084] 3) SRIO memory management Complete the management of SRIO transmit and receive address space, including the unified allocation of transmit addresses and the management of transmit and receive buffers.

[0085] 1.2.2 FC Function Integration like Figure 4 and Figure 5 As shown, taking an ARM platform FC device as an example, this illustrates the expansion of the processing board's capabilities.

[0086] The general-purpose ARM platform does not provide an FC (Focus Functions) interface. Hardware boards typically implement dedicated FC hardware modules through FPGA chips to provide FC hardware capabilities for the ARM platform. This model defines a general-purpose FC peripheral model. Simultaneously, based on the unified driver interface corresponding to the business software, it develops and provides drivers for the processing boards, achieving seamless switching between the virtual platform and the real platform, and between the PCIe bus and the FC bus.

[0087] 1.2.2.1 Model Design 1) Control Register Set The peripheral provides a control register set accessible by the host to enable and disable FC data transmission and reception. This enables and disables data transmission and reception to facilitate relevant control processes within the device, such as device shutdown. It also facilitates the debugging of certain business functions.

[0088] 2) Stream message management engine It is responsible for managing the reception and transmission of streaming messages, including managing send and receive buffers, message IDs, and message structure. Depending on the application's needs, it provides operations such as message transmission and reception monitoring and abnormal message discarding.

[0089] 3) Cache management engine This device uses a dedicated internal storage area for data caching and management. After the application completes message framing, it configures control information via PCIe and updates the transmit buffer queue, completing the message transmission preparation operation. When receiving a message, the received message data is copied from the buffer area to the corresponding management area, and an interrupt is used to notify the upper-layer application to read and process the message.

[0090] 1.2.2.2 Driver Design 1) Control Register Management It manages access to control registers, including hardware switches, system status feedback, and device resource management.

[0091] 2) Stream message management It manages streaming messages, including message lifecycle management, and builds a complete message processing chain; it features a resource pooling design, pre-allocates resource pools to improve efficiency, and has a built-in message exception handling mechanism.

[0092] 3) Cache Management It provides underlying functional support for message caching management, including dedicated storage area management, zero-copy data transmission management, and cache queue management.

[0093] II. Real-time Communication Transmission Technology Based on DDS A highly efficient real-time data transmission mechanism is proposed, combining hardware acceleration and optimized drivers to achieve near-realistic real-time performance. This mechanism includes: underlying model hardware acceleration to improve model execution speed, thereby increasing data transmission rate; driver software optimization to improve the efficiency of simulation environment software operation; cross-platform communication framework construction to improve communication efficiency between different platforms and simulation subsystems; hardware platform acceleration to improve hardware execution speed, thereby improving the simulation system's execution speed; and a highly efficient real-time data transmission interface designed to ensure real-time synchronization of data between the virtual environment and the actual hardware. Through hardware acceleration and optimized drivers, near-realistic real-time performance is achieved.

[0094] The communication module encapsulates Fast DDS to implement publish and subscribe data communication, the principle of which is as follows: Figure 6 As shown, each node can define the data type and name through Topics, use DataWriter / DataReader to read and write the actual data, and control various communication behaviors through QoS Policies.

[0095] This embodiment can also perform functional module modeling of the interactive objects (hardware modules) of the application software, realizing fully digital verification of the application software. It simulates the input / output interfaces of relevant hardware modules and performs digital modeling, including process modeling of functional implementation, interface modeling (CAN, Ethernet, serial port, SRIO, and I2C, etc.), supports instantiated applications, and can interface with calls and deployments under different digital stimulus environments; it can adapt to the rapid adaptation and expansion of peripherals of different embedded boards. Users can flexibly configure the communication modules of the virtual board according to their needs, such as GPIO, serial port, Ethernet (TSN, FC), etc.

[0096] The fully digital deployment and verification platform, with its components interacting via communication middleware, is illustrated below. Figure 7 As shown.

[0097] In summary, the core advantage of the fully digital stimulus deployment modeling method for embedded software proposed in this embodiment lies in transferring many development, debugging, and testing activities that heavily rely on physical hardware to a highly controllable, reproducible, and visualized digital simulation environment through a virtual-first strategy. This not only reduces R&D costs and risks, but more importantly, it comprehensively improves software development efficiency and software quality through modularization, automation, visualization, and in-depth analysis. Specific advantages are as follows.

[0098] 1) Reduce development costs and risks Hardware dependency elimination: In the early stages of a project, especially when the hardware prototype (FT2000) is not yet ready or its supply is limited, the FT2000-based simulation platform allows for parallel software development and testing, avoiding hardware-related obstacles to the development process and shortening the project cycle.

[0099] Reduce the risk of hardware damage: In embedded software development, defective code may cause damage to hardware (such as incorrect configuration of peripherals). Under the simulation platform, you can safely try various operations without worrying about the risk of "bricking" your hardware.

[0100] 2) Improve development efficiency and software quality Build a complete virtual testing environment: Construct a complete virtual system including processors and peripherals, which can be adapted to various domestic operating systems, support the injection of various test signals or stimuli and observe their responses, thereby performing system-level integration testing, fault injection testing, boundary testing, etc., to discover some defects in software design and implementation in advance and improve software quality.

[0101] Early verification and accelerated iteration: The correctness and performance of the algorithm can be verified early in the development process on the simulation platform. Iterative testing, parameter adjustment and optimization can be carried out quickly without waiting for each long hardware burning and testing cycle.

[0102] Continuous Integration and Automated Testing: Supports continuous integration and automated testing in a virtual environment, enabling automated regression testing to ensure that code modifications do not introduce new problems.

[0103] 3) Optimize system performance and resource utilization System optimization using the FT2000's QEMU model focuses on achieving three-level collaboration through its programmable and observable simulation environment. At the hardware level, parameters such as the number of cores and cache size can be simulated and adjusted. QEMU tracks instruction flow and cache access to pinpoint CPU, memory, and I / O bottlenecks that match application characteristics. At the OS level, scheduling strategies are adapted to the ARM architecture, such as NUMA node task binding to reduce cross-core accesses and optimizing driver efficiency by combining interrupt response tracing. At the application level, instruction statistics are analyzed to assess ARMv8 instruction utilization and optimize compilation options and vector operations.

[0104] In addition, the model can simulate load growth and provide early warnings of resource bottlenecks, dynamically adjust scheduling strategies to balance the load, optimize energy-saving strategies in low-load scenarios, and ultimately maximize the hardware performance and resource utilization of FT2000 through a simulation-verification-iteration closed loop.

[0105] Example 3 This embodiment is based on embodiment 1: This embodiment provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the embedded software fully digital stimulus deployment modeling method of Embodiment 1. The computer program can be in the form of source code, object code, executable file, or some intermediate form.

[0106] Example 4 This embodiment is based on embodiment 1: This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the embedded software fully digital stimulus deployment modeling method of Embodiment 1. The computer program can be in the form of source code, object code, executable file, or some intermediate form. The storage medium includes any entity or device capable of carrying computer program code, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.

[0107] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

[0108] It should be noted that, for the sake of simplicity, the foregoing method embodiments are described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

Claims

1. A fully digital incentive deployment modeling method for embedded software, characterized in that, include: Virtualization modeling of the processing board of a multi-core heterogeneous system yields a general-purpose digital target machine; Data transmission is performed using real-time communication transmission technology based on data distribution services to build real-time communication links; By combining the general-purpose digital target machine with the real-time communication link, a fully digital incentive deployment model is constructed, thereby realizing the digital verification of embedded software.

2. The embedded software fully digital stimulus deployment modeling method according to claim 1, characterized in that, The virtualization modeling of the processing board of the multi-core heterogeneous system includes: simulating the CPU architecture, operating system, board support package, peripheral interfaces and board peripherals of the target processor, so that the general digital target machine is independent of the target processor model and operating system.

3. The embedded software fully digital stimulus deployment modeling method according to claim 2, characterized in that, Simulation of the target processor's CPU architecture includes optimization of atomic operation instructions: The complete load-modify-store atomic instruction sequence is identified within the basic instruction block, and the identified atomic instruction sequence is directly mapped to the hardware instructions of the host platform; the atomic instruction sequence includes instruction combinations corresponding to addition, XOR, OR, bit clear, and swap operations; Optimize the execution status check logic of atomic instructions, directly return the execution success result in single-core simulation scenarios, and utilize the implicit state of atomic instructions in multi-core simulation scenarios; Preserve the memory order semantics of the target processor to ensure the correctness of atomic operations.

4. The embedded software fully digital stimulus deployment modeling method according to claim 2, characterized in that, Simulation of the target processor's CPU architecture includes vector instruction optimization: Identify the vector instructions of the target processor and merge the multiple scalar operations corresponding to the vector instructions into a single vector operation; If the host platform supports the vector instruction set corresponding to the vector instruction, then the vector instructions of the target processor will be directly mapped to the corresponding vector instructions of the host platform. All data corresponding to the vector instruction is loaded at once, and the result is stored at once after vector operation, replacing multiple single data access operations.

5. The embedded software fully digital stimulus deployment modeling method according to claim 2, characterized in that, Simulating the target processor's operating system includes: Initialize the processor state, define a structure containing all processor registers, distinguish between the master and slave cores, and set the boot order of the master and slave cores and the initialization state of shared resources; The device tree binary file is dynamically generated based on command-line parameters, placed in a specified location in physical memory, and its address is passed to the operating system kernel during system startup. Multiple virtual CPU instances are created using the symmetric multiprocessing option of the simulation platform. Shared cache or global memory is simulated through memory-mapped regions. Atomic operation instructions are used to implement a locking mechanism in the shared memory region to complete the synchronization of inter-core communication. Multiple boot methods are used to adapt to different types of operating systems, achieving multi-system boot compatibility.

6. The embedded software fully digital stimulus deployment modeling method according to claim 2, characterized in that, Simulation of the target processor's board peripherals includes: A protocol conversion engine is built to encapsulate the raw data layer by layer according to the high-speed serial bus protocol and send it to the target device. After receiving the data packets from the target device, the engine parses them layer by layer according to the same protocol, temporarily stores the valid data payload obtained from the parsing, and reports the reception status. A message management engine is built to allocate a memory buffer for the parsed data packets. The valid data payload is temporarily stored in the buffer and then inserted into the message queue of the corresponding type. The application retrieves data from the message queue according to the first-in-first-out principle and releases the memory buffer after retrieval. A window mapping and memory management module is constructed, which uses output windows and input windows in conjunction with local window mapping to realize the mutual conversion between processor physical addresses and high-speed serial bus global addresses; Develop a driver program, which includes a device initialization management module, a message management module, and a memory management module, which respectively perform basic device configuration, message sending and receiving management, and address space management.

7. The embedded software fully digital stimulus deployment modeling method according to claim 2, characterized in that, Simulation of the target processor's board peripherals includes: Configure the control register group. The host controls the enabling and disabling of fiber optic channel data transmission and reception by accessing the control register group, and works with the equipment to complete the control process and service function debugging. Build a streaming message management engine to manage the sending and receiving buffers, message identifiers and message construction of streaming messages, and provide message sending and receiving monitoring and abnormal message discarding functions; A cache management engine is built, and a dedicated internal storage area is used for data cache management. After the application completes message framing, it configures control information through the bus and updates the sending cache queue. When receiving a message, the data is copied from the cache area to the corresponding management area, and the upper layer application is notified to read and process it through an interrupt. Develop a driver program, which includes a control register management module, a stream message management module, and a cache management module, which respectively perform control register access, stream message lifecycle management, and cache resource management.

8. The embedded software fully digital stimulus deployment modeling method according to claim 1, characterized in that, The real-time communication transmission technology based on data distribution service performs data transmission, including: The data distribution service communication module is encapsulated, and a publish-subscribe pattern is used to realize data communication between nodes. The data type and name are defined by topics, and data writing operations are performed by data writers and data reading operations are performed by data readers. Communication behavior is controlled through quality of service policies; the input and output interfaces of hardware modules are digitally modeled, including functional implementation process modeling, interface type modeling, and instantiated application support, thereby enabling rapid adaptation and expansion of different embedded board peripherals.

9. The embedded software fully digital stimulus deployment modeling method according to claim 9, characterized in that, The interface type modeling includes modeling of controller LAN interfaces, Ethernet interfaces, serial interfaces, high-speed serial bus interfaces, and integrated circuit bus interfaces, which can flexibly configure the communication module type of the virtual board according to requirements.

10. An embedded software fully digital stimulus deployment modeling system, characterized in that, include: The general-purpose digital target machine construction module is configured to perform virtualization modeling of the processing board of a multi-core heterogeneous system to obtain a general-purpose digital target machine; The real-time communication link construction module is configured to transmit data and construct a real-time communication link based on the real-time communication transmission technology of the data distribution service. The fully digital incentive deployment model construction module is configured to combine the general digital target machine with the real-time communication link to construct a fully digital incentive deployment model, thereby realizing the digital verification of embedded software.

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