Address remapping method, electronic equipment and storage medium

Abstract

The invention relates to the technical field of memory management, and provides an address remapping method, electronic equipment and a storage medium, and the method comprises the steps: obtaining a first sequence in an original access address corresponding to a memory resource access request, the first sequence comprises an index number of a memory resource determined according to the memory resource access request and first high-order data with an address bit higher than that of the index number; performing address remapping on a target sequence corresponding to the first sequence through a remapping matrix to obtain a remapping sequence; and performing multi-level exclusive-or linked list processing on the data in the remapping sequence to obtain a remapped target index number of the memory resource.

Description

Technical Field

[0001] This application relates to the field of memory management technology, and in particular to an address remapping method, electronic device, and storage medium. Background Technology

[0002] The memory subsystem is a crucial component of a system-on-a-chip (SoC), with DDR (Double Data Rate Synchronous Dynamic Random-Access Memory, also known as DDR SDRAM) memory subsystems being the most widely used. A DDR memory subsystem typically consists of a memory controller and DDR chips. The memory controller schedules system access requests (also known as load) to appropriate memory locations, and the scheduling method significantly impacts the actual performance of the DDR memory subsystem.

[0003] In existing multi-channel DDR memory subsystems, only fixed positions in the address are used to determine the distribution of access load. However, for some access patterns, such as non-contiguous access with fixed step size (such as interlacing of image pixels) and random access with uneven address distribution, the direct address mapping method is very likely to cause significant load imbalance on channels, banks and bankgroups. This manifests as a certain memory unit (which may be a certain channel, bank or bankgroup) being accessed frequently, while other memory units are always idle. Summary of the Invention

[0004] This application provides an address remapping method, an electronic device, and a storage medium to address the shortcomings of memory resource allocation imbalance caused by uneven service loads in the prior art.

[0005] This application provides an address remapping method, which includes the following steps.

[0006] Obtain the first sequence from the original access address corresponding to the memory resource access request, wherein the first sequence includes the index number of the memory resource determined according to the memory resource access request and the first high-order data with an address higher than the index number; The target sequence corresponding to the first sequence is remapped using a remapping matrix to obtain a remapped sequence. The data in the remapping sequence is processed by a multi-level XOR linked list to obtain the target index number of the memory resource after remapping.

[0007] As one embodiment, before performing address remapping on the target sequence corresponding to the first sequence using a remapping matrix to obtain the remapped sequence, the method further includes: Perform S-box mapping on the first sequence to obtain the target sequence corresponding to the first sequence; or, The first sequence is the target sequence; or, The index number of the memory resource in the first sequence is the target sequence.

[0008] As one embodiment, the step of performing multi-level XOR linked list processing on the data in the remapping sequence to obtain the remapped target index number of the memory resource includes: The data in the remapping sequence is subjected to several multi-level XOR linked list processing steps to obtain several processed data. By combining several of the processed data, the target index number of the memory resource after remapping is obtained.

[0009] As an example, when the memory resource includes a channel, the remapping sequence includes multiple remapping index numbers of the channel and a second high-order data whose address bits are higher than the multiple remapping index numbers of the channel, wherein the second high-order data corresponds to the first high-order data; The process of performing multiple multi-level XOR linked list processing on the data in the remapping sequence yields several processed data sets, including: When performing single-level XOR linked list processing, multiple remapping index numbers of the channel and the second high-order data with address bits higher than the remapping index number are XORed pairwise to obtain several intermediate results. Several intermediate results are used as inputs to the next level and XORed pairwise. The resulting new intermediate results are then used as inputs to the next level and XORed pairwise again. This process continues until a single intermediate result is obtained, at which point the single intermediate result is used as the processing data.

[0010] As an example, when the memory resource includes a Bank, the remapping sequence includes multiple remapping index numbers of the Bank and a third high-order data whose address is higher than the multiple remapping index numbers of the Bank, and the third high-order data corresponds to the first high-order data; The process of performing multiple multi-level XOR linked list processing on the data in the remapping sequence yields several processed data sets, including: When performing single-level XOR linked list processing, the third highest bit of the data with the address bit higher than the remapping index number is XORed pairwise to obtain several intermediate results. Several intermediate results are used as inputs to the next level and subjected to pairwise XOR operations to obtain several new intermediate results. Several new intermediate results are XORed with a single remapping index number of the Bank as the input of the new next level. The resulting updated intermediate results are then XORed again as the input of the new next level until a single intermediate result is obtained. The single intermediate result is then used as the single processing data corresponding to the single remapping index number of the Bank.

[0011] As one embodiment, when the memory resource includes a Bank, after obtaining the remapped target index number of the memory resource, the method further includes: The remapped target index number of the Bank is concatenated with other addresses in the memory resource access request to obtain the final access address of the Bank.

[0012] As one embodiment, the method further includes: Limit the number of times a single memory resource can be accessed within a time window.

[0013] As one embodiment, the memory resource includes a group of banks consisting of multiple banks, and the method further includes: Obtain the real-time data processing volume of each of the Bank groups; When the real-time data processing volume of any of the Bank groups exceeds the threshold, the time priority of that Bank group is increased.

[0014] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement any of the address remapping methods described above.

[0015] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the address remapping method as described above.

[0016] The address remapping method, electronic device, and storage medium provided in this application obtain a first sequence from the original access addresses corresponding to memory resource access requests. This first sequence includes an index number of the memory resource determined according to the memory resource access request and a first high-order bit data whose address is higher than the index number. The method then performs address remapping on the target sequence corresponding to the first sequence using a remapping matrix to obtain a remapped sequence. Finally, it performs multi-level XOR linked list processing on the data in the remapped sequence to obtain the remapped target index number of the memory resource. This method, through address remapping using a remapping matrix, can evenly distribute the index numbers or high-order addresses and index numbers of memory resources corresponding to frequently accessed memory address ranges. This effectively distributes memory resource access requests across various memory resources, avoiding load concentration and reducing the probability of load clustering on a few hardware resources. It improves the parallelism and response speed of memory access. Furthermore, the multi-level XOR linked list processing eliminates random deviations caused by uneven address distribution, comprehensively addressing the problem of uneven memory resource allocation due to uneven business operations. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the memory subsystem provided in this application.

[0019] Figure 2 This is a schematic diagram of the access request splitting based on the splitting granularity provided in this application.

[0020] Figure 3 This is a flowchart illustrating the address remapping method provided in this application.

[0021] Figure 4 This is a schematic diagram of the remapping matrix provided in this application.

[0022] Figure 5 This is a schematic diagram of the channel address remapping process provided in this application.

[0023] Figure 6 This is a schematic diagram of the address remapping process for different banks provided in this application.

[0024] Figure 7 This is a flowchart illustrating the Bank scheduling process provided in this application.

[0025] Figure 8 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] The address remapping scheme provided in this application applies to the memory subsystem. The storage hierarchy of the memory subsystem is described below: The memory subsystem can consist of one or more memory modules (or memory modules, i.e., DIMMs). A DIMM (Dual Inline Memory Module) is a common type of memory module; a single DIMM (memory module) contains several memory chips (also called memory modules).

[0028] The most common memory chip (memory particle) is DDR (i.e., Double Speed ​​SDRAM). A memory particle consists of multiple banks, and the storage capacity of each bank within the same memory chip is the same. Each bank is a storage matrix, divided into multiple rows and columns. Specific storage units can be located based on row and column addresses. As the capacity of a single memory particle increases, the number of banks also increases. Therefore, the banks within the memory particle need to be grouped together, forming a Bank Group. Thus, the total number of banks in each memory particle = the number of Bank Groups × the number of banks in each group. A page is a logical storage unit within a bank, specifically referring to a data block that is currently open (or active) and available for fast access within that bank. At any given time, a bank can have at most one active page.

[0029] It should be noted that each memory chip (memory particle) has its own device width, which is the amount of data that can be transmitted simultaneously in one transmission cycle. The device width of a single memory chip is generally one of three: 4, 8, or 16 bits.

[0030] The data interface between a processor (such as a CPU) and memory is typically 64-bit, meaning that the processor sends or reads 64 bits of data from memory per clock cycle. However, a single memory chip has a bit width of only 4, 8, or 16 bits. Therefore, multiple memory chips must be connected in parallel to form a 64-bit data interface to interconnect with the processor. A collection of one or more memory chips with a 64-bit bit width is usually called a Rank.

[0031] A memory module (or memory stick, or DIMM) can have one or more Ranks.

[0032] The DDR controller is a crucial component that controls memory and is responsible for data exchange between memory and the processor. A channel (or memory channel) is actually a memory bandwidth acceleration technology. A DDR controller may have one or two memory channels. Dual-channel is the most common, where one memory channel can connect to one or more memory modules (or memory modules, or DIMMs).

[0033] Reference Figure 1 The memory subsystem provided in this application includes a multi-service access scheduling and resource management layer, a port arbitrator, a channel splitter, a quality of service buffer manager, an address mapper, a physical interface and timing control layer, and a physical storage layer.

[0034] The multi-service access scheduling and resource management layer can be represented as AXI_TOP, which is used to handle parallel address access requests from multiple service modules and achieve hardware-level load balancing and scheduling guarantees.

[0035] The port arbitrator, PORT_ARB, is used to dynamically arbitrate the access rights of multiple service modules to the AXI bus and resolve resource preemption conflicts based on priority / weight strategies.

[0036] The channel splitter, represented as CHN_SPLIT, is used to split access requests from multiple service modules into sub-requests according to splitting granularity boundaries and distribute them to X main memory channels, achieving fine-grained load balancing. X is the number of main memory channels. See the channel splitting diagram for reference. Figure 2 .

[0037] The Quality of Service (QoS) Buffer Manager, represented as QOS_BUF, is used to implement allocation processing, order preservation processing, exception request handling, and priority scheduling processing. Allocation processing refers to assigning a unique queue identifier (QID) and physical buffer to each request, isolating different business data streams. Order preservation processing refers to ensuring the read and write order of the same business stream (such as AXI read order preservation) to prevent data consistency issues caused by out-of-order requests. Exception request handling refers to detecting and handling abnormal scenarios such as exclusive access and security authentication. Priority scheduling processing refers to scheduling sub-requests to the target channel according to business priority levels.

[0038] The address mapper, represented as ADDR_MAP, is used to translate bus (AXI) logical addresses into DRAM physical addresses, including Rank address, BG (Bank Group) address, Bank address, Row address, and Col address. It splits requests according to different Pages to maximize Bank-level parallelism and reduce row conflicts.

[0039] The physical interface and timing control layer can be represented as DFI_TOP, which is used to adapt to the physical protocols of different DRAM chips and achieve precise timing control and data path optimization.

[0040] The physical storage layer is represented as DRAM, which is mainly used for physical storage and can expand storage capacity and throughput according to bandwidth requirements.

[0041] This application provides an address remapping method applicable to DDR memory subsystems, which solves the problem of uneven hardware load distribution in DDR memory subsystems, achieves balanced distribution at the hardware level such as memory channels and banks, and improves the hardware parallel efficiency, access latency and utilization of DDR memory subsystems to adapt to high-performance memory usage scenarios with high bandwidth, multiple channels and low latency.

[0042] The address remapping method provided in this application will be described in detail below with reference to the accompanying drawings.

[0043] Reference Figure 3 This application provides an address remapping method, which includes the following steps: Step S100: Obtain the first sequence in the original access address corresponding to the memory resource access request. The first sequence includes the index number of the memory resource and the first high-order data with the address bit higher than the index number. The index number of the memory resource can be determined based on the memory resource access request.

[0044] Step S200: Remap the address of the target sequence corresponding to the first sequence using a remapping matrix to obtain a remapped sequence; Step S300: Perform multi-level XOR linked list processing on the data in the remapping sequence to obtain the target index number of the memory resource after remapping.

[0045] Memory resource access requests are access requests initiated in response to business scenarios. Business scenarios refer to actual application requirements, such as copying audio data streams, refreshing displays, and rendering game graphics. These different scenarios have different requirements for memory access. Some are particularly sensitive to latency, while others are sensitive to bandwidth and require the acquisition of large amounts of data at once. Therefore, different memory access methods need to be determined based on different business scenarios.

[0046] A memory resource access request refers to a business module's request to access memory space (e.g., reading instructions or data from a memory address or writing instructions or data to a memory address). The business module can be a CPU, GPU (Graphics Processing Unit), DSP (Digital Signal Processing), MCU (Microcontroller Unit), etc.

[0047] Specifically, different business scenarios have different memory access requirements. For example, copying audio data streams requires sequential, streaming memory access; display refresh is extremely sensitive to latency; while game graphics rendering is not sensitive to latency but requires acquiring large amounts of image data (including texture, color, depth, etc.) at once, necessitating multi-threaded, high-concurrency (bandwidth-sensitive) memory access. The load balancing method proposed in this application can adapt the optimal load distribution method according to the memory access patterns of the actual application scenario.

[0048] In detail, different business scenarios configure registers in the memory controller. These register parameters are used to determine the memory read and write timing. When a business module (such as the CPU, GPU, etc.) sends an access request to be scheduled to the memory controller, the memory controller determines the splitting granularity based on the correspondence between the access request and the local register parameters. For example, if a memory resource access request requires writing 4KB of data to a contiguous region (logical address), the determined splitting granularity is 1KB.

[0049] The granularity of the split refers to how much of a large access request (such as a read or write operation on a contiguous range of addresses) is broken down into several smaller, independently schedulable sub-requests. A large granularity means fewer sub-requests, each covering a larger address range; a small granularity means more sub-requests, each covering a smaller address range. This granularity is not fixed but dynamically determined based on the business scenario.

[0050] For example, if the business scenario requires high concurrency and low latency, the granularity of the splitting needs to be small and fine to facilitate parallel scheduling and reduce queuing time; if the business scenario requires high-bandwidth sequential read and write, the granularity of the splitting needs to be large to reduce the number of splits and reduce scheduling overhead; if the business scenario is address-aligned, it needs to be split by page, by channel, etc., and the granularity is limited by the hardware.

[0051] It should be noted that, generally speaking, if channel-level load balancing is required, the splitting granularity is the channel request; if bank-level load balancing is required, the splitting granularity is determined by the page size of the memory chip (DRAM).

[0052] Correspondingly, in step S100, obtaining the first sequence of the original access addresses corresponding to the memory resource access request includes receiving the memory resource access request and splitting the memory resource access request and its corresponding original access address based on the splitting granularity corresponding to the load balancing level to be implemented, thereby obtaining the first sequence.

[0053] For example, taking a memory resource access request as writing 4KB of data to a contiguous region (referring to a logical address) as an example, if the splitting granularity is determined to be 1KB, then the access request to write 4KB is split into 4 sub-requests of "writing 1KB". At the same time, the original logical address also needs to be split into multiple address fragments according to the splitting granularity.

[0054] Reference Figure 2 The address is divided into segments along the increasing address direction (i.e., from the least significant bit to the most significant bit). Taking the 4KB data example above, 4KB is... If data B has 12 characters in its address code, and the splitting granularity is determined to be 1KB (meaning the smallest indivisible address space is 1KB – 10 address code bits can represent the addresses of 1KB of data), then in the above 12-character address code sequence, the splitting granularity boundary is determined from the low bit to the high bit (10 bits). This allows for splitting into 4 sub-requests. Taking a 4-channel sub-request as an example, the actual boundary of the channel split is at the 10th bit of the address. At this splitting granularity, the range of data addresses belonging to the same channel is: data with the same high-order address code (high 2 bits) and different AXI_ADDR[9:0] (i.e., the low 10 bits) codes. Here, AXI_ADDR[9:0] represents the bus address code from bit 0 to bit 9.

[0055] It should be noted that the split can be performed exactly at the smallest split granularity. For example, if the split granularity is 1KB, the actual boundary of the channel split is determined at the 10th bit of the address code. Alternatively, it can be any bit in the high-order part of the address code. For example, AXI_ADDR[ADDR_W-1:10] can be the range of positions where the channel split occurs, where W represents the bit width (i.e., the width of the data bus interface), which is typically 64 bits.

[0056] Understandably, because memory resource access requests are split, the corresponding memory resources also need to be split, such as channel / bank splitting. The address boundaries of the data access in the split sub-requests will never exceed the boundaries of each of the split channels / banks. Taking the actual split boundary as the 10th bit of the address encoding as an example, let's denote the binary sequence of this address encoding as AXI_ADDR[ADDR_W-1:10]. The address is encoded in binary sequence AXI_ADDR[ADDR_W-1:10], which is also the first sequence. ADDR_W-1:10 is the index number, and the first high-order data includes the data of AXI_ADDR[9:0].

[0057] The binary sequence corresponding to the logical address is split so that when the logical address is mapped later, different segments are mapped to different channels (or banks). This allows the access requests of business modules (such as the CPU) to be distributed across multiple channels (or banks) when accessing memory, so that they can work in parallel instead of queuing up to wait for the same channel (or bank).

[0058] In step S200, the target sequence is used to characterize all or part of the first sequence or the sequence obtained after nonlinear mapping of the first sequence. Address remapping of the target sequence includes address remapping of the target sequence based on the remapping matrix to obtain a remapped sequence.

[0059] Address remapping refers to the process of converting a logical address into a physical address in memory space.

[0060] It should be noted that in multi-channel DDR memory subsystems, the traditional method generally uses direct address mapping to allocate the load (i.e., access requests) to different memory channels and different banks. That is, the current load allocation method is determined directly based on certain bits of the memory access address (e.g., the first 3 bits of the high-order bits represent the channel number or bank ID). For example, according to the above, the first 3 bits of the high-order bits represent the channel number or bank ID, and the load is allocated to the corresponding channel based on the channel number.

[0061] However, this approach has obvious limitations. When certain address ranges are accessed frequently, these access requests are concentrated on the same channel or bank, resulting in excessive load on that channel or bank, while other channels or banks remain relatively idle, ultimately affecting the overall performance and efficiency of memory access.

[0062] In contrast, to achieve load balancing, this embodiment can use a remapping matrix to shuffle and rearrange the target sequence so that it is eventually evenly mapped to different storage units / memory resources (e.g., different channel numbers). This allows memory resource access sub-requests to be scheduled to different storage units / memory resources, avoiding uneven load that could ultimately lead to a longer delay in the entire memory resource access request.

[0063] The aforementioned different storage units / memory resources are split according to the same level. For example, different storage units at the Channel level (memory channel level) refer to different channel numbers. Similarly, different memory chips can be considered as different storage units at the same storage level (memory chip level).

[0064] In step S300, the data in the remapped sequence is processed by a multi-level XOR linked list, including performing pairwise XOR processing on the data in the remapped sequence to eliminate random bias.

[0065] Understandably, this application uses a remapping matrix to remap addresses, which can evenly distribute the index numbers or high-order addresses and index numbers of memory resources corresponding to some frequently accessed memory address ranges. This allows memory resource access requests to be effectively distributed across various memory resources, thereby avoiding load concentration and reducing the probability of load clustering on a few hardware resources. It can improve the parallelism and response speed of memory access. Furthermore, through multi-level XOR linked list processing, it eliminates random deviations caused by uneven address distribution, thus comprehensively solving the problem of memory resource allocation tilt caused by uneven business operations.

[0066] As one embodiment, before performing address remapping on the target sequence corresponding to the first sequence to obtain the remapped sequence, the method further includes: Perform S-box mapping on the first sequence to obtain the target sequence corresponding to the first sequence; or, The first sequence is the target sequence; or, The index number of the memory resource in the first sequence is the target sequence.

[0067] Among them, S-box mapping is a non-linear substitution operation that transforms an input n-bit vector into an m-bit vector through a fixed lookup table.

[0068] Specifically, the split binary sequence, such as the one described above... =AXI_ADDR[ADDR_W-1:10] is used for S-box mapping, mapping the high-order address encoding sequence to a new binary sequence. , i.e., target sequence .

[0069] The S-box mapping requires traversing the split binary sequence. The entire address space must be mapped in a reversible one-to-one manner, and the target sequence obtained after the output is mapped using an S-box must be guaranteed. It exhibits good statistical uniformity.

[0070] To achieve the best results, mapping can be performed by selecting different splitting granularities (i.e., different splitting granularities for different scenarios) and different data at the splitting granularities (flexibly selecting different address segments according to the actual scenario, such as determining the index number of memory resources based on memory resource access requests).

[0071] It is understandable that since different business scenarios correspond to different ports and different memory access addresses, the access addresses are not uniform. S-box mapping shuffles the access addresses to make the corresponding address data present a uniform distribution, which facilitates the balance of subsequent address remapping and channel assignment. In addition, directly using the first sequence as the target sequence can improve the efficiency of address remapping.

[0072] As an example, the binary sequence after S-box mapping The binary sequence is obtained by combining the remapping matrix and address remapping. (i.e., remapping sequence), where address remapping is achieved by constructing a remapping matrix pair. The sequence is linearly mapped. To ensure the invertibility of the address mapping, the remapping matrix needs to be invertible.

[0073] In detail, the remapping matrix is ​​used to reconfigure and store remapping vectors. This matrix is ​​an N×N invertible matrix, where N is the binary sequence after S-box mapping. The length. For example... Figure 4 As shown, Figure 4 This is a schematic diagram of the remapping matrix.

[0074] The remapping matrix consists of N sets of remapping vectors (such as...) Figure 4 Each line in the vector represents a remapping vector. For the binary sequence to be remapped (the address to be remapped)... In order to ensure the uniqueness and reversibility of the mapping, only all address bits corresponding to the high-order address codes divided by the split granularity boundary will be remapped.

[0075] Figure 4 The remapping vector corresponding to the (Ni)th row from top to bottom of the remapping matrix is ​​the binary sequence (address to be remapped) to be remapped mentioned above. The remapping vector of the i-th bit.

[0076] To ensure the reversibility of DDR memory space address mapping, the mapping must be injective (i.e., a one-to-one correspondence) and surjective (all addresses can be accessed after mapping). Since remapping is actually a linear transformation of a certain bit in the original address segment to be mapped, the remapping matrix must be invertible.

[0077] To simplify the generation of the remapping matrix, one implementation method ensures that the remapping matrix is ​​a unit lower triangular matrix. This means that all elements on and below the diagonal of the remapping matrix are 1, while all elements above the diagonal are 0, thus guaranteeing the remapping matrix's invertibility.

[0078] Optionally, for practical application scenarios, the remapping vector can be selectively constructed based on access behavior. If bit j (the j-th bit) within the address segment / target sequence to be mapped does not require remapping, then the elements in the j-th row and j-th column of the remapping matrix are set to 1, and all other elements in the j-th row are set to 0. Accordingly, there is no need to equip this bit with a remapping unit for computation.

[0079] Alternatively, for actual hardware load balancing needs, a resource-saving approach is to remap only the channel index (index is address), BANK index, and BANK GROUP index; that is, only the parts that require load balancing in the actual application scenario are remapped. This corresponds to the index numbers of memory resources in the first sequence as the target sequence mentioned above.

[0080] If the influence of bit k (the kth bit) in the original actual address to be mapped needs to be excluded when mapping the current bit, bit k (the kth bit) in its remapping vector is set to 0. If the change of bit k in the mapping address needs to be included when mapping the current bit, bit k in its remapping vector is set to 1.

[0081] To improve load balancing for random access while adhering to the above constraints, one approach is to generate remapping vectors randomly. This method can be combined with the method described above, which determines the remapping vectors based on specific memory access patterns, to generate the remapping matrix.

[0082] To ensure the invertibility of the mapping, the remapping matrix is ​​determined and configured only during system initialization.

[0083] It is understandable that, for the mapped index, if the high-order bits of the original address corresponding to the bits set to 1 in its remapping vector change continuously, the mapped index will change uniformly, thus achieving load balancing across hardware resources. For random access, since remapping changes the regular arrangement of addresses for directly mapped accesses, it can reduce the probability of load clustering on a few hardware resources.

[0084] As an example, step S300 above involves performing multi-level XOR linked list processing on the data in the remapping sequence to obtain the target index number of the memory resource after remapping, including: S310, Perform multi-level XOR linked list processing on the data in the remapping sequence several times to obtain several processed data; S320, combine several of the processed data to obtain the target index number of the memory resource after remapping.

[0085] Specifically, depending on the type of load balancing required, the memory resources include at least one of channels, banks, and bank groups. The data in the remapping sequence is processed by a multi-level XOR linked list several times. Correspondingly, this includes processing the data in the remapping sequence of a channel by a multi-level XOR linked list several times, or processing the data in the remapping sequence of a bank by a multi-level XOR linked list several times.

[0086] It is important to note that when splitting a channel, the low-order address is strictly isolated at the granular boundary, and only the high-order address is mapped, while the low-order address remains unchanged; this ensures that there are no address conflicts among the sub-requests after splitting and that the order is strictly maintained.

[0087] It is understood that this application performs several multi-level XOR linked list processing on the data in the remapping sequence to obtain several processed data; the several processed data are combined to obtain the target index number of the memory resource after remapping. By combining remapping and XOR linked list, random deviations in memory resource access under business scenarios are eliminated, ensuring load balancing.

[0088] The aforementioned random deviation refers to the phenomenon where the final result does not meet the standard uniform distribution due to randomness.

[0089] As an example, when the memory resource includes a channel, the remapping sequence includes multiple remapping index numbers of the channel and a second high-order data whose address bits are higher than the multiple remapping index numbers of the channel, wherein the second high-order data corresponds to the first high-order data; In step S310, the data in the remapping sequence undergoes several multi-level XOR linked list processing steps to obtain several processed data sets, including: When performing single-level XOR linked list processing, multiple remapping index numbers of the channel and the second high-order data with address bits higher than the remapping index number are XORed pairwise to obtain several intermediate results. Several intermediate results are used as inputs to the next level and XORed pairwise. The resulting new intermediate results are then used as inputs to the next level and XORed pairwise again. This process continues until a single intermediate result is obtained, at which point the single intermediate result is used as the processing data.

[0090] Reference Figure 5 , Figure 5 This illustration demonstrates a flowchart of channel address remapping. Building upon the previous example, this embodiment utilizes a remapping matrix and... Multiply to obtain the sequence Then use the XOR linked list to... Perform multiple XOR operations to obtain the final channel number.

[0091] Specifically, the binary sequence obtained after S-box mapping and address remapping... Perform pairwise XOR operations to eliminate random bias.

[0092] Assuming the original binary sequence = , It belongs to {0, 1} (meaning it takes the value 0 or 1). ,in, express The probability of.

[0093] Ideally, the third sequence after remapping The probability distribution should ideally be uniform; however, in real-world applications, this is often affected by multi-port access scenarios. Not equal to 0.5, if this sequence is used Combining channel numbers can cause distribution uniformity defects.

[0094] This application uses an XOR linked list to eliminate random bias. Assume the sequence... The probability of a certain bit being 1 is 0.6. The sequences corresponding to the output of 1 in the two-level XOR linked list are 01 and 10. The probability distribution is 2 * 0.6 * 0.4 = 0.48.

[0095] When using an n-level XOR linked list, the probability of outputting 1 is calculated as follows: The probability of outputting 0 is Using multi-level XOR linked lists can eliminate random biases caused by uneven bus access.

[0096] Understandably, the XOR linked list works in conjunction with the S-box, which makes the data distribution tend towards a uniform distribution. In the above formula, P will be closer to a probability distribution of 0.5, which will greatly improve the randomness bias of the above process.

[0097] When traversing addresses, this mathematical model is necessarily a perfect mathematical model, with P=0.5. Therefore, the above mapping of 0s and 1s must be evenly distributed. Under the premise of the one-to-one correspondence of the above mapping, the original binary sequence... There will definitely be four channels in a ratio of 1:1:1:1 (this is just an example, and the actual number of channels may not be limited to four).

[0098] Furthermore, since data at or above the channel splitting granularity is used as the original sequence for mapping, and the split data is mapped one by one, address stacking will not occur and the channel imbalance problem can be effectively eliminated.

[0099] Optionally, this application also adopts a channel dynamic balancing scheme: when the number of outstanding commands pending in a single channel causes its DFI (DRAM Physical Interface, i.e., the interface between the memory controller and the memory physical layer) interface resource utilization rate to exceed the effective utilization threshold (i.e., the preset threshold), the system will actively limit the scheduling of that channel.

[0100] The principle is as follows: (1) Resource bottleneck effect: There is a physical limit to the internal resources of a single channel's DFI (such as request queues and timing control units).

[0101] (2) Performance saturation characteristics: Once the outstanding amount of data (incomplete / pending access requests) exceeds the preset threshold, the throughput will no longer increase (marginal benefits will become zero), and even the delay will increase due to congestion.

[0102] In response, the control mechanism adopted in this application is as follows: dynamically configure the upper limit of resource thresholds. When the channel occupancy exceeds the preset threshold, the QoS_BUF (Quality of Service Buffer Manager) module directly rejects the request for dequeueing and scheduling.

[0103] Alternatively, after address mapping, real-time dynamic load balancing can be performed to avoid channel congestion.

[0104] It is understood that the embodiments of this application eliminate random bias by combining S-box mapping, address remapping and XOR linked lists, ensuring load balance among channels and avoiding inefficiency caused by overloaded channels or insufficient commands on some channels.

[0105] As an example, when the memory resource includes a Bank, the remapping sequence includes multiple remapping index numbers of the Bank and a third high-order data whose address is higher than the multiple remapping index numbers of the Bank, and the third high-order data corresponds to the first high-order data; In step S310, the data in the remapping sequence undergoes several multi-level XOR linked list processing steps to obtain several processed data sets, including: When performing single-level XOR linked list processing, the third highest bit of the data with the address bit higher than the remapping index number is XORed pairwise to obtain several intermediate results. Several intermediate results are used as inputs to the next level and subjected to pairwise XOR operations to obtain several new intermediate results. Several new intermediate results are XORed with a single remapping index number of the Bank as the input of the new next level. The resulting updated intermediate results are then XORed again as the input of the new next level until a single intermediate result is obtained. The single intermediate result is then used as the single processing data corresponding to the single remapping index number of the Bank.

[0106] Reference Figure 6 , Figure 6The diagram illustrates the address remapping process for different banks. The overall scheme for bank remapping is similar to that for channel remapping, the difference being that the remapping address range for banks is AXI_ADDR[AXI_ADDR_W:BANK_ADDR], and the arrangement order of S-cell mapping differs from channel mapping. Bank mapping determines the split command size at the granularity of the DRAM chip's page size and performs remapping at the granularity of the split page commands. In contrast, channel split remapping is performed based on the different channel commands split.

[0107] It is understandable that this application makes reasonable use of the various Bank areas of DRAM by combining S-box mapping, address remapping and XOR linked lists to ensure balanced requests between Banks and thus achieve load balancing.

[0108] As one embodiment, when the memory resource includes a Bank, after obtaining the remapped target index number of the memory resource, the method further includes: The remapped target index number of the Bank is concatenated with other addresses in the memory resource access request to obtain the final access address of the Bank.

[0109] Optionally, the address codes of different banks are concatenated with the row address and column address in the access request to be scheduled to obtain the final access address, and each sub-request is scheduled to a different bank based on the final access address.

[0110] Reference Figure 7 , Figure 7 The flowchart of Bank scheduling is shown, in which the Bank remapping address and the original address (the row address and column address in the original access request) are concatenated, and the address order is preserved according to the concatenated remapping address.

[0111] The DFI (DRAM Physical Interface) interface is processed according to Bank group.

[0112] The QOS_BUF (Quality of Service Manager) performs round-robin and bank limit functions on the remapped bank addresses. Specifically, the DFI interface counts the amount of data processed by each bank group and reports this data back to the QOS_BUF. If the number of corresponding bank groups is too large, the priority of the bank groups on the DFI interface is increased. Bank round-robin ensures that each bank group can receive access evenly and fairly.

[0113] Bank address remapping and concatenation with order preservation includes: remapping the target Bank address of the access request; concatenating the remapped Bank address with the row address, column address, etc. in the original access request to form the final access address; and strictly maintaining the address order of the original access request throughout the remapping and concatenation process (order preservation).

[0114] The DFI interface is processed by Bank Group, including: when receiving and processing access requests, the DFI interface is organized and managed in units of Bank Group.

[0115] It is understood that this application concatenates the remapped target index number of the Bank with other addresses in the memory resource access request to obtain the final access address of the Bank, thereby realizing Bank address remapping. This is beneficial for making reasonable use of the various Bank areas of DRAM, ensuring balanced requests between Banks, and thus achieving load balancing.

[0116] As an example, the number of times a single memory resource can be accessed within a time window can be limited, for example, the number of times a single Bank within any Bank group can be accessed within a time window or the number of times any channel can be accessed within a single time window.

[0117] For example, if the memory resource includes a group of banks consisting of multiple banks, then the number of times a single bank can be accessed within a time window can be limited within the group of banks.

[0118] Optionally, this application proposes QoS buffer polling and Bank access restrictions. Specifically, the Quality of Service Manager (QOS_BUF) performs the following actions on memory resource access requests based on the remapped Bank address: Polling: Traverses different banks according to a preset strategy (such as fixed order or priority); Bank access frequency limit: Limits the number of times a single bank can be accessed within a specific time window to prevent a single bank from becoming overloaded.

[0119] Understandably, by implementing load balancing strategies to restrict Banks, more flexible and efficient Bank-level concurrent access control can be achieved. Through coordinated scheduling between and within Bank Groups, access blocking caused by local Bank overload can be effectively reduced, further improving the overall system throughput and response stability. The same principle applies to channel access restrictions.

[0120] As one embodiment, the memory resource includes a group of banks consisting of multiple banks, and the method further includes: Obtain the real-time data processing volume of each of the Bank groups; When the real-time data processing volume of any of the Bank groups exceeds the threshold, the time priority of that Bank group is increased.

[0121] Optionally, this application uses the DFI interface for statistical feedback and dynamic priority adjustment. Specifically, the DFI interface provides real-time statistics on the amount of data being processed or already processed by each Bank Group and feeds this statistical information back to QOS_BUF (Quality of Service Manager).

[0122] Dynamic priority adjustment: If QOS_BUF (Quality of Service Manager) determines based on feedback information that the current processing load (data volume) of a BankGroup exceeds the preset threshold or is relatively too high, it will proactively increase the processing priority of that BankGroup in the DFI layer to accelerate the processing of its requests.

[0123] Optionally, this application uses a bank polling method to ensure fairness among groups, with the polling rules as follows: Within the Bank Group, access requests from each Bank are scheduled through a round-robin mechanism to ensure that all Banks within the same Bank Group receive equal and fair access opportunities. At the Bank Group level, a combination of polling and dynamic priority adjustment mechanisms ensures that high-load Bank Groups receive timely responses while also maintaining access fairness between different Bank Groups.

[0124] In summary, the above-mentioned technical solution of this application proposes a two-level dynamic balancing mechanism, including bank-level balancing and channel-level balancing.

[0125] Bank-level equilibrium includes the following rules: Basic strategy: Ensure a relatively balanced distribution of output commands across banks through round-robin scheduling; Fine-tuning: The DFI interface layer counts the amount of outstanding data to be processed in each Bank Group in real time and feeds it back to the QoS_BUF module; Dynamic weighting: QoS_BUF dynamically increases the scheduling priority of high-load Bank Groups based on load status, while maintaining BANK round-robin within priority constraints.

[0126] Channel-level equalization includes the following rules: Resource hard limits: Dynamically configure the DFI resource thresholds of CHANNEL (such as command queue depth).

[0127] Congestion prevention: When the number of outstanding commands in CHANNEL exceeds the threshold, QoS_BUF directly rejects the commands from the queue to avoid performance collapse caused by resource overload.

[0128] Understandably, this application introduces a dynamic priority mechanism, which not only enhances adaptability to high-load scenarios but also ensures the controllability of Quality of Service (QoS), thereby achieving better storage access performance in complex environments with multiple tasks and high concurrency. Furthermore, PORT arbitration normalizes business scenarios from different PORTs into an AXI_TOP structure for processing, while CHN_SPLIT distributes different services to different channels for parallel processing. QOS_BUF refines the processing of commands within the channel according to BANK information and performs scheduling. Combined with the load balancing characteristics of the above-mentioned load balancing scheme, it fully utilizes granular resources to achieve maximum efficiency in scheduling control.

[0129] Figure 8 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 8 As shown, the electronic device may include: a bus top-level decoding module 810, a communication interface 820, a memory chip (DRAM) 830, and a communication bus 840. The bus top-level decoding module 810, the communication interface 820, and the memory chip (DRAM) 830 communicate with each other via the communication bus 840. When the bus top-level decoding module 810 and the memory chip (DRAM) 830 exchange data or instructions, an address remapping method is executed. This method includes the address remapping method of the above embodiment, and for example, includes the following steps: Obtain the first sequence from the original access address corresponding to the memory resource access request, wherein the first sequence includes the index number of the memory resource determined according to the memory resource access request and the first high-order data with an address higher than the index number; The target sequence corresponding to the first sequence is remapped using a remapping matrix to obtain a remapped sequence. The data in the remapping sequence is processed by a multi-level XOR linked list to obtain the target index number of the memory resource after remapping.

[0130] On the other hand, this application also provides a computer program product, which includes a computer program that can be stored on a computer-readable storage medium. When the computer program is executed by a processor, the computer is able to execute the address remapping method provided by the above methods, the method including: Obtain the first sequence from the original access address corresponding to the memory resource access request, wherein the first sequence includes the index number of the memory resource determined according to the memory resource access request and the first high-order data with an address higher than the index number; The target sequence corresponding to the first sequence is remapped using a remapping matrix to obtain a remapped sequence. The data in the remapping sequence is processed by a multi-level XOR linked list to obtain the target index number of the memory resource after remapping.

[0131] In another aspect, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the address remapping methods provided by the methods described above, the method comprising: Obtain the first sequence from the original access address corresponding to the memory resource access request, wherein the first sequence includes the index number of the memory resource determined according to the memory resource access request and the first high-order data with an address higher than the index number; The target sequence corresponding to the first sequence is remapped using a remapping matrix to obtain a remapped sequence. The data in the remapping sequence is processed by a multi-level XOR linked list to obtain the target index number of the memory resource after remapping.

[0132] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0133] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An address remapping method, characterized in that, include: Obtain the first sequence from the original access address corresponding to the memory resource access request, wherein the first sequence includes the index number of the memory resource determined according to the memory resource access request and the first high-order data with an address higher than the index number; The target sequence corresponding to the first sequence is remapped using a remapping matrix to obtain a remapped sequence. The data in the remapping sequence is processed by a multi-level XOR linked list to obtain the target index number of the memory resource after remapping.

2. The address remapping method according to claim 1, characterized in that, Before performing address remapping on the target sequence corresponding to the first sequence using a remapping matrix to obtain the remapped sequence, the method further includes: Perform S-box mapping on the first sequence to obtain the target sequence corresponding to the first sequence; or, The first sequence is the target sequence; or, The index number of the memory resource in the first sequence is the target sequence.

3. The address remapping method according to claim 1, characterized in that, The step of performing multi-level XOR linked list processing on the data in the remapped sequence to obtain the target index number of the memory resource after remapping includes: The data in the remapping sequence is subjected to several multi-level XOR linked list processing steps to obtain several processed data. By combining several of the processed data, the target index number of the memory resource after remapping is obtained.

4. The address remapping method according to claim 3, characterized in that, When the memory resource includes a channel, the remapping sequence includes multiple remapping index numbers of the channel and a second high-order data whose address is higher than the multiple remapping index numbers of the channel, and the second high-order data corresponds to the first high-order data; The process of performing multiple multi-level XOR linked list processing on the data in the remapping sequence yields several processed data sets, including: When performing single-level XOR linked list processing, multiple remapping index numbers of the channel and the second high-order data with address bits higher than the remapping index number are XORed pairwise to obtain several intermediate results. Several intermediate results are used as inputs to the next level and XORed pairwise. The resulting new intermediate results are then used as inputs to the next level and XORed pairwise again. This process continues until a single intermediate result is obtained, at which point the single intermediate result is used as the processing data.

5. The address remapping method according to claim 3, characterized in that, When the memory resource includes a Bank, the remapping sequence includes multiple remapping index numbers of the Bank and a third high-order data whose address is higher than the multiple remapping index numbers of the Bank, and the third high-order data corresponds to the first high-order data; The process of performing multiple multi-level XOR linked list processing on the data in the remapping sequence yields several processed data sets, including: When performing single-level XOR linked list processing, the third highest bit of the data with the address bit higher than the remapping index number is XORed pairwise to obtain several intermediate results. Several intermediate results are used as inputs to the next level and subjected to pairwise XOR operations to obtain several new intermediate results. Several new intermediate results are XORed with a single remapping index number of the Bank as the input of the new next level. The resulting updated intermediate results are then XORed again as the input of the new next level until a single intermediate result is obtained. The single intermediate result is then used as the single processing data corresponding to the single remapping index number of the Bank.

6. The address remapping method according to claim 1, characterized in that, When the memory resource includes a Bank, after obtaining the remapped target index number of the memory resource, the method further includes: The remapped target index number of the Bank is concatenated with other addresses in the memory resource access request to obtain the final access address of the Bank.

7. The address remapping method according to any one of claims 1 to 6, characterized in that, The method further includes: Limit the number of times a single memory resource can be accessed within a time window.

8. The address remapping method according to any one of claims 1 to 6, characterized in that, The memory resources include a group of banks consisting of multiple banks, and the method further includes: Obtain the real-time data processing volume of each of the Bank groups; When the real-time data processing volume of any of the Bank groups exceeds the threshold, the time priority of that Bank group is increased.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the address remapping method as described in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the address remapping method as described in any one of claims 1 to 8.

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