RapidIO physical layer data seamless segmentation and alignment device

Abstract

According to the RapidIO physical layer data seamless segmentation and alignment device, a determined conversion delay is achieved in the bit width conversion link, compared with an FIFO scheme, additional filling bits do not need to be processed, and compared with an asynchronous FIFO scheme for achieving equal bit width conversion and elastic buffering through a dual-port RAM, the scheme mainly depends on a register and combinational logic, and the conversion delay is determined. Storage resources can be saved, the chip area and static power consumption are correspondingly reduced, and the method is more suitable for application scenarios of large-scale SoC integration. Meanwhile, the device has universal expansibility between a high-speed interface and a Serdes chip, and the application of the device can also be expanded to high-speed interfaces such as PCIe, Ethernet and the like only by ensuring that code block bit width and synchronization head detection logic conform to protocol specifications.

Description

Technical Field

[0001] This invention relates to the field of data stream transmission technology, and more specifically, to a RapidIO physical layer data seamless segmentation and alignment device. Background Technology

[0002] As Moore's Law approaches its physical limits, the development of chip computing power is also beginning to hit a bottleneck. Against the backdrop of the high computing power demands brought about by the rapid development of AI, using high-speed interconnect technology to interconnect multiple chips to form computing power clusters has become an effective solution. RapidIO, as a mature high-speed interconnect interface, is widely used in aerospace, wireless base stations, and other fields due to its low latency and high reliability.

[0003] RapidIO physical layer data streams have two encoding methods: 8b / 10b and 64b / 67b. These require a serial receiver (SerDes) to convert high-speed serial differential signals between boards into parallel data. However, SerDes can only perform serial-to-parallel conversion with fixed data widths, such as 10b and 20b. Therefore, in the physical layer implementation, there is a non-integer multiple bit width conversion requirement between the RapidIO controller's data stream and the SerDes interface (e.g., the least common multiple of 67 and 20 is 1340, with a conversion ratio of 3.35). RapidIO link initialization and maintenance, including link training, clock synchronization, and error recovery, all require data code groups to maintain strict continuity during transmission. Therefore, it is necessary to adopt an efficient measure for seamless code group segmentation and correct alignment.

[0004] Current data bit width conversion methods use multiple RAM buffer units and focus on bit width conversion between different interfaces. Physical layer data stream segmentation methods include boundary recovery when the physical layer data stream of a flash memory storage device is unlocked, using SRAM to cache data, and segmenting the complete code group in the unlocked data stream by detecting specific codeword sequences. Summary of the Invention

[0005] To address the issue of efficient and seamless segmentation and character alignment of physical layer data streams between RapidIO and the high-speed serial receiver SerDes interface, a device for seamless segmentation and alignment of RapidIO physical layer data is provided.

[0006] This invention provides a RapidIO physical layer data seamless segmentation and alignment device, including a data width conversion module, a data buffer module, a codeword boundary detection module, an alignment control module, and a data output module;

[0007] The data width conversion module is used to receive data from the serial receiver SerDes. Bit-width parallel data, and convert it into Bit width data and corresponding valid conversion signal, converted Bit-width data is fed into the data buffer module and the codeword boundary detection module, respectively. The data width conversion module converts the data width based on a phase cyclic shift register.

[0008] The data buffer module is used for processing the converted data. Buffer bit-width data;

[0009] The codeword boundary detection module is used to detect... The synchronization header at each position of the bit-width data outputs the currently detected synchronization header index and codeword lock signal;

[0010] The alignment control module is used to generate an alignment control signal based on the synchronization header index and the codeword locking signal output by the codeword boundary detection module.

[0011] The data output module is used to perform alignment operations on the data buffered by the data buffer module according to the alignment control signal output by the alignment control module, and output the aligned data and codeword alignment signal.

[0012] This invention provides a RapidIO physical layer data seamless segmentation and alignment device. In the bit-width conversion stage, it utilizes a circular shift register to achieve data bit-width conversion, providing a definite conversion delay. Compared to FIFO schemes, it eliminates the need for additional padding bits. Compared to asynchronous FIFO schemes that use dual-port RAM to achieve equal bit-width conversion and elastic buffering, this invention primarily relies on registers and combinational logic, saving storage resources and correspondingly reducing chip area and static power consumption, making it more suitable for large-scale SoC integration applications. Furthermore, this device possesses universal scalability between high-speed interfaces and SerDes chips. As long as the code group bit width and synchronization header detection logic conform to the protocol specifications, the application of this device can also be extended to high-speed interfaces such as PCIe and Ethernet. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a RapidIO physical layer data seamless segmentation and alignment device according to an embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram illustrating data width conversion according to an embodiment of the present invention;

[0015] Figure 3 This is a schematic diagram of a codeword boundary detection state machine according to an embodiment of the present invention;

[0016] Figure 4This is a schematic diagram of a data alignment process according to an embodiment of the present invention;

[0017] Figure 5 This is a schematic diagram of the alignment data output according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0019] In RapidIO board interconnects, data is transmitted serially over transmission lines at extremely high speeds. The receiving end receives a long, continuous stream of bits and cannot determine the correct character boundaries of the received serial data. Therefore, to ensure correct character alignment at the receiving end, the transmitting end typically inserts a special bit sequence (such as the k28.5 sequence in 8b / 10b encoding) periodically into the data stream to assist in data alignment, ensuring that the data can be correctly and completely reconstructed at the receiving end.

[0020] However, when faced with a mismatch in data bit width between the RapidIO controller and the SerDes interface, the controller must first segment the physical layer data to match the SerDes bit width before concatenating and aligning it. This results in a complete code group needing to be sampled multiple times at the receiving end, and ensuring that the multiple sampled code groups can be efficiently and correctly concatenated and aligned becomes a problem that needs to be solved.

[0021] Currently, general data segmentation typically employs an asynchronous FIFO design. However, in non-integer multiple bit-width conversions, the addition of padding bits leads to insufficient bandwidth utilization. Let the input data bit width be... The output data bit width is The size of data fragments generated by each conversion for:

[0022] ;

[0023] The size of the data fragment after n transformations is:

[0024] ;

[0025] The required padding bit size for:

[0026] ;

[0027] Corresponding bandwidth utilization for:

[0028] ;

[0029] FIFO designs can flexibly handle conversions of various bit widths, but require additional storage to cope with burst data. However, the bit width conversion and data rate between the high-speed interface controller and the SerDes interface are relatively fixed, lacking high flexibility and the ability to handle burst data. Furthermore, FIFO designs cannot perform character alignment operations simultaneously during bit width conversions.

[0030] This invention employs a multi-phase rotation buffering method for seamless code group segmentation, utilizing the control word of the code itself for character alignment, thus solving the problem of insufficient bandwidth utilization caused by periodic insertion of padding bits. In terms of hardware implementation, a multi-width shift register is used, and the control word is detected in parallel using multiple segments of data, significantly improving segmentation and alignment efficiency compared to traditional FIFO buffering schemes.

[0031] This invention provides a RapidIO physical layer data seamless segmentation and alignment device. This device achieves reliable data recovery in high-speed serial data transmission through seamless data segmentation and dynamic character alignment technology. The following describes the device in conjunction with… Figure 1 The technical solution of the present invention will be described in detail below.

[0032] Reference Figure 1 The overall architecture diagram of this invention shown primarily comprises: a data width conversion module, a data buffer module, a codeword boundary detection module, an alignment control module, and a data output module. These modules coordinate their operation through a state machine, forming a complete data processing pipeline.

[0033] The working principle of each module is as follows:

[0034] The data width conversion module receives data from the serial receiver SerDes. Bit-width parallel data, and convert it into The data consists of bit-width data (rx_data_xxb_in) and a corresponding valid signal (rx_data_xxb_in_val). The valid signal indicates that the data has undergone bit-width conversion. This conversion process is implemented by an N-phase circular shift register, with only one phase active per clock cycle. The converted data... Bit-width data is sent to the data buffer module, which... The bit-width data is buffered with a delay to facilitate subsequent processing. Meanwhile, the bit-width converted data... The bit-width data is also sent to the codeword boundary detection module, which detects... The synchronization header (SyncHeader) in the bit-wide data stream is used to determine possible codeword boundaries. The codeword boundary detection module outputs the currently detected synchronization header index (sync_hdr_index) and the codeword lock signal (cw_lock). The alignment control module controls the data alignment operation based on the synchronization header index and codeword lock signal output by the codeword boundary detection module. It generates alignment control signals to control the data buffer module and the data output module. The data output module, based on the alignment control signals from the alignment control module, aligns the buffered data output by the data buffer module, outputting the aligned data (rx_data_cw_xxb) and a valid signal (rx_data_cw_xxb_val).

[0035] Reference Figure 2 The data width conversion diagram shown represents the data width for any receiver input bit width. and output bit width The data width conversion module converts the data bit width.

[0036] The data width conversion module includes: Data buffer unit, phase generation unit, data accumulation unit, and data reassembly unit.

[0037] The data width conversion module is used to receive data from the serial receiver SerDes. Bit-width parallel data, and convert it into Bit-width data and corresponding valid signals, including:

[0038] Data buffer unit, used to receive data from serial receiver SerDes. Bit-width parallel data is buffered with a delay.

[0039] calculate and Least common multiple L = LCM ( , );

[0040] Calculate N and M respectively, where:

[0041] when > When calculating the number of input cycles, N = L / Calculate the number of output cycles M = L / ;

[0042] when < When calculating the number of output cycles, N = L / ; Calculate the number of input cycles M = L / .

[0043] Here, it should be noted that if > Then N is the number of input cycles, and M is the number of output cycles; if < Then N is the number of output cycles and M is the number of input cycles, which means N > M.

[0044] The phase generation unit is used to generate a phase cyclic shift register with N phases based on the calculated value of N, and the state cycles from 0 to N-1.

[0045] In each state, the input The data is temporarily stored in the data accumulation unit, which is an accumulation register;

[0046] In M specific states, i.e., states 0 to M-1, to ensure that M output cycles are generated within N input cycles, the number of bits in the accumulation register is greater than or equal to... At this point, the output will be... Bit data, and remove the output data from the accumulation register;

[0047] The data recombination unit is used to recombine the accumulated data with the current input data when a specific phase of the phase cyclic shift register is activated, forming a complete data reconstructed data. Bit data output.

[0048] The data bit-width conversion module of this invention uses deterministic delay and fixed phase control logic to convert... Bit input stream converted to The data bit-width conversion module includes an N-state phase loop register. This register controls data accumulation and concatenation, generating a fixed number of N-bit data blocks within M clock cycles. The entire process does not rely on complex buffer management, reducing storage resource consumption. This segmented accumulation and reassembly mechanism achieves seamless conversion from input to output data.

[0049] In one embodiment of the present invention, the codeword boundary detection module includes a codeword boundary detection unit, a synchronization head detection array, a state machine controller, and various counters, such as a valid counter, an invalid counter, and a codeword counter.

[0050] The codeword boundary detection module is used to detect... The synchronization header at each position of the bit-width data outputs the currently detected synchronization header index and codeword lock signal, including:

[0051] The synchronization head detection array is used for parallel detection. The synchronization headers of K blocks of bit-width data are detected, the synchronization header index of each block is calculated, and the synchronization header index of each block is passed to the alignment control module. Bit-width data is divided into K blocks of data in bytes for detection, where K=⌈ / 8⌉;

[0052] The codeword boundary detection unit is used to detect codeword boundaries based on the number of consecutively detected valid synchronization headers at the same position in different code groups, as counted by the valid counter, and output a codeword lock signal.

[0053] The state machine controller is used to control the transition between each state.

[0054] Reference Figure 3 The diagram shown illustrates the state machine for codeword boundary detection. The codeword boundary detection module is implemented using a finite state machine (FSM), which includes six main states: initial state, detection control word, synchronization counting, locking, and slider alignment. The spike codeword detection process is as follows:

[0055] In the initial state, the system initializes, sets the synchronization header index to 0, clears the valid counter V_cntr and the invalid counter IV_cntr to zero, and prepares to start the boundary detection process.

[0056] During the detection of the control word status, the system scans the input data stream and simultaneously detects the status via the synchronization header detection array. The synchronization header is located at a specific position. The synchronization header detection logic is based on the RapidIO protocol's encoding specification, identifying the synchronization header by detecting the XOR relationship between two adjacent data bits. The specific detection logic is: val_sync_hdr_i=(rx_data_xxb[i]&!rx_data_xxb[i+1]) | (!rx_data_xxb[i] & rx_data_xxb[i+1]) where i ranges from 0 to... -1, when i equals When -1, the 0th bit is checked against the 1st bit. -1 bit XOR relationship.

[0057] In synchronization counting mode, the system verifies the stability of candidate synchronization header positions. The V_cntr counter counts the number of consecutive successful synchronization headers detected at the same position in different code groups. When the number of consecutive successful detections exceeds a preset threshold V_CNTR_MAX (usually the full codeword width), the codeword boundary is considered successfully locked, and a codeword lock signal is output. For example, if the third bit of the current code group is detected as a valid synchronization header, then the system checks the validity of the third bit of each subsequent code group. If the third bit of w consecutive code groups is valid, and w is greater than or equal to the codeword width, then the third bit is considered a codeword boundary, and a codeword lock signal is output, indicating that the third bit of the code group is a codeword boundary.

[0058] Once character alignment is complete, the system confirms the alignment is finished, outputs the codeword lock signal cw_lock, resets all counters, and enters a stable operating mode. At this point, the device begins outputting the aligned valid data.

[0059] During the lock period, the system maintains the locked state and continuously monitors the synchronization header position. The CW_cntr codeword counter counts consecutive correct synchronization header detections, while the IV_cntr counter monitors for anomalies. The IV_cntr counter counts the number of consecutive invalid synchronization headers at the same position. When the number of consecutive invalid synchronization headers exceeds the set IV_cntr_max threshold (usually no greater than 5), the system determines that synchronization has been lost and returns to the initial state for resynchronization.

[0060] In this embodiment of the invention, the codeword boundary detection unit detects codeword boundaries by means of slider alignment. In the slider alignment state, if a valid synchronization header at the current position is not detected in a certain code group data, the slider is automatically moved to the next synchronization header index position of the next code group for detection, and the valid count is cleared. The detection is then carried out again with a new candidate synchronization header position to achieve dynamic alignment.

[0061] Among them, in parallel detection of the synchronization head detection array During the synchronization header process for each bit-width data position, the input... Bit-width data is divided into K units, each consisting of 8 bytes (K = ⌈). The system performs parallel detection of 8 blocks of data, calculates the synchronization header index (sync_hdr_index) of the corresponding block based on the detected synchronization header, and passes it to the alignment control module.

[0062] The codeword boundary detection module in this invention divides the input data into multiple detection channels in bytes and scans candidate synchronization header positions in parallel. The control state machine includes six main states: initial state, detection control word, synchronization count, locking, and slider alignment. It makes state transition decisions through valid and invalid counters, and can quickly recover when synchronization loss is detected.

[0063] Reference Figure 4 The data alignment flowchart shown illustrates that, in one embodiment of the present invention, the alignment control module includes an index parsing unit, a data slider unit, and a multiplexed output selection unit. The alignment control module is used to generate an alignment control signal based on the synchronization header index and the codeword locking signal output by the codeword boundary detection module, including:

[0064] The index parsing unit is used to parse the synchronization header index transmitted by the codeword boundary detection module, and decompose the synchronization header index into a high-order segment selection signal and a low-order offset. The high-order segment selection signal is used to determine the block to which the data belongs, and the low-order offset is used to control the specific cyclic shift operation of the data.

[0065] Specifically, the index parsing unit in the alignment control module decomposes the synchronization header index `sync_hdr_index` into a high-order segment selection signal and a 3-bit low-order offset. The high-order segment selection signal is used to determine the processing stage to which the data belongs, and the low-order offset is used to control the specific cyclic shift operation. The block to which the data belongs is determined based on the high-order `sync_hdr_index` [2+log2K:3], and each block is responsible for processing a different range of synchronization header indices.

[0066] When sync_hdr_index[2+log2K:3]=0, the index range is 0-7 bits;

[0067] When sync_hdr_index[2+log2K:3]=1, the index range is 8-15 bits;

[0068] When sync_hdr_index[2+log2K:3]=2, the index range is 16-23 bits.

[0069] The data slider unit is used to read data from the data buffer module based on the high-order segment selection signal and the low-order offset. Bit width data, for The corresponding block data in the bit-width data is subjected to the corresponding cyclic shift operation to obtain the corresponding block data after the shift operation.

[0070] Specifically, the data slider unit performs a corresponding cyclic shift operation on the input data based on the lower 3 bits of the synchronization header index sync_hdr_index[2:0]. The shift logic is based on the following principles:

[0071] When sync_hdr_index[2:0]=0, the data is output as is;

[0072] When sync_hdr_index[2:0]=1, the data is cyclically shifted right by 1 bit;

[0073] When sync_hdr_index[2:0]=2, the data is cyclically shifted right by 2 bits;

[0074] And so on.

[0075] The multi-output selection unit is used to select the corresponding channel to transmit the corresponding block data after the shift operation to the data output module.

[0076] In this embodiment of the invention, the alignment control module divides the calculated synchronization header index into high-order block selection and low-order offset, achieving two-level control. The data segmentation and alignment device can quickly locate the position of the next candidate synchronization header when the current synchronization header is invalid, without scanning the entire code group bit by bit. In optimal conditions, alignment can be completed within N cycles.

[0077] In one embodiment of the present invention, the data output module includes a multi-channel output array and an output selection logic unit. The data output module is used to read buffered data from the data buffer module according to the alignment control signal of the alignment control module, perform alignment operation on the data, and output aligned data and codeword alignment signal, including:

[0078] A multi-channel output array is used to receive the shifted block data output by the multi-output selection unit through corresponding channels, perform a concatenation and alignment operation based on the current valid codeword and the previous valid codeword of the block data, and transmit the concatenated and aligned block data and codeword alignment signal to the output selection logic unit. The concatenation logic is as follows:

[0079] data_out={rx_data_xxb_d[m*8+n-1:0], rx_data_xxb[ -1:m*8+n]};

[0080] Where data_out is the data after the current block splicing and alignment operation, rx_data_xxb_d is the previous valid codeword, rx_data_xxb is the current valid codeword, m is the channel number, and n is the offset;

[0081] The output selection logic unit is used to output the block data after splicing and alignment operation according to the channel selection signal and the codeword alignment signal. The channel selection signal indicates the currently active channel to output the corresponding block data. The codeword alignment signal indicates whether the codeword has been successfully aligned based on whether the count of the effective counter is greater than the codeword bit width.

[0082] Specifically, the data output module divides the received current valid codeword rx_data_xxb and the previous valid codeword rx_data_xxb_d into K blocks according to the synchronization index, and performs concatenation and alignment operations on each block. The concatenation logic is as follows:

[0083] When sync_hdr_index[2+log2K:3]=m and sync_hdr_index[2:0]=n, the output data is as follows:

[0084] data_out={rx_data_xxb_d[m*8+n-1:0],rx_data_xxb[ -1:m*8+n]};

[0085] The outputs of all blocks are simultaneously sent to the output selection logic unit, which receives two control signals:

[0086] 1. Channel selection signal: Indicates which channel is currently active;

[0087] 2. Codeword alignment signal (cw_lock): Indicates whether the system has successfully aligned the codeword based on whether the valid count is greater than the codeword width.

[0088] The output selection logic unit selects the corresponding channel output as the final aligned data based on the channel selection signal. If the codeword alignment signal cw_lock=0, it outputs invalid data or retains the output of the previous cycle. The aligned data output is as follows: Figure 5 As shown.

[0089] The purpose of this invention is to address the bit-width conversion and character alignment issues in RapidIO physical layer data transmission by providing an efficient and reliable device for seamless segmentation and alignment of RapidIO physical layer data, achieving high-bandwidth, low-latency, and low-error-rate data transmission. It has the following advantages:

[0090] (1) A circular shift register is used in the bit-width conversion stage, which has a definite conversion delay and does not require additional padding bits compared to the FIFO scheme. Parallel processing structure is used in the codeword boundary detection and character alignment stages, which can achieve high throughput and low synchronization time. Compared with the asynchronous FIFO scheme that uses dual-port RAM to achieve the same bit-width conversion and elastic buffer, the present invention mainly relies on registers and combinational logic, which can save storage resources, reduce chip area and static power consumption, and is more suitable for large-scale SoC integration application scenarios. At the same time, the device has universal scalability between high-speed interfaces and SerDes chips. As long as the code group bit width and synchronization header detection logic conform to the protocol specifications, the application of the device can also be extended to high-speed interfaces such as PCIe and Ethernet.

[0091] (2) It is suitable for physical layer data processing in the RapidIO protocol, providing reliable data link layer support for high-speed interconnect communication systems, and has industrial application value in fields such as 5G communication, high-performance computing, and industrial automation.

[0092] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0093] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0094] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0095] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0096] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0097] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0098] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A RapidIO physical layer data seamless segmentation and alignment device, characterized in that, It includes a data width conversion module, a data buffer module, a codeword boundary detection module, an alignment control module, and a data output module; The data width conversion module is used to receive data from the serial receiver SerDes. Bit-width parallel data, and convert it into Bit width data and corresponding valid conversion signal, converted Bit-width data is fed into the data buffer module and the codeword boundary detection module, respectively. The data width conversion module converts the data width based on a phase cyclic shift register. The data buffer module is used for processing the converted data. Buffer bit-width data; The codeword boundary detection module is used to detect... The synchronization header at each position of the bit-width data outputs the currently detected synchronization header index and codeword lock signal; The alignment control module is used to generate an alignment control signal based on the synchronization header index and the codeword locking signal output by the codeword boundary detection module. The data output module is used to perform alignment operations on the data buffered by the data buffer module according to the alignment control signal output by the alignment control module, and output the aligned data and codeword alignment signal.

2. The RapidIO physical layer data seamless segmentation and alignment device according to claim 1, characterized in that, The data width conversion module includes Data buffer unit, phase generation unit, data accumulation unit, and data reassembly unit; The data width conversion module is used to receive data from the serial receiver SerDes. Bit-width parallel data, and convert it into Bit-width data and the corresponding valid conversion signal, including: The Data buffer unit, used to receive data from serial receiver SerDes. Bit-width parallel data is buffered; The phase generation unit is used to calculate the least common multiple L = LCM( , ), and calculate N and M respectively, where: when > When calculating the number of input cycles, N = L / Calculate the number of output cycles M = L / ; when < When calculating the number of output cycles, N = L / ; Calculate the number of input cycles M = L / ; The phase generation unit is also used to generate a phase cyclic shift register with N phases based on the calculated N, with the state cycling from 0 to N-1. In each state, the input The data is temporarily stored in the data accumulation unit, which is an accumulation register; Under M specific states, the number of bits in the accumulation register is greater than or equal to At this point, the output will be... Bit data, and remove the output data from the accumulation register; The data recombination unit is used to recombine the accumulated data with the current input data when a specific phase of the phase cyclic shift register is activated, forming a complete... Bit data output.

3. The RapidIO physical layer data seamless segmentation and alignment device according to claim 1, characterized in that, The codeword boundary detection module includes a codeword boundary detection unit, a synchronization head detection array, and a state machine controller; The codeword boundary detection module is used to detect... The synchronization header at each position of the bit-width data outputs the currently detected synchronization header index and codeword lock signal, including: The synchronization head detection array is used for parallel detection. The synchronization headers of K blocks of bit-width data are detected, the synchronization header index of each block is calculated, and the synchronization header index of each block is passed to the alignment control module. Bit-width data is divided into K blocks of data in bytes for detection, where K=⌈ / 8⌉; The codeword boundary detection unit is used to detect codeword boundaries based on the number of consecutively detected valid synchronization headers at the same position in different code groups, as counted by the valid counter, and output a codeword lock signal. The state machine controller is used to control the transition between each state.

4. The RapidIO physical layer data seamless segmentation and alignment device according to claim 3, characterized in that, The synchronization head detection array is used for parallel detection. The synchronization headers of K blocks of bit-width data are checked, including: The coding specification based on the RapidIO protocol identifies the synchronization header by detecting the XOR relationship of adjacent bits in each block of data. Its retrieval logic is as follows: val_sync_hdr_i=(rx_data_xxb[i]&!rx_data_xxb[i+1])|(!rx_data_xxb[i] & rx_data_xxb[i+1]); Where val_sync_hdr_i is the synchronization header detection result of the i-th bit data, rx_data_xxb[i] is the i-th bit data in the block data, rx_data_xxb[i+1] is the (i+1)-th bit data in the block data, and the value of i ranges from 0 to 7. When i equals 7, the XOR relationship between the 0th bit and the 7th bit is detected. The codeword boundary detection unit is used to detect codeword boundaries based on the number of consecutively detected valid synchronization headers at the same position in different code groups, as counted by an effective counter, and outputs a codeword lock signal, including: According to The synchronization header detection results for each block of data in the bit-width code group are based on the number of consecutive valid synchronization headers detected at the same position in different code group data according to the effective counter. When the number of consecutive valid synchronization headers detected is greater than or equal to the preset effective threshold V_CNTR_MAX, it is determined that the codeword boundary has been successfully locked, and a codeword locking signal is output. The codeword locking signal indicates the position of the codeword boundary, and the preset effective threshold V_CNTR_MAX is the full codeword bit width.

5. The RapidIO physical layer data seamless segmentation and alignment apparatus according to claim 3 or 4, characterized in that, Also includes: During the locking period, the codeword boundary detection unit maintains the locked state and continuously monitors the synchronization header position. It uses a codeword counter to count consecutive correct synchronization header detections and an invalid counter to monitor for abnormal synchronization header detections. When the invalid counter counts more than the preset invalid threshold number of consecutive invalid synchronization headers at the same position in different code groups, synchronization is determined to be lost, and the system returns to the initial state to re-detect the synchronization header.

6. The RapidIO physical layer data seamless segmentation and alignment apparatus according to claim 3, characterized in that, The codeword boundary detection unit is used to detect codeword boundaries based on the number of times a valid synchronization header is continuously detected at the same position in different code groups, as counted by a valid counter, and to output a codeword lock signal. It also includes: The codeword boundary is detected by a slider alignment method. In the slider alignment state, if a valid synchronization header at the current position is not detected in the current code group data, the slider is automatically moved to the next synchronization header index position in the next code group data. At the same time, the valid counter is cleared and the detection is re-detected with the new candidate synchronization header position to achieve dynamic alignment.

7. The RapidIO physical layer data seamless segmentation and alignment apparatus according to claim 3, characterized in that, The alignment control module includes an index parsing unit, a data slider unit, and a multiplex output selection unit; The alignment control module is used to generate an alignment control signal based on the synchronization header index and the codeword locking signal output by the codeword boundary detection module, including: The index parsing unit is used to parse the synchronization header index transmitted by the codeword boundary detection module, and decompose the synchronization header index into a high-order segment selection signal and a low-order offset. The high-order segment selection signal is used to determine the block to which the data belongs, and the low-order offset is used to control the specific cyclic shift operation of the data. The data slider unit is used to adjust the output of the data buffer module according to the high-order segment selection signal and the low-order offset. The corresponding block data in the bit-width data is subjected to the corresponding cyclic shift operation to obtain the corresponding block data after the shift operation; The multi-output selection unit is used to select the corresponding channel to transmit the corresponding block data after the shift operation to the data output module.

8. The RapidIO physical layer data seamless segmentation and alignment apparatus according to claim 7, characterized in that, The low-order offset is 3 bits, and it is used to control the specific cyclic shift operation of the data, including: When the low-order offset is 0, the output remains unchanged. When the lower 3 bits offset is 1, the data is cyclically shifted right by 1 bit; When the lower 3 bits offset is 2, the data is cyclically shifted right by 2 bits.

9. The RapidIO physical layer data seamless segmentation and alignment apparatus according to claim 7, characterized in that, The data output module includes a multi-channel output array and an output selection logic unit. The data output module is used to perform alignment operations on the data buffered by the data buffer module according to the alignment control signal from the alignment control module, and output the aligned data and codeword alignment signal, including: The multi-channel output array is used to receive the shifted block data output by the multi-output selection unit through corresponding channels, perform a concatenation and alignment operation based on the current valid codeword and the previous valid codeword of the block data, and transmit the concatenated and aligned block data and codeword alignment signal to the output selection logic unit. The concatenation logic is as follows: data_out={rx_data_xxb_d[m*8+n-1:0], rx_data_xxb[ -1:m*8+n]}; Where data_out is the data after the current block splicing and alignment operation, rx_data_xxb_d is the previous valid codeword, rx_data_xxb is the current valid codeword, m is the channel number, and n is the offset; The output selection logic unit is used to output the block data after splicing and alignment operation according to the channel selection signal and the codeword alignment signal. The channel selection signal indicates the currently active channel to output the corresponding block data. The codeword alignment signal indicates whether the codeword has been successfully aligned based on whether the count of the effective counter is greater than the codeword bit width.

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