Serial communication interface and processor

Abstract

The invention discloses a serial communication interface and a processor. Wherein the serial communication interface comprises a register, a main controller, a dynamic reconfiguration controller and a self-adaptive forward error correction module; the dynamic reconstruction controller is tightly coupled with the register, controls the main controller and the adaptive forward error correction module, automatically constructs a command frame in a predefined format, monitors a data stream of the register, and starts an in-band signaling mechanism; and the dynamic reconstruction controller receives an internal negotiation request actively initiated by the adaptive forward error correction module, initiates an external negotiation request, requests to enter a forward error correction mode or quits the forward error correction mode according to a judgment condition of the adaptive forward error correction module, and realizes adaptive closed-loop control. According to the embodiment of the invention, the corresponding communication parameters of the serial communication interface can be directly and seamlessly adjusted, the communication quality of the channel can be actively monitored, the hardware forward error correction function is automatically enabled when the error rate is increased, and the hardware forward error correction function is automatically disabled when the channel is recovered to be good.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more particularly to a serial communication interface and processor. Background Technology

[0002] Serial communication interfaces are fundamental peripherals in microcontroller units (MCUs) and embedded systems for inter-device communication. Among related technologies, the universal asynchronous receiver / transmitter (UART) and universal synchronous / asynchronous receiver / transmitter (USART) are currently widely used serial communication interfaces in MCUs and embedded systems. The working principle of a serial communication interface is to convert parallel data from the central processing unit (CPU) into serial data for transmission. A typical serial communication interface hardware structure mainly includes a programmable baud rate generator, a transmit shift register, a receive shift register, and a set of control registers for configuration and status monitoring. Before serial communication, the system software must statically configure the communication parameters by writing to the control registers. Communication parameters may include: baud rate, data bits (usually 8 bits), stop bits (usually 1 bit), and parity mode (such as no parity, odd parity, or even parity). After the communication parameters are configured, serial communication can be performed through the serial communication interface: When sending, the CPU writes the data into the transmit shift register, the hardware automatically adds the start bit, parity bit and stop bit, and then shifts it out bit by bit through the transmit shift register at the set baud rate; when receiving, after the hardware detects the start bit, it samples bit by bit at the same rate, stores it in the receive shift register, and provides the data to the CPU after stripping the frame control bit.

[0003] The serial communication interfaces in related technologies have obvious inherent limitations and defects. First, the configuration of these interfaces is rigid. Once communication begins, any change in parameters requires disabling the interface, reconfiguring, and restarting, leading to communication interruptions and failing to meet the needs of complex application scenarios requiring dynamic adaptation to different devices or protocols. Second, the anti-interference capability of these interfaces is very weak. Traditional parity checks can only detect errors in an odd number of bits and cannot correct them. In environments with severe electromagnetic interference, such as industrial automation or automotive electronics, high bit error rates severely impact communication reliability, forcing upper-layer application software to frequently retransmit data, thereby reducing system efficiency. Therefore, the serial communication interfaces in these technologies are no longer sufficient to meet the demands of modern intelligent and high-reliability applications in terms of flexibility and robustness. Summary of the Invention

[0004] This invention provides a serial communication interface and processor to solve the problems of rigid configuration and weak anti-interference capability of serial communication interfaces in related technologies.

[0005] According to one aspect of the present invention, a serial communication interface is provided, including registers and a main controller, characterized in that it further includes: a dynamic reconfiguration controller and an adaptive forward error correction module;

[0006] Among them, the dynamic reconfiguration controller is connected to the main controller, the adaptive forward error correction module is connected to the register, and the dynamic reconfiguration controller and the adaptive forward error correction module are directly connected through signal lines.

[0007] The dynamic reconfiguration controller is tightly coupled with the registers, controls the main controller and the adaptive forward error correction module, automatically constructs command frames in a predefined format, monitors the data flow of the registers, and initiates the in-band signaling mechanism;

[0008] Based on the judgment conditions of the adaptive forward error correction module, the dynamic reconfiguration controller receives the internal negotiation request initiated by the adaptive forward error correction module, initiates the external negotiation request, and requests to enter or exit the forward error correction mode.

[0009] Optionally, the dynamic reconfiguration controller includes a command detector, a command parser, a main state machine, a parameter update logic unit, and a response generator; wherein, the command detector is connected to the main state machine and the command parser respectively, the command detector monitors the data stream sent by the registers and identifies command frames in a predefined format, the command frame including an escape sequence, a command identifier, parameters, parameter length, and a checksum.

[0010] Optionally, the command parser is connected to the main state machine, the command detector, and the parameter update logic unit, respectively. The command parser is driven by the main state machine to extract and verify command frames in a predefined format.

[0011] Optionally, the parameter update logic unit generates control signals based on the commands parsed by the command parser and sends them to the main controller for control.

[0012] Optionally, the response generator is driven by the master state machine to construct the corresponding acknowledgment command frame or negative acknowledgment command frame, send it to the transmission path, and send it back.

[0013] Optionally, the dynamic reconfiguration controller initiates in-band signaling mechanisms, including:

[0014] The dynamic reconfiguration controller receives parameter modification commands;

[0015] After receiving a parameter modification instruction, the dynamic reconfiguration controller constructs a parameter modification command frame in a predefined format and sends the parameter modification command frame into a register.

[0016] After receiving the confirmation command frame, the dynamic reconfiguration controller performs a synchronous switch.

[0017] Optionally, the dynamic reconfiguration controller initiation in-band signaling mechanism also includes:

[0018] The dynamic reconfiguration controller receives command frames and continuously monitors the data stream while receiving data. When it detects a received parameter modification command frame, it intercepts the subsequent byte stream from the main data path and performs command parsing on the parameter modification command frame.

[0019] After confirming that the checksum is correct, the dynamic reconfiguration controller executes the parameter modification command, and after successful execution, constructs a confirmation command frame and sends it back.

[0020] Optionally, the adaptive forward error correction module includes an encoding path and a decoding path;

[0021] The encoding path includes an FEC encoder;

[0022] The FEC encoder is responsible for converting raw data bytes into codewords with redundant check bits.

[0023] The decoding path includes an accompanying calculator, an error corrector, and a data extractor. The accompanying calculator is connected to the error corrector, and the error corrector is connected to the data extractor.

[0024] The accompanying calculator is used to detect data errors, the error corrector repairs errors in the data based on the output of the accompanying calculator, and the data extractor is used to restore the original data.

[0025] Optionally, the adaptive forward error correction module also includes adaptive control logic, which includes an error rate monitor and a decision logic unit, with the error rate monitor connected to the decision logic unit.

[0026] The error rate monitor calculates the communication error rate of the current line based on the error status information of the current line obtained from the decoding path.

[0027] The decision logic unit receives the communication error rate value provided by the error rate monitor, compares the communication error rate value with the preset enable / disable threshold, and actively sends an internal negotiation request to the dynamic reconfiguration controller based on the comparison result.

[0028] Optionally, the dynamic reconfiguration controller, based on internal negotiation requests, initiates external negotiation requests to request entry into or exit from forward error correction mode, including:

[0029] When the decision logic unit inside the adaptive forward error correction module determines that the communication error rate of the current line exceeds the activation threshold, it actively sends an internal negotiation request to the dynamic reconfiguration controller.

[0030] After receiving an internal negotiation request, the dynamic reconfiguration controller uses in-band signaling to initiate an external negotiation request, requesting to enter forward error correction mode.

[0031] After successful negotiation, the adaptive forward error correction module is activated and intervenes in the data path; when sending data, the adaptive forward error correction module performs hardware encoding on each data byte, generates a long codeword containing redundancy check information according to the preset error correction algorithm, and sends the long codeword for transmission.

[0032] When receiving data, the adaptive forward error correction module performs a reverse operation, decodes the received long codeword, uses redundant information to detect and repair bit errors generated in the data bytes during transmission, and restores the original data.

[0033] Optionally, the dynamic reconfiguration controller, based on internal negotiation requests, initiates external negotiation requests to request entry into or exit from forward error correction mode, and also includes:

[0034] When the decision logic unit inside the adaptive forward error correction module determines that the communication error rate of the current line is continuously lower than the disable threshold, it actively sends an internal negotiation request to the dynamic reconfiguration controller.

[0035] After receiving an internal negotiation request, the dynamic reconfiguration controller uses in-band signaling to initiate an external negotiation request to request to exit the forward error correction mode.

[0036] After successful negotiation, the adaptive forward error correction module exits the activation mode and stops intervening in the data path.

[0037] According to another aspect of the present invention, a processor is provided, including the serial communication interface provided by the present invention.

[0038] In the technical solution of this invention, the dynamic reconfiguration controller is tightly coupled with the register, controlling the main controller and the adaptive forward error correction module. It automatically constructs command frames in a predefined format, monitors the data flow of the register, and initiates an in-band signaling mechanism. Based on the judgment conditions of the adaptive forward error correction module, the dynamic reconfiguration controller receives internal negotiation requests initiated by the adaptive forward error correction module, initiates external negotiation requests, and requests to enter or exit the forward error correction mode, thus achieving adaptive closed-loop control. This solves the problems of rigid serial communication interface configuration and weak anti-interference capability in related technologies. Based on the dynamic reconfiguration controller, it can monitor the control signaling transmitted on the physical channel in real time, and directly and seamlessly adjust the corresponding serial communication interface after detecting valid control signaling for modifying communication parameters. The communication parameters can be negotiated and seamlessly switched in real time without interrupting the data flow, realizing online dynamic adjustment of communication parameters. This completely solves the problem of lack of flexibility caused by static configuration of traditional interfaces. Based on the collaborative work between the dynamic reconfiguration controller and the adaptive forward error correction module, it can actively monitor the communication quality of the channel. When an increase in error rate is detected, it automatically negotiates with the peer and enables the hardware forward error correction function to encode and correct the transmitted data in real time. When the channel recovers well, it automatically disables the hardware forward error correction function to optimize data throughput and improve the anti-interference capability of the serial communication interface. This enables the serial communication interface to intelligently achieve a dynamic balance between communication reliability and efficiency, thereby greatly enhancing the robustness of the serial communication interface in complex environments.

[0039] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a serial communication interface provided in an embodiment of the present invention.

[0042] Figure 2 This is a schematic diagram of a serial communication interface provided in an embodiment of the present invention.

[0043] Figure 3 This is a schematic diagram of a dynamic reconfiguration controller provided in an embodiment of the present invention.

[0044] Figure 4 This is a schematic diagram illustrating a communication parameter modification process provided in an embodiment of the present invention.

[0045] Figure 5 This is a schematic diagram of the structure of an adaptive forward error correction module provided in an embodiment of the present invention.

[0046] Figure 6 This is a schematic diagram of an adaptive error correction process provided in an embodiment of the present invention.

[0047] Figure 7 This is a schematic diagram of the structure of a processor provided in an embodiment of the present invention. Detailed Implementation

[0048] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "target," "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising," "including," and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0050] Figure 1 This is a schematic diagram of a serial communication interface provided in an embodiment of the present invention. This embodiment is applicable to situations where an MCU and an embedded system communicate with each other. The serial communication interface is located on the MCU or the embedded system. Figure 1 As shown, the serial communication interface 100 may specifically include: register 101, main controller 102, dynamic range controller (DRC) 103 and adaptive forward error correction module (AFEC) 104. Its structure and function are described below.

[0051] Among them, the dynamic reconfiguration controller 103 is connected to the main controller 102, the adaptive forward error correction module 104 is connected to the register 101, and the dynamic reconfiguration controller 103 and the adaptive forward error correction module 104 are directly connected through signal lines.

[0052] The dynamic reconfiguration controller 103 is tightly coupled with the register 101, controls the main controller 102 and the adaptive forward error correction module 104, automatically constructs command frames in a predefined format, monitors the data flow of the register 101, and initiates the in-band signaling mechanism.

[0053] The dynamic reconfiguration controller 103 receives an internal negotiation request initiated by the adaptive forward error correction module 104 based on the judgment conditions of the adaptive forward error correction module, initiates an external negotiation request, and requests to enter or exit the forward error correction mode to achieve adaptive closed-loop control.

[0054] like Figure 2 As shown, the serial communication interface 200 includes: a register 201, a main controller 202, a dynamic reconfiguration controller 203, and an adaptive forward error correction module 204. Optionally, the register 201 includes a control register 2011, a data transceiver register 2012, and a shift register 2013; the main controller 202 includes a baud rate generator 2021 and a frame format controller 2022, and the control register 2011, baud rate generator 2021, and frame format controller 2022 are connected to the dynamic reconfiguration controller 203; the data transceiver register 2012 and shift register 2013 are connected to the adaptive forward error correction module 204.

[0055] Optionally, the control register 2011, dynamic reconfiguration controller 103, baud rate generator 2021, frame format controller 2022, and adaptive forward error correction module 104 constitute the control path in the serial communication interface 200. The data transceiver register 2012, adaptive forward error correction module 104, and shift register 2013 constitute the data path in the serial communication interface 200.

[0056] Optionally, the control register 2011 can be a set of registers used to manage all configuration and status information of the serial communication interface 200. The CPU in the device housing the serial communication interface 200 connects to the control register 2011 via a bus interface in the CPU core. The control register 2011 can interact with the dynamic reconfiguration controller 103. The CPU can send instructions to the control register 2011 to configure the communication parameters of the serial communication interface 200. The control register 2011 then sends the received instructions to the dynamic reconfiguration controller 203.

[0057] Optionally, the dynamic reconfiguration controller 203 can be a controller used to monitor command frames and instructions for modifying the communication parameters of the serial communication interface 200, and to modify the communication parameters of the serial communication interface 200 according to the monitored command frames or instructions. The communication parameters of the serial communication interface 200 may include the baud rate, data bits, stop bits, and parity method of the serial communication interface 200. For example, the data bits are 8, the stop bits are 1, and the parity method is no parity, odd parity, or even parity. The baud rate is stored in the register of the baud rate generator 2021. The data bits, stop bits, and parity method are stored in the register of the frame format controller 2022. The dynamic reconfiguration controller 203 is also used to activate the adaptive forward error correction module 204 or control the adaptive forward error correction module 204 to exit the activation state, thereby performing mode control on the adaptive forward error correction module 204. The dynamic reconfiguration controller 203 is the intelligent control center of the entire control path of the serial communication interface 200. The dynamic reconfiguration controller 203 is tightly coupled with the control register 2011 and has direct control over underlying hardware units such as the baud rate generator 2021, the frame format controller 2022, and the adaptive forward error correction module 204. The dynamic reconfiguration controller 203 and the adaptive forward error correction module 204 are directly connected via a set of dedicated control and status signal lines, forming a crucial control closed loop. This connection allows the dynamic reconfiguration controller 203 to issue mode control commands (e.g., enable or disable error correction commands) to the adaptive forward error correction module 204, and to receive channel quality status reports from the adaptive forward error correction module 204 or internal negotiation requests initiated by the adaptive forward error correction module 204 (e.g., error correction mode enable or disable requests).

[0058] Optionally, the baud rate generator 2021 may be a hardware module for generating a clock signal that matches the baud rate of the serial communication interface 200. The registers of the baud rate generator 2021 are registers configured within the baud rate generator 2021 for storing data. The frame format controller 2022 may be a controller for managing information related to the format of the data transmitted and received by the serial communication interface 200. The registers of the frame format controller 2022 are registers configured within the frame format controller 2022 for storing data.

[0059] Optionally, the data transceiver register 2012 can be a register for temporarily storing data. The shift register 2013 can be a register for shifting out data that needs to be serially output bit by bit according to the baud rate of the serial communication interface 200, or for saving data serially input from external devices bit by bit according to the baud rate of the serial communication interface 200. An adaptive forward error correction module 204 is embedded between the data transceiver register 2012 and the shift register 2013, which is responsible for actual serialization and deserialization. The adaptive forward error correction module 204 can be a hardware module that monitors the communication quality of the serial communication interface 200 and provides error correction functionality by adding redundant check information before data transmission and actively correcting bit errors generated during transmission when a significant degradation in communication quality is detected.

[0060] Optional, such as Figure 3 As shown, the dynamic reconfiguration controller 303 includes a command detector 3031, a command parser 3032, a main state machine 3033, a parameter update logic unit 3034, and a response generator 3035. The command detector 3031 is connected to the main state machine 3033 and the command parser 3032 respectively. The command detector 3031 monitors the data stream sent by the register. In this specific embodiment, the register is a shift register 3013, and it identifies command frames with a predefined format. The command frame includes an escape sequence, a command identifier, parameters, parameter length, and a checksum.

[0061] Optionally, the command frame can be data transmitted between the serial communication interfaces of two devices performing serial communication, used to instruct the serial communication interface to perform a specified operation. Specified operations include, but are not limited to: modifying the baud rate, entering forward error correction mode, confirming that the sent command frame has been successfully received and processed, modifying the data bits, modifying the stop bits, modifying the parity method, confirming that the sent command frame has not been successfully received and processed, and exiting forward error correction mode.

[0062] Table 1 Command Frame Format Table

[0063]

[0064] As shown in Table 1, the format definition of a command frame includes five fields: escape sequence, command identifier, parameter length, parameters, and checksum. The escape sequence can be a pre-set two-byte hexadecimal sequence used to explicitly identify the beginning of the command frame, distinguishing it from ordinary data. The escape sequence is 2 bytes long. For example, the escape sequence is "0x1B, 0x1B". The command identifier can be a hexadecimal byte defining the operation to be performed. A command identifier of 0x01 indicates the operation to be performed is "modify baud rate". A command identifier of "0x02" indicates the operation to be performed is "enter forward error correction mode". A command identifier of 0x80 indicates the operation to be performed is "acknowledge that the sent command frame was not successfully received and processed". The command identifier is 1 byte long. The parameter length is a hexadecimal byte indicating the number of bytes in the subsequent "parameter" field. If there are no parameters, the parameter length is 0x00. The parameter length is 1 byte long. The parameter is the specific hexadecimal parameter required to perform the operation. The length of the parameter is defined by the preceding "Parameter Length" field. For example, for a command frame modifying the baud rate, the "Parameter" field could contain a 4-byte new baud rate value. The checksum is a cyclic redundancy checksum obtained by performing a cyclic redundancy check on all bytes from the "Command Identifier" field to the "Parameter" field to ensure the integrity and accuracy of the command frame during transmission. Cyclic redundancy check can be performed using the CRC-8 cyclic redundancy check algorithm. For example, when a request is made to modify the baud rate to 115200 (hexadecimal 0x0001C200), the dynamic reconfiguration controller 203 will construct and send a command frame [0x1B, 0x1B, 0x01, 0x04, 0x00, 0x01, 0xC2, 0x00, CRC]. CRC represents the checksum.

[0065] Optionally, the parameter modification command frame can be a command frame used to instruct the serial communication interface to modify the target communication parameters. The target communication parameters can be any one of the following: baud rate, data bits, stop bits, and parity mode. The command identifier in the parameter modification command frame is a hexadecimal byte used to define the operation to modify the target communication parameters to be performed. The parameters in the parameter modification command frame are the new target communication parameters. Modifying the target communication parameters means updating the target communication parameters in the registers of the baud rate generator or frame format controller to the new target communication parameters.

[0066] Optionally, a positive acknowledgment command frame can be a command frame used to indicate to the serial communication interface that the sent command frame has been successfully received and processed. The command identifier in the positive acknowledgment command frame is a hexadecimal byte used to define the operation to be performed to acknowledge that the sent command frame has been successfully received and processed. The parameters in the positive acknowledgment command frame are empty, i.e., there are no parameters.

[0067] Optionally, a negative acknowledgment command frame can be a command frame used to indicate that the serial communication interface acknowledged that the sent command frame was not successfully received and processed. The command identifier in the negative acknowledgment command frame is a hexadecimal byte used to define the operation to be performed to acknowledge that the sent command frame was not successfully received and processed. The parameters in a positive acknowledgment command frame are empty, i.e., there are no parameters.

[0068] Optionally, the error correction mode enable command frame can be a command frame used to instruct the serial communication interface to enter forward error correction mode. The command identifier in the error correction mode enable command frame is a hexadecimal byte used to define the operation to be performed to enter forward error correction mode. The parameters in the error correction mode enable command frame are empty, i.e., there are no parameters. Entering forward error correction mode means activating the adaptive forward error correction module, which provides error correction functionality by adding redundant check information before data transmission and using the redundant check information to actively correct bit errors generated during transmission when receiving data.

[0069] Optionally, the error correction mode disable command frame can be a command frame used to instruct the serial communication interface to exit forward error correction mode. The command identifier in the error correction mode disable command frame is a hexadecimal byte used to define the operation to be performed to exit forward error correction mode. The parameters in the error correction mode disable command frame are empty, i.e., no parameters. Exiting forward error correction mode means controlling the adaptive forward error correction module to exit the active state, so that the adaptive forward error correction module stops providing error correction functionality by adding redundant check information before data transmission and using the redundant check information to actively correct bit errors generated during transmission when receiving data.

[0070] Optionally, the command parser 3032 is connected to the main state machine 3033, the command detector 3031, and the parameter update logic unit 3034 respectively. The command parser 3032 is driven by the main state machine 3033 to extract and verify command frames in a predefined format.

[0071] Optionally, the command detector 3031 may be a hardware module for monitoring whether an escape sequence exists in the data sent by the shift register 3013. The command parser 3032 may be a hardware module for extracting and verifying the command identifier, parameter length, parameters, and checksum of the command frame to which the detected escape sequence belongs. The master state machine 3033 may be a hardware module for processing the detected command frames by driving the command parser 3032, the parameter update logic unit 3034, and the response generator.

[0072] Optionally, the command detector 3031 is responsible for continuously monitoring the data stream from the receive shift register 3013 to identify predefined escape sequences. The command detector 3031 activates the main state machine 3033 when it successfully detects an escape sequence in the data sent by the shift register 3013. Upon activation, the main state machine 3033 immediately drives the command parser 3032 to extract the command identifier, parameter length, parameters, and checksum of the command frame to which the escape sequence belongs from the data path, and verifies the extracted command identifier, parameter length, parameters, and checksum. Verification of the parsed command identifier, parameter length, parameters, and checksum includes: performing a cyclic redundancy check on all bytes of the parsed command identifier, parameter length, and parameters to obtain a cyclic redundancy checksum; determining whether the obtained cyclic redundancy checksum is the same as the extracted checksum; if so, the verification is successful; if not, the verification fails, and the modification fails.

[0073] After successful verification, the master state machine 3033 can determine the type of command frame based on the command identifier. The command frame type can be a parameter modification command frame instructing the serial communication interface to modify the baud rate. It can also be a parameter modification command frame instructing the serial communication interface to modify the data bits, stop bits, or parity mode. Furthermore, the command frame type can be a positive acknowledgment command frame, a negative acknowledgment command frame, an error correction mode enable command frame, or an error correction mode disable command frame.

[0074] Optionally, the parameter update logic unit 3034 generates control signals based on the commands parsed by the command parser 3032 and sends them to the main controller for control.

[0075] Optionally, the parameter update logic unit 3034 may be a hardware module for generating control signals for modifying communication parameters based on the parameters parsed by the command parser 3032 and sending them to the baud rate generator or frame format controller, so that the baud rate generator or frame format controller modifies the communication parameters in the register according to the control signals.

[0076] Optionally, the response generator is driven by the master state machine 3033 to construct the corresponding acknowledgment command frame or negative acknowledgment command frame, send it to the transmission path, and send it back.

[0077] Optionally, the response generator can be a hardware module used to construct a positive acknowledgment command frame or a negative acknowledgment command frame and send the constructed positive acknowledgment command frame or a negative acknowledgment command frame to the transmit shift register 3013.

[0078] Optionally, when the command frame is a parameter modification command frame used to instruct the serial communication interface to modify the baud rate, the parameter parsed by the command parser 3032 is the new baud rate. If it is determined that the command frame is a parameter modification command frame used to instruct the serial communication interface to modify the baud rate, the main state machine 3033 drives the parameter update logic unit 3034 to generate a control signal to instruct the baud rate generator to update the baud rate in the baud rate generator's register to the new baud rate according to the new baud rate parsed by the command parser 3032, and sends the generated control signal to the baud rate generator. After receiving the control signal, the baud rate generator can update the baud rate in its register to the new baud rate according to the control signal, thereby modifying the baud rate. After successful modification, the baud rate generator can send a modification confirmation signal to the parameter update logic unit 3034. The modification confirmation signal can be a pre-set signal used to indicate successful modification of communication parameters. After failed modification, the baud rate generator can send a modification failure signal to the parameter update logic unit 3034. The modification failure signal can be a pre-set signal used to indicate failed modification of communication parameters. The parameter update logic unit 3034 can send the received modification confirmation signal or modification failure signal to the main state machine 3033. Upon receiving the modification confirmation signal, the main state machine 3033 determines that the modification was successful. Upon receiving the modification failure signal, the main state machine 3033 determines that the modification failed.

[0079] Optionally, when the command frame is a parameter modification command frame used to instruct the serial communication interface to modify the data bit width, stop bit width, or parity mode, the parameters parsed by the command parser 3032 are the new data bit width, stop bit width, or parity mode. If it is determined that the command frame is a parameter modification command frame used to instruct the serial communication interface to modify the data bit width, stop bit width, or parity mode, the main state machine 3033 drives the parameter update logic unit 3034 to generate a control signal to instruct the frame format controller to update the data bit width, stop bit width, or parity mode in the frame format controller's register to the new data bit width, stop bit width, or parity mode, based on the new data bit width, stop bit width, or parity mode obtained by the command parser 3032, and sends the generated control signal to the frame format controller. After receiving the control signal, the frame format controller can update the data bit width, stop bit width, or parity mode in the frame format controller's register to the new data bit width, stop bit width, or parity mode, thereby modifying the data bit width, stop bit width, or parity mode. After successful modification, the frame format controller can send a modification confirmation signal to the parameter update logic unit 3034. The frame format controller can send a modification failure signal to the parameter update logic unit 3034 after a modification failure. The parameter update logic unit 3034 can then send the received modification confirmation signal or modification failure signal to the main state machine 3033. Upon receiving the modification confirmation signal, the main state machine 3033 determines that the modification was successful. Upon receiving the modification failure signal, the main state machine 3033 determines that the modification failed.

[0080] Optionally, the master state machine 3033 can drive the response generator to construct a positive acknowledgment command frame after confirming successful modification, and send the positive acknowledgment command frame to the shift register 3013, thereby sending the positive acknowledgment command frame to the transmit path in the serial communication interface. The shift register 3013 will send the positive acknowledgment command frame to the dialog interface through the physical line, thus completing a complete in-band command interaction. The dialog interface is a serial communication interface set on another device that communicates with the device where the serial communication interface is located. The dynamic reconfiguration controller in the dialog interface can determine that the serial communication interface has successfully modified its communication parameters when it detects a positive acknowledgment command frame, and then synchronously modify the communication parameters of the dialog interface to keep the communication parameters of the two interfaces consistent.

[0081] Optionally, the master state machine 3033 can drive the response generator to construct a negative acknowledgment command frame after determining that the modification has failed. This negative acknowledgment command frame is then sent to the shift register 3013, which in turn sends it to the transmission path in the serial communication interface. The shift register 3013 then sends the negative acknowledgment command frame to the dialog interface via the physical line, thus completing a full in-band command interaction. The dynamic reconfiguration controller in the dialog interface can determine that the serial communication interface has failed to modify communication parameters upon detecting a negative acknowledgment command frame and resend the command frame.

[0082] Optionally, the dynamic reconfiguration controller 303 initiates an in-band signaling mechanism, including: the dynamic reconfiguration controller 303 receiving a parameter modification instruction; after receiving the parameter modification instruction, the dynamic reconfiguration controller 303 constructs a parameter modification command frame in a predefined format and sends the parameter modification command frame into a register; after receiving the returned confirmation command frame, the dynamic reconfiguration controller 303 performs a synchronous switch.

[0083] Optionally, the parameter modification instruction can be an instruction requesting modification of the target communication parameters of the serial communication interface. The CPU can send the parameter modification instruction to the control register. The control register will then send the received parameter modification instruction to the dynamic reconfiguration controller 303. After receiving the parameter modification instruction, the dynamic reconfiguration controller 303 constructs a parameter modification command frame to instruct the serial communication interface to modify the target communication parameters, and sends the parameter modification command frame to the shift register 3013, thereby sending a negative acknowledgment command frame to the transmission path in the serial communication interface. The shift register 3013 will then send the parameter modification command frame to the dialog interface via the physical line. The dynamic reconfiguration controller in the dialog interface receives the command frame and continuously monitors the data stream while receiving data. When it detects the received parameter modification command frame, it intercepts the subsequent byte stream from the main data path and performs command parsing on the parameter modification command frame. After confirming that the checksum is correct, the dynamic reconfiguration controller in the dialog interface executes the parameter modification command, and upon successful execution, constructs an acknowledgment command frame and sends it back. After detecting the presence of a command frame in the data stream sent by the shift register 3013, the dynamic reconfiguration controller 303 extracts the command identifier, parameter length, parameters, and checksum of the command frame from the data and performs verification. After successful verification, the type of the command frame is determined based on the command identifier. If the command frame is determined to be a positive acknowledgment command frame, it confirms that the sent parameter modification command frame has been successfully received and processed. Then, the target communication parameters are synchronously modified to ensure that the communication parameters of the two interfaces remain consistent.

[0084] Optionally, the dynamic reconfiguration controller 303 initiates an in-band signaling mechanism, which further includes: the dynamic reconfiguration controller 303 receives command frames and continuously monitors the data stream while receiving data; when a received parameter modification command frame is detected, the subsequent byte stream is intercepted from the main data path, and the parameter modification command frame is parsed; after confirming that the checksum is correct, the dynamic reconfiguration controller 303 executes the parameter modification command, and after successful execution, constructs an acknowledgment command frame and sends it back.

[0085] Optionally, after receiving a parameter modification instruction, the dynamic reconfiguration controller in the dialogue interface constructs a parameter modification command frame to instruct the serial communication interface to modify the target communication parameters. This parameter modification command frame is then sent to shift register 3013, thereby sending a negative acknowledgment command frame to the transmission path in the serial communication interface. The dynamic reconfiguration controller 303 receives the command frame and continuously monitors the data stream while receiving data. When a received parameter modification command frame is detected, the subsequent byte stream is intercepted from the main data path, and the parameter modification command frame is parsed. After confirming that the checksum is correct, the dynamic reconfiguration controller 303 executes the parameter modification command. Upon successful execution, it constructs an acknowledgment command frame and sends it back. After detecting the presence of a command frame in the data stream sent by shift register 3013, the dynamic reconfiguration controller in the dialogue interface extracts the command identifier, parameter length, parameters, and checksum of the command frame from the data and performs verification. After successful verification, the type of the command frame is determined based on the command identifier. If the command frame is determined to be a positive acknowledgment command frame, it confirms that the sent parameter modification command frame has been successfully received and processed. Then, the target communication parameters are synchronously modified to ensure that the communication parameters of the two interfaces remain consistent.

[0086] Optional, attached Figure 4In a specific example, the two devices communicating with each other are device A 40 and device B 41. Device A 40 includes a serial communication interface A 401. Serial communication interface A 401 includes register 4011, a main controller 4012, a dynamic reconfiguration controller 4013, and an adaptive forward error correction module 4014. Register 4011 includes a shift register 4015. Device B 41 includes a serial communication interface B 411. Serial communication interface B 411 includes register 4111, a main controller 4112, a dynamic reconfiguration controller 4113, and an adaptive forward error correction module 4114. Register 4111 includes a shift register 4115. Device A 40 acts as the requester, and device B 41 acts as the responder. The CPU of device A 40 issues a parameter modification instruction to the dynamic reconfiguration controller 4013 of device A 40. The parameter modification instruction may request to increase the baud rate from 9600 baud to 115200 baud. After receiving the parameter modification command, the dynamic reconfiguration controller 4013 of device A 40 automatically constructs a parameter modification command frame to instruct the serial communication interface to modify the baud rate to 115200 baud. Once the parameter modification command frame is constructed, the entire in-band signaling interaction process officially begins. The parameter modification command frame is sent by the dynamic reconfiguration controller 4013 of device A 40 (as the requesting party) to the shift register 4015 of device A 40, and then transmitted to device B 41 (as the responding party) via the physical line. At device B 41, the dynamic reconfiguration controller 4113 continuously monitors the data stream while receiving data. Once an escape sequence is detected, the dynamic reconfiguration controller 4113 of device B 41 immediately intercepts the subsequent byte stream from the main data path and transfers it to its internal command parsing logic to detect and parse the parameter modification command frame. After confirming that the checksum is correct, the dynamic reconfiguration controller 4113 of device B 41 directly executes the operation to modify the baud rate to 115200 baud. After successful execution, the dynamic reconfiguration controller 4113 of device B 41 constructs a positive acknowledgment command frame and sends it to device A 40. As the final step in the closed loop, device A 40, as the initiator, only switches its baud rate to the new value after receiving the positive acknowledgment command frame from device B 41. Through this complete "request-parsing-execution-response" closed-loop handshake mechanism, device A 40 and device B 41 achieve synchronized and seamless switching of communication parameters without interrupting the communication session. The communication parameter modification process between device A 40 and device B 41 mainly includes five parts: command initiation, command frame construction and sending, command reception and parsing, command execution and response, and synchronization switching. Command initiation refers to the CPU of device A 40 requesting to modify communication parameters by issuing a parameter modification instruction.Command frame construction and transmission refers to the dynamic reconfiguration controller 4013 of device A 40 constructing and sending parameter modification command frames. Command reception and parsing refers to the dynamic reconfiguration controller 4113 of device B 41 detecting and parsing the parameter modification command frames. Command execution and acknowledgment refers to the dynamic reconfiguration controller 4113 of device B 41 executing the operation and replying with a positive acknowledgment command frame. Synchronous switching refers to the synchronous modification by the dynamic reconfiguration controller 4013 of device A 40 after receiving the positive acknowledgment command frame. Parameter modification command frames and positive acknowledgment command frames are transmitted over physical lines.

[0087] Optional, as shown in the appendix Figure 5 As shown, the adaptive forward error correction module 500 includes an encoding path 501 and a decoding path 502. The encoding path 501 includes an FEC encoder 5011, which is responsible for converting raw data bytes into codewords with redundant check bits. The decoding path 502 includes an accompaniment calculator 5021, an error corrector 5022, and a data extractor 5023. The accompaniment calculator 5021 is connected to the error corrector 5022, and the error corrector 5022 is connected to the data extractor 5023. The accompaniment calculator 5021 is used to detect data errors, the error corrector 5022 repairs errors in the data based on the output of the accompaniment calculator 5021, and the data extractor 5023 is used to restore the original data. The adaptive forward error correction module 500 also includes adaptive control logic 503, which includes an error rate monitor 5031 and a decision logic unit 5032. The error rate monitor 5031 is connected to the decision logic unit 5032. The error rate monitor 5031 calculates the communication error rate of the current line based on the error status information of the current line obtained from the decoding path 502. The decision logic unit 5032 receives the communication error rate value provided by the error rate monitor 5031, compares the communication error rate value with a preset enable / disable threshold, and actively sends an internal negotiation request to the dynamic reconfiguration controller 504 based on the comparison result.

[0088] Optionally, encoding path 501 and decoding path 502 are two parallel hardware data paths. Encoding path 501 is a hardware data path used to connect data transceiver register 505 and shift register 506. FEC encoder 5011 is connected to data transceiver register 505 and shift register 506. Decoding path 502 is a hardware data path used to connect shift register 506 and data transceiver register 505. Shift register 506 is connected to the accompanying calculator 5021. Data extractor 5023 is connected to data transceiver register 505. Adaptive control logic 503 is the intelligent hub of adaptive forward error correction module 500.

[0089] Optionally, in the encoding path 501, the FEC encoder 5011 is a hardware module used to convert data into data with redundancy check information using a preset error correction algorithm. The preset error correction algorithm can be a Hamming code error correction algorithm. The redundancy check information is a check code obtained by encoding the bytes in the data using a Hamming code error correction algorithm.

[0090] Optionally, in the decoding path 502, the accompanying calculator 5021 is a hardware module used to perform error detection on the data to obtain error status information. The accompanying calculator 5021 can perform frame error detection on the data to obtain error status information or verify the data according to the verification method of the serial communication interface to obtain error status information. The data error status information is used to indicate whether an error exists in the data. The data error status information indicates whether an error exists or not. Performing frame error detection on the data to obtain error status information includes: detecting whether the data format is incorrect; if so, determining that an error exists; if not, determining that an error does not exist. The error status information of the data is obtained by verifying the data according to the verification method of the serial communication interface. This includes: when the verification method is odd parity, odd parity is performed on the data; if the verification passes, the data error status information is determined to be error-free; if the verification fails, the data error status information is determined to be error-present. When the verification method is even parity, even parity is performed on the data; if the verification passes, the data error status information is determined to be error-free; if the verification fails, the data error status information is determined to be error-present. Error corrector 5022 is a hardware module used to decode the redundant parity information in the data and repair bit errors in the data when the error status information of the data with redundant parity information is error-present, using a preset error correction algorithm. Data extractor 5023 is a hardware module used to extract the original data before conversion from the data with redundant parity information.

[0091] Optionally, in the adaptive control logic 503, the error rate monitor 5031 is a hardware module used to calculate the communication error rate based on the error status information sent by the accompanying calculator 5021. The communication error rate can refer to the number of error status messages received per second that contain errors. A lower communication error rate indicates higher communication quality, while a higher communication error rate indicates lower communication quality. The decision logic unit 5032 is a hardware module used to send an error correction mode enable request to the dynamic reconfiguration controller 504 when the detected communication error rate exceeds the enable threshold, and to send an error correction mode disable request to the dynamic reconfiguration controller 504 when the detected communication error rate remains below the disable threshold. The decision logic unit 5032 can interact with the interface of the dynamic reconfiguration controller 504 to transmit requests or instructions.

[0092] Optionally, the enable threshold and disable threshold can be two preset values. If the detected communication error rate exceeds the enable threshold, it indicates low communication quality, requiring activation of the adaptive forward error correction module 500. This allows the adaptive forward error correction module 500 to provide error correction by adding redundant check information before data transmission and actively correcting bit errors generated during transmission using this redundant check information when receiving data. A communication error rate consistently below the disable threshold can mean that all statistically recorded communication error rate values ​​are less than the disable threshold within a preset time period. The preset time period can be a pre-set duration. For example, the preset time period could be 10 seconds, 20 seconds, or 30 seconds. If the detected communication error rate consistently falls below the disable threshold, it indicates high communication quality, allowing the adaptive forward error correction module 500 to exit the active state and stop providing error correction functionality. The error correction mode enable request can be a pre-set message requesting the dynamic reconfiguration controller 504 to activate the adaptive forward error correction module 500, enabling it to provide error correction functionality and enter forward error correction mode. The error correction mode disable request can be a pre-set message requesting the dynamic reconfiguration controller 504 to control the adaptive forward error correction module 500 to exit the active state, so that the adaptive forward error correction module 500 stops providing error correction function and exits the forward error correction mode. The decision logic unit 5032 can enable the FEC encoder 5011, error corrector 5022, and data extractor 5023 by sending enable commands to them. The enable command can be a pre-set command for enabling the hardware module. The decision logic unit 5032 can disable the FEC encoder 5011, error corrector 5022, and data extractor 5023 by sending disable commands to them. The disable command can be a pre-set command for disabling the hardware module. The decision logic unit 5032 can issue enable or disable commands to the internal encoder / decoder path 502, thereby achieving complete adaptive closed-loop control.

[0093] Optionally, the error rate monitor 5031 calculates the communication error rate based on the error status information sent by the accompanying calculator 5021 and sends the communication error rate value to the decision logic unit 5032. When the decision logic unit 5032 detects that the communication error rate value exceeds the activation threshold, it sends an error correction mode activation request to the dynamic reconfiguration controller 504. After receiving the mode activation instruction sent by the dynamic reconfiguration controller 504, it determines that the adaptive forward error correction module 500 is activated and sends an enable instruction to the FEC encoder 5011, error corrector 5022, and data extractor 5023. When the decision logic unit 5032 detects that the communication error rate value is continuously lower than the disable threshold, it sends an error correction mode disable request to the dynamic reconfiguration controller 504. After receiving the mode disable instruction sent by the dynamic reconfiguration controller 504, it determines that the adaptive forward error correction module 500 is deactivated and sends a disable instruction to the FEC encoder 5011, error corrector 5022, and data extractor 5023. The mode activation command can be a pre-set command used to instruct the adaptive forward error correction module 500 to be activated. The mode deactivation command can be a pre-set command used to instruct the adaptive forward error correction module 500 to deactivate.

[0094] Optionally, when the adaptive forward error correction module 500 is not activated, the disabled FEC encoder 5011 sends the raw transmission data to the shift register 506 after receiving the raw transmission data from the data transceiver register 505. When the adaptive forward error correction module 500 is activated, the enabled FEC encoder 5011, after receiving the raw transmission data from the data transceiver register 505, uses a preset error correction algorithm to convert the raw transmission data into target transmission data with redundancy check information, and sends the target transmission data to the shift register 506. The raw transmission data can be data from the CPU that needs to be sent to the interface via the shift register 506. The target transmission data is the data with redundancy check information obtained after converting the raw transmission data. The enabled FEC encoder 5011 can use a Hamming code error correction algorithm to hardware encode each data byte (e.g., 8 bits) in the raw transmission data to generate a long codeword (e.g., 14 bits) containing redundancy check information, converting the raw transmission data into target transmission data with redundancy check information, and then sending the target transmission data to the shift register 506.

[0095] Optionally, when the adaptive forward error correction module 500 is not activated, the accompanying calculator 5021, after receiving the received data sent by the shift register 506, performs error detection on the received data to obtain error status information, sends the error status information to the error rate monitor 5031, and sends the received data to the disabled error corrector 5022. The disabled error corrector 5022 sends the received data to the disabled data extractor 5023. The disabled data extractor 5023 sends the received data to the data transceiver register 5052012. When the adaptive forward error correction module 500 is activated, the accompanying calculator 5021, after receiving the received data sent by the shift register 506, performs error detection on the received data to obtain error status information, sends the error status information to the error rate monitor 5031, and sends the received data and error status information to the enabled error corrector 5022. When the error status information indicates an error exists, the enabled error corrector 5022 uses a preset error correction algorithm to decode the redundant check information in the received data, repairs the bit errors in the received data, and sends the repaired received data to the enabled data extractor 5023. The enabled data extractor 5023 extracts the original received data from the repaired received data and sends the original received data to the data transceiver register 505.

[0096] Optionally, when the adaptive forward error correction module 500 is not activated, the received data is data from the shift register 506 without redundant check information, and the received data can be directly sent to the data transceiver register 505. The data transceiver register 505 then sends the raw received data to the CPU.

[0097] Optionally, when the adaptive forward error correction module 500 is activated, the received data is data with redundancy check information from the shift register 506. This received data needs to be decoded and error-corrected before being sent to the CPU. When the error status information indicates an error exists, the enabled error corrector 5022 can use a Hamming code error correction algorithm to decode the redundancy check information in the received data, determine the erroneous data bits, correct the erroneous data bits, and restore them to correct data bits, thereby correcting the bit errors in the received data and obtaining the repaired received data. The original received data is the raw data to be sent to the CPU before it is converted into data with redundancy check information. The enabled data extractor 5023 can extract the original received data from the repaired received data and then send the original received data to the data transceiver register 505. The data transceiver register 505 sends the original received data to the CPU. When the error status information indicates no error exists, the enabled error corrector 5022 sends the received data to the enabled data extractor 5023. The enabled data extractor 5023 extracts the raw received data from the received data and sends the raw received data to the data transceiver register 505. The data transceiver register 505 then sends the raw received data to the CPU.

[0098] Optionally, the dynamic reconfiguration controller 504 initiates an external negotiation request based on the internal negotiation request, requesting to enter or exit the forward error correction mode. This includes: when the decision logic unit 5032 inside the adaptive forward error correction module 500 determines that the communication error rate of the current line exceeds the activation threshold, it actively sends an internal negotiation request to the dynamic reconfiguration controller 504; after receiving the internal negotiation request, the dynamic reconfiguration controller 504 initiates an external negotiation request using an in-band signaling mechanism, requesting to enter the forward error correction mode; after successful negotiation, the adaptive forward error correction module 500 is activated and intervenes in the data path; when sending data, the adaptive forward error correction module 500 performs hardware encoding on each data byte, generates a long codeword containing redundancy check information according to a preset error correction algorithm, and sends the long codeword for transmission; when receiving data, the adaptive forward error correction module 500 performs a reverse operation, decodes the received long codeword, uses the redundancy information to detect and repair bit errors generated by the data byte during transmission, and restores the original data.

[0099] Optionally, the dynamic reconfiguration controller 504 initiates an external negotiation request based on the internal negotiation request, requesting to enter or exit the forward error correction mode. This also includes: when the decision logic unit 5032 inside the adaptive forward error correction module 500 determines that the communication error rate of the current line is continuously lower than the disable threshold, it actively sends an internal negotiation request to the dynamic reconfiguration controller 504; after receiving the internal negotiation request, the dynamic reconfiguration controller 504 initiates an external negotiation request using an in-band signaling mechanism, requesting to exit the forward error correction mode; after successful negotiation, the adaptive forward error correction module 500 exits the active mode and stops intervening in the data path.

[0100] Optionally, if the command frame is determined to be an error correction mode enabled command frame, the dynamic reconfiguration controller 504 activates the adaptive forward error correction module 500, constructs a positive confirmation command frame, and sends the positive confirmation command frame to the dialog interface via the shift register 506, so that the dialog interface synchronously activates the adaptive forward error correction module 500. The dynamic reconfiguration controller 504 can activate the adaptive forward error correction module 500 and construct a positive confirmation command frame when it detects an error correction mode enabled command frame, and send the positive confirmation command frame to the dialog interface via the shift register 506. After detecting the presence of a command frame in the data stream sent by the receive shift register 506, the dynamic reconfiguration controller 504 of the dialogue interface extracts the command identifier, parameter length, parameters, and checksum of the command frame from the data and verifies them. After successful verification, the type of the command frame is determined based on the command identifier. If the command frame is determined to be a positive acknowledgment command frame, it confirms that the error correction mode enable command frame has been successfully received and processed. It also confirms that the forward error correction mode has been negotiated with the serial communication interface, i.e., the negotiation is successful. Then, it sends a mode enable instruction to the decision logic unit 5032 inside the adaptive forward error correction module 500, thereby activating the adaptive forward error correction module 500.

[0101] Optionally, if it is determined that the command frame is a disabled command frame in error correction mode, the dynamic reconfiguration controller 504 controls the adaptive forward error correction module 500 to exit the active state, constructs a positive confirmation command frame, and sends the positive confirmation command frame to the dialog interface through the shift register 506 so that the dialog interface synchronously controls the adaptive forward error correction module 500 to exit the active state.

[0102] When the dynamic reconfiguration controller 504 detects a command frame disabling error correction mode, it controls the adaptive forward error correction module 500 to exit the active state and constructs a positive acknowledgment command frame, which is then sent to the dialog interface via shift register 506. After detecting the presence of a command frame in the data stream received by shift register 506, the dynamic reconfiguration controller 504 extracts the command identifier, parameter length, parameters, and checksum of the command frame from the data and verifies them. Upon successful verification, it determines the type of the command frame based on the command identifier. If the command frame is determined to be a positive acknowledgment command frame, it confirms that the sent error correction mode disabling command frame has been successfully received and processed. It also confirms successful negotiation with the serial communication interface to exit the forward error correction mode, i.e., successful negotiation. Then, it sends a mode disabling instruction to the decision logic unit 5032 inside the adaptive forward error correction module 500, thereby controlling the adaptive forward error correction module 500 to exit the active state.

[0103] The adaptive error correction function of the serial communication interface begins with the continuous monitoring of communication quality by the adaptive forward error correction module 500. The error rate monitor 5031 inside the adaptive forward error correction module 500 analyzes the received data and calculates the communication error rate in real time. When the decision logic unit 5032 inside the adaptive forward error correction module 500 determines that the communication error rate exceeds the activation threshold, it means that the communication quality has significantly deteriorated. Instead of passively waiting for upper-layer software intervention, the decision logic unit 5032 actively sends an error correction mode activation request to the dynamic reconfiguration controller 504, suggesting that the error correction function be enabled. After receiving the error correction mode activation request, the dynamic reconfiguration controller 504 constructs an error correction mode activation command frame and sends it to the shift register 506. The shift register 506 then sends the error correction mode activation command frame to the interface via the physical line. This initiates a "negotiation" with the device where the interface is located, requesting both parties to enter forward error correction (FEC) mode. The dynamic reconfiguration controller 504 in the dialogue interface can activate the adaptive forward error correction module 500 and construct a positive acknowledgment command frame when it detects an error correction mode enable command frame. This positive acknowledgment command frame is then sent to the serial communication interface 200 via the shift register 506. After detecting the presence of a command frame in the data stream sent by the shift register 506, the dynamic reconfiguration controller 504 extracts the command identifier, parameter length, parameters, and checksum of the command frame from the data and verifies them. Upon successful verification, it determines the type of the command frame based on the command identifier. If the command frame is determined to be a positive acknowledgment command frame, it confirms that the error correction mode enable command frame has been successfully received and processed. It then confirms that it has negotiated with the dialogue interface to enter the forward error correction mode, indicating successful negotiation. Finally, it sends a mode enable command to the decision logic unit 5032 within the adaptive forward error correction module 500, thereby activating the adaptive forward error correction module 500. The activated adaptive forward error correction module 500 then enters the data path. When transmitting data, the activated adaptive forward error correction module 500 performs hardware encoding on each data byte (e.g., 8 bits) received from the CPU using a pre-defined Hamming code error correction algorithm, generating a long codeword (e.g., 14 bits) containing redundancy check information, and sends the codeword for transmission. When receiving data, the activated adaptive forward error correction module 500 performs the reverse operation, decoding the received long codeword. The internal modules of the activated adaptive forward error correction module 500 can automatically detect and immediately "repair" bit errors caused by noise interference during transmission using the redundancy check information, and finally provide the recovered, correct original data bytes to the CPU.

[0104] Subsequently, when the decision logic unit 5032 inside the adaptive forward error correction module 500 detects that the communication error rate value is consistently lower than the disable threshold, indicating improved communication quality, it sends an error correction mode disable request to the dynamic reconfiguration controller 504. Upon receiving the error correction mode disable request, the dynamic reconfiguration controller 504 constructs an error correction mode disable command frame and sends it to the shift register 506. The shift register 506 then sends the error correction mode disable command frame to the dialogue interface via the physical line. This initiates another "negotiation" with the device where the dialogue interface is located, requesting both parties to jointly exit the forward error correction (FEC) mode, thereby fully returning the channel bandwidth to valid data and maximizing efficiency. The dynamic reconfiguration controller 504 in the dialogue interface can, upon detecting the error correction mode disable command frame, control the adaptive forward error correction module 500 to exit the active state and construct a positive acknowledgment command frame, sending it to the serial communication interface via the shift register 506. After detecting the presence of a command frame in the data stream sent by the shift register 506, the dynamic reconfiguration controller 504 extracts the command identifier, parameter length, parameters, and checksum of the command frame from the data and verifies them. Upon successful verification, it determines the type of the command frame based on the command identifier. If the command frame is determined to be a positive acknowledgment command frame, it confirms that the sent error correction mode disable command frame has been successfully received and processed. It then confirms and negotiates with the dialogue interface to exit the forward error correction mode, indicating successful negotiation. Finally, it sends a mode disable command to the decision logic unit 503 inside the adaptive forward error correction module 500, thereby controlling the adaptive forward error correction module 500 to exit the active state. The activated adaptive forward error correction module 500 no longer intervenes in the data path. Through this hardware-level intelligent adaptive mechanism, the serial communication interface can achieve a dynamic balance between reliability and transmission efficiency, realizing a strong adaptability to environmental changes.

[0105] Figure 6 This is a schematic diagram of an adaptive error correction process provided in an embodiment of the present invention. S601, the adaptive forward error correction module monitors the communication error rate. S602, the adaptive forward error correction module determines whether the communication error rate exceeds the activation threshold: if yes, proceed to S603; if no, return to S601. S603, the forward error correction mode is enabled through negotiation with the dynamic reconfiguration controller. S604, the forward error correction mode is activated by the dynamic reconfiguration controller. S605, the adaptive forward error correction module determines whether the communication error rate remains below the disable threshold: if yes, proceed to S606; if no, return to S604. S606, the forward error correction mode is disabled through negotiation with the dynamic reconfiguration controller. After completing S606, the process returns to S601.

[0106] In the technical solution of this invention, the dynamic reconfiguration controller is tightly coupled with the register, controlling the main controller and the adaptive forward error correction module. It automatically constructs command frames in a predefined format, monitors the data flow of the register, and initiates an in-band signaling mechanism. Based on the judgment conditions of the adaptive forward error correction module, the dynamic reconfiguration controller receives internal negotiation requests initiated by the adaptive forward error correction module, initiates external negotiation requests, and requests to enter or exit the forward error correction mode, thus achieving adaptive closed-loop control. This solves the problems of rigid serial communication interface configuration and weak anti-interference capability in related technologies. Based on the dynamic reconfiguration controller, it can monitor the control signaling transmitted on the physical channel in real time, and directly and seamlessly adjust the corresponding serial communication interface after detecting valid control signaling for modifying communication parameters. The communication parameters can be negotiated and seamlessly switched in real time without interrupting the data flow, realizing online dynamic adjustment of communication parameters. This completely solves the problem of lack of flexibility caused by static configuration of traditional interfaces. Based on the collaborative work between the dynamic reconfiguration controller and the adaptive forward error correction module, it can actively monitor the communication quality of the channel. When an increase in error rate is detected, it automatically negotiates with the peer and enables the hardware forward error correction function to encode and correct the transmitted data in real time. When the channel recovers well, it automatically disables the hardware forward error correction function to optimize data throughput and improve the anti-interference capability of the serial communication interface. This enables the serial communication interface to intelligently achieve a dynamic balance between communication reliability and efficiency, thereby greatly enhancing the robustness of the serial communication interface in complex environments.

[0107] The technical solution of this invention provides a novel, intelligent serial communication interface that can dynamically adjust itself without interrupting communication and proactively adapt to and overcome channel noise interference. By monitoring the data line, specific in-band command frames transmitted for dynamic reconstruction can be clearly captured, along with the real-time changes in the subsequent communication baud rate. Similarly, after enabling adaptive error correction, it can be observed that the original data bytes are hardware-encoded into serial frames of significantly different physical lengths. By introducing innovative hardware control logic, the serial communication interface can negotiate and seamlessly switch communication parameters with the peer in real time, greatly improving the system's flexibility and adaptability. Simultaneously, the serial communication interface can intelligently and automatically enable or disable hardware-level forward error correction based on the monitored channel quality, thereby significantly enhancing the robustness of data transmission without significantly increasing the CPU load. The entire dynamic reconstruction and adaptive error correction process is completed transparently in hardware, thus providing the device with highly flexible, intelligent, and robust serial communication capabilities. The technical solution of this invention not only solves the problems existing in related technologies, but also keeps its implementation transparent to upper-layer application software, without introducing new software complexity, thus achieving a balance between flexibility, reliability and ease of use.

[0108] Figure 7 This is a schematic diagram of a processor provided in an embodiment of the present invention. Figure 7 As shown, the processor 70 includes a serial communication interface 700. The serial communication interface 700 is disposed in the processor 70.

[0109] The serial communication interface 700 includes a register 701 and a main controller 702, and also includes a dynamic reconfiguration controller 703 and an adaptive forward error correction module 704.

[0110] The dynamic reconfiguration controller 703 is connected to the main controller 702, the adaptive forward error correction module 704 is connected to the register 701, and the dynamic reconfiguration controller 703 and the adaptive forward error correction module 704 are directly connected through signal lines.

[0111] The dynamic reconfiguration controller 703 is tightly coupled with the register 701, controls the main controller 702 and the adaptive forward error correction module 704, automatically constructs command frames in a predefined format, monitors the data flow of the register 701, and initiates the in-band signaling mechanism.

[0112] The dynamic reconfiguration controller 703 receives an internal negotiation request initiated by the adaptive forward error correction module 704 based on the judgment conditions of the adaptive forward error correction module 704, initiates an external negotiation request, and requests to enter or exit the forward error correction mode to achieve adaptive closed-loop control.

[0113] In the technical solution of this invention, the serial communication interface set in the chip can monitor the control signaling transmitted on the physical channel in real time based on the dynamic reconfiguration controller. After detecting a valid control signaling for modifying communication parameters, the corresponding communication parameters of the serial communication interface can be directly and seamlessly adjusted. Without interrupting the data flow, communication parameters can be negotiated and seamlessly switched in real time, realizing online dynamic adjustment of communication parameters. This completely solves the problem of lack of flexibility caused by static configuration of traditional interfaces. Based on the collaborative work between the dynamic reconfiguration controller and the adaptive forward error correction module, the communication quality of the channel can be actively monitored. When an increase in error rate is detected, the hardware forward error correction function is automatically negotiated with the peer and enabled to encode and correct the transmitted data in real time. When the channel recovers well, the hardware forward error correction function is automatically disabled to optimize data throughput.

[0114] In this invention, the processor 70 is a circuit with signal processing capabilities. In one implementation, the processor 70 can be a circuit with instruction reading and execution capabilities, such as a central processing unit (CPU), a microprocessor, a graphics processing unit (GPU) (which can be understood as a type of microprocessor), or a digital signal processor (DSP). In another implementation, the processor 70 can implement certain functions through the logical relationships of hardware circuits. These logical relationships are fixed or reconfigurable. For example, the processor 70 can be a hardware circuit implemented as an ASIC or a programmable logic device (PLD), such as an FPGA. In a reconfigurable hardware circuit, the process of the processor loading a configuration document and configuring the hardware circuit can be understood as the process of the processor loading instructions to implement the functions of some or all of the above modules. Furthermore, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), or a deep learning processing unit (DPU). The processor 70 is used to execute related programs to implement the functions required by the units in the efficiency lane change capability assessment device of this application embodiment, or to execute the efficiency lane change capability assessment method of this application method embodiment.

[0115] As can be seen, each module in the above device can be one or more processors (or processing circuits) configured to implement the above methods, such as: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor types.

[0116] Furthermore, the modules in the above devices can be integrated in whole or in part, or they can be implemented independently. In one implementation, these modules are integrated together as a system-on-a-chip (SOC). The SOC may include at least one processor for implementing any of the above methods or for implementing the functions of the modules of the device. The at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0117] The serial communication interface 700 is used, for example but not limited to, transceivers, to enable communication between the transceiver and other devices or communication networks. For example, data can be acquired through the serial communication interface 700.

[0118] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0119] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A serial communication interface, comprising registers and a main controller, characterized in that, Also includes: Dynamically reconfigurable controller and adaptive forward error correction module; Among them, the dynamic reconfiguration controller is connected to the main controller, the adaptive forward error correction module is connected to the register, and the dynamic reconfiguration controller and the adaptive forward error correction module are directly connected through signal lines. The dynamic reconfiguration controller is tightly coupled with the registers, controls the main controller and the adaptive forward error correction module, automatically constructs command frames in a predefined format, monitors the data flow of the registers, and initiates the in-band signaling mechanism; Based on the judgment conditions of the adaptive forward error correction module, the dynamic reconfiguration controller receives the internal negotiation request initiated by the adaptive forward error correction module, initiates the external negotiation request, and requests to enter or exit the forward error correction mode.

2. The serial communication interface according to claim 1, characterized in that, The dynamic reconfiguration controller includes a command detector, a command parser, a main state machine, a parameter update logic unit, and a response generator; among which, The command detector is connected to the main state machine and the command parser, respectively. The command detector monitors the data stream sent by the registers and identifies command frames in a predefined format. The command frame includes an escape sequence, command identifier, parameters, parameter length, and checksum.

3. The serial communication interface according to claim 2, characterized in that, The command parser is connected to the main state machine, the command detector, and the parameter update logic unit, respectively. Driven by the main state machine, the command parser extracts and verifies command frames in a predefined format.

4. The serial communication interface according to claim 2, characterized in that, The parameter update logic unit generates control signals based on the commands parsed by the command parser and sends them to the main controller for control.

5. The serial communication interface according to claim 2, characterized in that, The response generator is driven by the master state machine, constructs the corresponding acknowledgment command frame or negative acknowledgment command frame, sends it to the transmission path, and sends it back.

6. The serial communication interface according to claim 1, characterized in that, The dynamic reconfiguration controller initiates in-band signaling mechanisms, including: The dynamic reconfiguration controller receives parameter modification commands; After receiving a parameter modification instruction, the dynamic reconfiguration controller constructs a parameter modification command frame in a predefined format and sends the parameter modification command frame into a register. After receiving the confirmation command frame, the dynamic reconfiguration controller performs a synchronous switch.

7. The serial communication interface according to claim 6, characterized in that, The dynamic reconfiguration controller initiates in-band signaling mechanisms, which also include: The dynamic reconfiguration controller receives command frames and continuously monitors the data stream while receiving data. When it detects a received parameter modification command frame, it intercepts the subsequent byte stream from the main data path and performs command parsing on the parameter modification command frame. After confirming that the checksum is correct, the dynamic reconfiguration controller executes the parameter modification command, and after successful execution, constructs a confirmation command frame and sends it back.

8. The serial communication interface according to claim 1, characterized in that, The adaptive forward error correction module includes an encoding path and a decoding path; The encoding path includes an FEC encoder; The FEC encoder is responsible for converting raw data bytes into codewords with redundant check bits. The decoding path includes an accompanying calculator, an error corrector, and a data extractor. The accompanying calculator is connected to the error corrector, and the error corrector is connected to the data extractor. The accompanying calculator is used to detect data errors, the error corrector repairs errors in the data based on the output of the accompanying calculator, and the data extractor is used to restore the original data.

9. The serial communication interface according to claim 8, characterized in that, The adaptive forward error correction module also includes adaptive control logic, which includes an error rate monitor and a decision logic unit. The error rate monitor is connected to the decision logic unit. The error rate monitor calculates the communication error rate of the current line based on the error status information of the current line obtained from the decoding path. The decision logic unit receives the communication error rate value provided by the error rate monitor, compares the communication error rate value with the preset enable / disable threshold, and actively sends an internal negotiation request to the dynamic reconfiguration controller based on the comparison result.

10. The serial communication interface according to claim 9, characterized in that, The dynamic reconfiguration controller initiates an external negotiation request based on the internal negotiation request, requesting to enter or exit the forward error correction mode, including: When the decision logic unit inside the adaptive forward error correction module determines that the communication error rate of the current line exceeds the activation threshold, it actively sends an internal negotiation request to the dynamic reconfiguration controller. After receiving an internal negotiation request, the dynamic reconfiguration controller uses in-band signaling to initiate an external negotiation request, requesting to enter forward error correction mode. After successful negotiation, the adaptive forward error correction module is activated and intervenes in the data path; when sending data, the adaptive forward error correction module performs hardware encoding on each data byte, generates a long codeword containing redundancy check information according to the preset error correction algorithm, and sends the long codeword for transmission. When receiving data, the adaptive forward error correction module performs a reverse operation, decodes the received long codeword, uses redundant information to detect and repair bit errors generated in the data bytes during transmission, and restores the original data.

11. The serial communication interface according to claim 10, characterized in that, The dynamic reconfiguration controller initiates external negotiation requests based on internal negotiation requests, requesting to enter or exit forward error correction mode. This also includes: When the decision logic unit inside the adaptive forward error correction module determines that the communication error rate of the current line is continuously lower than the disable threshold, it actively sends an internal negotiation request to the dynamic reconfiguration controller. After receiving an internal negotiation request, the dynamic reconfiguration controller uses in-band signaling to initiate an external negotiation request to request to exit the forward error correction mode. After successful negotiation, the adaptive forward error correction module exits the activation mode and stops intervening in the data path.

12. A processor, characterized in that, Includes the serial communication interface as described in any one of claims 1-11.

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