Semiconductor device layout design apparatus and semiconductor device layout design method
By adjusting and classifying the parameters of Pcell, and distinguishing between preset parameters and parameters with the same value, the problem of unsuccessful Pcell instance docking was solved, and efficient DRC verification was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-03-05
- Publication Date
- 2026-06-19
AI Technical Summary
In existing technologies, when assigning random values to each parameter of a Pcell to generate instances, there are many combinations that cannot be matched, resulting in low efficiency of Design Rule Check (DRC) verification.
By using a judgment device and a classification device, the parameters of adjacent components are adjusted and classified, distinguishing between preset parameters and parameters with the same value, ensuring that streaming data is generated for DRC verification after successful docking.
While maintaining the same verification coverage, the number of incompatible instances has been reduced, improving the efficiency of DRC verification.
Smart Images
Figure CN121787361B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor device layout design apparatus and a semiconductor device layout design method. Background Technology
[0002] In semiconductor device design, a Pcell library is typically created by first constructing parameterized cells (Pcells) for components such as transistors and resistors. Then, circuit design is performed by instantiating these Pcells in a circuit diagram editor. By assigning parameters to Pcells, various versions of circuits and layouts can be efficiently generated, including those with gate length, gate index, width, and number of contacts.
[0003] One of the layout design functions implemented in Pcell is cell adjacency. Cell adjacency is used to correctly join adjacent instances according to design rules so that they share connection points, thereby efficiently forming the layout. However, due to the specifications of cell adjacency, certain combinations of parameters sometimes cannot achieve interconnection between cells.
[0004] In existing verification work, instances are first generated by assigning random values to each parameter of the Pcell, and then the instances are paired up to perform Design Rule Check (DRC). Among the relevant prior art, disclosed solutions include a scheme that connects parameterized units according to the minimum design rule, and a scheme that performs DRC verification after generating Pcell instances in a software development kit.
[0005] Although the existing approach of assigning random values to each parameter of Pcell can find a wide range of parameter combinations, there is a problem that many instances of combinations cannot be matched, which makes the efficiency of DRC verification in generating valid data low and affects the overall verification efficiency. Summary of the Invention
[0006] The purpose of this invention is to provide a semiconductor device layout design apparatus and a semiconductor device layout design method. This apparatus and method can reduce the number of incompatible combinations between instances while maintaining the verification coverage during the Pcell verification process, thereby achieving efficient DRC verification.
[0007] To address the aforementioned technical problems, according to a first aspect of the present invention, a semiconductor device layout design apparatus is provided, comprising determining parameters for docking adjacent first and second elements, including:
[0008] The determining device uses one of a plurality of specification parameters of the second element as an adjustment parameter, adjusts its value, and determines whether the docking with the first element is successful; and,
[0009] The classification device classifies the adjustment parameters according to the judgment result of the judgment device into: preset parameters that should not be adjusted for docking purposes, and same-value parameters that require the first element and the second element to be set to the same value for docking purposes.
[0010] Optionally, in the classification device, if the judgment result of the judgment device is docking failure, the adjustment parameter of the first element and the parameter corresponding to the adjustment parameter of the second element are set to the same value. Subsequently, if the docking of the first element and the second element fails, the adjustment parameter is the preset parameter, and if the docking is successful, the adjustment parameter is the parameter with the same value.
[0011] Optionally, the operation of the judgment device and the classification device can be performed after the adjustment parameter is adjusted to other different parameter values.
[0012] Optionally, it also includes a random parameter setting device, which uses the classification results of the preset parameters and the same-value parameters of the classification device to set the preset parameters to a predetermined value, and sets the same-value parameters to random values in a way that keeps the first element and the second element the same value, then performs instance docking and generates streaming data for design rule checking.
[0013] To address the aforementioned technical problems, according to a second aspect of the present invention, a semiconductor device layout design method is provided, comprising determining parameters for docking adjacent first and second elements, including:
[0014] The judgment step involves using one of the multiple specification parameters of the second component as an adjustment parameter, adjusting its value, and determining whether the docking with the first component is successful; and...
[0015] The classification step, based on the judgment result of the judgment step, classifies the adjustment parameters into: preset parameters that should not be adjusted for docking purposes, and parameters that require the first element and the second element to be set to the same value for docking purposes.
[0016] Optionally, in the classification step, if the judgment result of the judgment step is docking failure, the adjustment parameter of the first element and the parameter corresponding to the adjustment parameter of the second element are set to the same value. Subsequently, if the docking of the first element and the second element fails, the adjustment parameter is the preset parameter, and if the docking is successful, the adjustment parameter is the parameter with the same value.
[0017] Optionally, the judgment step and the classification step can be performed after the adjustment parameter is adjusted to other different parameter values.
[0018] Optionally, it also includes a random parameter setting step, in which the preset parameter is set to a predetermined value using the classification results of the preset parameter and the same value parameter in the classification step, and the same value parameter is set to a random value in a way that keeps the first element and the second element the same value, then instance docking is performed, and streaming data for design rule checking is generated.
[0019] Optionally, the semiconductor device layout design method includes four stages: the first stage sets the parameters of the components to be connected to default values; the second stage determines whether the parameters of the components to be connected are preset parameters or parameters with the same value; the third stage generates streaming data under the condition that the components can be connected; and the fourth stage uses the generated streaming data to perform design rule checks.
[0020] Optionally, the element includes a transistor, and the parameters of the element include gate length, gate index, or gate index width.
[0021] In summary, the semiconductor device layout design apparatus and method provided by this invention can reduce the number of incompatible combinations between instances while maintaining the verification coverage during Pcell verification, thereby achieving efficient DRC verification. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of a semiconductor device layout design apparatus provided in an embodiment of the present invention.
[0023] Figure 2 This is a schematic diagram illustrating an example of the circuit design stage provided in an embodiment of the present invention.
[0024] Figure 3 This is a schematic diagram illustrating an example of the layout design stage provided in an embodiment of the present invention.
[0025] Figure 4 This is a schematic diagram illustrating an example of docking achieved through unit adjacency according to an embodiment of the present invention.
[0026] Figure 5 This is a schematic diagram of example parameters provided in an embodiment of the present invention.
[0027] Figure 6 This is a flowchart of the first stage of a semiconductor device layout design method provided in an embodiment of the present invention.
[0028] Figure 7 This is a flowchart illustrating the second stage of a semiconductor device layout design method according to an embodiment of the present invention.
[0029] Figure 8 This is a flowchart illustrating the third stage of a semiconductor device layout design method according to an embodiment of the present invention.
[0030] Figure 9 This is a flowchart illustrating the fourth stage of a semiconductor device layout design method according to an embodiment of the present invention.
[0031] Figure 10 This is a flowchart illustrating the judgment operation of preset parameters and parameters with the same value provided in an embodiment of the present invention.
[0032] Figure 11 This is a functional block diagram of the layout design operation-related functions in a semiconductor device layout design apparatus provided in an embodiment of the present invention.
[0033] Explanation of reference numerals in the attached figures:
[0034] 10-Processing unit; 12-Storage unit; 14-Input unit; 16-Output unit; 18-Communication unit; 20-Schematic editor; 22-Layout editor; 24-DRC tool; 100-Layout design device; 102-Communication network. Detailed Implementation
[0035] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0036] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature.
[0037] This invention provides a semiconductor device layout design apparatus for determining parameters used to connect adjacent first and second elements, comprising:
[0038] The determining device uses one of a plurality of specification parameters of the second element as an adjustment parameter, adjusts its value, and determines whether the docking with the first element is successful; and,
[0039] The classification device categorizes the adjustment parameters according to the judgment result of the judgment device into: preset parameters that should not be adjusted for docking purposes, and parameters with the same value that require the first element and the second element to be set to the same value for docking purposes. In other words, the adjustment parameters are classified into preset parameters and parameters with the same value.
[0040] In one embodiment of the present invention, in the classification device, if the judgment result of the judgment device is that docking fails, the adjustment parameter of the first element and the parameter corresponding to the adjustment parameter of the second element are set to the same value. Then, if the docking of the first element and the second element fails, the adjustment parameter is the preset parameter, and if the docking is successful, the adjustment parameter is the parameter with the same value.
[0041] In one embodiment of the present invention, after the adjustment parameter is adjusted to other different parameter values, the operation of the judgment device and the classification device is performed.
[0042] In one embodiment of the present invention, a random parameter setting device is further included. The random parameter setting device uses the classification results of the preset parameters and the same-value parameters of the classification device to set the preset parameters to a predetermined value, and sets the same-value parameters to random values in a manner that keeps the first element and the second element the same value, and then performs instance docking and generates streaming data for design rule checking.
[0043] Figure 1 This is a schematic diagram of a semiconductor device layout design apparatus according to an embodiment of the present invention. In one embodiment, please refer to... Figure 1 As shown, the semiconductor device layout design apparatus 100 includes a processing unit 10, a storage unit 12, an input unit 14, an output unit 16, and a communication unit 18.
[0044] The semiconductor device layout design apparatus 100 may be, for example, composed of a conventional computer. The processing unit 10 includes a CPU or other device for computational operations. The processing unit 10 executes the semiconductor device layout design program stored in the storage unit 12, thereby providing the function of providing semiconductor device layout design within the semiconductor device layout design apparatus 100. The storage unit 12 includes a semiconductor memory, a memory card, or other storage device. The storage unit 12 is connected to the processing unit 10 in an accessible manner and stores the semiconductor device layout design program and the information required for its operation. The input unit 14 includes an information input device. The input unit 14 may include, for example, a keyboard, a touchscreen, buttons, or other devices for receiving user input. The output unit 16 includes a user interface (UI) for receiving user input information, or other devices for outputting the processing results of the semiconductor device layout design apparatus 100. The output unit 16 may include, for example, a display for showing images to the user. The communication unit 18 includes an interface for communicating with external devices such as cloud storage devices via a communication network 102. The communication unit 18 may employ either wired or wireless communication.
[0045] Furthermore, although this embodiment takes the semiconductor device layout design apparatus 100 as a single device as an example, the operations performed by the semiconductor device layout design apparatus 100 may also be partially or entirely implemented by the same terminal device, or by different terminal devices that are distributed from each other.
[0046] Accordingly, the present invention also provides a semiconductor device layout design method for determining the parameters of docking adjacent first and second elements, comprising:
[0047] The judgment step involves using one of the multiple specification parameters of the second component as an adjustment parameter, adjusting its value, and determining whether the docking with the first component is successful; and...
[0048] The classification step, based on the judgment result of the judgment step, classifies the adjustment parameters into: preset parameters that should not be adjusted for docking purposes, and parameters that require the first element and the second element to be set to the same value for docking purposes.
[0049] In one embodiment of the present invention, in the classification step, if the judgment result of the judgment step is docking failure, the adjustment parameter of the first element and the parameter corresponding to the adjustment parameter of the second element are set to the same value. Subsequently, if the docking of the first element and the second element fails, the adjustment parameter is the preset parameter, and if the docking is successful, the adjustment parameter is the parameter with the same value.
[0050] In one embodiment of the present invention, after the adjustment parameter is adjusted to other different parameter values, the judgment step and the classification step are performed.
[0051] In one embodiment of the present invention, a random parameter setting step is further included. In the random parameter setting step, the preset parameter is set to a predetermined value using the classification results of the preset parameter and the same value parameter in the classification step, and the same value parameter is set to a random value in a way that keeps the first element and the second element the same value. Then, instance docking is performed, and streaming data for design rule checking is generated.
[0052] In one embodiment of the present invention, the semiconductor device layout design method includes four stages: the first stage sets the parameters of the component to be docked to default values; the second stage determines whether the parameters of the component to be docked are preset parameters or parameters with the same value; the third stage generates streaming data under the condition that the components can be docked; and the fourth stage performs design rule checks using the generated streaming data. The component includes a transistor, and the parameters of the component include gate length, gate index, or gate index width.
[0053] The following describes a method for performing semiconductor device layout design using the semiconductor device layout design apparatus 100.
[0054] In this embodiment, semiconductor device layout design is achieved by combining the circuit design stage performed by the schematic editor with the layout design stage performed by the layout editor.
[0055] like Figure 2 As shown, in the circuit design phase of the schematic editor, using parameterized cells (Pcells) or components such as transistors and resistors as examples, for instance... Figure 2Examples 1 and 2 demonstrate designing semiconductor devices in a circuit diagram. Following this, the layout design phase using a layout editor begins. Figure 3 As shown, during the layout design phase, examples 1 and 2 in the circuit diagram are laid out. Among them, as... Figure 4 As shown, the connection ends of Instance 1 and Instance 2, which have completed electrical connections, are connected to each other. If the cell adjacency function of the layout editor determines that the connection is possible, the connection between the instances is realized.
[0056] Figure 5 This is a schematic diagram illustrating example parameters provided in an embodiment of the present invention. For example... Figure 5 As shown, instances are characterized by multiple parameters such as gate length (L), gate index (NF), and gate index width (FW). These parameters affect whether docking can be achieved through cell adjacency. For example, sometimes there are cases where FW values do not match. In this case, instances cannot be docked because the connection ends cannot be correctly aligned.
[0057] The following is for reference. Figures 6 to 10 The flowchart shown illustrates the layout design method for semiconductor devices.
[0058] The semiconductor device layout design method of this embodiment consists of the following four stages: setting the parameters of the instance to be docked to default values for docking (first stage); determining whether the parameters of the instance to be docked are preset parameters or parameters with the same value (second stage); generating streaming data under the condition that the instance can be docked (third stage); and performing DRC with the generated streaming data (fourth stage).
[0059] Figure 6 This is a flowchart of the first stage operation of a semiconductor device layout design method according to an embodiment of the present invention. In this stage, the parameters of the instance to be docked are set to default values and docking verification is performed without fine-tuning of the instance parameters.
[0060] In step S10, in the schematic editor, the first instance (e.g., instance 1, or the first element) and the second instance (e.g., instance 2, or the second element) are set to default values. The default values refer to the initial settings of multiple characterization parameters (such as gate length, gate index, gate finger width, etc.) for each instance.
[0061] In step S11, in the schematic editor, the connection ends of instances 1 and 2 to be connected are connected to each other. Specifically, the connection ends of the instances to be connected are connected to each other.
[0062] In step S12, instances 1 and 2 are arranged in the schematic editor. This operation is performed according to the connection relationship defined in the schematic editor, and the instances to be docked are arranged adjacent to each other within the layout area. This arrangement operation is a prerequisite for docking between instances.
[0063] In step S13, the cell adjacency function of the layout editor is activated to automatically perform instance docking. Whether docking is successful depends on the parameter values of instances 1 and 2 to be docked; under certain parameter values, docking may fail. If docking is successful, the coordinates of instances 1 and 2 are adjusted in the semiconductor device layout so that the docking connection ends of instances 1 and 2 coincide with each other.
[0064] In step S14, the result indicating whether the instance successfully docked is saved as data. Specifically, a success message is saved when docking is successful, and a failure message is saved when docking fails. This result information is used for parameter classification operations in the subsequent second stage; that is, it serves as basic information when analyzing parameters affecting the success or failure of docking.
[0065] Figure 7 This is a flowchart of the second-stage operation process for semiconductor device layout design according to an embodiment of the present invention. In this stage, instance parameters are classified. Specifically, among multiple parameters related to the instances to be docked, parameters that should not be adjusted for docking purposes are identified as preset parameters, and parameters that require both instances to be set to the same value for docking purposes are identified as same-value parameters.
[0066] In step S20, in the schematic editor, instance 1 of the instances to be docked is set to a specified value, and one of the multiple characterizing parameters of instance 2 of the instances to be docked is selected as an adjustment parameter, and its value is adjusted, that is, one of the parameters of instance 2 is randomly adjusted. The adjustment parameter is a parameter that has a direct impact on the layout design, such as gate length, gate index, and gate index width, and is used as the judgment object to determine whether docking can be achieved in subsequent operations.
[0067] In step S21, in the schematic editor, the connection ends of instance 1 (without adjusted parameters) and instance 2 (with adjusted parameters) are connected to each other. Specifically, the connection ends of the instances to be docked are connected to each other.
[0068] In step S22, instances 1 and 2 are arranged in the layout editor. This operation is performed according to the connection relationship defined in the schematic editor, and the instances to be docked are arranged adjacent to each other within the layout area. This arrangement operation is a prerequisite for realizing the docking between instances.
[0069] In step S23, the cell adjacency function of the layout editor is activated to automatically perform instance docking. Whether docking is successful depends on the parameter values of instances 1 and 2 to be docked; under certain parameter values, docking may not be achieved. If docking is successful, the coordinates of instances 1 and 2 are adjusted in the semiconductor device layout so that the docking connection ends of instances 1 and 2 coincide with each other.
[0070] In step S24, the results indicating whether instance 1 (without adjusted parameters) and instance 2 (with adjusted parameters) successfully docked are saved as data. Specifically, a success message is saved when docking is successful, and a failure message is saved when docking fails. This result information is subsequently used in parameter classification operations.
[0071] In step S25, the adjusted parameters are classified according to the instance docking judgment result. For example, the adjusted parameters are judged as preset parameters or parameters with the same value. Figure 10 This is a detailed flowchart of the parameter classification operation performed in step S25, specifically the flowchart for judging preset parameters and parameters with the same value. The operation in step S25 follows... Figure 10 The flowchart shown is followed.
[0072] In step S250, the information saved in step S24 is read. In step S251, it is determined whether the docking was successful. If the docking was successful, the adjustment parameters are determined to be parameters that can achieve docking even with random adjustments. At this time, return to step S20 to determine the new parameters. If the docking failed, proceed to step S252.
[0073] In step S252, the value of the parameter corresponding to the adjustment parameter in instance 1 is set to the same value as the adjustment parameter in instance 2. In step S253, the cell adjacency function of the layout editor is activated to automatically perform instance docking; specifically, instance 1 and instance 2 are docked. In step S254, the result indicating whether instance 1 and instance 2 have successfully docked is saved as data. Specifically, when docking is successful, a success message is saved; when docking fails, a failure message is saved.
[0074] In step S255, it is determined whether the docking was successful. If the docking failed, i.e., no, then in step S256, the current adjustment parameter is classified as a preset parameter. That is, since docking still fails even if the parameter values are set to be consistent, the current parameter is determined to be a parameter that must be fixed for the purpose of docking. If the docking was successful, i.e., yes, then in step S257, the current adjustment parameter is classified as a parameter with the same value. That is, since docking will succeed once the parameter values are set to be consistent, the current parameter is determined to be a parameter that must be set to the same value between instances for the purpose of docking.
[0075] Then, return Figure 7 The main process shown proceeds to step S26. In step S26, information indicating whether the adjustment parameter is a preset parameter or a parameter with the same value is saved. This classification result is used to generate streaming data in the third stage.
[0076] In step S27, it is determined whether there are any parameters in the specifications of the instance to be docked that have not yet been adjusted. If there are still unadjusted parameters, proceed to step S20 to use the new parameters as adjustment parameters and perform the corresponding operations. If all parameters to be determined have been processed, proceed to step S30 of the third stage.
[0077] Figure 8 This is a flowchart of the third stage operation process for semiconductor device layout design according to an embodiment of the present invention. In this stage, streaming data is generated using the preset parameters and the classification results of the same-value parameters from the second stage, provided that the instances can be connected.
[0078] In step S30, for instances 1 and 2 to be docked, the preset parameters classified in the second stage are set to predetermined fixed values. Since docking cannot be achieved between instances if the preset parameters are not fixed to specific values, this approach eliminates the possibility of docking failure in subsequent operations due to automatically assigning preset parameters to specific values.
[0079] In step S31, for instance 1 and instance 2 to be docked, the parameters other than the preset parameters are adjusted to random values.
[0080] In step S32, the value of the same-value parameter is set. The same-value parameter is the parameter that needs to have the same value in both Instance 1 and Instance 2. In this step, the value of the same-value parameter in Instance 2 is set to be the same as the value of the same-value parameter in Instance 1. In this way, while meeting the conditions for successful docking, the generated streaming data can also ensure the diversity of parameters.
[0081] In step S33, it is determined whether the predetermined number of repetitions has been reached. This number of repetitions is the maximum number of random values taken during the streaming data generation process. If the number of repetitions has not been reached (i.e., no), the process returns to step S30 to continue setting the parameters. If the number of repetitions has been reached (i.e., yes), the process proceeds to step S34.
[0082] In step S34, for one of the settings in steps S30 to S33, instance 1 and instance 2 are arranged in the layout editor. This operation is performed according to the connection relationship defined in the schematic editor, and the instances to be docked are arranged adjacent to each other within the layout area.
[0083] In step S35, the cell adjacency function of the layout editor is activated to automatically perform instance docking. At this point, since the preset parameters and same-value parameters classified in the second stage have been set, successful docking is guaranteed. After successful docking, the instance coordinates are adjusted to achieve a layout where the connected ends overlap.
[0084] In step S36, the instance docking results are saved. Specifically, the result indicating whether instance 1 and instance 2 successfully docked is saved as data.
[0085] In step S37, it is determined whether the predetermined number of repetitions has been reached. This number of repetitions is the maximum number of random values taken during the streaming data generation process. If the number of repetitions has not been reached (i.e., no), the process returns to step S34 to perform instance layout operations (instance docking) for the next setting. If the number of repetitions has been reached (i.e., yes), the process proceeds to the fourth stage, i.e., step S40.
[0086] In addition, the aforementioned judgment and classification of preset parameters and equivalent parameters can be performed after adjusting the adjustment parameters to other parameter values. For example, when the gate index of an instance is set to 1, if the adjustment parameter is the source-drain connection parameter (connectSD) of that instance, it is impossible to determine whether this parameter (connectSD) is a preset parameter or an equivalent parameter because the setting of this parameter (connectSD) is meaningless. For this reason, the gate index of the instance can be adjusted to any value that allows for cell adjacency before the judgment and classification of preset parameters and equivalent parameters can be performed. That is, the gate index of the instance can be set to 2 or a larger value first, and then the judgment and classification of preset parameters and equivalent parameters can be performed for the parameter (connectSD) of that instance.
[0087] Figure 9 This is a flowchart of the fourth stage operation process for semiconductor device layout design according to an embodiment of the present invention. In this stage, a semiconductor device layout is generated under each setting in the third stage, streaming data is output, and design rule checking (DRC) is performed on the streaming data to verify whether the instance docking implemented by cell adjacency is effective.
[0088] In step S40, along with the semiconductor device layout generated in the third stage, streaming data is output. The streaming data reflects the layout data from the placement and docking operations in the layout editor and uses standard layout data formats such as GDS. Based on this data input, the target of DRC operations can be determined.
[0089] In step S41, DRC is performed using streaming data. DRC is an automatic check for violations of design rules, such as verifying whether transistor spacing, line width, and contact layout conform to specified rules. In this embodiment, the verification object is particularly the part where instances are connected through cell adjacency, and the verification focus is on confirming whether the connection violates design rules.
[0090] In step S42, the DRC result is saved. When a violation is found, the location or content of the violation is recorded in the saved information; when no violation is found, the verification result is recorded as acceptable. This result can be used as Pcell verification data for designer confirmation. Furthermore, this result can also be used in subsequent design processes and automation tools.
[0091] In this invention, by classifying the aforementioned parameters into preset parameters that should not be adjusted for docking purposes and identical parameters that require two instances to have the same value for docking purposes, instances capable of docking can be generated efficiently. Thus, by... Figure 5 The parameters L, NF, FW, etc. shown are automatically used as the judgment objects, which means that the unit adjacency verification can be achieved efficiently without the need for the designer to make judgments for individual specific cases.
[0092] Figure 11 This is a functional block diagram of the layout design operation-related functions in a semiconductor device layout design apparatus provided in an embodiment of the present invention.
[0093] Please refer to Figure 11 As shown, the schematic editor 20 includes placement and routing functions. The schematic editor 20 functions to design circuits using parametric cells (Pcells). Specifically, after placing instances in the schematic using the placement function, the routing function defines the connection methods between the terminals. The schematic editor 20 saves the parameters of the Pcell instances as circuit information. The information set in the schematic cell (schematic database), parameter settings, and verification information refer to the schematic database (DB) used for parameter settings and the schematic database used for verification.
[0094] The layout editor 22 has the function of designing layouts at the physical level based on the circuit information defined by the schematic editor 20. The layout editor 22 has placement, cell adjacency, and streaming output functions. In the layout editor 22, the placement function arranges instances within the layout area, and the cell adjacency function achieves efficient cell docking by automatically overlapping the connection ends of the instances to be docked. Furthermore, the layout editor 22 also has parameter judgment and parameter setting functions, which are features of this invention. The parameter judgment function classifies the parameters of the instances into preset parameters that should be fixed for docking purposes and identical parameters that need to be set to the same value for docking purposes, based on the docking results. The classification results are passed to the parameter setting function, which assigns specified fixed values to the preset parameters and, while setting random values for identical parameters, ensures that identical parameters maintain the same value between the instances to be docked. The layout editor 22 outputs streaming data for the semiconductor device layout set in the parameter setting function, while referencing the layout database used for parameter setting and the layout database used for verification.
[0095] The DRC tool 24 takes the streaming data output by the layout editor 22 as input and performs verification operations according to design rules. Specifically, it automatically determines whether transistor size and spacing, line width, contact arrangement, etc., meet specified rules, and saves the results as DRC results. In this way, it can clearly determine whether the layout generated by cell adjacency conforms to the design rules, ensuring the efficiency and comprehensiveness of the verification process.
[0096] It should be noted that, Figure 11 In the diagram, the arrows at the positions of the two ① are connected, and the arrows at the positions of the two ② are connected.
[0097] In summary, the semiconductor device layout design apparatus and method provided by this invention can automatically determine multiple parameters of a Pcell with cell adjacency functionality. Parameters that should not be adjusted for docking purposes are set to fixed values as preset parameters, while parameters that require two components to have the same value for docking purposes are categorized as identical parameters. This not only allows for random parameter settings but also generates a semiconductor device layout that enables efficient docking of dockable instances and verifies the layout.
[0098] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A semiconductor device layout design apparatus, characterized in that, it determines parameters for docking adjacent first and second elements, and that, include: The judgment device uses one of the multiple specification parameters of the second element as an adjustment parameter, adjusts its value, and determines whether the docking with the first element is successful. as well as The classification device classifies the adjustment parameters according to the judgment result of the judgment device into: preset parameters that should not be adjusted for docking purposes, and same-value parameters that require the first element and the second element to be set to the same value for docking purposes. In the classification device, if the judgment result of the judgment device is docking failure, the parameter corresponding to the adjustment parameter of the first element is set to the same value as the adjustment parameter of the second element. Subsequently, if the docking of the first element and the second element fails, the adjustment parameter is the preset parameter, and if the docking is successful, the adjustment parameter is the same value parameter.
2. The semiconductor device layout design apparatus according to claim 1, wherein After adjusting the adjustment parameter to other different parameter values, the operation of the judgment device and the classification device is performed.
3. The semiconductor device layout design apparatus according to claim 1, wherein It also includes a random parameter setting device, which uses the classification results of the preset parameters and the same-value parameters of the classification device to set the preset parameters to predetermined values, and sets the same-value parameters to random values in a way that keeps the first element and the second element the same value, then performs instance docking and generates streaming data for design rule checking.
4. A semiconductor device layout design method, characterized in that, parameters for connecting adjacent first and second elements are determined, include: The judgment step involves using one of the multiple specification parameters of the second component as an adjustment parameter, adjusting its value, and determining whether the docking with the first component is successful. as well as The classification step, based on the judgment result of the judgment step, classifies the adjustment parameters into: preset parameters that should not be adjusted for docking purposes, and parameters with the same value that require the first element and the second element to be set to the same value for docking purposes. In the classification step, if the judgment result of the judgment step is docking failure, the parameter corresponding to the adjustment parameter of the first element is set to the same value as the adjustment parameter of the second element. Subsequently, if the docking of the first element and the second element fails, the adjustment parameter is the preset parameter, and if the docking is successful, the adjustment parameter is the same value parameter.
5. The semiconductor device layout design method according to claim 4, wherein After adjusting the adjustment parameter to other different parameter values, the judgment step and the classification step are performed.
6. The semiconductor device layout design method according to claim 4, characterized in that, It also includes a random parameter setting step, in which the preset parameter and the classification result of the same value parameter in the classification step are used to set the preset parameter to a predetermined value, and the same value parameter is set to a random value in a way that keeps the first element and the second element the same value, then instance docking is performed, and streaming data for design rule checking is generated.
7. The semiconductor device layout design method according to claim 4, wherein The semiconductor device layout design method includes four stages: the first stage sets the parameters of the components to be connected to default values; the second stage determines whether the parameters of the components to be connected to are preset parameters or parameters with the same value; the third stage generates streaming data under the condition that the components can be connected; and the fourth stage uses the generated streaming data to check design rules.
8. The semiconductor device layout design method according to claim 7, wherein The element includes a transistor, and the parameters of the element include gate length, gate index, or gate index width.