Display driving system, chip, electronic device and display device

Abstract

The invention relates to a display driving system, a chip, electronic equipment and display equipment, the display driving system comprises a time schedule controller and a plurality of source electrode driving chips, the time schedule controller is used for dividing each line of received image data into a plurality of sub-line data, and the sub-line data are output through a plurality of output interface pairs. Respectively and simultaneously outputting the plurality of sub-row data to the plurality of source electrode driving chips so as to reduce the data rate required to be processed by each source electrode driving chip; and the source electrode driving chip is used for expanding the data volume of the sub-row data to two times to obtain driving data. By using the display driving system disclosed by the invention, a pixel copying function under a high-speed output interface pair of the time schedule controller can be supported, and normal and high-quality display of a screen is ensured.

Description

Technical Field

[0001] This disclosure relates to the field of display drivers, and more particularly to a display driver system, chip, electronic device, and display device. Background Technology

[0002] In the field of large-screen displays, source driver chips are generally manufactured using mature processes such as 130nm to control costs and ensure reliability. However, this process node is extremely unfriendly to digital logic design. Specifically, when the target operating frequency enters the 5GHz range, even for basic logic operations such as adders, the circuit path delay often exceeds the process limits, making the design impossible to implement using related technologies. This fundamentally limits the chip's data processing capabilities at high speeds.

[0003] With the widespread adoption of high-resolution, high-refresh-rate display technologies, the output data rate of timing controllers has increased significantly. For example, existing timing controllers require two output interfaces to output data, with each output interface pair having a transmission rate of up to 1.5Gbps. To achieve pixel duplication (DPLC), the source driver chip typically needs to internally expand the amount of received data to twice the input, which correspondingly requires its internal data processing clock frequency to also be increased to twice the input clock frequency.

[0004] In this configuration, if the source driver chip internally performs a two-fold data expansion, the final output data rate of the source driver chip will increase to four times the input rate, since the timing controller outputs data through two output interfaces. This would require an internal clock frequency of approximately 6 GHz. However, the characteristic frequency and switching speed of transistors in the 130nm process are limited, making it difficult to stably support high-frequency clock signals in the 6 GHz range. Summary of the Invention

[0005] In view of this, the present disclosure provides a display driving system, a chip, an electronic device, and a display device.

[0006] According to one aspect of this disclosure, a display driving system is provided, comprising: a timing controller and a plurality of source driver chips, wherein: the timing controller is configured to divide each line of received image data into a plurality of sub-line data, and simultaneously output the plurality of sub-line data to the plurality of source driver chips through a plurality of output interface pairs, thereby reducing the data rate required to be processed by each source driver chip; the source driver chips are configured to expand the data volume of the sub-line data by two times to obtain driving data.

[0007] In one possible implementation, the source driver chip is used to perform interpolation processing on two adjacent pixel data for each pixel data of the sub-row data, so as to expand the data volume of the sub-row data to twice the size, thereby obtaining driving data.

[0008] In one possible implementation, the source driver chip is used for:

[0009] For the pixel sequence in the sub-row data, the pixel values ​​of every two adjacent pixels are averaged to interpolate the two adjacent pixel data, generating a new pixel value between the two adjacent pixels, thus forming the driving data.

[0010] In one possible implementation, the data transmission rate of each output interface pair ranges from 0.7Gbps to 1.5Gbps.

[0011] In one possible implementation, the number of sub-rows of each row of image data is equal to the number of output interface pairs and the number of source driver chips.

[0012] In one possible implementation, the timing controller is configured to: when the number of output interface pairs is two, divide each row of image data into a first half row of data and a second half row of data, wherein the first half row of data is used as a first sub-row of data and the second half row of data is used as a second sub-row of data.

[0013] In one possible implementation, the first output interface pair of the output interface pair outputs the first sub-row data to the first source driver chip, and the second output interface pair of the output interface pair outputs the second sub-row data to the second source driver chip.

[0014] According to one aspect of this disclosure, a chip is provided, including the display driver system described above.

[0015] According to one aspect of this disclosure, an electronic device is provided, including the display driving system provided in this disclosure.

[0016] According to one aspect of this disclosure, a display device is provided, including a plurality of display units and at least one of the display driving systems provided in this disclosure.

[0017] In one possible implementation, the display unit includes a display panel, which includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0018] According to another aspect of this disclosure, an electronic device is provided, including the display device described above.

[0019] This disclosure provides a display driving system, including: a timing controller and multiple source driver chips. The timing controller is configured to divide each received line of image data into multiple sub-line data, and simultaneously output the multiple sub-line data to the multiple source driver chips through multiple output interface pairs, thereby reducing the data processing rate required by each source driver chip. The source driver chips are configured to double the data volume of the sub-line data to obtain driving data. In this disclosure, by dividing each received line of image data into multiple sub-line data through the timing controller, each source driver chip only needs to process a portion of the data, which reduces the data processing rate requirement of each source driver chip. Furthermore, by double-doubling the sub-line data internally within the source driver chip (pixel duplication function), image quality can be improved. Therefore, the display driving system provided by this disclosure can maintain overall driving capability while reducing the data rate of a single source driver chip, thereby ensuring normal and high-quality screen display.

[0020] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0022] Figure 1 A block diagram of a display driving system according to an embodiment of the present disclosure is shown.

[0023] Figure 2 A schematic diagram illustrating a large-screen display pixel copying function according to an embodiment of the present disclosure is shown.

[0024] Figure 3 A schematic diagram of a display driving system in a 2Pair mode according to an embodiment of the present disclosure is shown.

[0025] Figure 4A schematic diagram of the internal configuration of a source driver chip according to an embodiment of the present disclosure is shown. Detailed Implementation

[0026] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0027] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0028] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0029] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0030] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0031] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0032] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0033] In the field of large-screen displays (large screens can refer to high-resolution, high-refresh-rate displays requiring high data throughput, such as 4K / 8K displays of 55 inches and above), source driver chips are generally manufactured using mature processes such as 130nm to control costs and ensure reliability. However, this process node is extremely unfriendly to digital logic design. Specifically, when the clock frequency of the core logic circuit for data processing inside the source driver chip enters the 5GHz range, even when performing basic logic operations such as adders, the circuit path delay often exceeds the process limit, making the design impossible to implement using related technologies. This fundamentally limits the chip's data processing capabilities at high speeds.

[0034] With the widespread adoption of high-resolution, high-refresh-rate display technologies, the output data rate of timing controllers has increased significantly. For example, existing timing controllers require two output interfaces to output data, with each output interface pair having a transmission rate of up to 1.5Gbps. To achieve pixel duplication (DPLC), the source driver chip typically needs to internally expand the amount of received data to twice the input, which correspondingly requires its internal data processing clock frequency to also be increased to twice the input clock frequency.

[0035] In this configuration, if the source driver chip internally performs a two-fold data expansion, the final output data rate of the source driver chip will increase to four times the input rate, since the timing controller outputs data through two output interfaces. This would require an internal clock frequency of approximately 6 GHz. However, the characteristic frequency and switching speed of transistors in the 130nm process are limited, making it difficult to stably support high-frequency clock signals in the 6 GHz range.

[0036] In view of this, embodiments of this disclosure provide a display driving system, including: a timing controller and a plurality of source driver chips, wherein: the timing controller is configured to divide each line of received image data into a plurality of sub-line data, and simultaneously output the plurality of sub-line data to the plurality of source driver chips through a plurality of output interface pairs, thereby reducing the data rate required to be processed by each source driver chip; the source driver chips are configured to expand the data volume of the sub-line data by two times to obtain driving data. By using the display driving system of this disclosure, pixel copying function under the high-speed output interface pairs of the timing controller can be supported, ensuring normal and high-quality display of the screen.

[0037] Figure 1 A block diagram of a display driving system according to an embodiment of the present disclosure is shown. Figure 1 As shown, the system includes:

[0038] The timing controller 11 and multiple source driver chips 12 are configured to: divide each line of received image data into multiple sub-line data, and simultaneously output the multiple sub-line data to the multiple source driver chips 12 through multiple output interface pairs, so as to reduce the data rate required to be processed by each source driver chip; the source driver chips 12 are configured to expand the data volume of the sub-line data to twice the amount to obtain driving data.

[0039] A timing controller (TCON) is the control and processing unit of a display driving system. It is responsible for receiving video data streams from the main processor or image source and generating the timing signals and processed image data required to drive the display panel. It can act as the system's main controller, coordinating the synchronous operation of the source driver chip and the gate driver chip to ensure that image data is written to each pixel at precise moments.

[0040] The source driver chip can be a key execution unit in a display driving system. It can be directly connected to the data line of the display panel and can convert the digital pixel values ​​sent by the timing controller into precise analog voltages or currents, which are then applied to the corresponding pixel electrodes to control the transmittance or luminance of each sub-pixel, ultimately achieving grayscale display of the image.

[0041] An output pair can be two physical traces used to transmit a differential signal. An output pair (1Pair) can be a pair of symmetrical transmission lines used to transmit a differential signal.

[0042] The timing controller can divide each line of received image data into multiple sub-line data. The division can be average. After being divided into multiple sub-line data, the sub-line data can be simultaneously output to multiple source driver chips through multiple output interfaces. After receiving the sub-line data, each source driver chip can perform pixel copying function to expand the data volume of the sub-line data to twice the original, thus obtaining the driving data for driving the screen.

[0043] This disclosure provides a display driving system, including: a timing controller and a plurality of source driver chips. The timing controller is configured to divide each line of received image data into multiple sub-line data, and simultaneously output the multiple sub-line data to the plurality of source driver chips through multiple output interface pairs, thereby reducing the data processing rate required by each source driver chip. The source driver chips are configured to expand the data volume of the sub-line data by two times to obtain driving data. By using the display driving system of this disclosure, pixel duplication function under the high-speed output interface pairs of the timing controller can be supported, ensuring normal and high-quality screen display.

[0044] In one possible implementation, the source driver chip is used to perform interpolation processing on two adjacent pixel data for each pixel data of the sub-row data, so as to expand the data volume of the sub-row data to twice the size, thereby obtaining driving data.

[0045] Specifically, when implementing the pixel replication function in the source driver chip, for each pixel data in the sub-row data, interpolation processing can be performed on the adjacent pixel data. In this way, the data volume of the sub-row data is expanded to twice the size to obtain the driving data. Among them, the interpolation can be nearest neighbor interpolation, linear interpolation, etc.

[0046] In this embodiment of the disclosure, the data volume of the sub-row data is expanded to twice by interpolation processing. This allows the source driver chip to achieve pixel copying function without increasing external memory resources and bandwidth requirements, thereby reducing hardware costs.

[0047] In the large-screen display pixel duplication (DPLC) function, the source driver chip can expand the received data amount to twice the input. Under this function, when the TCON inputs half a row of pixels, the receiving end (using the source driver as the receiving end) expands the received half-row of pixels into one row of pixels through calculation. For example, Figure 2 A schematic diagram illustrating a large-screen display pixel replication function according to an embodiment of the present disclosure is shown. (See also...) Figure 2 COF N and COF N-1 are the source driver chip numbers, TX is the transmitter (with TCON as the transmitter), and RX is the receiver. Each source driver chip has 960 physical driver channels (ch) to drive 320 complete pixels, based on a 3-channel / pixel structure. In pixel replication mode, the amount of logical data sent by TCON to each chip is halved, meaning the source driver chip receives data corresponding to 480 logical channels (ch). Through internal interpolation and other processes, the source driver chip expands the logical data of these 480 channels to drive all 960 physical channels.

[0048] In one possible implementation, the source driver chip is configured to: for the pixel sequence in the sub-row data, perform interpolation processing on the two adjacent pixel data by averaging the pixel values ​​of every two adjacent pixels to generate a new pixel value located between the two adjacent pixels, thereby forming the driving data.

[0049] That is, linear interpolation can be used to average the pixel values ​​of two adjacent pixels in the pixel sequence of the sub-row data (add the adjacent sub-pixels and divide by 2) to generate a new pixel value between the two adjacent pixels, thus forming the driving data.

[0050] In this embodiment, linear interpolation is used to process the pixel sequence in the sub-row data. The pixel values ​​of two adjacent pixels are averaged (i.e., the adjacent sub-pixels are added and divided by 2) to generate a new pixel value located between the two adjacent pixels. Since linear interpolation consumes less hardware resources, this method can reduce hardware resource consumption while ensuring the smoothness and continuity of the image.

[0051] In one possible implementation, the number of sub-rows of each row of image data is equal to the number of output interface pairs and the number of source driver chips.

[0052] Specifically, the timing controller can have M output interface pairs for connecting M source driver chips. The timing controller can logically divide the image data containing N pixels in each row into M consecutive pixel data blocks to form M sub-row data, and transmit them simultaneously to the corresponding M source driver chips through the M output interface pairs, where M and N are positive integers.

[0053] In this embodiment of the disclosure, by dividing each row of image data into multiple sub-rows and assigning the multiple sub-rows to different source driver chips for processing, each source driver chip only needs to process a portion of the data, which can reduce the data processing rate requirement of each source driver chip and ensure normal and high-quality display of the screen.

[0054] In one possible implementation, the timing controller is configured to: when the number of output interface pairs is two, divide each row of image data into a first half row of data and a second half row of data, wherein the first half row of data is used as a first sub-row of data and the second half row of data is used as a second sub-row of data.

[0055] When the number of output interface pairs is two (2Pair), each row of image data can be evenly divided into the first half of the data and the second half of the data. The first half of the data can be used as the first sub-row data, and the second half of the data can be used as the second sub-row data.

[0056] In one possible implementation, the first output interface pair of the output interface pair outputs the first sub-row data to the first source driver chip, and the second output interface pair of the output interface pair outputs the second sub-row data to the second source driver chip.

[0057] After dividing the data into the first sub-row and the second sub-row, the first sub-row data can be output to the first source driver chip via the first output interface pair, and the second sub-row data can be output to the second source driver chip via the second output interface pair. The first source driver chip and the second source driver chip can be different source driver chips, used to process half of the data in each row respectively.

[0058] In this embodiment of the disclosure, by dividing each row of data into a first half and a second half, and transmitting them simultaneously through two output interfaces, each source driver chip only needs to process half of the data in that row of the image. For example, where the source driver chip originally needed to implement a 6GHz clock frequency, now it only needs to implement a 3GHz clock frequency, which is more feasible for the 130nm process technology.

[0059] For example, Figure 3 A schematic diagram of a display driving system in a 2Pair mode according to an embodiment of the present disclosure is shown. Figure 3 As shown, Figure 3 The diagram illustrates the workflow of a display driver system in a 2-Pair pixel replication mode that inputs 960 channels of data. Figure 3 As can be seen, TCON divides each line of data into a first half and a second half, transmitting them to two source driver chips via Pair1 and Pair2 respectively. The source driver chips then transmit the image pixel data to the screen. In this way, the final output data rate of each source driver chip is twice the input rate, not four times. Therefore, its internal data processing clock frequency is also twice the input clock frequency. Thus, when the transmission rate of each output interface pair reaches 1.5Gbps, the corresponding output frequency is 3GHz, which is supported by a 130nm process.

[0060] In one possible implementation, the data transmission rate of each output interface pair ranges from 0.7Gbps to 1.5Gbps.

[0061] When the source driver chip operates in pixel replication mode, the effective data rate that its internal data processing unit needs to process will reach four times the interface rate. Therefore, the clock frequency and data processing capability of the core logic inside the chip need to meet the corresponding data throughput requirements of 2.8Gbps to 6Gbps, and the source driver chip needs to implement a clock frequency of 2.8GHz to 6GHz. However, by using the display driver system of this disclosure embodiment, the required data rate and clock frequency of each source driver chip can be reduced. For example, in the case of two output interface pairs, the clock frequency that the source driver chip needs to implement is reduced to 1.4GHz to 3GHz, thereby ensuring normal and high-quality display of the screen.

[0062] For example, Figure 4 A schematic diagram of the internal configuration of a source driver chip according to an embodiment of the present disclosure is shown. In the 1+1 Pair pixel copying mode, two output interfaces output to two Source Drivers respectively, and the Source Drivers operate in pixel copying mode. Figure 4 In the DPHY Freq and Latch Freq, X and Y are 6 GHz. From Figure 4 As can be seen, in the 2-Pair DPLC mode, the output latch frequency is 6GHz / 13.5 (i.e., the latch period is extremely short). For the 130nm process latch, its inherent switching delay is relatively large, which cannot meet the extremely narrow timing window requirement corresponding to the 6GHz / 13.5 output latch frequency, thus failing to receive data correctly. However, through the 1+1 Pair DPLC mode of this disclosure embodiment, the latch can receive data correctly, thereby ensuring normal and high-quality display of the screen.

[0063] This disclosure provides a display driving system, including: a timing controller and a plurality of source driver chips. The timing controller is configured to divide each line of received image data into multiple sub-line data, and simultaneously output the multiple sub-line data to the plurality of source driver chips through multiple output interface pairs, thereby reducing the data processing rate required by each source driver chip. The source driver chips are configured to expand the data volume of the sub-line data by two times to obtain driving data. By using the display driving system of this disclosure, pixel duplication at high frequencies can be supported, ensuring normal and high-quality screen display.

[0064] Application scenario examples

[0065] When the TCON receives 1.5Gbps high-frequency video data from a 2-Pair input, it requests the TCON to split each line of data into two halves, outputting them simultaneously in two pairs. Specifically, Pair1 outputs the first half of each line, and Pair2 outputs the second half. The Source Driver can then receive data from both pairs simultaneously. Figure 3As shown. At this point, the source driver operates with two pairs simultaneously in the pixel copying function of one pair. Since the data volume of a single pair is halved, the pixel copying rate of the source driver for one pair is doubled to 3Gbps. The source driver supports an output frequency of 3GHz. Therefore, the single-chip 2-pair pixel copying mode, which lacks the supported rate, is transformed into a mode where each of the two source driver chips operates in the pixel copying mode of one pair. This enables the support of the 2-pair pixel copying mode at high frequencies and successfully drives the screen. The mode transition is as follows: Figure 4 As shown.

[0066] Bottlenecks in implementing DPLC functionality within the Source Driver include: Figure 4 As shown, the output frequency of the DPLC in 2-Pair mode is four times the input data frequency. With such a high frequency, the subsequent latch cannot correctly receive the data under the current 130nm process. However, for 1-Pair mode, the latch can accept the data frequency output by the Display Physical Layer (DPLC) under the 130nm DPLC function. Therefore, it is feasible to implement 2-Pair DPLC reception using two chips: a 1-Pair DPLC and a 1-Pair DPLC.

[0067] The Source Driver chip provided in this embodiment can work with TCON under the low process conditions of 130nm to achieve the 2Pair DPLC function that a single Source Driver chip cannot achieve, thereby correctly driving the screen under this process condition.

[0068] This disclosure also provides a chip, including the display driver system described above.

[0069] This disclosure also provides an electronic device, including the display driving system described above.

[0070] This disclosure also provides a display device, including a plurality of display units and at least one of the display driving systems described above.

[0071] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0072] This disclosure also provides a computer program product, including a computer program or a non-volatile computer-readable storage medium carrying the computer program, wherein the computer program, when executed by a processor, implements the steps of the above method.

[0073] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0074] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A display driving system, characterized in that, include: Timing controller, multiple source driver chips, including: The timing controller is used to divide each line of received image data into multiple sub-line data, and output the multiple sub-line data to the multiple source driver chips simultaneously through multiple output interface pairs, so as to reduce the data rate required to be processed by each source driver chip. The source driver chip is used to expand the data volume of the sub-row data to twice the amount to obtain driving data.

2. The system according to claim 1, characterized in that, The source driver chip is used to perform interpolation processing on two adjacent pixel data for each pixel data of the sub-row data, so as to expand the data volume of the sub-row data to twice the size, and obtain driving data.

3. The system according to claim 2, characterized in that, The source driver chip is used for: For the pixel sequence in the sub-row data, the pixel values ​​of every two adjacent pixels are averaged to interpolate the two adjacent pixel data, generating a new pixel value between the two adjacent pixels, thus forming the driving data.

4. The system according to claim 1, characterized in that, The data transmission rate of each output interface pair ranges from 0.7Gbps to 1.5Gbps.

5. The system according to claim 1, characterized in that, The number of sub-rows of each row of image data is equal to the number of output interface pairs and the number of source driver chips.

6. The system according to claim 1, characterized in that, The timing controller is used for: When there are two output interface pairs, each row of image data is divided into a first half row of data and a second half row of data, with the first half row of data serving as the first sub-row of data and the second half row of data serving as the second sub-row of data.

7. The system according to claim 6, characterized in that, The first output interface pair in the output interface pair outputs the first sub-row data to the first source driver chip, and the second output interface pair in the output interface pair outputs the second sub-row data to the second source driver chip.

8. A chip, characterized in that, Includes the display driving system as described in claims 1 to 7.

9. An electronic device, characterized in that, Includes the display driving system as described in claims 1 to 7.

10. A display device, characterized in that, It includes multiple display units and at least one display driving system according to claims 1 to 7.

11. The display device according to claim 10, characterized in that, The display unit includes a display panel, which includes at least one of the following: liquid crystal display panel, micro light-emitting diode display panel, light-emitting diode display panel, mini light-emitting diode display panel, quantum dot light-emitting diode display panel, organic light-emitting diode display panel, cathode ray tube display panel, digital light processing display panel, field emission display panel, plasma display panel, electrophoretic display panel, electrowetting display panel, and small-pitch display panel.

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