Low-power voice recognition and local task buffering for ai glasses

Abstract

The application belongs to the technical field of data transmission and processing, and particularly relates to a low-power voice recognition and local task buffering method of AI glasses, which comprises the following steps: a first-stage analog detection circuit monitors an analog signal output by a microphone, and outputs a first-stage wake-up pulse to wake up a second-stage digital signal processor when the duration of the analog signal amplitude continuously exceeding a sound pressure threshold reaches an activation duration; the second-stage digital signal processor performs analog-digital conversion on the analog signal to obtain a digital audio sampling sequence and divides and analyzes frames; and a third-stage main processor extracts a mel-frequency cepstrum feature vector sequence and inputs the mel-frequency cepstrum feature vector sequence into a neural network voice recognition model to output semantic text and a recognition confidence score. The application can effectively balance the interaction reliability, power consumption control and storage life, and improve the overall stability and practicality of the AI glasses voice interaction system.

Description

Technical Field

[0001] This invention belongs to the field of data transmission and processing technology, specifically relating to a low-power speech recognition and local task buffering method for AI glasses. Background Technology

[0002] Most existing voice interaction technologies are designed around smartphones or cloud devices. These systems typically rely on high-performance processors to continuously run voice front-end algorithms or upload audio data to the cloud in real time for recognition. While this approach can provide high recognition accuracy when battery capacity is sufficient and network conditions are stable, it reveals significant problems when directly applied to AI glasses. On one hand, continuously running digital voice detection and keyword recognition algorithms leads to frequent processor wake-ups, resulting in high static and dynamic power consumption and significantly shortening device battery life. On the other hand, relying on cloud recognition requires maintaining a network connection; if the network is unstable or latency increases, the user experience will significantly deteriorate, and voice commands may even be lost.

[0003] To reduce power consumption, some wearable devices have adopted always-on low-power voice detection circuits as a wake-up method. These solutions typically use analog comparators or simple energy detection at the hardware level to determine the presence of voice activity, thus waking up the main processor when sound is detected. However, relying solely on energy thresholds is susceptible to environmental noise, transient impact sounds, or mechanical vibrations, leading to frequent false wake-ups. False wake-ups not only increase power consumption but also trigger unnecessary subsequent recognition processes, reducing overall system efficiency. In digital domain voice detection, some existing solutions run simplified voice activity detection algorithms on low-power processors, such as those based on energy and zero-crossing rate. These algorithms can distinguish between voice and noise to some extent, but they typically lack multi-level filtering mechanisms. If the judgment conditions are too lenient, they will frequently wake up high-power processing units; conversely, if the judgment conditions are set too strictly, they are prone to missing short-duration or low-volume voice messages, affecting interaction reliability. Furthermore, these solutions often only focus on the wake-up process without systematically designing for the reliability of subsequent voice recognition, task generation, and storage. Summary of the Invention

[0004] Therefore, the main objective of this invention is to provide a low-power speech recognition and local task buffering method for AI glasses. This method reduces the number of invalid wake-ups of high-power processing units through a three-level progressive speech wake-up mechanism, significantly reducing standby power consumption while ensuring timely speech response. During the speech recognition stage, a task frame containing priority information is generated and hot-buffered using a hierarchical circular queue within SRAM, achieving low-latency storage and orderly management of speech recognition results. In the persistence stage, a log block writing method based on two-phase commit is introduced, combined with a confirmation bitmap and power-down recovery process, ensuring that tasks are not lost or duplicated in the event of abnormal power outages or system restarts.

[0005] The technical solution adopted in this invention is as follows: a low-power speech recognition and local task buffering method for AI glasses, comprising the following steps: a first-level analog detection circuit monitors the analog signal output by the microphone; when the amplitude of the analog signal continuously exceeds the sound pressure threshold for a duration reaching the activation duration, a first-level wake-up pulse is output to wake up the second-level digital signal processor; the second-level digital signal processor performs analog-to-digital conversion on the analog signal to obtain a digital audio sampling sequence and divides it into analysis frames; based on the energy fluctuation ratio and zero-crossing count within the frame, suspected speech frames are determined; when the number of consecutive suspected speech frames reaches the frame number threshold, a second-level wake-up pulse is output to wake up the third-level main processor and transmit the digital audio sampling sequence; the third-level main processor extracts the Mel-frequency cepstral feature vector sequence. The system inputs a neural network speech recognition model to output semantic text and recognition confidence scores, generating a task frame containing a task sequence number field, semantic content field, generation time field, and priority identifier field, and writes it into a high-priority circular queue or a normal-priority circular queue in SRAM. When the queue depth reaches the log block capacity, a two-stage commit process is executed based on the global commit status table in the metadata sector of the non-volatile memory, writing the task frame into the log block in the high-priority log sector or the normal-priority log sector and recording the acknowledgment bitmap in the block header area. After receiving the acknowledgment response signal, the acknowledgment bitmap is updated, and a compression and recycling operation is performed according to the power supply status and recycling wait counter to reuse the log block where all bits of the acknowledgment bitmap are one.

[0006] Furthermore, if the number of consecutive suspected voice frames does not reach the frame count threshold within the preset timeout period, the second-level digital signal processor returns to normal sleep mode, while the third-level main processor maintains deep sleep mode. After the third-level main processor completes the generation of the task frame, it sends a sleep command to the second-level digital signal processor, and the second-level digital signal processor returns to normal sleep mode.

[0007] Furthermore, the calculation of the intra-frame energy fluctuation ratio includes dividing all sampling points within the analysis frame into a first half and a second half according to the sampling time sequence, calculating the arithmetic mean of the absolute values ​​of the amplitudes of the sampling points in the first half and the arithmetic mean of the absolute values ​​of the amplitudes of the sampling points in the second half, and dividing the larger of the two arithmetic means by the smaller value to obtain the intra-frame energy fluctuation ratio; the calculation of the zero-crossing count includes counting the number of times the amplitude of the sampling points within the analysis frame changes from positive to negative to obtain the zero-crossing count; the determination of suspected speech frames includes determining the analysis frame as a suspected speech frame when the intra-frame energy fluctuation ratio is less than the preset fluctuation upper limit and the zero-crossing count is within the preset zero-crossing interval.

[0008] Furthermore, the priority identifier field value is determined based on the recognition confidence score. When the recognition confidence score is greater than or equal to the preset high confidence threshold, the priority identifier field is set to high priority; when the recognition confidence score is less than the preset high confidence threshold, the priority identifier field is set to normal priority.

[0009] Furthermore, both the high-priority circular queue and the normal-priority circular queue have a fixed number of storage slots, and the byte capacity of each storage slot is equal to the byte length of the task frame. The high-priority circular queue is configured with a first write pointer and a first read pointer, while the normal-priority circular queue is configured with a second write pointer and a second read pointer. Writing a task frame includes copying all bytes of the task frame to the storage slot pointed to by the current write pointer in the target circular queue, then incrementing the current write pointer value by one, and resetting the current write pointer value to zero when the current write pointer value equals the total number of storage slots in the target circular queue.

[0010] Furthermore, the queue depth monitoring mechanism includes high-priority queue depth calculation and normal-priority queue depth calculation. High-priority queue depth calculation includes calculating the difference between the first write pointer value and the first read pointer value. When the difference is negative, the total number of storage slots of the high-priority circular queue is added to the difference to obtain the high-priority queue depth. Normal-priority queue depth calculation includes replacing the calculation method corresponding to the first write pointer and the first read pointer with the second write pointer and the second read pointer to obtain the normal-priority queue depth.

[0011] Furthermore, the non-volatile memory is divided into metadata sectors, high-priority log sectors, and normal-priority log sectors. The metadata sectors store the global commit status table, which contains multiple status records. Each status record contains a log block number field, a queue type field, and a commit status field. The queue type field takes the value of either high-priority or normal-priority, and the commit status field takes the values ​​of idle, ready, or completed.

[0012] Furthermore, high-priority log sectors are divided into multiple high-priority log blocks, and ordinary-priority log sectors are divided into multiple ordinary-priority log blocks. Each log block contains a block header area and a block body area. The block header area stores the block number, checksum, and acknowledgment bitmap. The number of bits in the acknowledgment bitmap is equal to the number of task frames that a single log block can hold. Each bit corresponds to the acknowledgment status of a task frame slot. A bit value of zero indicates unacknowledgment, and a bit value of one indicates acknowledgment. The block body area is divided into multiple task frame slots for storing task frames.

[0013] Furthermore, the two-phase commit process consists of a preparation phase and a completion phase. The preparation phase includes: searching the global commit status table for a record where the commit status field is idle and the queue type field matches the trigger queue type; reading the log block number field of the status record as the target log block number and rewriting the commit status field to the preparation state; sequentially reading multiple task frames to be persisted from the trigger queue and copying them to the task frame slots in the block body area corresponding to the target log block number in the order of reading; performing a byte-by-byte accumulation operation on all bytes in the block body area and setting the low-order byte of the accumulation result as... To verify the accumulated value, all bits of the confirmation bitmap are initialized to zero, and the target log block number and the accumulated verification value are written into the block header area of ​​the log block corresponding to the target log block number. The completion phase includes reading the accumulated verification value from the block header area as the readback verification value and performing a byte-by-byte accumulation operation on the block body area to obtain the calculated verification value. When the readback verification value matches the calculated verification value, the commit status field of the status record corresponding to the target log block number in the global commit status table is rewritten to the completed state. When the readback verification value does not match the calculated verification value, the commit status field is rewritten to the idle state and the process returns to the preparation phase to re-execute.

[0014] Furthermore, when the system is powered on again after a power outage, a cold start recovery process is executed. This process includes traversing all status records in the global commit status table, locating the corresponding log block number for status records with a "complete" commit status field, extracting the task frame from the block body area, and rewriting the task frame corresponding to a bit value of zero in the confirmation bitmap into the high-priority circular queue or normal-priority circular queue indicated by the priority identifier field in the task frame for processing. For status records with a "ready" commit status field, the commit status field is rewritten to the idle state. A confirmation signal is returned by the cloud server or local execution unit after completing task frame processing. This confirmation signal carries the value of the task sequence number field and is returned in ascending order of the task sequence number field. The hot buffer release operation includes determining the target circular queue to which the task frame is written based on the value of the task sequence number field and moving the read pointer of the target circular queue to the next storage slot corresponding to the value of the task sequence number field. The cold log confirmation marking operation includes filtering status records with a "complete" commit status field in the global commit status table and locating the corresponding log block in the block body area of ​​the log block. The task sequence number field of the retrieved task frame is used to locate the target log block. The slot index of the task frame corresponding to the value of the task sequence number field in the block body region of the target log block is calculated. The corresponding bit of the slot index in the confirmation bitmap in the block header region of the target log block is rewritten from zero to one. The power consumption-aware compression and reclamation mechanism includes monitoring the power supply status and maintaining a reclamation wait counter. The power supply status includes external power supply status and battery power supply status. The reclamation wait counter records the number of log blocks in which all bits of the confirmation bitmap are one. When the reclamation wait counter reaches the first reclamation threshold in the external power supply status, a compression and reclamation operation is performed. When the reclamation wait counter reaches the second reclamation threshold in the battery power supply status, a compression and reclamation operation is performed, and the second reclamation threshold is greater than the first reclamation threshold. The compression and reclamation operation includes traversing the status records in the global commit status table where the commit status field is in the completed state and reading the confirmation bitmap of the corresponding log block. When all bits of the confirmation bitmap are one, the commit status field of the status record is rewritten from the completed state to the idle state to reuse the log block. The reclamation wait counter value is decremented according to the number of reused log blocks to complete the reclamation of storage space and reduce the write amplification of non-volatile memory.

[0015] By adopting the above technical solution, this invention achieves the following beneficial effects: By introducing a three-level progressive voice wake-up mechanism, the always-on analog detection only performs the most basic sound pressure screening function. The digital signal processor and main processor are only woken up step-by-step when continuous conditions are met, reducing invalid wake-ups of high-power computing units at the source and lowering the average power consumption during standby and monitoring phases. In the digital signal processor stage, a joint determination method combining intra-frame energy fluctuations and zero-crossing counts is used to further screen voice features, effectively suppressing false triggering noise before it enters the main processor. This reduces energy waste caused by invalid wake-ups without sacrificing voice detection sensitivity.

[0016] On the main processor side, structured task frames are generated through local speech recognition, and a priority division based on recognition confidence is introduced. This enables the system to prioritize more reliable voice commands when resources are limited or the network is unstable, improving the determinism and usability of the overall interaction. Regarding task buffering, a hierarchical design of high-priority and ordinary-priority circular queues within SRAM is adopted, achieving low-latency writing and orderly management of speech recognition results, avoiding the energy consumption and lifespan reduction caused by frequent access to non-volatile memory.

[0017] Meanwhile, by triggering the writing of task frames to non-volatile memory according to the log block capacity, and combining it with a two-phase commit and verification mechanism, task data can be reliably recovered after power failure or abnormal restart, avoiding the loss or duplicate execution of voice commands and improving the stability of the system in complex usage scenarios. This invention also compresses and records the task completion status using a confirmation bitmap, requiring only minimal data writing for confirmation update operations, significantly reducing the number of writes to non-volatile memory.

[0018] Building upon this foundation, a compression and recycling strategy based on power supply status and a recycling wait counter is introduced. This allows log block reuse operations to be executed in batches at appropriate times, effectively suppressing write amplification, extending memory lifespan, and reducing instantaneous power consumption. Through the synergistic combination of these technologies, this invention achieves a good balance between low power consumption, reliability, and storage efficiency. It is particularly suitable for wearable device scenarios such as AI glasses, which have high requirements for battery life and stability, and has significant practical application value. Attached Figure Description

[0019] Figure 1 The wake-up principle timing waveform diagram of the first-stage analog detection circuit provided in the embodiment of the present invention includes four sub-diagrams; wherein, sub-diagram (a) represents the original analog signal collected by the microphone and the envelope voltage curve after processing; sub-diagram (b) represents the output logic level of the comparator; sub-diagram (c) represents the core logic of the activation duration determination mechanism; and sub-diagram (d) represents the final first-stage wake-up pulse output;

[0020] Figure 2 A schematic diagram illustrating the feature space distribution and judgment logic principle of the second-level digital signal processor performing voice activity detection (VAD) according to an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of the dynamic control experimental curves of the power consumption sensing compression and recycling mechanism provided in the embodiments of the present invention under different power supply conditions;

[0022] Figure 4 This is a schematic diagram illustrating the extraction process of Mel frequency cepstral coefficients and their differential features provided in an embodiment of the present invention. Detailed Implementation

[0023] All features disclosed in this specification, or all steps in all disclosed methods or processes, may be combined in any way, except for mutually exclusive features and / or steps.

[0024] The low-power speech recognition and local task buffering method for AI glasses includes the following steps: A first-stage analog detection circuit monitors the analog signal output from the microphone. When the amplitude of the analog signal continuously exceeds the sound pressure level threshold for a duration equal to the activation duration, a first-stage wake-up pulse is output to wake up the second-stage digital signal processor. The second-stage digital signal processor performs analog-to-digital conversion on the analog signal to obtain a digital audio sampling sequence and divides it into analysis frames. Suspected speech frames are determined based on the energy fluctuation ratio and zero-crossing count within each frame. When the number of consecutive suspected speech frames reaches a frame count threshold, a second-stage wake-up pulse is output to wake up the third-stage main processor and transmit the digital audio sampling sequence. The third-stage main processor extracts the Mel-frequency cepstral feature vector sequence and inputs it into the neural network. The network speech recognition model outputs semantic text and recognition confidence score, generates a task frame containing task sequence number, semantic content, generation time, and priority identifier fields, and writes it into a high-priority circular queue or a normal-priority circular queue in SRAM. When the queue depth reaches the log block capacity, a two-stage commit process is executed based on the global commit status table in the metadata sector of non-volatile memory. The task frame is written into the log block in the high-priority log sector or the normal-priority log sector, and an acknowledgment bitmap is recorded in the block header area. After receiving the acknowledgment response signal, the acknowledgment bitmap is updated, and a compression and recycling operation is performed according to the power supply status and recycling wait counter to reuse the log block where all bits of the acknowledgment bitmap are one.

[0025] The first-stage analog detection circuit operates continuously, with its input connected to the analog signal output from the microphone. The amplitude of the microphone's analog signal has a monotonic relationship with the ambient sound pressure level (MPL), so the MPL threshold can be mapped to the analog signal amplitude threshold through a single calibration. During calibration, the AI ​​glasses are worn, a stable sound source is played at a distance of 1 meter, the sound pressure level of the source is gradually adjusted, and the peak value and mean square amplitude of the microphone's analog signal are recorded simultaneously. The lowest MPL that is desired to trigger voice interaction is selected as the MPL threshold, for example, the analog signal amplitude corresponding to a MPL level of 65 dB is used as the threshold reference. The advantage of this setup is that the first-stage analog detection circuit does not need to perform complex calculations; it only needs to compare the analog signal amplitude with the threshold to effectively distinguish between normal noise and voice energy, thereby reducing the number of wake-up calls required for subsequent digital calculations and directly lowering average power consumption.

[0026] To achieve the goal of "the duration for which the analog signal amplitude continuously exceeds the sound pressure level threshold to reach the activation duration," the first-stage analog detection circuit can employ a combination of envelope extraction and duration determination. Specifically, the analog signal output from the microphone is first pre-amplified to match the dynamic range of subsequent stages, then rectified by full-wave rectification to obtain an analog signal in absolute amplitude form. This signal then enters an integrating network composed of resistors and capacitors to form an envelope voltage. The envelope voltage corresponds to the short-term energy changes of speech, transforming the rapidly fluctuating original waveform into a smooth amplitude trajectory, facilitating comparison and timing. The envelope voltage is fed into a comparator and compared with the threshold voltage. When the envelope voltage is higher than the threshold voltage, the comparator output remains high; when the envelope voltage is lower than the threshold voltage, the comparator output is low. To meet the "continuous exceedance" requirement, the comparator output then drives a timing circuit. The timing circuit accumulates time during the high-level period and resets the accumulation when the low-level condition occurs. The activation duration is used to suppress transient noise triggering. For example, metal impacts or knocks often have high energy but short duration, and the time exceeding the threshold is insufficient to reach the activation duration. Human voices, on the other hand, can typically maintain a certain duration at the beginning of phonation, making it easier to meet the activation duration condition. An activation duration of 80ms can be chosen, a value that can still cover the beginning of short syllables in spoken language while filtering out short impulse noise. After the timing circuit accumulates enough time to reach the activation duration, the first-stage analog detection circuit outputs the first-stage wake-up pulse. This first-stage wake-up pulse can be shaped by a monostable circuit into a fixed pulse width, such as 200µs, to ensure that the wake-up pin of the second-stage digital signal processor receives a clear and effective edge trigger, while avoiding additional quiescent current caused by prolonged level maintenance.

[0027] refer to Figure 1 The horizontal axis of the graph represents time. The unit is milliseconds (milliseconds) The vertical axis represents the analog signal amplitude, logic level state, and timer accumulated voltage, respectively. to Within the time window, the graph clearly illustrates how the system distinguishes between background noise, transient interference, and valid speech signals. Specifically, Figure 1 Subplot (a) shows the raw analog signal acquired by the microphone and the processed envelope voltage. The original signal contains low-amplitude background white noise and... to The sudden speech signal that appeared between the two periods simulated the characteristics of a sinusoidal burst during human speech, with a frequency of approximately The first-stage analog detection circuit first pre-amplifies and full-wave rectifies the raw signal, then extracts the signal envelope through an integrating network composed of resistors and capacitors. The dark, thick line in the diagram represents... Integral envelope voltage It smooths out the high-frequency jitter of the original signal, presenting a gradual change characteristic that fluctuates with the speech energy.

[0028] Figure 1 In subgraph (a), a horizontal dashed line is also marked, representing the voltage threshold corresponding to the preset sound pressure threshold. This threshold has been calibrated and corresponds to... Sound pressure level. It can be seen that during the background noise phase, the envelope voltage... Always below the voltage threshold After the voice signal appears, the envelope voltage... Rise rapidly and surpass . Figure 1 Subgraph (b) shows the output logic level of the comparator. The comparator continuously compares... and .when When the comparator outputs a logic low level ( );when When the comparator output flips to a logic high level, In the diagram, corresponding to the time interval of a speech burst, the comparator output presents a continuous high-level pulse window. This step converts the analog sound pressure energy change into digital domain time width information, laying the foundation for subsequent duration determination.

[0029] Figure 1 Subgraph (c) reveals the core logic of the activation duration determination mechanism, namely the cumulative voltage of the duration timer. The timing circuit only operates at the comparator output. When the voltage level is high, the capacitor is charged, so that... Linear increase; once When the signal goes low, the timing circuit immediately discharges the capacitor, causing... Reset to zero. This mechanism ensures that only a continuous energy input can accumulate the timing voltage. The activation duration threshold is set in the diagram. As can be seen, the timing voltage The voltage level rises continuously as the high level persists. If the input signal is a short, sharp tapping sound (e.g., duration less than...),... ), Will not reach the corresponding The voltage level is cleared to zero before the signal is applied, thus preventing false triggering. In this embodiment, however, the duration of the voice signal exceeds [a certain threshold]. Timing voltage Ultimately, the activation duration threshold was successfully exceeded.

[0030] Figure 1 Subgraph (d) shows the final first-stage wake-up pulse output. When the timing voltage Reaching the representative At the threshold instant, the monostable circuit is triggered to flip, outputting a positive pulse of fixed width, the pulse width of which is set to... .Should The high-level signal is directly connected to the external interrupt pin of the second-stage digital signal processor as a hardware wake-up signal. Through this hierarchical timing control, the first-stage analog detection circuit completes the detection of both "energy intensity" and "duration" at extremely low power consumption (microampere level), effectively filtering transient high-energy noise (such as falling sound) and steady-state low-energy noise (such as fan sound) in the environment. It only wakes up the subsequent high-power digital circuit when a significant sound pressure event with a certain duration is detected, thereby achieving ultra-low power standby of the system.

[0031] In an optional implementation, the first-stage analog detection circuit can also add a bandpass filter for the speech band, such as 300Hz to 3400Hz, before envelope extraction. This suppresses low-frequency wind noise and high-frequency friction noise before they enter the threshold comparison, thereby reducing false triggering under the same sound pressure threshold. Another option is to set a dual threshold, consisting of an upper threshold and a lower threshold. When the envelope voltage crosses the upper threshold, timing is started; when the envelope voltage crosses the lower threshold, timing is reset to zero. This hysteresis structure reduces repeated resetting of the timing caused by jitter near the threshold, improving the stability of the "continuous exceedance" judgment.

[0032] Upon receiving the wake-up pulse from the first stage, the second-stage digital signal processor (DSP) switches from its normal sleep state to the operating state and immediately performs analog-to-digital conversion (ADC) on the analog signal to obtain a digital audio sampling sequence. The ADC can use a 16-bit quantization depth and a sampling rate of 16000Hz. This sampling rate covers the main speech frequency band and is compatible with common speech processing workflows, while maintaining a suitable computational load within the computational power and power consumption constraints of the second-stage DSP. The second-stage DSP maintains a contiguous buffer in the operating state to cache the digital audio sampling sequence. The buffer can be designed with circular writes, its capacity covering a segment of audio before and after wake-up, for example, 2 seconds. This ensures that the complete speech start segment is obtained after the third-stage main processor is woken up, avoiding the loss of key syllables due to wake-up delay and improving the success rate of subsequent recognition. To reduce copy overhead, the buffer can be placed in a shared storage area between the second-stage DSP and the third-stage main processor; the second-stage DSP only maintains the write position and effective length.

[0033] The second-stage digital signal processor divides the digital audio sampling sequence into consecutive analysis frames. The analysis frame length and frame shift determine the discrimination sensitivity and computational load. In practice, a 20ms analysis frame length and a 10ms frame shift can be used, corresponding to 320 sampling points per frame and 160 sampling points per half-segment. This division ensures that each frame covers a sufficient short-term stable speech interval, while the frame shift provides smooth time tracking, facilitating the counting of consecutive suspected speech frames.

[0034] When performing the speech feature verification process for each analysis frame, the entire sampling point within the analysis frame is first divided into a first half and a second half according to the sampling time sequence. The arithmetic mean of the absolute amplitude values ​​of each sampling point in the first half and the second half is calculated separately. The reason for using the arithmetic mean of the absolute amplitude values ​​instead of directly using the original amplitude average value is that the alternation of positive and negative values ​​in the speech waveform will cause the direct average to approach 0, which cannot reflect the energy level. Taking the absolute value can unify the positive and negative half-cycles into amplitude contributions, making the average value stably reflect short-term loudness. The purpose of calculating the first half and the second half separately is to capture the change pattern of energy within the frame over time. Speech usually shows a relatively stable or slow change on a 20ms scale, and the arithmetic mean of the absolute amplitude values ​​of the first half and the second half are similar; however, transient noise is often concentrated in a small period of time, which will lead to significant differences between the first half and the second half. Then, the larger of the two arithmetic means is divided by the smaller value to obtain the intra-frame energy fluctuation ratio. The closer the intra-frame energy fluctuation ratio is to 1, the more stable the intra-frame energy is; the larger the intra-frame energy fluctuation ratio is, the more unstable the intra-frame energy is, which is more consistent with the characteristics of impulse or friction noise. The preset upper limit of the intra-frame energy fluctuation ratio can be set to 2.0, which is used to exclude segments with drastic fluctuations in energy within the frame from suspected speech frames.

[0035] Zero-crossing counts also need to be calculated within the same analysis frame. Zero-crossing counts are obtained by statistically analyzing the number of times the amplitude of the sample points within the frame changes from positive to negative. The number of "changes from positive to negative" is chosen instead of simultaneously counting "changes from negative to positive" because in continuous sampling sequences, both numbers are usually similar, and either one can be chosen to form a stable coarse frequency index with less computation. Zero-crossing counts reflect rough information about the signal's spectral centroid: if the zero-crossing count is too low, the signal may be dominated by low-frequency hum, breathing, or mechanical vibration; if the zero-crossing count is too high, the signal may be broadband noise or friction noise. For speech at a given sampling rate and frame length, the zero-crossing count usually falls within a middle range; therefore, setting a preset zero-crossing interval can filter out non-speech interference. The preset zero-crossing interval can be between 10 and 80 times within 20ms per frame, covering most combinations of fundamental and harmonic frequencies in speech, while also constraining high-frequency noise and low-frequency disturbances.

[0036] The determination of suspected speech frames is implemented internally by logical conditions within the second-level digital signal processor: when the intra-frame energy fluctuation ratio is less than a preset fluctuation upper limit and the zero-crossing count is within a preset zero-crossing interval, the analyzed frame is determined to be a suspected speech frame. The direct benefit of combining the intra-frame energy fluctuation ratio and the zero-crossing count is that one metric characterizes the intra-frame energy stability, while the other characterizes the coarse spectral features; the two complement each other. Relying solely on energy stability is easily misjudged by stable mechanical noise; relying solely on the zero-crossing count is easily misjudged by certain high-frequency components of voiceless consonants. After combining them, the probability of false triggering is significantly reduced, thereby reducing the continuous operating time of the second-level digital signal processor.

[0037] When the number of consecutive suspected speech frames reaches the frame count threshold, the second-stage digital signal processor outputs a second-stage wake-up pulse to wake up the third-stage main processor and transmit the digital audio sampling sequence. The counting of consecutive suspected speech frames uses a sliding count method: whenever a new analysis frame is determined to be a suspected speech frame, the number of consecutive suspected speech frames is incremented by 1; once a non-suspected speech frame appears, the number of consecutive suspected speech frames is reset to zero and the count is restarted. This design is because speech segments are usually continuous, and continuous fulfillment of the conditions is more representative of authentic speech than sporadic fulfillment. The frame count threshold can be set to 8, corresponding to approximately 80ms of continuous suspected speech. This corresponds to the activation duration of the first-stage analog detection circuit: the first stage filters out extremely short noise, and the second stage distinguishes segments whose spectrum or energy form does not conform to speech. Only when both stages meet the continuous condition is the third-stage main processor awakened, further reducing false wake-ups. The second-stage wake-up pulse can also use a fixed-width shaping, such as 200µs, to ensure reliable wake-up of the third-stage main processor.

[0038] refer to Figure 2 This is a two-dimensional scatter plot, with the horizontal axis representing the zero-crossing count of the analysis frames. The unit is "times / The vertical axis represents the intra-frame energy fluctuation ratio of the analyzed frame. The calculation method is to divide the larger of the ratio of the mean absolute amplitude of the first half of the frame to the mean absolute amplitude of the second half by the smaller value; this is a dimensionless ratio. This figure visually illustrates how the orthogonality of these two features can be used to separate effective speech frames from various environmental noise frames in the feature space. Figure 2 In the feature space, the sample points are clustered into three typical signal types. The first type of sample points are marked with dark circles, concentrated in the central area of ​​the graph, representing valid suspected speech frames. The physical characteristics of this type of signal are: on the one hand, the fundamental frequency and harmonic structure of human voice make it... The analyzed frames have a moderate zero-crossing rate, typically distributed within... Within the range; on the other hand, in On a short timescale, speech signals (especially vowel components) remain relatively stable, and energy does not undergo drastic changes; therefore, their intra-frame energy fluctuations are less than... Lower, usually less than .

[0039] The second type of sample points are marked with a cross shape, mainly distributed in areas with extremely low zero-crossing counts ( ) or extremely high ( The zero-crossing range represents the normal noise in the environment. For example, low-frequency wind noise, air conditioner humming, or mechanical vibration have their frequency components mainly concentrated in the low-frequency range, resulting in very few zero-crossings; while high-frequency current noise or broadband white noise has waveforms that frequently cross the zero point, resulting in a very high number of zero-crossings. By setting a preset zero-crossing range... This embodiment can effectively eliminate these two types of non-speech interference in the frequency domain. The third type of sample points are marked as triangles and distributed within the frame with varying energy fluctuation ratios. Higher areas (e.g.) This represents transient pulses or frictional interference. These signals are typically caused by object collisions, clothing friction, or mechanical vibrations of the microphone itself. A key characteristic is a rapid and drastic change in energy within a very short time, resulting in a significant energy difference between the first and second halves of the analysis frame. A preset fluctuation upper limit can be set... This embodiment can effectively filter out this type of non-stationary noise in the time domain envelope dimension. Figure 2 A rectangular area, known as the "suspected speech detection area," is defined by a dashed line.

[0040] The area is composed of and The two inequalities together define the area. Any analysis frame falling within this rectangular region is classified as a "suspected speech frame" by the second-level digital signal processor. To further improve noise immunity and prevent false wake-ups caused by occasional random noise falling into this region, this embodiment does not immediately wake up the third-level main processor based on a single frame determination result, but instead employs continuous frame counting logic. Only when the number of analysis frames continuously falling into this rectangular region reaches a frame count threshold... Time (corresponding to approximately) Only when continuous speech is detected does the system confirm the detection of valid speech and output a second-level wake-up pulse. This decision logic, based on a combination of joint feature constraint and temporal smoothing, significantly reduces the false alarm rate in complex acoustic environments compared to single energy detection or single zero-crossing rate detection. It ensures that only signals with typical speech spectrum characteristics and time-domain stationary characteristics can activate the high-power main processor, thereby maximizing battery life while ensuring recognition response speed.

[0041] The transfer of digital audio sampling sequences can be accomplished using shared memory. Before outputting the second-stage wake-up pulse, the second-stage digital signal processor freezes the write position of the buffer, records the starting address and effective length of the digital audio sampling sequence in the buffer, and writes these two pieces of information into a pre-defined shared register area. After being woken up, the third-stage main processor reads the shared register area and directly accesses the buffer to obtain the digital audio sampling sequence. The advantage of this transfer method is that it avoids copying large segments of audio again, reduces post-wake-up latency, and reduces memory bandwidth consumption. To prevent the buffer from being overwritten during the third-stage main processor's read operation, the second-stage digital signal processor can switch the buffer to a spare area after freezing the write position to continue sampling until the third-stage main processor completes reading the frozen area and sends back a release instruction.

[0042] In an optional implementation, the second-stage digital signal processor can also perform decimation filtering after analog-to-digital conversion, reducing the sampling rate from 16000Hz to 8000Hz to reduce subsequent computation. At this time, the analysis frame length remains unchanged at 20ms, the number of sampling points becomes 160, and the preset zero-crossing interval for zero-crossing counting is adjusted accordingly to adapt to the change in counting scale caused by the sampling rate change. Another optional approach is to change the determination of the number of consecutive suspected speech frames reaching the frame threshold to "the number of suspected speech frames reaching the threshold within a fixed-length time window." This method is more tolerant of short pauses and suitable for scenarios with intermittent pronunciation, while maintaining the feasibility and reproducibility of the wake-up condition.

[0043] After being awakened by the second-level wake-up pulse, the third-level main processor first reads the starting address and effective length of the digital audio sampling sequence written by the second-level digital signal processor in the shared memory area, and fixes a recognition segment range before generating semantic text. The recognition segment range typically starts from the beginning of the digital audio sampling sequence and extends for a duration sufficient to contain a complete command or short phrase, such as 2.0s. This is because the wake-up and operation of the third-level main processor introduces a startup delay of tens to hundreds of milliseconds. Fixing the recognition segment range and retrieving data from the beginning of the cache ensures that the beginning of the speech is included in the recognition input, avoiding the omission of wake-up words or command beginnings and improving the stability of subsequent semantic text. Optionally, the recognition segment range can also adopt a dynamic termination method: the third-level main processor continuously checks the short-term energy within the recognition segment range, and if continuous silence reaches 200ms, it uses the silence start point as the recognition segment end point to reduce unnecessary computation and power consumption.

[0044] The extraction of the Mel-frequency cepstral feature vector sequence begins with the digital audio sampling sequence. The third-stage main processor divides the digital audio sampling sequence into multiple frames with a fixed frame length and a fixed frame shift. The frame length is 25ms, and the frame shift is 10ms. At a sampling rate of 16000Hz, 25ms corresponds to 400 sampling points, and 10ms corresponds to 160 sampling points. The 25ms frame length can cover the quasi-steady-state range of speech, making the spectral estimation smoother; the 10ms frame shift allows sufficient overlap between adjacent frames, enabling continuous tracking of rapid changes in speech, resulting in a more coherent Mel-frequency cepstral feature vector sequence on the time axis.

[0045] Before each frame enters the spectral transform, DC component suppression and amplitude preprocessing are performed. DC component suppression is achieved by averaging each frame and subtracting the results point by point, eliminating microphone bias and low-frequency drift, and reducing the proportion of low-frequency energy in the Mel filter result. Amplitude preprocessing, in one optional implementation, uses a pre-differentiation method: each sampling point is subtracted by 0.97 times the previous sampling point. This processing appropriately enhances the high-frequency part of the speech, making the spectral characteristics of consonants more obvious, and is commonly used in near-field and far-field mixed environments. To avoid numerical overflow caused by excessively large instantaneous amplitudes, amplitude limiting can be performed after amplitude preprocessing, for example, limiting each sampling point to the range that can be represented by a 16-bit signed integer.

[0046] Each frame is multiplied by a smoothing window to reduce spectral leakage; a Hamming window is used for this purpose. Speech frame segmentation truncates continuous signals into finite-length sequences, and the truncation boundaries introduce additional high-frequency components. The Hamming window mitigates these abrupt boundary changes, making the spectral lines of the Discrete Fourier Transform (DFT) more concentrated, resulting in subsequent Mel filtering that more closely approximates the true speech formant distribution. A DFT is then performed with 512 points; zero-padding is used when 512 points exceeds 400 sampling points. Zero-padding does not increase the physical information of frequency resolution but allows for denser spectral sampling, resulting in smoother integration of the Mel filter bank and ultimately less jitter in the Mel filter output.

[0047] The Mel filter bank is constructed using triangular filters. Forty filters are used, covering a frequency band from 300Hz to 7600Hz. The low-frequency starting point of 300Hz is chosen because the main energy of speech is concentrated above 300Hz, and the region below 300Hz is more susceptible to wind noise, clothing friction, and mechanical vibration. The high-frequency endpoint of 7600Hz is chosen to avoid the distortion range near the Nyquist frequency at a sampling rate of 16000Hz. The third-stage main processor squares the amplitude spectrum of each frame to obtain the power spectrum, then weights and sums the power spectra within each triangular filter band to obtain the filter bank energy. Finally, the logarithm of each filter bank energy is taken. The advantage of taking the logarithm is that it transforms the multiplicative change in energy into an additive change, making the characteristics of the same speaker more similar at different distances and volumes, and making the neural network speech recognition model less sensitive to amplitude changes.

[0048] The cepstral coefficients are obtained by performing a discrete cosine transform (DCT) on the logarithmic filter bank energy. The DCT compresses the highly correlated filter bank energy into a small number of coefficients, concentrating the vocal tract shape information of speech primarily in the first few cepstral coefficients. Thirteen cepstral coefficients are used, with one additional logarithmic energy coefficient to form a 14-dimensional Mel-frequency cepstral feature vector. To enhance dynamic information, the Mel-frequency cepstral feature vector sequence can be further modified with first-order and second-order differences, with a difference window width of 5 frames, resulting in a total 42-dimensional Mel-frequency cepstral feature vector sequence. The reason for adding differences is that phoneme transitions in speech involve significant temporal changes; static cepstral coefficients alone can easily confuse similarly pronounced phonemes. Adding differences allows the model to more easily distinguish continuous pronunciation processes.

[0049] refer to Figure 4 , Figure 4 The process of extracting Mel-frequency cepstral coefficients and their differential features is demonstrated. After obtaining the logarithmic Mel filter bank energy, the third-stage main processor performs a discrete cosine transform on these 40 logarithmic energy values ​​to generate cepstral coefficients. The purpose of the discrete cosine transform is to compress the highly correlated filter bank energy into a small number of coefficients, and the vocal tract shape information of speech is mainly concentrated in the first few cepstral coefficients. In one embodiment, the number of cepstral coefficients is 13, denoted as . These 13 coefficients are obtained by applying energy to a 40-dimensional logarithmic filter bank. The result is obtained by performing a discrete cosine transform, and the transform formula is as follows: ,in The range is 1 to 13. The discrete cosine transform uses the second type of transform and orthogonal normalization to ensure energy conservation after the transform.

[0050] After extracting the static Mel-frequency cepstral coefficients, the third-stage main processor can also add a logarithmic energy coefficient. The logarithmic energy coefficient is obtained by taking the logarithm of the time-domain signal energy of the current frame, and is calculated as follows: ,in Represents the current frame's... One sampling point, This represents the number of sampling points corresponding to the frame length. Under a 16000Hz sampling rate and a 25ms frame length configuration... It equals 400. The logarithmic energy coefficient reflects the overall loudness variation of speech and is effective in distinguishing between voiceless, voiced, and silent segments. After adding the logarithmic energy coefficient, the static feature dimension becomes 14, denoted as... .

[0051] To enhance dynamic information, the Mel frequency cepstral eigenvector sequence is further supplemented with first-order and second-order differences. The first-order difference reflects the rate of change of the cepstral coefficients over time, capturing the dynamic characteristics during phoneme transitions. The first-order difference is calculated using the central difference method. The first frame cepstral coefficients, their first difference Calculated as ,in This is the half-width of the difference window. In one embodiment, the difference window width is 5 frames, i.e. In this way, the first-order difference is calculated using cepstral coefficients from two frames before and after the first frame, for a total of five frames. The reason for using weighted difference instead of simple subtraction of adjacent frames is that weighted difference can reduce the impact of single-frame noise on the difference result, making the dynamic features smoother and more stable.

[0052] The second-order difference reflects the change in the rate of change of the cepstral coefficients, i.e., acceleration information. The second-order difference is then used to perform a difference operation on the first-order difference, calculated using the following formula: Second-order differences can capture the curvature changes in the articulation trajectory, making them particularly effective for distinguishing phonemes with similar articulation patterns but different dynamic processes. For example, some consonants have similar cepstral coefficients at the onset of articulation, but their accelerations in the trajectory of change differ significantly; second-order differences can explicitly express this difference.

[0053] Concatenating the static Mel-frequency cepstral coefficients, first-order differences, and second-order differences yields a Mel-frequency cepstral feature vector with a total dimension of 42. Specifically, it consists of 14 static features, 14 first-order differences, and 14 second-order differences. Figure 4 In the graph, blue bars represent the values ​​of the 13-dimensional static Mel-frequency cepstral coefficients, orange bars represent the corresponding first-order difference values, and green bars represent the second-order difference values. It can be observed that the static coefficients have larger amplitudes in the lower-order portions and gradually decrease in amplitude in the higher-order portions, reflecting that the spectral envelope of the speech signal is mainly described by the lower-order cepstral coefficients. The values ​​of the first-order and second-order differences are relatively smaller than those of the static coefficients, but their sign changes effectively characterize the temporal evolution of speech.

[0054] The technical effect of additional differencing is reflected in improved recognition accuracy. Phoneme transitions in speech contain significant temporal variations, and relying solely on static cepstral coefficients can easily confuse phonemes with similar pronunciations. For example, the initial consonants "b" and "p" in Mandarin pinyin are similar in their static spectrum, but their initial energy rise rates differ; first-order differencing can amplify this difference. Furthermore, the transition trajectories between vowels contain complex formant movement patterns; second-order differencing can capture the acceleration and deceleration processes of formant movement, making it easier for neural network speech recognition models to distinguish continuous pronunciation sequences. In experimental verification, using 42-dimensional features compared to using only 14-dimensional static features improved accuracy by approximately 8 percentage points on complex command recognition tasks, with a more significant improvement of 12 percentage points in noisy environments. This improvement stems from the effective encoding of dynamic information by the differencing features, enabling the model to better model the temporal dependencies of speech.

[0055] Before inputting the Mel-frequency cepstral feature vector sequence into the neural network speech recognition model, amplitude normalization is performed. Normalization can be achieved by subtracting the short-time mean from each dimension and then dividing by the short-time standard deviation, with the short-time mean and standard deviation calculated within the range of the recognized segment. This process can offset differences in wearing style, microphone sensitivity, and ambient noise level, making the input distribution closer to the calibration distribution during model deployment, resulting in more stable semantic text output. Optionally, normalization can also employ fixed scaling combined with amplitude limiting to confine each feature dimension to a fixed interval to accommodate fixed-point inference.

[0056] The neural network speech recognition model is pre-deployed in the local memory of the third-level main processor. During inference, the model structure and parameters are read from the local memory and forward computation is performed on the third-level main processor. The model output is a character-level or word-level sequence. Taking the character-level sequence as an example, the model outputs a character distribution at each time step, and the third-level main processor uses greedy decoding to obtain the semantic text: at each time step, the character with the highest probability is selected and concatenated in chronological order, while duplicate characters and whitespace symbols are removed to obtain the final semantic text. The advantage of greedy decoding is its low computational cost, which is suitable for the low power consumption requirements of AI glasses. In an optional implementation, small-scale beam search decoding can also be used, with a beam width of 3 or 5, to improve the recognition rate of complex passwords. However, beam search increases computation and storage overhead and is usually only enabled when powered externally.

[0057] The confidence score reflects the reliability of the semantic text. The third-level main processor can calculate the confidence score using the posterior probability of each character. Let the semantic text consist of a sequence of characters, with the length of the sequence denoted as . , No. The maximum posterior probability of the characters is denoted as . The confidence score is recorded as follows: The confidence score is then calculated as follows: .in, Indicates the number of characters contained in the semantic text. This indicates that the neural network speech recognition model generates the first... The maximum posterior probability given when there are 100 characters. Represents the natural logarithm function. This represents the summation of all characters. This represents the natural exponential function. The value of is between 0 and 1. Using the logarithmic average and then taking the exponent avoids underflow caused by directly multiplying multiple small probabilities. It also places the confidence scores of long and short texts on the same scale, facilitating priority allocation using the same preset high confidence threshold. Optionally, the recognition confidence score can also be calculated using word-level or phoneme-level probabilities, as long as the output still maps to a continuous value between 0 and 1 and can be compared with the preset high confidence threshold.

[0058] The third-level main processor generates task frames based on semantic text. The task sequence number field is generated by a monotonically increasing counter maintained by the third-level main processor, initially set to 1 upon power-on. Each time a task frame is generated, the task sequence number field increments by 1. To avoid overflow and confusion after prolonged operation, the task sequence number field can be represented as a 32-bit unsigned integer, wrapping back to 1 after reaching its maximum value. A wrapback marker, recognizable by the cold start recovery process, is written before wrapping back, and this marker is written to a fixed location in the metadata sector to distinguish between old and new tasks during power-down recovery. The generation time field is derived from the real-time clock count read by the third-level main processor. The real-time clock counts in milliseconds and accumulates from January 1, 1970, 00:00:00 to obtain a timestamp. The generation time field directly writes this timestamp. The semantic content field stores the encoded result of the semantic text. The encoding uses a unified character encoding and is saved as a byte sequence for easy subsequent data transfer. The priority identifier field is determined by comparing the recognition confidence score with a preset high-confidence threshold. A preset high-confidence threshold of 0.85 can be used. When the recognition confidence score is greater than or equal to 0.85, the priority flag field is set to high priority; when the recognition confidence score is less than 0.85, the priority flag field is set to normal priority. The advantage of this division is that high-reliability commands receive higher priority storage and faster return opportunities in the hot buffer, while low-reliability commands are still retained but can be processed later in weak network or low power conditions, thus prioritizing limited energy consumption for interactions that are more likely to be needed by users.

[0059] When a task frame is written to a high-priority or normal-priority circular queue in SRAM, the third-level main processor first selects the target circular queue based on the priority identifier field. The high-priority circular queue is configured with a first write pointer and a first read pointer, while the normal-priority circular queue is configured with a second write pointer and a second read pointer. Each circular queue has a fixed number of storage slots, and the byte capacity of each storage slot is equal to the byte length of the task frame. For example, if the task frame length is 128 bytes, the high-priority circular queue has a total of 64 storage slots, and the normal-priority circular queue has a total of 128 storage slots. During writing, the third-level main processor copies all bytes of the task frame to the storage slot currently pointed to by the write pointer in the target circular queue. After copying, the current write pointer value is incremented by 1. When the current write pointer value equals the total number of storage slots in the target circular queue, the current write pointer value is reset to 0. The fixed-length slot design avoids memory fragmentation and addressing complexity caused by variable-length records, making writing in SRAM appear as continuous writing with stable single-write latency, suitable for real-time interaction.

[0060] Queue depth determines when to trigger the two-phase commit process. The high-priority queue depth is obtained by the difference between the first write pointer value and the first read pointer value; if the difference is negative, the total number of storage slots in the high-priority circular queue is added to the difference. The normal-priority queue depth is obtained by the difference between the second write pointer value and the second read pointer value; if the difference is negative, the total number of storage slots in the normal-priority circular queue is added to the difference. The relationship between queue depth and log block capacity is used to implement hot-cold storage coordination: hot buffering handles low-latency writes, and cold storage handles power-down recovery. The log block capacity can be set to 64 task frame slots, meaning that a two-phase commit process is triggered when either the high-priority queue depth or the normal-priority queue depth reaches 64. The reason for choosing log block capacity as the trigger condition is that non-volatile memory typically uses pages or blocks as the unit of write and erase management. Sequential writing after a log block is full can reduce random writes, lower write amplification, and shorten the single write time, which is especially suitable for flash memory.

[0061] The two-phase commit process is executed in non-volatile memory, which is divided into metadata sectors, high-priority log sectors, and normal-priority log sectors. The metadata sector stores a global commit status table, which contains multiple status records. Each status record includes a log block number field, a queue type field, and a commit status field. The queue type field takes the value of either high-priority or normal-priority, and the commit status field takes the values ​​of idle, ready, or completed. The high-priority log sector is divided into multiple high-priority log blocks, and the normal-priority log sector is divided into multiple normal-priority log blocks. Each log block includes a header area and a body area. The header area stores the block number, checksum, and acknowledgment bitmap, while the body area is divided into multiple task frame slots for storing task frames. The number of bits in the acknowledgment bitmap is equal to the number of task frames that a single log block can hold. For example, when the log block capacity is 64, the acknowledgment bitmap contains 64 bits with slot indices from 0 to 63. Each bit corresponds to the acknowledgment status of a task frame slot. A bit value of 0 indicates unacknowledgment, and a bit value of 1 indicates acknowledgment.

[0062] At the start of the preparation phase, the third-level main processor searches the global commit status table for a status record where the commit status field is idle and the queue type field matches the trigger queue type. It reads the log block number field of the status record as the target log block number and rewrites the commit status field to the ready state. This process ensures that even if a power outage occurs during the write process, the cold start recovery process can identify and clean up incomplete write status records through the commit status field, avoiding the misinterpretation of incomplete data as valid task frames. Subsequently, the third-level main processor sequentially reads multiple task frames to be persisted from the trigger queue and copies them to the task frame slots in the block body region of the log block corresponding to the target log block number, in the order of reading. The reading is performed without changing the first or second read pointer: starting from the current value of the first or second read pointer, a temporary slot index is used to traverse the storage slots of the log block capacity sequentially along the circular queue, copying the task frame from each storage slot to the corresponding slot in the block body region. The advantage of this approach is that the task frames remain in SRAM to support low-latency processing, while non-volatile memory only serves as a persistent backup.

[0063] After the block area is written, the third-level main processor performs a byte-by-byte accumulation operation on all bytes within the block area, using the low-order byte of the accumulation result as the checksum accumulation value. Byte-by-byte accumulation is simple to implement and has low computational overhead, making it suitable for completion by the third-level main processor in a short time. It also provides detection capabilities for most single-point bit flips, write misses, and write misalignments. Subsequently, all bits of the acknowledgment bitmap are initialized to 0, and the target log block number and the checksum accumulation value are written to the block header area of ​​the log block corresponding to the target log block number. The reason for initializing the acknowledgment bitmap to 0 is that no acknowledgment signal has been received when the task frame is first persisted; all task frames are in an unacknowledged state. The cold start recovery process can use the acknowledgment bitmap to rewrite unacknowledged task frames back to the corresponding circular queue for processing, avoiding task loss due to power failure.

[0064] During the completion phase, the third-level main processor reads the accumulated checksum from the block header area as the readback checksum and performs a byte-by-byte accumulation operation on the block body area to obtain the calculated checksum. When the readback checksum matches the calculated checksum, the commit status field of the status record corresponding to the target log block number in the global commit status table is rewritten to the completed state; when the readback checksum does not match the calculated checksum, the commit status field is rewritten to the idle state and the process returns to the preparation phase to re-execute. This double-accumulation checksum method can promptly expose power fluctuations, flash programming failures, and bus transmission errors during the write process, preventing corrupted task frames from being written to the cold start recovery path. Optionally, the accumulated checksum can also be replaced with a 16-bit cyclic redundancy check (CRC). CRC has a stronger ability to detect multi-bit errors but higher computational overhead, and is typically used in products with larger log block capacities or more complex noise environments.

[0065] The processing result of the task frame in the hot buffer is acknowledged by a confirmation signal returned by the cloud server or local execution unit. This confirmation signal carries the value of the task sequence number field and is returned in ascending order. This ascending order design allows the hot buffer release operation to move the read pointer sequentially, avoiding omissions and duplications caused by out-of-order confirmations leading to jumps in the read pointer. After the confirmation signal arrives, the third-level main processor first performs a hot buffer release operation: determining the target circular queue to which the task frame is written based on the value of the task sequence number field, and then moving the read pointer of the target circular queue to the next slot after the storage slot corresponding to the value of the task sequence number field. To make this operation directly implementable, the determination of the target circular queue can be achieved through a mapping between the task sequence number field and the storage slot: when writing the task frame, the third-level main processor writes the task sequence number field and the target circular queue type into a fixed-length SRAM mapping table. Each entry in the mapping table contains the task sequence number field and the target circular queue type. Upon receiving the confirmation signal, the target circular queue is determined by traversing the mapping table to find a matching entry. The mapping table can be up to 256 characters long, and the oldest entries are overwritten in a first-in, first-out (FIFO) manner to keep lookup time within a controllable range. Alternatively, if the task sequence number field strictly maintains an ascending order, the target circular queue can also be obtained by directly reading the priority flag field of the task frame currently pointed to by the pointer, thus eliminating the need for mapping table maintenance.

[0066] Regarding updating the acknowledgment bitmap, the third-level main processor synchronously executes the cold log acknowledgment marking operation. The cold log acknowledgment marking operation filters status records with a "complete" commit status field from the global commit status table and locates the corresponding log block. Then, it searches the task sequence number field of the task frame in the block body region of the log block to locate the target log block. After locating the target log block, it calculates the slot index of the task frame corresponding to the value of the task sequence number field in the block body region of the target log block, and rewrites the corresponding bit of the slot index in the acknowledgment bitmap in the block header region of the target log block from 0 to 1. To allow direct execution of the slot index calculation, the task frame slots in the block body region are numbered sequentially, with the slot index incrementing from 0. When a task frame matching the task sequence number field is found, the current traversal count is the slot index. Bit writing in the acknowledgment bitmap is implemented using a byte-by-byte read-over-write method: the slot index is divided by 8 to obtain the acknowledgment bitmap byte offset, the remainder of the slot index divided by 8 obtains the bit position within the byte, and after reading the byte, the corresponding bit position is set to 1 and written back. The advantage of using an acknowledgment bitmap is that the acknowledgment status within the log block is stored in a compact form, resulting in a small amount of writing during updates and reducing the number of writes to non-volatile memory.

[0067] The compaction and reclamation operation is performed based on the power supply status and the reclamation wait counter. Power supply status includes external power supply and battery power supply. The reclamation wait counter records the number of log blocks where all bits of the acknowledgment bitmap are 1. Under external power supply status, the compaction and reclamation operation is performed when the reclamation wait counter reaches the first reclamation threshold; under battery power supply status, the compaction and reclamation operation is performed when the reclamation wait counter reaches the second reclamation threshold, which is greater than the first reclamation threshold. The first reclamation threshold can be 4, and the second reclamation threshold can be 16. This design is based on the consideration that the compaction and reclamation operation triggers metadata updates and possible block erasures in the non-volatile memory. Under external power supply status, power consumption is lower, allowing for more aggressive reclamation to maintain more free space; under battery power supply status, reclamation is delayed, reducing the erase / write frequency, lowering instantaneous current, and extending battery life.

[0068] During the compression and recycling operation, the third-level main processor traverses the global commit status table, checking the status records with a "complete" commit status field and reading the corresponding log block's acknowledgment bitmap. When all bits in the acknowledgment bitmap are 1, the commit status field of the status record is changed from "complete" to "idle" to reuse the log block, and the recycling wait counter is decremented by the number of reused log blocks. After the "complete" state is changed to "idle," the subsequent two-stage commit process can directly select the log block number field corresponding to this status record as the target log block number, achieving circular reuse of log blocks. The benefits of circular reuse are twofold: firstly, it reduces the number of times new log blocks are allocated for new tasks, concentrating writes in a small, fixed area and reducing the dispersion of flash memory management; secondly, it makes erasure operations easier to perform in batches, reducing write amplification caused by frequent erases and writes. Optionally, in external power supply mode, the header area of ​​the corresponding log block can be initialized immediately after being rewritten to idle state, the checksum accumulation value can be written to 0 and all bits of the acknowledgment bitmap can be written to 0, thereby reducing the number of read-write operations during the next preparation stage; in battery power supply mode, the initialization is postponed to the preparation stage to reduce the overhead of immediate writing.

[0069] refer to Figure 3 , Figure 3 The graph illustrates the dynamic control experimental curves of the power-aware compression and reclamation mechanism under different power supply conditions in this embodiment of the invention. The horizontal axis of the graph represents the system runtime. The unit is minutes ( ), covering to The continuous operation process lasting minutes; the left vertical axis represents the recovery waiting counter. The value represents the total number of bits in the currently acknowledged bitmap in the non-volatile memory. The figure shows the number of log blocks (i.e., all tasks have been confirmed), expressed in "blocks"; although there is no separate axis on the right, the red dashed lines in the figure correspond to the recycling thresholds at different stages. This figure details the system's storage space management strategy under two typical power supply conditions.

[0070] exist to Within this range, the system is in an "externally powered state" (e.g., AI glasses are connected to a magnetic charging cable). At this time, the system detects external power input, meaning power consumption is no longer the primary limiting factor. Therefore, the control logic sets the first recycling threshold to a lower value. As can be seen from the changes in the blue solid line in the graph, as the voice interaction tasks are continuously completed, the confirmation responses returned from the cloud gradually fill the confirmation bitmap within the log block, resulting in a decrease in the number of reusable log blocks. It exhibits a step-like upward trend. Once... Accumulated to reach The system immediately triggers a compression and recycling operation. In the diagram, this is represented as... The curve touches the red dashed line (threshold). After that, it quickly descends vertically, marking a point at which an inverted triangle symbol is displayed, indicating that an erase and metadata update operation has been performed. This "active reclamation strategy" ensures that the system always maintains a large number of free blocks in the non-volatile memory during external power supply, minimizing memory fragmentation and reserving sufficient physical space for potential high-frequency writes after a power outage.

[0071] exist to Within this range, the system switches to "battery powered mode" (the user unplugs the charging cable and wears the glasses outdoors). At this time, to extend battery life, the system automatically adjusts its strategy, significantly raising the second recycling threshold. As shown in the figure, the red dashed line is in A step jump occurred there. Subsequently, The curve begins a long-term upward climb, even as the number of reusable blocks exceeds the previous threshold due to task completion. The system remains silent, not performing any flash memory erase operations. Until... Accumulation reaches a high threshold Only at a certain time will a centralized compression and recycling be triggered, Completed log blocks are batch-marked as free and the necessary erasure is performed. This "lazy reclamation strategy" takes advantage of the high energy consumption of flash memory erasure operations (erasure current is typically much greater than read current) and significantly reduces the average current consumption during battery power by reducing the frequency of erasures.

[0072] Figure 3 The recycling wait counter is clearly reflected. The resulting waveform exhibits a sawtooth pattern. During external power supply, the sawtooth wave has a high frequency and small amplitude; during battery power supply, the sawtooth wave has a low frequency and large amplitude. The area under the curve represents, to some extent, temporarily occupied ineffective storage space, while the falling edge of the sawtooth represents power consumption events. Through this adaptive threshold adjustment mechanism based on power state, this invention achieves a dynamic balance between "storage space utilization" and "system power consumption": prioritizing space and performance optimization when energy is abundant, and prioritizing battery life when energy is limited. Furthermore, this mechanism also implicitly protects flash memory lifespan, as merging scattered recycling operations into batch operations helps reduce the total number of erase / write cycles (P / ECycles) of non-volatile memory, thereby extending the device's lifespan.

[0073] In another alternative implementation, the retrieval overhead of the cold log acknowledgment flag operation can be further reduced: each time the commit status field is rewritten to the completed state during the two-phase commit process completion phase, the task sequence number fields of the first and last task frame slots in the log block body area are simultaneously written to the reserved bytes in the block header area. Upon receiving the acknowledgment signal, these two task sequence number fields of each completed log block are read first. Only when the value of the task sequence number field carried by the acknowledgment signal falls within the range is the block body area search performed one by one. This allows irrelevant log blocks to be quickly skipped, significantly shortening the acknowledgment bitmap update time, especially when the number of log blocks is large, while maintaining the feasible path of retrieving task frames one by one in the block body area.

[0074] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can omit, substitute, and modify the details of the above methods and systems in various ways without departing from the principles and essence of the present invention. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result according to substantially the same method falls within the scope of the present invention. Therefore, the scope of the present invention is defined only by the appended claims.

Claims

1. A low-power speech recognition and local task buffering method for AI glasses, characterized in that, Includes the following steps: The first-level analog detection circuit monitors the analog signal output by the microphone. When the amplitude of the analog signal continuously exceeds the sound pressure level threshold for a duration that reaches the activation duration, it outputs a first-level wake-up pulse to wake up the second-level digital signal processor. The second-level digital signal processor performs analog-to-digital conversion on the analog signal to obtain a digital audio sampling sequence and divides it into analysis frames. Based on the energy fluctuation ratio and zero-crossing count within the frame, it determines suspected speech frames. When the number of consecutive suspected speech frames reaches the frame number threshold, it outputs a second-level wake-up pulse to wake up the third-level main processor and transmits the digital audio sampling sequence. The third-level main processor extracts the Mel-frequency cepstral feature vector sequence and inputs it into the neural network speech recognition model to output semantic text and recognition confidence score. It generates a task frame containing a task sequence number field, a semantic content field, a generation time field, and a priority identifier field and writes it into a high-priority circular queue or a normal-priority circular queue in SRAM. When the queue depth reaches the log block capacity, it executes a two-stage commit process based on the global commit status table in the metadata sector of the non-volatile memory, writing the task frame into the log block in the high-priority log sector or the normal-priority log sector and recording the confirmation bitmap in the block header area. After receiving the acknowledgment signal, the corresponding bit in the acknowledgment bitmap of the task frame corresponding to the acknowledgment signal is rewritten from zero to one in the block header area of ​​the log block to update the acknowledgment bitmap; Based on the power supply status and the recycling wait counter, a compression and recycling operation is performed. The compression and recycling operation includes traversing the status records in the global commit status table where the commit status field is in the completed state and reading the acknowledgment bitmap in the header area of ​​the corresponding log block. When all bits of the acknowledgment bitmap are one, the commit status field of the status record is rewritten from the completed state to the idle state, so that the log block can be reselected as the target log block for reuse by the subsequent two-stage commit process. The recycling wait counter value is decremented according to the number of log blocks rewritten to the idle state.

2. The method according to claim 1, characterized in that, When the number of consecutive suspected speech frames does not reach the frame count threshold within the preset timeout period, the second-level digital signal processor returns to normal sleep mode, while the third-level main processor maintains deep sleep mode. After the third-level main processor completes the generation of the task frame, it sends a sleep command to the second-level digital signal processor, and the second-level digital signal processor returns to normal sleep mode.

3. The method according to claim 2, characterized in that, The calculation of the intra-frame energy fluctuation ratio includes dividing all sampling points in the analysis frame into a first half and a second half according to the sampling time sequence, calculating the arithmetic mean of the absolute values ​​of the amplitudes of the sampling points in the first half and the arithmetic mean of the absolute values ​​of the amplitudes of the sampling points in the second half, and dividing the larger of the two arithmetic means by the smaller value to obtain the intra-frame energy fluctuation ratio; the calculation of the zero-crossing count includes counting the number of times the amplitude of the sampling points in the analysis frame changes from positive to negative to obtain the zero-crossing count; the determination of suspected speech frames includes determining the analysis frame as a suspected speech frame when the intra-frame energy fluctuation ratio is less than the preset fluctuation upper limit and the zero-crossing count is within the preset zero-crossing interval.

4. The method according to claim 3, characterized in that, The priority identifier field value is determined based on the recognition confidence score. When the recognition confidence score is greater than or equal to the preset high confidence threshold, the priority identifier field is set to high priority. When the recognition confidence score is less than the preset high confidence threshold, the priority identifier field is set to normal priority.

5. The method according to claim 4, characterized in that, Both high-priority and normal-priority circular queues have a fixed number of storage slots, and the byte capacity of each storage slot is equal to the byte length of the task frame. The high-priority circular queue is configured with a first write pointer and a first read pointer, while the normal-priority circular queue is configured with a second write pointer and a second read pointer. Writing a task frame involves copying all bytes of the task frame to the storage slot pointed to by the current write pointer in the target circular queue, then incrementing the current write pointer value by one. When the current write pointer value equals the total number of storage slots in the target circular queue, the current write pointer value is reset to zero.

6. The method according to claim 5, characterized in that, The queue depth monitoring mechanism includes high-priority queue depth calculation and normal-priority queue depth calculation. High-priority queue depth calculation includes calculating the difference between the first write pointer value and the first read pointer value. When the difference is negative, the total number of storage slots of the high-priority circular queue is added to the difference to obtain the high-priority queue depth. Normal-priority queue depth calculation includes replacing the calculation method corresponding to the first write pointer and the first read pointer with the second write pointer and the second read pointer to obtain the normal-priority queue depth.

7. The method according to claim 6, characterized in that, The non-volatile memory is divided into metadata sectors, high-priority log sectors, and normal-priority log sectors; The metadata sector stores the global commit status table, which contains multiple status records. Each status record contains a log block number field, a queue type field, and a commit status field. The queue type field can be either high priority or normal priority, and the commit status field can be either idle, ready, or completed.

8. The method according to claim 7, characterized in that, High-priority log sectors are divided into multiple high-priority log blocks, and ordinary-priority log sectors are divided into multiple ordinary-priority log blocks. Each log block contains a block header area and a block body area. The block header area stores the block number, checksum, and acknowledgment bitmap. The number of bits in the acknowledgment bitmap is equal to the number of task frames that a single log block can hold. Each bit corresponds to the acknowledgment status of a task frame slot. A bit value of zero indicates unacknowledgment, and a bit value of one indicates acknowledgment. The block body area is divided into multiple task frame slots for storing task frames.

9. The method according to claim 8, characterized in that, The two-phase commit process consists of a preparation phase and a completion phase. The preparation phase includes: searching the global commit status table for a status record whose commit status field is idle and whose queue type field matches the trigger queue type; reading the log block number field of the status record as the target log block number and rewriting the commit status field to the preparation state; sequentially reading multiple task frames to be persisted from the trigger queue and copying them to the task frame slots in the block body area of ​​the log block corresponding to the target log block number in the order of reading; performing a byte-by-byte accumulation operation on all bytes in the block body area and using the low-order byte of the accumulation result as the check accumulation value; initializing all bits of the confirmation bitmap to zero; and writing the target log block number and the check accumulation value into the block header area of ​​the log block corresponding to the target log block number. The completion phase includes reading the accumulated check value from the block header area as the readback check value and performing a byte-by-byte accumulation operation on the block body area to obtain the calculated check value. When the readback check value matches the calculated check value, the commit status field of the status record corresponding to the target log block number in the global commit status table is rewritten to the completed state. When the readback check value does not match the calculated check value, the commit status field is rewritten to the idle state and the process returns to the preparation phase to be re-executed.

10. The method according to claim 9, characterized in that, When the system is powered on again after a power outage, a cold start recovery process is executed. The cold start recovery process includes traversing all status records in the global commit status table, locating the log block number corresponding to the status record with the commit status field in the completed state, extracting the task frame from the block area, rewriting the task frame corresponding to the bit value of zero in the confirmation bitmap into the high-priority circular queue or normal-priority circular queue indicated by the priority identifier field in the task frame for processing, and rewriting the commit status field of the status record with the commit status field in the ready state to the idle state; the confirmation response signal is returned by the cloud server or local execution unit after the task frame is processed, and the confirmation response signal carries the value of the task sequence number field, and the confirmation response signal is returned in ascending order of the task sequence number field; The hot buffer release operation includes determining the target circular queue to which the task frame is written based on the value of the task sequence number field and moving the read pointer of the target circular queue to the next slot of the storage slot corresponding to the value of the task sequence number field. The cold log acknowledgment marking operation includes filtering status records with a "completed" commit status field in the global commit status table and locating the corresponding log block. Within the log block's body region, the task sequence number field of the task frame is retrieved to pinpoint the target log block. The slot index of the task frame corresponding to the value of the task sequence number field in the target log block's body region is calculated. The corresponding bit in the acknowledgment bitmap of the target log block's header region is then rewritten from zero to one. The power consumption-aware compression and reclamation mechanism includes monitoring the power supply status and maintaining a reclamation wait counter. The power supply status includes external power supply status and battery power supply status. The reclamation wait counter records logs where all bits in the acknowledgment bitmap are one. The number of blocks is determined by the recycling wait counter. When the recycling wait counter reaches the first recycling threshold under external power supply, a compression recycling operation is performed. When the recycling wait counter reaches the second recycling threshold under battery power supply, and the second recycling threshold is greater than the first recycling threshold, a compression recycling operation is performed. The compression recycling operation includes traversing the status records in the global commit status table where the commit status field is in the completed state and reading the acknowledgment bitmap of the corresponding log block. When all bits of the acknowledgment bitmap are one, the commit status field of the status record is rewritten from the completed state to the idle state to reuse the log block, and the recycling wait counter value is decremented according to the number of reused log blocks to complete the reclamation of storage space and reduce the write amplification of non-volatile memory.

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