Memory controller and oversampled memory I / O

Abstract

A memory controller in an integrated circuit system includes a receive circuit that performs oversampling over time and voltage. The receiving circuit receives, from the storage module through the data channel, a data signal having N signal levels modulated by pulse amplitude modulation (PAM), where Ngt; 2. The receiving circuit generates K samples by sampling a data signal by a sequence of time points within a unit time interval. The receive circuit generates R signal level estimates from the same one of the K samples using the R voltage comparator blocks. The voltage comparator blocks compare the same sample to (N-1) voltage thresholds, and different offsets are configured for different voltage comparator blocks. The receiving circuit identifies one of N signal levels to which the data signal is mapped, based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.

Description

[0001] Cross-referencing

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 702,615, filed October 2, 2024, and U.S. Provisional Application No. 63 / 702,607, filed October 2, 2024, the entire contents of which are incorporated herein by reference. [Technical Field]

[0003] Embodiments of the present invention relate to memory controllers and memory input / output technologies in integrated circuit systems. [Background Technology]

[0004] Modern storage controllers support efficient, low-latency data transfer between processors and storage devices. The storage controller translates and coordinates high-level storage access requests from the processor into low-level electrical signals for reading or writing to memory. Based on the storage access request, the storage controller determines which row and column in the storage cell array to access.

[0005] The storage controller also schedules storage I / O commands from the processor according to timing rules, such as read, write, activation (row access), precharge (row close), and flush. Furthermore, the storage controller performs timing management and read / write data buffering to manage data rate or timing differences between the processor and memory.

[0006] Modern high-speed storage I / O requires storage controllers to handle large amounts of data transfer at high frequencies. High data rates can lead to signal integrity issues. Noise, distortion, crosstalk, and inter-symbol interference become significant problems that can corrupt data. A powerful transceiver is needed to maintain signal integrity. Storage controller designs are constantly evolving to support faster, larger, and more energy-efficient computing. The requirements for storage controllers in terms of timing, power consumption, and reliability are continuously increasing. Therefore, further improvements to storage controller technology are necessary. [Summary of the Invention]

[0007] In one embodiment, a method is performed by a receiving circuit of a memory controller in an integrated circuit system. The method includes receiving a data signal having N signal levels, which are integers greater than 2, modulated by pulse amplitude modulation (PAM), from a memory module through a data channel. The method further includes generating K samples by sampling the data signal as a time point sequence within a unit time interval, where K is an in-phase oversampling factor; and generating R signal level estimates from the same sample using R voltage comparator blocks. The R voltage comparator blocks compare the same sample with (N-1) voltage thresholds, with different offsets for different voltage comparator block configurations, where R is a quadrature phase oversampling factor. The method further includes identifying one of the N signal levels to which the data signal is mapped based on all signal level estimates generated from the K samples; and outputting a symbol corresponding to the identified signal level.

[0008] In another embodiment, the memory controller in the integrated circuit system includes a transmit module for sending outgoing data to the memory module and a receive module containing multiple receive circuits for receiving incoming data. The incoming data is PAM modulated, has N signal levels, and is transmitted from the memory module through multiple data channels, where N is an integer greater than 2. Each receive circuit includes K samplers that sample a time-point sequence of the data signal received on the data channel within a unit time interval to generate K samples, where K is an in-phase oversampling factor. Each signal level detector includes R voltage comparator blocks, where R is a quadrature phase oversampling factor. The R voltage comparator blocks operate to compare one of the K samples with (N-1) voltage thresholds, with different offsets configured for different voltage comparator blocks, thereby generating R signal level estimates. Each receive circuit further includes a decision circuit. The decision circuit identifies one of the N signal levels to which the data signal is mapped, based on all signal level estimates generated from the K samples, and outputs a symbol corresponding to the identified signal level.

[0009] Other aspects and features will become apparent in the detailed description of the embodiments taken in conjunction with the accompanying drawings. [Attached Image Description]

[0010] The invention is illustrated in the accompanying drawings by way of example rather than limitation, wherein like reference numerals denote similar elements. It should be noted that different references to "a" or "an embodiment" in this specification do not necessarily refer to the same embodiment, and these references imply at least one. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, the submitter believes that a person skilled in the art would be able to implement such a feature, structure, or characteristic in other embodiments, whether or not it is explicitly described.

[0011] Figure 1 This is a block diagram illustrating an integrated circuit system that may operate according to an embodiment of the present invention.

[0012] Figure 2 This is a block diagram illustrating the Rx module in a storage controller according to one embodiment.

[0013] Figure 3 It is a block diagram illustrating the Rx circuitry for each data channel according to one embodiment.

[0014] Figure 4 This is a block diagram illustrating a signal level detector according to one embodiment.

[0015] Figure 5A This is a block diagram illustrating a signal quality monitor that operates according to one embodiment to monitor the quality of a received signal.

[0016] Figure 5B This is a block diagram illustrating a control circuit that operates according to one embodiment to control the amount of oversampling.

[0017] Figure 6 It is a flowchart illustrating a method performed by a storage controller according to one embodiment.

[0018] Figure 7A , Figure 7B , Figure 7C and Figure 7D This describes storage controllers connected to different types of storage modules according to some embodiments.

Detailed Implementation Methods

[0019] Numerous specific details are set forth in the following description. However, it should be understood that embodiments of the invention can be performed without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail so as not to affect the understanding of this description. However, those skilled in the art will understand that the invention can be performed without these specific details. Those of ordinary skill will be able to implement appropriate functionality without improper experimentation based on the included description.

[0020] This disclosure describes a receiving circuit in a memory controller that can oversample received signals from the memory module in both the time and voltage domains. In one embodiment, the memory controller communicates with the memory module using pulse amplitude modulation (PAM) with multiple signal levels. The order of PAM refers to the number of different signal levels represented by a symbol transmitted using PAM. For example, "PAM-N" means using N signal levels to represent a symbol transmitted using PAM. Higher-order PAM means a larger value for N. Using higher-order PAM means transmitting more bits per symbol, thereby increasing throughput without increasing the symbol rate. For the same bit rate, higher-order PAM allows for a slower symbol rate, thus reducing inter-symbol interference and crosstalk.

[0021] However, there are trade-offs in increasing the order of PAM. As the number of signal levels increases, the amplitude difference between each level decreases, resulting in a smaller eye diagram opening. Due to the smaller eye diagram opening, the signal-to-noise ratio (SNR) requirement increases significantly with higher-order PAM. To improve the SNR of higher-order PAM signals received by the memory controller, the receiving circuitry in the memory controller oversamples the received signal. Oversampling can be performed in time to prevent voltage noise. Alternatively, oversampling can be performed across multiple voltage levels to prevent timing noise. Time-based oversampling is called "in-phase" or "I-phase" oversampling, and voltage-based oversampling is called "quadrature-phase" or "Q-phase" oversampling. In the following description, specific PAM orders are mentioned, such as PAM-4, PAM-8, PAM-16, etc. It should be understood that the disclosed memory controller is not limited to the specific PAM mentioned herein.

[0022] In one embodiment, the receiving circuitry in the storage controller can turn I-phase or Q-phase sampling on and off according to the channel conditions during operation. The receiving circuitry can be a matched receiver or an unmatched receiver.

[0023] Figure 1 This is a block diagram illustrating an integrated circuit system 100 (“System 100”) capable of operating embodiments of the present invention. System 100 includes a processor 110 coupled to a memory controller 130. When instructed by the processor 110, the memory controller 130 reads from and writes to a memory module 120. The memory module 120 includes a memory cell array 122 for data storage. In one embodiment, the memory controller 130 may be located on the same chip as the processor 110, while the memory module 120 may be located off-chip. In another embodiment, the memory controller 130, the processor 110, and the memory module 120 may all be located on the same chip.

[0024] although Figure 1 A processor 110 is shown, but it should be understood that system 100 may include multiple processors, each of which may include one or more processing cores or computing units. Non-limiting examples of processor 110 include a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a neural processing unit (NPU), and any processing unit that uses a storage controller to access storage module 120.

[0025] The storage controller 130 includes one or more transmit (Tx) modules 150 and one or more receive (Rx) modules 170, as well as other components. The Tx modules 150 and Rx modules 170 communicate with the storage module 120 to write to and read from the storage cells 122 of the storage module 120.

[0026] Figure 2 This is a block diagram illustrating further details of an Rx module 170 according to one embodiment. The Rx module 170 includes a plurality of Rx circuits 270, each receiving a data signal (ds) on a corresponding data channel. In one embodiment, the storage module 120 may transmit a timing signal (ts) accompanying the data signal as a timing reference. In another embodiment, the storage controller 130 may use its internal clock signal as a timing reference. In one embodiment, there are m data channels between the storage controller 130 and the storage module 120, and the Rx module 170 includes m receive (Rx) circuits 270 to receive and process m data signals from the storage module 120. Each receive circuit 270 detects the signal level of the data signal in each unit time interval based on a corresponding timing signal. The detected signal level is mapped to a bit group representing a symbol (sb) and sent to the processor 110. In one embodiment, the detected signal level may be mapped to a Gray code bit group. For PAM-4, there are 4 signal levels, with each symbol containing 2 bits; for PAM-8, there are 8 signal levels, with each symbol containing 3 bits; for PAM-16, there are 16 signal levels, with each symbol containing 4 bits, and so on.

[0027] Figure 3This is a block diagram illustrating one embodiment of a receiver circuit 270. The receiver circuit 270 includes other circuit components, one of which is an equalizer and gain amplifier circuit (“EQ_GA 375”) for compensating for signal loss and distortion along the receive path. An example of the EQ_GA375 might include a voltage gain amplifier (VGA) and a continuous-time linear equalizer (CTLE). Figure 3 The location of EQ_GA 375 is illustrative only and not limiting. In one embodiment, the receiving circuit 270 receives a data signal (ds) and a timing signal (ts) from the storage module 120. In embodiments where the storage module 120 is a dual data rate (DDR) or DDR-based storage module, an example of the data signal and timing signal might be DQ and DQS, respectively.

[0028] In one embodiment, the receiving circuit 270 includes a series of samplers 320, each sampler sampling the received data signal in a sequence of time points within a unit time interval. The time points can be uniformly distributed in time. Alternatively, the spacing between any two adjacent time points can be programmable. As a non-limiting example, the timing signal channel may include a delay tap 326 of a delay chain. Each sampler 320 receives timing input from a corresponding interpolator 325. The interpolator 325 performs weighted interpolation on timing signals with different delays to generate a fine-grained delayed timing signal aligned with the data sampling time of the corresponding sampler 320. The weights used by each interpolator 320 for timing signal interpolation are programmable. By programming the weights, the spacing between any two adjacent time points of the data sampling can be programmed.

[0029] The output of sampler 320 is a series of samples sp_1, sp_2, ..., sp_K, where K is the number of samplers 320 in the sequence. Therefore, in-phase oversampling is achieved by oversampling the data signal by a factor of K through sampler 320.

[0030] In one embodiment, each sample is sent to a signal level detector 340, which includes R voltage comparator blocks 330. Each voltage comparator block 330 includes (N-1) comparators 310 for comparing the voltage level of the sample with (N-1) voltage thresholds, where N is the order of PAM and is greater than 2. The output of each voltage comparator block 330 is a signal level estimate corresponding to a bit group (i.e., a symbol) of log2(N) bits.

[0031] Each voltage comparator block 330 generates a signal level estimate. Different voltage comparator blocks 330 use different voltage thresholds for their corresponding comparators 310. Quadrature phase oversampling is achieved by oversampling the data samples by a factor of R through the signal level detector 340. More details about quadrature phase oversampling will be discussed later. Figure 4 Provided by China.

[0032] Since there are K signal level detectors 340 and each signal level detector 340 generates R signal level estimates, the total number of signal level estimates for the data signal on the data channel within a unit time interval is (R x K). The decision circuit 350 in the receiving circuit 270 identifies a signal level based on (R x K) signal level estimates and maps the identified signal level to a symbol (i.e., a bit group). The deserializer 372 converts the bit groups of the incoming high-speed serial data stream into parallel data for further processing by downstream circuit components. The processed data may be forwarded to the processor 110 (… Figure 1 Previously stored in read queue 312.

[0033] For example, the identified signal level might be the signal level estimate with the most votes, i.e., the most repeated signal level estimate among a total of (R x K) signal level estimates. As another example, the identified signal level might be a signal level estimate that is equal to or closest to the average or weighted average of the total (R x K) signal level estimates. Decision circuit 330 might use a weighted average to emphasize certain signal level estimates over others. In some embodiments, decision circuit 350 might assign a weight to each of the R x K signal level estimates. For example, a signal level estimate generated from one of the K samplers 320 or by one of the R voltage comparator blocks 330 might be assigned a higher weight than one or more other signal level estimates within the same unit time interval.

[0034] Figure 4 This is a block diagram illustrating one of a signal level detectors 340 according to one embodiment. (Refer to...) Figure 3, each sampler 320 outputs a data sample to a corresponding signal level detector 340. Each signal level detector 340 includes R voltage comparator blocks 330. For simplicity of illustration, in the example, R = 3 is shown, and the three voltage comparator blocks are labeled 330-1, 330-2, and 330-3 (collectively referred to as voltage comparator blocks 330). It can be understood that R can be any positive integer. Each voltage comparator block 330 includes (N - 1) comparators 310 that respectively compare the data sample with (N - 1) voltage thresholds, where N is the order of the PAM for storing I / O and is greater than 2. In the example of PAM-4, the voltage level (v) of the data sample is compared with 3 voltage thresholds (e.g., VT1, VT2, and VT3) that define the 4 signal levels of PAM-4 (e.g., v < VT1, VT1 < v < VT2, VT2 < v < VT3, and v > VT3). Through in-phase oversampling and / or quadrature phase oversampling, higher-order PAMs such as PAM-8 or PAM-16 can be used. In the cases of PAM-8 and PAM-16, the voltage level of the data sample is compared with 7 voltage thresholds and 15 voltage thresholds respectively.

[0035] Quadrature phase oversampling is implemented by R voltage comparator blocks 330. Each voltage comparator block 330 includes (N - 1) comparators 310. In Figure 4 it, each comparator 310 is represented as C[VT

[0037] , Figure 5A , +offset], where VT represents the voltage threshold, i is an index from 1 to (N - 1), and offset can be a positive number, a negative number, or zero. The comparators 310 in the same voltage comparator block 330 are configured with the same offset. Different voltage comparator blocks 330 are configured with different offsets. In one embodiment, the offsets of the voltage comparator blocks 330 in the same signal level detector 340 can be evenly spaced. For example, the offset of voltage comparator block 330-1 is -D, the offset of voltage comparator block 330-2 is zero, and the offset of voltage comparator block 330-3 is D. In some embodiments, the offset of each voltage comparator block 330 can be programmed individually.

[0036] Therefore, the data sample undergoes R x (N - 1) comparisons and generates R signal level estimates. The decision circuit 350 collects the R signal level estimates of each of the K samples in each unit time interval and determines the symbol output.

[0037] Figure 5AThis is a block diagram illustrating the operation of a signal quality monitor 510 according to one embodiment to monitor the quality of a received signal. In this embodiment, the storage controller 130 includes a signal quality monitor 510 for monitoring the received signal quality (e.g., noise level or signal-to-noise ratio SNR) for each data channel, which may include data signal quality and timing signal quality. Based on the received signal quality, oversampling (OS) control circuitry 520 in the storage controller 130 can dynamically adjust the in-phase and quadrature phase oversampling amounts in the receive circuitry 270 of each data channel. See also Figure 3 When the noise level of the data signal is below a threshold, the oversampling control circuit 520 can disable one or more samplers 320 (and corresponding signal level detectors 340) and / or one or more voltage comparator blocks 330 to reduce the amount of oversampling. The signal level detector 340 that receives data samples from a given sampler 320 is the "corresponding signal level detector 340" for that sampler 320. For a substantially noise-free data path, the oversampling control circuit 520 can activate only one sampler 320, one signal level detector 340, and one voltage comparator block 330 within that signal level detector 340. When the noise level is above a threshold, the oversampling control circuit 520 can activate additional samplers 320 and / or voltage comparator blocks 330 to increase the amount of oversampling. In one embodiment, each sampler 320 and signal level detector 340 is power-gated. Activating and deactivating the sampler 320 and the corresponding signal level detector 340 means turning the power supply on and off the sampler 320 and the signal level detector 340, respectively.

[0038] Figure 5B This is a block diagram illustrating the operation of oversampling control circuitry 520 according to one embodiment to control the amount of oversampling. Oversampling control circuitry 520 can selectively activate and deactivate one or more samplers 320 and corresponding signal level detectors 340. For example, samplers 320-1, 320-2, ..., 320-K (collectively referred to as samplers 320) correspond to signal level detectors 340-1, 340-2, ..., 340-K (collectively referred to as signal level detectors 340), respectively. Oversampling control circuitry 520 can adjust the in-phase oversampling factor K and / or the quadrature-phase oversampling factor R according to the quality of the received signal. In some embodiments, oversampling factors K and R can be reduced when power consumption needs to be reduced.

[0039] In one embodiment, the oversampling control circuit 520 generates a control signal ctrl_K for each sampler 320 and signal level detector 340 to control the in-phase oversampling factor K. When voltage noise increases, the oversampling control circuit 520 can activate more K samplers 320 and corresponding signal level detectors 340. When voltage noise decreases, the oversampling control circuit 520 can deactivate some samplers 320 and corresponding signal level detectors 340. In low-noise or noise-free conditions, all samplers 320 may be deactivated except for one sampler 320 (and its corresponding signal level detector 340); that is, in-phase oversampling may be deactivated.

[0040] In one embodiment, the oversampling control circuit 520 generates a control signal ctrl_R to each signal level detector 340 to control the quadrature phase oversampling factor R. When timing noise increases, the oversampling control circuit 520 may activate more R voltage comparator blocks 330 in each signal level detector 340. When timing noise decreases, the oversampling control circuit 520 may deactivate one or more voltage comparator blocks 330 in each signal level detector 340. In low-noise or noise-free conditions, all voltage comparator blocks 330 except for one voltage comparator block 330 in each signal level detector 340 may be deactivated; that is, quadrature phase oversampling may be deactivated. In one embodiment, each voltage comparator block 330 is power-gated. Activating and deactivating a voltage comparator block 330 means turning the power supply to the voltage comparator block 330 on and off, respectively. In one embodiment, the decision circuit 350 may adjust the weights of the signal level estimation (if used) based on the quality of the received signal.

[0041] Figure 6 This is a flowchart illustrating method 600 performed by a receiving circuit of a memory controller in an integrated circuit system, according to one embodiment. An example of the receiving circuit could be receiving circuit 270. Figure 3Method 600 begins at step 610, whereby, when the receiving circuit receives a data signal from a storage module in the integrated circuit system via a data channel, the data signal is modulated into pulse amplitude modulation (PAM) with N signal levels, where N is an integer greater than 2. At step 620, the receiving circuit generates K samples by sampling the data signal using a time point sequence within a unit time interval, where K is an in-phase oversampling factor. At step 630, the receiving circuit uses R voltage comparator blocks to generate R signal level estimates from the same sample from the K samples. The R voltage comparator blocks compare the same sample with (N-1) voltage thresholds, with different offsets for different voltage comparator block configurations, where R is a quadrature phase oversampling factor. At step 640, based on all voltage level estimates generated from the K samples, the receiving circuit identifies one of the N signal levels to which the data signal is mapped, and at step 650, outputs a symbol corresponding to the identified signal level.

[0042] Step 630 is performed for each K samples. In one embodiment, the receiving circuit generates K sets of R signal level estimates from the K samples, and generates a total of (K x R) signal level estimates within the unit time interval. In one embodiment, the identified signal level is the most repetitive signal level among all signal level estimates. In another embodiment, the decision circuit in the storage controller calculates the average of all signal level estimates and identifies the signal level that is equal to or closest to the average among all signal level estimates. In yet another embodiment, the signal level estimates can be weighted. The decision circuit assigns a weight to each signal level estimate, calculates a weighted average of all signal level estimates, and identifies the signal level that is equal to or closest to the weighted average among all signal level estimates.

[0043] In one embodiment, the offset and the spacing between time points can be programmable. In one embodiment, when the receiving circuit receives an indication of the signal quality of the received signal, the receiving circuit activates or deactivates one or more samplers sampling K samples based on the signal quality to increase or decrease the in-phase oversampling factor K. In one embodiment, the signal quality can be indicated by the voltage noise level in the data signal. In one embodiment, when the receiving circuit receives an indication of the signal quality of the received signal, the receiving circuit activates or deactivates one or more of R voltage comparator blocks based on the signal quality to increase or decrease the quadrature oversampling factor R. In one embodiment, the signal quality can be indicated by the timing noise level in the timing signal accompanying the data signal. In one embodiment, the data signal is modulated as PAM-8. In another embodiment, the data signal is modulated as PAM-16.

[0044] Figures 7A-7DThe illustration shows the storage controller 130 connected to different types of storage modules, according to some embodiments. Figure 7A The display memory controller 130 is connected to one or more memory chips 710. The memory chips 710 can be manufactured using any known manufacturing technology and can communicate with the memory controller 130 according to any known memory I / O protocol. For example, the memory chip 710 can be Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Ferroelectric RAM (FeRAM), Phase-Change Memory (PCM), etc. Figure 7B In this configuration, the memory controller 130 communicates with a high-bandwidth memory (HBM) module 720, which includes memory chips arranged in a vertically stacked manner and accessed via a through-silicon via (TSV) 721. The memory controller 130 and the HBM module 720 may coexist on a substrate chip 723, which sits above an interposer and a substrate 725. It should be noted that stacked memory technology is not limited to the HBM module 720. The memory controller 130 described above can operate with memory stacks formed by other memory technologies, such as a low-power dual data rate (LPDDR) memory stack. In one embodiment, the LPDDR memory chips can be vertically stacked via wire bonding, with the bottom LPDDR chip wire-bonded to a package substrate. Alternatively, the LPDDR memory stack can be packaged in a single package. Figure 7C The display memory controller 130 communicates with a DDR-based memory chip 730, such as a DDR4, DDR5, DDR6, LPDDR, or graphics DDR (GDDR) memory chip. The memory controller 130 and the DDR-based memory chip 730 can coexist on the same package substrate 735. Alternatively, the DDR-based memory chip 730 can be packaged separately from the memory controller 130. Figure 7D The display storage controller 130 communicates with a DIMM 740 containing multiple storage chips. The storage controller 130 and the dual-line storage module DIMM 740 can coexist on the same printed circuit board (PCB) 745. Figures 7A-7D The storage controller 130 performs the oversampling operation described above. More specifically, Figures 7A-7D The storage controller 130 in the middle executes method 600 ( Figure 6 ).

[0045] Figure 6 Flowchart operations have been combined Figure 1-4 Exemplary embodiments of 5A, 5B, and 7 are described. However, it should be understood that... Figure 6 The flowchart operations can be performed by other embodiments of the present invention, and are not limited to those described herein. Figure 1-4The embodiments 5A, 5B, and 7 are provided, and these embodiments may perform operations different from those discussed in the reference flowchart. Although Figure 6 The flowchart illustrates a specific sequence of operations performed in certain embodiments of the present invention, but it should be understood that such sequence is exemplary (e.g., alternative embodiments may perform operations in a different order, combine certain operations, overlap certain operations, etc.).

[0046] This document describes various functional components or modules. As those skilled in the art will understand, functional modules are best implemented by circuitry (whether dedicated circuitry or general-purpose circuitry operating under the control of one or more processors and coded instructions), which typically includes transistors configured to operate according to the functional and operational control circuitry described herein.

[0047] While the invention has been described through several embodiments, those skilled in the art will recognize that the invention is not limited to the described embodiments and that modifications and alterations can be made within the spirit and scope of the appended claims. Therefore, the description should be considered illustrative rather than restrictive.

Claims

1. A method for a receiving circuit of a memory controller in an integrated circuit system, comprising: Receive data signals with N signal levels modulated by pulse amplitude modulation (PAM), which are integers greater than 2, from the storage module of the integrated circuit system through the data channel; K samples are generated by sampling the data signal through a time point sequence within a unit time interval, where K is the in-phase oversampling factor. R signal levels are estimated from the same sample from the K samples by using R voltage comparator blocks, where the same sample is compared with (N-1) voltage thresholds by the R voltage comparator blocks, different offsets are configured for different voltage comparator blocks, and R is the quadrature phase oversampling factor; Based on all signal level estimates generated from the K samples, one of the N signal levels is identified, and the data signal is mapped to that signal level. Output the symbol corresponding to the identified signal level.

2. The method of claim 1, wherein generating the R signal level estimates further comprises: Generate K sets of R signal level estimates from these K samples; A total of (K x R) signal level estimates are generated within this unit time interval.

3. The method of claim 1, wherein identifying one of the N signal levels further comprises: Identify the signal level that is most repeated among all signal level estimates.

4. The method of claim 1, wherein identifying one of the N signal levels further comprises: Calculate the average of all the signal level estimates; Identify the signal level that is equal to or closest to the average value among all signal level estimates.

5. The method of claim 1, wherein identifying one of the N signal levels further comprises: Assign a weight to each of all signal level estimates; Calculate the weighted average of all the signal level estimates; Identify the signal level that is equal to or closest to the weighted average among all signal level estimates.

6. The method of claim 1, wherein the offset and the interval between the time points are programmable.

7. The method of claim 1, further comprising: An indication of the quality of the received signal; Based on the signal quality, one or more samplers that sample the K samples are activated or deactivated to increase or decrease the in-phase oversampling factor K.

8. The method of claim 1, further comprising: An indication of the quality of the received signal; Based on the signal quality, activate or deactivate one or more of the R voltage comparator blocks to increase or decrease the quadrature oversampling factor R.

9. The method of claim 1, wherein the data signal is modulated as PAM-8.

10. The method of claim 1, wherein the data signal is modulated as PAM-16.

11. A memory controller in an integrated circuit system, comprising: A transmitting module is used to send external data to the storage module of the integrated circuit system; A receiving module, comprising multiple receiving circuits, for receiving incoming data modulated by pulse amplitude modulation (PAM) with N signal levels, which are integers greater than 2, from the storage module through multiple data channels. Each receiving circuit includes: Multiple (K) samplers sample the data signal received on the data channel within a unit time interval to generate K samples, where K is the in-phase oversampling factor; Multiple (K) signal level detectors receive the K samples respectively, wherein each signal level detector includes multiple (R) voltage comparator blocks, where R is an orthogonal phase oversampling factor, wherein the R voltage comparator blocks operate to compare the same of the K samples with (N-1) voltage thresholds, and different offsets are configured for different voltage comparator blocks, thereby generating R signal level estimates; A decision circuit identifies one of the N signal levels to which the data signal is mapped, estimates based on all signal levels generated from the K samples, and outputs a symbol corresponding to the identified signal level.

12. The memory controller of claim 11, wherein the K signal level detectors are further operated to: Generate K sets of R signal level estimates from these K samples; A total of (K x R) signal level estimates are generated within this unit time interval.

13. The memory controller of claim 11, wherein the decision circuit further operates to: Identify the most recurring signal level among all signal level estimates.

14. The memory controller of claim 11, wherein the decision circuit further operates to: Calculate the average of all signal level estimates; and Identify the signal level that is equal to or closest to the average value among all signal level estimates.

15. The memory controller of claim 11, wherein the decision circuit further operates to: Assign weights to all signal level estimates; Calculate the weighted average of all signal level estimates; and Identify a signal level that is equal to or closest to the weighted average among all signal level estimates.

16. The memory controller of claim 11, wherein the spacing between offsets and time points is programmable.

17. The memory controller of claim 11, further comprising: A signal quality detector is used to detect the signal quality of the received signal; as well as An oversampling control circuit is used to activate or deactivate one or more K samplers based on signal quality to increase or decrease the in-phase oversampling factor K.

18. The memory controller of claim 17, wherein the signal quality is indicated by the voltage noise level in the data signal.

19. The memory controller of claim 11, further comprising: A signal quality detector is used to detect the signal quality of the received signal; as well as An oversampling control circuit is used to activate or deactivate one or more R voltage comparator modules in each signal level detector based on signal quality, in order to increase or decrease the quadrature oversampling factor R.

20. The memory controller of claim 19, wherein the signal quality is indicated by the timing noise level in the timing signal accompanying the data signal.

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