Parallel test sequence optimization method and system for DDR5 memory write-in and refresh operation

Abstract

The invention relates to the technical field of memory refresh testing, in particular to a parallel test sequence optimization method and system for DDR5 memory write-in refresh operation, and the method comprises the steps: obtaining historical write-in refresh parameters, delay data and error rate data of a target memory module in normal and fault states through test equipment; conflict detection and redundancy elimination are carried out; analyzing a bank grouping structure based on historical parameters, refreshing a cycle constraint and a command dependency relationship, establishing a bank-level parallel test sequence optimization model, and rearranging historical data to generate an optimized test sequence; dynamically mapping historical parameters and an optimization sequence, and constructing a test sequence optimization platform in combination with a test principle and process data; virtual time sequence simulation is carried out by importing current operation parameters, and a prediction optimization test sequence is output; and finally formulating an actual test scheme according to the prediction sequence. According to the method, the test parallelism and the time sequence coordination are remarkably improved, the bank conflict probability is effectively reduced, and the test coverage rate and efficiency are enhanced.

Description

Technical Field

[0001] This invention relates to the field of memory refresh testing technology, and in particular to a method and system for optimizing parallel test sequences for DDR5 memory write refresh operations. Background Technology

[0002] With the widespread adoption of fifth-generation Double Data Rate Synchronous Dynamic Random Access Memory (DDR5 SDRAM), significant improvements have been achieved in data transfer rates, bandwidth density, and power efficiency compared to previous generations. However, the complexity of the DDR5 memory architecture has also increased, primarily due to finer-grained bank grouping structures (such as support for BankGroups), higher bank concurrency access requirements, stricter timing constraints, and enhanced refresh control mechanisms. While these features improve performance, they also place higher demands on command scheduling, timing coordination, and fault coverage during memory testing.

[0003] In existing memory testing processes, test equipment typically uses predefined or statically configured test sequences to perform functional verification and reliability assessment of write and refresh operations on DDR5 memory modules. These traditional test sequences lack the ability to adapt to dynamic behaviors such as bank-level resource contention, write latency fluctuations, and refresh error accumulation under actual operating conditions. This easily leads to frequent inter-bank access conflicts, refresh omissions, or over-refreshing, not only reducing testing efficiency but also potentially masking underlying stability defects and affecting the authenticity and completeness of test results. Furthermore, current testing methods largely rely on manual experience to set test parameter combinations, failing to effectively integrate write latency characteristics, refresh error patterns, and timing dependencies from historical test data. This results in a lack of data-driven support for test sequence optimization, making it difficult to achieve adaptive adjustments under different operating conditions (such as temperature changes, voltage shifts, and aging effects). Especially when facing multiple fault modes (such as row leakage, abnormal refresh counts, and bank activation failures), fixed test sequences struggle to cover complex boundary conditions, resulting in insufficient test coverage and extending the product verification cycle.

[0004] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a method and system for optimizing parallel test sequences for DDR5 memory write refresh operations. This aims to solve the technical problems of existing DDR5 memory testing methods, which lack adaptability to bank-level parallel characteristics and dynamic operating environments, resulting in frequent access conflicts, timing constraint violations, insufficient fault coverage, and reliance on manual experience for optimization, making it difficult to achieve efficient and intelligent parallel testing.

[0006] To achieve the above objectives, this invention provides a method for optimizing parallel test sequences of DDR5 memory write refresh operations, the method comprising: The test equipment is used to obtain the historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working conditions and fault conditions. Conflict detection and redundancy elimination are performed on the historical write latency data and historical refresh error rate data. Based on the historical write refresh parameters, the bank grouping structure, refresh cycle constraints, and write command dependencies of the target DDR5 memory module are analyzed to generate a bank-level parallel test sequence optimization model. The historical write latency data and historical refresh error rate data are rearranged according to the bank-level parallel test sequence optimization model to obtain the optimized test sequence. The historical write refresh parameters are dynamically mapped to the optimized test sequence to obtain historical parameter-sequence dynamic mapping data. The test principle data and test process data of the test equipment for the target DDR5 memory module are obtained. Based on the historical parameter-sequence dynamic mapping data, test principle data and test process data, the test sequence optimization platform of the test equipment for the target DDR5 memory module is constructed. Obtain the current operating parameter data of the target DDR5 memory module, import the current operating parameter data into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module, and obtain a predicted optimization test sequence; The actual test plan for the target DDR5 memory module is determined based on the predicted and optimized test sequence.

[0007] Optionally, the step of acquiring historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal and fault conditions through testing equipment, and performing conflict detection and redundancy elimination on the historical write latency data and historical refresh error rate data, specifically involves: The test equipment was used to obtain the historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working conditions and under different fault types. The historical write refresh parameters, historical write latency data, and historical refresh error rate data under different fault types were labeled with fault modes. Multiple bank conflict detection algorithms are pre-set and imported into the test device, and the conflict recognition threshold for each algorithm is determined; A bank access timing diagram is drawn for the historical write latency data and historical refresh error rate data. The bank activation conflict window and refresh command overlap area are calculated based on the bank access timing diagram. The conflict signal position is identified based on the bank activation conflict window and refresh command overlap area. Sequence segments are extracted from the conflict signal position in the bank access timing diagram to determine the command conflict type in the historical write latency data and historical refresh error rate data. Based on the command conflict type and the conflict identification threshold of each algorithm, a conflict elimination strategy is determined for historical write delay data and historical refresh error rate data. Based on the conflict elimination strategy, redundant commands are removed and sequences are compressed for historical write delay data and historical refresh error rate data.

[0008] Optionally, based on the historical write refresh parameters, the bank grouping structure, refresh cycle constraints, and write command dependencies of the target DDR5 memory module are analyzed to generate a bank-level parallel test sequence optimization model. The historical write latency data and historical refresh error rate data are then rearranged according to the bank-level parallel test sequence optimization model to obtain an optimized test sequence, specifically as follows: The bank grouping information, refresh cycle parameters, and write command timing constraints in the historical write refresh parameters are input into the bank dependency graph generator to construct a directed acyclic graph of bank dependencies. The nodes of the directed acyclic graph of bank dependencies represent bank groups, and the edges represent command dependency weights. Based on the directed acyclic graph of the bank dependencies, a topology sorting algorithm is used to determine the parallel execution priority sequence of bank groups, and the timing window of each bank group is calculated according to the refresh cycle constraints in the DDR5 specification. The historical write delay data and historical refresh error rate data are divided into M time-series data blocks according to bank grouping. The dynamic scheduling window algorithm is applied to the M time-series data blocks to rearrange the time-series data blocks according to the parallel execution priority sequence and the time-series window, generating conflict-free parallel test sequence fragments. The parallel test sequence segments are subjected to conflict verification. If a bank activation conflict exists, the scheduling window size is adjusted and the sequence is rearranged until the DDR5 refresh timing requirements are met, thus obtaining an optimized test sequence.

[0009] Optionally, the step of forming a dynamic mapping relationship between the historical write refresh parameters and the optimized test sequence to obtain historical parameter-sequence dynamic mapping data, acquiring the test principle data and test process data of the test equipment for the target DDR5 memory module, and constructing a test sequence optimization platform for the test equipment for the target DDR5 memory module based on the historical parameter-sequence dynamic mapping data, test principle data, and test process data, specifically involves: The optimized test sequences generated under different historical write-refresh parameters are associated with the corresponding historical write-refresh parameters to establish a parameter-sequence dynamic mapping table and obtain historical parameter-sequence dynamic mapping data. Obtain test principle data and test process data of the test equipment on the target DDR5 memory module; A virtual timing simulation model of DDR5 memory and test equipment is constructed. Based on the test principle data, bank grouping constraints and refresh cycle limits are applied to the virtual timing simulation model. The virtual data channel between the test equipment and DDR5 memory is configured to generate a timing interaction simulation environment between the test equipment and DDR5 memory. Based on the historical parameter-sequence dynamic mapping data and test principle data, the timing interactive simulation environment is iteratively trained and the parameters are tuned to obtain the test sequence optimization platform for the test equipment on the target DDR5 memory module.

[0010] Optionally, the test principle data includes the bank grouping architecture of DDR5 memory, refresh command timing specifications, write operation voltage threshold, bank conflict avoidance mechanism, and data link protocol between the test equipment and DDR5 memory.

[0011] Optionally, the step of obtaining the current operating parameter data of the target DDR5 memory module and importing the current operating parameter data into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module to obtain a predictive optimization test sequence specifically involves: Obtain data on the impact of temperature changes on bank timing parameters of the target DDR5 memory module, and obtain data on the correlation between operating voltage fluctuations and refresh error rate; The current operating parameter data of the target DDR5 memory module is obtained, and the current operating parameter data is used as the real-time test parameter data of the test device on the target DDR5 memory module. The real-time test parameter data is imported into the test sequence optimization platform to perform virtual timing simulation on the current write latency and refresh error rate of the target DDR5 memory module to obtain the initial predicted test sequence. Obtain the current operating temperature data and current operating voltage data of the target DDR5 memory module, determine the bank timing offset based on the current operating temperature data and current operating voltage data, and calculate the timing compensation coefficient based on the bank timing offset and associated data; The initial prediction test sequence is dynamically adjusted according to the timing compensation coefficient; the adjusted prediction test sequence is matched and verified with the historical write latency data and historical refresh error rate data of the target DDR5 memory module under normal working conditions and fault conditions, and the abnormal bank grouping and conflict risk level of the target DDR5 memory module are identified to obtain the prediction optimization test sequence.

[0012] Optionally, determining the actual test plan for the target DDR5 memory module based on the predicted and optimized test sequence specifically involves: Based on the predicted and optimized test sequence, if the conflict risk level is low, the number of bank group tests and the frequency of refresh command tests on the target DDR5 memory module by the test equipment will be reduced. If the conflict risk level is medium or high, the test bank group range of the test equipment for the target DDR5 memory module is determined according to the abnormal bank group identifier and the conflict risk level. The test timing window and test bandwidth weight of each bank group are allocated based on the bank group priority matrix to obtain the actual test plan of the test equipment for the target DDR5 memory module.

[0013] Furthermore, to achieve the above objectives, the present invention also provides a parallel test sequence optimization system for DDR5 memory write refresh operations, the system comprising: The data acquisition module is used to acquire historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working and fault conditions through the test equipment, and to perform conflict detection and redundancy elimination on the historical write latency data and historical refresh error rate data. The modeling and rearrangement module is used to analyze the bank grouping structure, refresh cycle constraints and write command dependencies of the target DDR5 memory module based on the historical write refresh parameters, generate a bank-level parallel test sequence optimization model, and rearrange the historical write latency data and historical refresh error rate data according to the bank-level parallel test sequence optimization model to obtain an optimized test sequence. The platform construction module is used to form a dynamic mapping relationship between the historical write refresh parameters and the optimized test sequence to obtain historical parameter-sequence dynamic mapping data, acquire the test principle data and test process data of the test equipment for the target DDR5 memory module, and construct the test sequence optimization platform of the test equipment for the target DDR5 memory module based on the historical parameter-sequence dynamic mapping data, test principle data and test process data. The simulation prediction module is used to obtain the current operating parameter data of the target DDR5 memory module, import the current operating parameter data into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module, and obtain the prediction optimization test sequence; The scheme generation module is used to determine the actual test scheme of the test equipment for the target DDR5 memory module based on the predicted optimized test sequence.

[0014] Furthermore, to achieve the above objectives, the present invention also provides a parallel test sequence optimization device for DDR5 memory write refresh operations. The device includes: a memory, a processor, and a parallel test sequence optimization program for DDR5 memory write refresh operations stored on the memory and executable on the processor. The parallel test sequence optimization program for DDR5 memory write refresh operations is configured to implement the steps of the parallel test sequence optimization method for DDR5 memory write refresh operations as described above.

[0015] Furthermore, to achieve the above objectives, the present invention also provides a medium storing a parallel test sequence optimization program for DDR5 memory write refresh operations, wherein when the parallel test sequence optimization program for DDR5 memory write refresh operations is executed by a processor, the program implements the steps of the parallel test sequence optimization method for DDR5 memory write refresh operations as described above.

[0016] This invention provides a parallel test sequence optimization method for DDR5 memory write-refresh operations. The method integrates multi-dimensional data such as historical write-refresh parameters, write latency, and refresh error rate, and performs conflict detection and redundancy elimination, improving the quality and effectiveness of test data. Based on the DDR5 memory's bank grouping structure, refresh cycle constraints, and command dependencies, a bank-level parallel test sequence optimization model is constructed, achieving refined modeling and intelligent rearrangement of the test sequence, significantly enhancing bank resource utilization and parallelism during testing. By establishing a dynamic mapping relationship between historical parameters and optimized test sequences, and combining test principles and process data to construct a test sequence optimization platform, it supports the generation of adaptive test strategies for different memory states. Furthermore, by introducing current operating parameters for virtual timing simulation, the optimal test sequence can be accurately predicted, proactively avoiding timing conflicts and refresh omission risks. The final generated predictive optimized test scheme can dynamically adapt to the actual working conditions of the target DDR5 memory module, improving test coverage and fault detection rate while effectively reducing invalid test operations and redundant test overhead, significantly improving test efficiency and intelligence. It is suitable for automated and high-reliability testing scenarios of high-density, high-speed DDR5 memory modules. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating an embodiment of the parallel test sequence optimization method for DDR5 memory write refresh operations according to the present invention.

[0018] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] Reference Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the parallel test sequence optimization method for DDR5 memory write refresh operation according to the present invention. An embodiment of the parallel test sequence optimization method for DDR5 memory write refresh operation according to the present invention is presented.

[0021] In one embodiment, the parallel test sequence optimization method for DDR5 memory write refresh operations includes: Step S100: Obtain historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working and fault conditions through the testing equipment, and perform conflict detection and redundancy elimination on the historical write latency data and historical refresh error rate data.

[0022] The target DDR5 memory module can be a physical or logical unit of the fifth-generation double data rate synchronous dynamic random access memory (DDR5) under test. It can be used as the target of the test sequence optimization method, and its internal structure and operating state determine the adaptability of the test strategy. In an exemplary embodiment, the target DDR5 memory module can be one or more of the following, including but not limited to single-row DDR5 DIMM modules, dual-row DDR5 RDIMM modules, and DDR5 LRDIMM modules with ECC functionality. Historical write / refresh parameters can be a set of configuration parameters related to write and refresh operations recorded in past tests of the target DDR5 memory module. These parameters can be used to provide basic input for building the test sequence optimization model, reflecting the operational characteristics under different operating conditions. Furthermore, historical write / refresh parameters can be automatically recorded and stored by the test equipment when performing test tasks under normal and fault conditions.

[0023] Historical write latency data can be a record of the time interval from the issuance of a write command to the stable completion of data writing in historical tests of the target DDR5 memory module. This data can be used to identify inter-bank resource contention and timing bottlenecks, supporting conflict detection and sequence rearrangement. In one specific embodiment, historical write latency data can be collected by a high-precision timer built into the test equipment during the write operation cycle. Historical refresh error rate data can be a statistical analysis of the frequency of data retention errors caused by refresh operation failures in historical tests of the target DDR5 memory module. This data can be used to reveal abnormal refresh mechanism patterns and assist in identifying potential faults such as row leakage and abnormal refresh counts. For example, historical refresh error rate data can be generated by comparing the data consistency verification results of storage units before and after a refresh.

[0024] By acquiring historical write / refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal and fault conditions using testing equipment, the testing equipment can perform write and refresh operations on the target DDR5 memory module under various preset operating conditions and simultaneously record relevant parameters and performance indicators. Furthermore, this operation can be implemented through multiple rounds of stress testing and fault injection experiments, thereby constructing a multi-dimensional historical dataset to provide basic input for subsequent conflict detection and model building. Conflict detection and redundancy elimination of historical write latency data and historical refresh error rate data can involve analyzing historical data for violations of DDR5 timing constraints or recurring invalid operation patterns, and marking or removing them. In a specific embodiment, this operation can be achieved by filtering based on a rule engine matching JEDEC timing violation patterns, or by using a clustering algorithm to identify highly similar latency-error combinations and merge redundant samples, thereby improving the quality and representativeness of the input data and reducing noise interference with model training.

[0025] Step S200: Based on historical write refresh parameters, analyze the bank grouping structure, refresh cycle constraints, and write command dependencies of the target DDR5 memory module, generate a bank-level parallel test sequence optimization model, and rearrange the historical write latency data and historical refresh error rate data according to the bank-level parallel test sequence optimization model to obtain the optimized test sequence.

[0026] Bank grouping structure can be a logical organization method in DDR5 memory that divides multiple banks into several independent, concurrently accessible bank groups. It can be used to support bank activation and precharge operations with higher parallelism, and is a key architectural feature for improving bandwidth. For example, bank grouping structure can include, but is not limited to, one or more of four-bank-group structures, eight-bank-group structures, and asymmetric bank-group structures. Refresh cycle constraints can be the maximum allowed time interval between two refresh operations and its scheduling rules as specified in the DDR5 memory specification. They can be used to ensure that all memory rows are refreshed within a specified time, preventing data loss and constituting boundary conditions for the legality of the test sequence. Write command dependencies can be the timing and state dependency rules between write commands and other commands (such as activation, precharge, and refresh) in DDR5 memory. They can be used to constrain the legality of the command arrangement in the test sequence and avoid invalid operations caused by violations of the JEDEC protocol.

[0027] A bank-level parallel test sequence optimization model can be a mathematical or logical model built based on the DDR5 bank grouping structure, refresh cycle constraints, and command dependencies to guide test sequence reordering. It can be used to achieve refined modeling of test sequences, improving bank resource utilization and parallel access efficiency. In an exemplary embodiment, the bank-level parallel test sequence optimization model can parse the structural information in historical write refresh parameters and formally model it using the DDR5 protocol specification. Furthermore, the bank-level parallel test sequence optimization model can receive historical write latency data and historical refresh error rate data as input and output a scheduling strategy for sequence reordering. The optimized test sequence can be a conflict- and redundancy-free test command sequence obtained after processing by the bank-level parallel test sequence optimization model. This sequence can be used as an intermediate product to build dynamic mapping relationships, improving the accuracy of subsequent test strategy generation.

[0028] Based on historical write refresh parameters, analyzing the bank grouping structure, refresh cycle constraints, and write command dependencies of the target DDR5 memory module can help extract structured rules by parsing the memory architecture features and protocol constraints implicit in historical parameters. In one specific embodiment, this operation can infer the number and topology of bankgroups through parameter pattern matching, or deduce key timing parameters such as tREFI from the refresh interval distribution, thus providing structured input for building an accurate bank-level parallel test sequence optimization model. Generating the bank-level parallel test sequence optimization model can be achieved by formalizing the extracted bank grouping structure, refresh cycle constraints, and command dependencies into a computable scheduling model. For example, this operation can be achieved by constructing a scheduling model based on the constraint satisfaction problem (CSP), or by using graph neural networks to model inter-bank dependencies, thereby enabling refined modeling of the test sequence and supporting intelligent reordering.

[0029] Based on the bank-level parallel test sequence optimization model, historical write latency data and historical refresh error rate data are rearranged to obtain an optimized test sequence. This can be achieved by rearranging the order of test commands under model constraints to maximize bank parallelism and avoid known conflict patterns. Furthermore, this operation can be implemented by using heuristic algorithms (such as simulated annealing) to search for the optimal sequence or by exploring high-reward sequences in the state space based on reinforcement learning agents, thereby significantly improving bank resource utilization and test parallelism.

[0030] Step S300: The historical write refresh parameters are dynamically mapped to the optimized test sequence to obtain historical parameter-sequence dynamic mapping data. The test principle data and test process data of the test equipment for the target DDR5 memory module are obtained. Based on the historical parameter-sequence dynamic mapping data, test principle data and test process data, the test sequence optimization platform of the test equipment for the target DDR5 memory module is constructed.

[0031] Historical parameter-sequence dynamic mapping data can be a dataset of associations between historical write-refresh parameters and corresponding optimized test sequences. This data can be used to support adaptive generation of test strategies, achieving a traceable mapping from parameters to sequences. In one specific embodiment, historical parameter-sequence dynamic mapping data can be structured and stored using historical write-refresh parameters as keys and optimized test sequences as values. Test principle data can describe the basic theoretical basis for the test equipment to perform functional verification and reliability assessment of DDR5 memory modules. This data can be used to provide logical correctness assurance for the test sequence optimization platform, ensuring that the generated scheme meets the test objectives. Test process data can be the standard operating steps and stage division information for the test equipment to perform DDR5 memory tests. This data can be used to constrain the context of the test sequence in actual execution, ensuring the feasibility of the scheme.

[0032] The test sequence optimization platform can be software or a hardware-software co-processing system that integrates historical parameter-sequence dynamic mapping data, test principle data, and test process data. It can be used to support adaptive test strategy generation and achieve intelligent scheduling and management of test sequences. In one exemplary embodiment, the test sequence optimization platform can construct a configurable test strategy generation framework through data fusion and a rule engine. Furthermore, the test sequence optimization platform can receive current operating parameter data as input and output predicted and optimized test sequences.

[0033] By writing historical data into refresh parameters and optimizing test sequences to form a dynamic mapping relationship, we obtain historical parameter-sequence dynamic mapping data. This can be achieved by establishing an association index from the parameter space to the sequence space, supporting fast retrieval and generalization. For example, this operation can be achieved by constructing a hash table to realize O(1) lookup from parameters to sequences, or by training a regression model to predict key feature vectors of the sequence, thereby supporting data-driven generation and adaptive adjustment of test strategies. Obtaining the test principle data and test process data of the test equipment for the target DDR5 memory module can be achieved by extracting test logic and execution process specifications from the test equipment configuration library or knowledge base, thereby ensuring that the generated test sequence meets the test objectives and engineering implementation requirements.

[0034] Based on historical parameter-sequence dynamic mapping data, test principle data, and test process data, a test sequence optimization platform for the target DDR5 memory module is constructed. This platform can integrate multi-source data to build a unified strategy generation framework, supporting parameterized input and sequence output. In a specific embodiment, this operation can be achieved by encapsulating each data module and inference engine using a microservice architecture, or by building a test strategy inference system based on a knowledge graph, thereby realizing the platformization and reusability of test strategy generation.

[0035] Step S400: Obtain the current operating parameter data of the target DDR5 memory module, import the current operating parameter data into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module, and obtain the predicted optimization test sequence.

[0036] The current operating parameter data can be the real-time environment and status parameters of the target DDR5 memory module before the test is executed. It can reflect the current operating condition of the memory module and be used for virtual timing simulation to generate a compatibility test sequence. For example, the current operating parameter data can include, but is not limited to, one or more of the following: operating temperature parameters, power supply voltage offset parameters, and aging degree characterization parameters. Virtual timing simulation can be the process of simulating and extrapolating the execution timing of DDR5 memory commands based on the current operating parameters in a test sequence optimization platform. It can be used to predict the timing behavior of the test sequence on real hardware and identify potential conflicts or violations in advance. In a specific embodiment, virtual timing simulation can utilize a DDR5 timing model and current operating parameters to drive an event scheduling simulation engine. The predicted and optimized test sequence can be the optimal test command sequence adapted to the current operating parameters, generated after verification by virtual timing simulation. It can be used as a direct basis for the final test plan, balancing coverage, efficiency, and security.

[0037] Obtaining the current operating parameter data of the target DDR5 memory module can be achieved by reading the current environmental and status parameters of the memory module through sensors or device interfaces, thus providing realistic operating condition input for virtual timing simulation. Importing the current operating parameter data into the test sequence optimization platform allows for virtual timing simulation of the target DDR5 memory module, resulting in a predicted optimized test sequence. This can be achieved by running the timing simulation engine within the platform to evaluate the compliance and performance of candidate sequences under the current parameters. Furthermore, this operation can be performed by deriving the timing state command-by-command based on discrete event simulation, or by verifying the feasibility of the sequence using a timing constraint solver. This allows for accurate prediction of the optimal test sequence, proactively avoiding timing conflicts and refresh omission risks.

[0038] Step S500: Determine the actual test plan for the target DDR5 memory module using the test equipment based on the predicted and optimized test sequence.

[0039] The actual test plan can be a specific execution instruction set and resource configuration plan formulated by the test equipment based on the predictive optimized test sequence. It can be used to guide the test equipment to conduct efficient and high-coverage automated testing of the target DDR5 memory module. Determining the actual test plan for the target DDR5 memory module based on the predictive optimized test sequence can involve converting the predictive optimized test sequence into an executable instruction stream and resource configuration instructions for the test equipment. In an exemplary embodiment, this operation can be achieved by generating an ATE (Automatic Test Equipment) script file or by directly issuing a command queue to the test controller via API, thereby enabling dynamic adaptation and efficient execution of the test plan.

[0040] For example, in the scenario of mass production testing of DDR5 server memory under high-temperature aging conditions, the parallel test sequence optimization method for DDR5 memory write refresh operations in this embodiment can be used to verify the reliability of a batch of DDR5 RDIMM modules in an 85°C high-temperature aging chamber. The test equipment first calls the historical write refresh parameter library to identify the pattern in which the batch of chips is prone to increased bank3 activation latency and refresh error rate under high temperature. After eliminating redundant and inefficient sequences through conflict detection, the bank-level parallel test sequence optimization model rearranges commands based on a four-bank-group structure, so that high-latency banks are activated alternately with other banks. The test sequence optimization platform performs virtual timing simulation in conjunction with the current 85°C temperature parameters, finds that the original refresh interval may exceed the limit under high temperature, automatically inserts additional refresh commands and adjusts the write interval. The final generated predictive optimized test sequence ensures full coverage while avoiding misjudgments caused by timing violations, shortens the single-module test time by 20%, and successfully detects two routine early leakage faults.

[0041] In one embodiment, historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal and fault conditions are obtained through a testing device. Conflict detection and redundancy elimination are performed on the historical write latency data and historical refresh error rate data, specifically as follows: The test equipment was used to obtain the historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working conditions and under different fault types. The historical write refresh parameters, historical write latency data, and historical refresh error rate data under different fault types were labeled with fault modes. Multiple bank collision detection algorithms were pre-set and imported into the test equipment, and the collision recognition threshold for each algorithm was determined. A bank access timing diagram is drawn for historical write latency data and historical refresh error rate data. The bank activation conflict window and refresh command overlap area are calculated based on the bank access timing diagram. The conflict signal location is identified based on the bank activation conflict window and refresh command overlap area. Sequence segments are extracted from the conflict signal location in the bank access timing diagram to determine the command conflict type in the historical write latency data and historical refresh error rate data. Based on the command conflict type and the conflict identification threshold of each algorithm, a conflict elimination strategy is determined for historical write delay data and historical refresh error rate data. Based on the conflict elimination strategy, redundant commands are removed and sequences are compressed for historical write delay data and historical refresh error rate data.

[0042] The normal operating state refers to the operating state of the target DDR5 memory module in compliance with JEDEC specifications, without functional faults, and with environmental parameters within the nominal range. This state can serve as a benchmark for historical test data to distinguish abnormal behavior patterns. Different fault type states refer to the operating states of the target DDR5 memory module under conditions simulating or inducing specific hardware defects (such as row leakage, refresh counter failure, or bank activation circuit failure). These states can provide behavioral characteristics under diverse fault scenarios, enhancing the test sequence's coverage of boundary and abnormal operating conditions. In an exemplary embodiment, different fault type states may include, but are not limited to, one or more of the following: row leakage fault state, refresh counter abnormal state, and bank activation failure state. Fault mode annotation can be the process or result of semantically tagging historical test data according to the fault type corresponding to its acquisition. This can be used to give historical data traceable fault semantics, supporting context-awareness in subsequent conflict analysis and strategy generation. Furthermore, fault mode annotation can be achieved by synchronously recording the fault injection type during test execution and associating it with the corresponding data sample. For example, fault mode annotation can be achieved by embedding JSON metadata fields to identify fault types during data storage or by associating with a fault configuration table through database foreign keys.

[0043] By acquiring historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal operating conditions and different fault types using testing equipment, test tasks can be executed under preset normal and multiple fault injection conditions, while simultaneously collecting multi-dimensional performance and parameter data. Furthermore, this operation can be achieved by cyclically applying different fault stimuli and recording response indicators through an automated testing platform, thereby expanding the coverage dimensions of historical data and enhancing the ability to characterize abnormal behavior. Fault mode labeling can be performed on the historical write refresh parameters, historical write latency data, and historical refresh error rate data tested under different fault types. This can be achieved by establishing a mapping relationship between the collected data and its corresponding fault injection type, and attaching semantic tags. Further, this operation can be achieved by embedding JSON metadata fields to identify fault types during data storage, or by linking a fault configuration table through database foreign keys, thus imbuing historical data with fault context information and supporting semantic understanding for subsequent analysis.

[0044] Bank conflict detection algorithms can be sets of computational logic used to identify violations of parallel access rules or timing constraints in DDR5 memory bank-level operations. They can support the automated identification of potential command conflicts in historical data, improving the accuracy and adaptability of conflict detection. In one specific embodiment, bank conflict detection algorithms may include, but are not limited to, conflict detection algorithms based on overlapping time windows, conflict detection algorithms based on state machine transition violations, and conflict detection algorithms based on resource occupancy graph coloring. The conflict identification threshold can be a quantized or logical boundary parameter used in the bank conflict detection algorithm to determine whether a valid conflict exists. It can be used to adjust the algorithm's sensitivity, avoid over-detection or under-detection, and adapt to the timing tolerance characteristics of different DDR5 modules. Furthermore, the conflict identification threshold can be dynamically set through calibration experiments or historical false alarm rate statistics.

[0045] Multiple pre-set bank collision detection algorithms can be imported into the test equipment. This can be achieved by integrating various collision identification logics into the test equipment's analysis engine as plug-ins or modules. Furthermore, this operation can be performed by loading different algorithm implementations as dynamic link libraries or by registering and instantiating algorithm classes through configuration files. This enhances the diversity and robustness of collision detection, adapting to different DDR5 architecture characteristics. The collision identification threshold for each algorithm is determined, which can be based on the DDR5 specifications or measured tolerance data to set a critical value for triggering collision judgment for each algorithm. Furthermore, this operation can be performed by automatically deriving the threshold based on JEDEC standard timing parameters or by optimizing the threshold on historical data through cross-validation to minimize the false alarm rate. This balances detection sensitivity and accuracy, avoiding excessive rejection of valid test commands.

[0046] A bank access time series diagram can be a two-dimensional time series chart with time as the horizontal axis and bank or bankgroup as the vertical axis. It visualizes the activation, precharging, and refresh events of historical write and refresh commands on various banks. This chart can be used to transform abstract time series data into an analyzable graphical structure, facilitating the identification of resource contention and command overlap areas. Furthermore, a bank access time series diagram can be drawn based on timestamps and bank address information from historical write latency and refresh error rate data. For example, a bank access time series diagram can visualize the command flow of each bank using a Gantt chart, or construct a sparse matrix to represent the changes in bank occupancy status over time.

[0047] A bank activation conflict window can be defined in the bank access sequence diagram as an illegal concurrent activation period caused by violations of inter-bank activation interval constraints such as tRRD_L / tRRD_S. It can be used to identify critical conflict areas leading to bank activation failure or performance degradation, serving as a basis for conflict signal localization. A refresh command overlap area can be defined in the bank access sequence diagram as an interval where refresh commands and other commands (such as ACT and WR) overlap unschedulably in terms of time or resources. It can be used to reflect risk areas that may lead to refresh omissions, data loss, or command discarding. A conflict signal location can be a specific time-resource coordinate point in the bank access sequence diagram identified as having a bank activation conflict window or a refresh command overlap area. It can be used as an anchor point for sequence segment extraction to locate the conflict command sequence that needs to be processed.

[0048] A sequence fragment can be a local command subsequence extracted from a complete test sequence, containing the location of the conflict signal and several commands preceding and following it. It can be used as a basic analytical unit for classifying command conflict types and formulating elimination strategies. In one specific embodiment, the sequence fragment can be extracted using a fixed-length window (e.g., five preceding and following commands), or the extraction range can be dynamically expanded based on dependency chains until no related commands remain. The command conflict type can be the classification result of the conflict nature in the sequence fragment according to the DDR5 protocol and timing rules. It can be used to guide the selection of differentiated conflict elimination strategies and improve processing accuracy. For example, command conflict types may include, but are not limited to, RAS-to-RAS cross-bankgroup conflicts, REF and ACT command timing violation conflicts, and WR and PRE command resource preemption conflicts.

[0049] Drawing bank access timing diagrams from historical write latency data and historical refresh error rate data can be achieved by parsing command timestamps and target bank addresses to generate a two-dimensional time-resource event graph. Furthermore, this operation can be implemented by visualizing the command flow of each bank using Gantt charts or by constructing sparse matrices to represent the changes in bank occupancy status over time, thus transforming abstract timing data into an analyzable structured graph to support conflict area identification. Calculating the bank activation conflict window and refresh command overlap area based on the bank access timing diagram can be achieved by traversing the command events in the timing diagram and determining illegal overlap intervals based on DDR5 timing constraints (such as tRRD and tRFC). Further, this operation can detect ACT command pairs that violate the minimum interval by scanning a sliding time window, or efficiently calculate command time overlap based on an interval tree algorithm, thereby accurately locating the core areas causing resource contention and timing violations.

[0050] Identifying conflict signal locations based on the overlapping region of bank activation conflict windows and refresh commands can be achieved by mapping the calculated illegal window back to the original command sequence, marking the specific location of the conflict, thus providing a precise index for sequence fragment extraction. Sequence fragment extraction from conflict signal locations in the bank access time sequence diagram can be performed by extracting a local sequence containing several preceding and following commands as the analysis unit, centered on the conflict signal. Furthermore, this operation can be performed using a fixed-length window (e.g., five preceding and following commands) or dynamically expanding the extraction range based on dependency chains until no related commands are implemented, thus forming a standardized input that can be used for conflict type classification. Determining the command conflict types present in historical write latency data and historical refresh error rate data can be achieved by comparing command combinations and temporal relationships in sequence fragments and matching them with predefined conflict type templates. Further, this operation can be performed by using regular expressions to match command patterns and temporal intervals, or by training a lightweight classifier to predict the conflict type of the fragments, thereby achieving semantic classification of conflicts and supporting strategy differentiation.

[0051] Conflict elimination strategies can be sets of rules for redundant command removal and sequence adjustment based on specific command conflict types and corresponding algorithm thresholds. These strategies can be used to clean and compress historical test data, retaining valid test paths and removing invalid or conflicting operations. Redundant commands can be write or refresh commands in historical test sequences that are duplicated, invalid, or violate timing constraints due to static configuration or conflicts. These can be used as targets for elimination in conflict elimination strategies to reduce test overhead. Sequence compression can be the result of compacting and reorganizing the test sequence after removing redundant commands. This can be used to shorten test sequence length, improve test efficiency, and maintain the integrity of fault-sensitive paths.

[0052] Based on the command conflict type and the conflict identification threshold of each algorithm, a conflict resolution strategy is determined for historical write latency data and historical refresh error rate data. This can be achieved by querying a strategy rule base, matching conflict type with threshold combinations, and outputting corresponding removal and rearrangement rules. Furthermore, this operation can generate elimination actions based on decision tree reasoning or call predefined strategy templates and parameterize them, thereby achieving precise and configurable conflict handling.

[0053] Based on the conflict resolution strategy, redundant commands are removed and sequences are compressed from historical write latency data and historical refresh error rate data. This can involve executing deletion, merging, or rearrangement operations specified by the strategy to generate a cleaned test sequence. Furthermore, this operation can be implemented by modifying the sequence in place and updating the timestamp, or by generating a new sequence copy while retaining the original data for auditing purposes. This improves the quality and temporal consistency of historical test data, providing high-fidelity input for subsequent modeling.

[0054] Taking early fault detection of row leakage in DDR5 memory as an example, the parallel test sequence optimization method for memory write refresh operation in this embodiment can be as follows: During mass production screening, the test equipment applies row leakage fault injection (simulating cell charge leakage acceleration) to a batch of DDR5 modules, collects the write latency and refresh error data under this state, and marks it as "row leakage" fault mode; the system draws a bank access timing diagram and finds that bank2 still has periodic data errors under high-frequency refresh, and further analyzes and identifies the conflict signal position where REF and ACT commands overlap in the tRFC window; extracts the sequence segment containing the conflict and determines it to be of the "REF-ACT timing violation" type; combined with the preset conflict detection algorithm based on tRFC threshold, the system generates an elimination strategy: forcibly inserts NOP after REF to fill until the tRFC requirements are met, and removes invalid WR commands caused by the conflict; after sequence compression, the test sequence successfully reproduces the leakage fault in the subsequent aging test, and the test time is reduced by 15%, without introducing new misjudgments.

[0055] In one embodiment, based on historical write refresh parameters, the bank grouping structure, refresh cycle constraints, and write command dependencies of the target DDR5 memory module are analyzed to generate a bank-level parallel test sequence optimization model. The historical write latency data and historical refresh error rate data are then rearranged according to this model to obtain an optimized test sequence, specifically: The bank grouping information, refresh cycle parameters, and write command timing constraints in the historical write refresh parameters are input into the bank dependency graph generator to construct a directed acyclic graph of bank dependencies. The nodes of the directed acyclic graph of bank dependencies represent bank groups, and the edges represent command dependency weights.

[0056] The bank dependency graph generator can be a processing module used to transform DDR5 memory bank group information, refresh cycle parameters, and write command timing constraints into a structured dependency graph. It can be used to formally model resource contention and timing dependencies between banks, providing graph structure input for subsequent scheduling. In an exemplary embodiment, the bank dependency graph generator can receive structure and constraint information from historical write refresh parameters and construct nodes and edges according to preset rules. The bank dependency directed acyclic graph (DAG) can be an acyclic graph structure with bank groups as nodes and command dependency weights as directed edges, used to explicitly express scheduling dependencies between different bank groups in DDR5 memory. It can be used to visualize and computable implicit timing and resource contention relationships, supporting priority sorting and window allocation. Furthermore, the bank dependency DAG can include, but is not limited to, one or more of the following: a DAG built based on activation-precharge dependencies, a hybrid dependency DAG incorporating refresh interval constraints, and a dynamic weighted DAG considering voltage-temperature coupling effects.

[0057] A node can be a graph element representing a single bank group in a directed acyclic graph (DAG) of bank dependencies. It can be used as a scheduling unit to carry historical data such as write latency and refresh error rate. An edge can be a directed connection line connecting two nodes in the DAG of bank dependencies. It can be used to represent the temporal or resource dependency of a source bank group on a target bank group in terms of command execution. The command dependency weight can be the value carried by the edge, quantifying the strength of the dependency between two bank groups caused by write, activation, or refresh commands. It can be used to guide the priority protection of critical paths when sorting topology and allocating scheduling windows. For example, the command dependency weight can be one or more of the following: weights calculated based on historical write latency differences, dependency strength derived from refresh error rate correlation, and hard constraint weights derived from the minimum interval of the JEDEC protocol.

[0058] The bank grouping information, refresh cycle parameters, and write command timing constraints from the historical write refresh parameters are input into the bank dependency graph generator. This can be achieved by extracting a structured subset from the historical write refresh parameters and passing it to a dedicated graph generation module. Furthermore, this operation can be implemented by parsing parameters such as bank group identifiers, tREFI values, and minimum write command intervals from historical logs or configuration files, thus providing the necessary input for constructing an explicit dependency model. Constructing a directed acyclic graph of bank dependencies can be done by using bank groups as nodes and establishing weighted directed edges based on command dependencies to ensure acyclicity. In a specific embodiment, this operation can be achieved by statistically inferring dependency directions and weights based on write command intervals, or by constructing an initial graph structure according to hard-coded dependency rules in the JEDEC protocol, thereby making implicit dependencies explicit and supporting subsequent graph algorithm processing.

[0059] Based on the directed acyclic graph of bank dependencies, a topology sorting algorithm is used to determine the parallel execution priority sequence of bank groups, and the timing window of each bank group is calculated according to the refresh cycle constraints in the DDR5 specification.

[0060] Topological sorting algorithms are graph algorithms that linearly sort directed acyclic graphs (DAGs) so that all edge directions are consistent with the sorted order. They can be used to extract valid parallel execution priority sequences from DAGs with bank dependencies. Furthermore, topological sorting algorithms can employ Kahn's algorithm (based on in-degree) or depth-first search (DFS) post-order traversal to generate a valid scheduling order basis, avoiding deadlocks caused by circular dependencies. The parallel execution priority sequence can be a list of bank group execution orders output by the topological sorting algorithm, satisfying all dependency constraints. This can be used as a scheduling benchmark for dynamic scheduling window algorithms, ensuring that command rearrangement does not violate dependency logic.

[0061] The refresh cycle constraint in the DDR5 specification can be the maximum interval of refresh operations (such as tREFI) and related scheduling rules explicitly defined in the JEDEC DDR5 standard. This can be used to calculate the legal time window within which each bank group must be refreshed in the test sequence. The timing window can be a time interval allocated to each bank group, within which at least one refresh operation must be completed. This can be used to constrain the insertion position of test commands in the dynamic scheduling window algorithm, preventing refresh omissions. A topology sorting algorithm is used to determine the parallel execution priority sequence of bank groups. This can be achieved by performing a topology sort on the directed acyclic graph of bank dependencies, outputting a linear sequence that satisfies all dependencies. This generates a legal scheduling order basis, avoiding deadlocks caused by circular dependencies.

[0062] The timing window for each bank group is calculated based on the refresh cycle constraints in the DDR5 specification. This can be done by using parameters such as tREFI and combining them with the current total test duration to allocate the time period during which the refresh must occur for each bank group. For example, this operation can be achieved by evenly dividing the global refresh window into each bank group, or by dynamically weighting and allocating more urgent windows based on historical refresh error rates, thereby ensuring that the rearranged sequence still meets the data retention reliability requirements.

[0063] The historical write delay data and historical refresh error rate data are divided into M time-series data blocks by bank grouping. The dynamic scheduling window algorithm is applied to the M time-series data blocks to rearrange them according to the parallel execution priority sequence and the time-series window, generating conflict-free parallel test sequence fragments.

[0064] The M time-series data blocks can be M independent data units formed by dividing historical write delay data and historical refresh error rate data into bank groups. These can be used as the scheduling granularity of a dynamic scheduling window algorithm, supporting fine-grained rearrangement by bank group. The dynamic scheduling window algorithm is a scheduling algorithm that adaptively rearranges time-series data blocks under the dual constraints of parallel execution priority sequence and time-series window. It can be used to generate physically concurrent, conflict-free test sequence fragments that satisfy refresh constraints. Furthermore, the dynamic scheduling window algorithm can employ a sliding window greedy filling strategy or preemptive scheduling based on earliest deadline (EDF), thereby producing locally concurrent sequences that meet dependency and timing constraints. The parallel test sequence fragment can be a local test command sequence corresponding to concurrent operations across multiple bank groups, generated after rearrangement by the dynamic scheduling window algorithm. It can be used as a building block for optimizing test sequences, demonstrating bank group-level parallelism.

[0065] Historical write latency data and historical refresh error rate data are divided into M time-series data blocks according to bank grouping. This can be achieved by grouping and aggregating historical performance data based on bank grouping identifiers to form time-series units that correspond one-to-one with nodes, thereby aligning data with scheduling units and supporting fine-grained rearrangement. Applying a dynamic scheduling window algorithm to the M time-series data blocks can map each data block to an appropriate position on the test time axis under priority sequence and time-series window constraints, thus generating preliminary parallel test sequence fragments.

[0066] The time-series data blocks are rearranged according to the parallel execution priority sequence and timing window to generate conflict-free parallel test sequence fragments. This can be achieved by attempting to fill the time-series window of the bank group to which the data blocks belong, in priority order, to avoid overlapping with other high-priority operations. In one specific embodiment, this operation can use non-preemptive filling to preserve the original command order within the block, or allow fine-tuning of commands within the block to improve window utilization, thereby producing a local concurrent sequence that conforms to dependency and timing constraints.

[0067] The parallel test sequence segments are conflict verified. If a bank activation conflict exists, the scheduling window size is adjusted and the sequence is rearranged until the DDR5 refresh timing requirements are met, thus obtaining an optimized test sequence.

[0068] Conflict verification can be a process of checking the bank activation status and timing compliance of parallel test sequence segments. It can be used to identify bank activation conflicts that violate the DDR5 protocol (such as multiple banks being activated simultaneously within the same bankgroup). The scheduling window size can be a parameter in the dynamic scheduling window algorithm that allows adjustment of the time interval length. It can be used as a conflict adjustment variable, rearranging commands by expanding or shrinking the window when a bank activation conflict is detected. DDR5 refresh timing requirements can be a set of all refresh-related timing specifications that must be met for DDR5 memory to function properly. It can be used as the final acceptance criterion for optimizing test sequence generation, ensuring that the testing itself is legal and valid.

[0069] Conflict verification of parallel test sequence segments can be performed by simulating the execution of the sequence segments to check for violations such as simultaneous activation of multiple banks within the same bankgroup, thereby identifying potential hardware conflicts in the scheduling results. If bank activation conflicts exist, the scheduling window size is adjusted and rearranged. This can be done by expanding or shifting the timing window of the involved bank group after a conflict is detected, triggering a new round of scheduling. Furthermore, this operation can be implemented by expanding the window boundary in fixed steps or by intelligently adjusting the window center based on the historical delay distribution of the conflicting banks, thus gradually approaching a conflict-free solution through a closed-loop feedback mechanism. The optimized test sequence is obtained until the DDR5 refresh timing requirements are met. This can be achieved by iteratively executing rearrangement and verification until the generated sequence simultaneously satisfies both bank activation conflict-free and refresh cycle constraints, thus outputting a final usable optimized test sequence that combines parallelism, legality, and fault sensitivity.

[0070] For example, in the scenario of DDR5 client memory verification under high parallel pressure, the parallel test sequence optimization method for DDR5 memory write refresh operation in this embodiment can be: for a DDR5 SODIMM module that supports 8 banks-group, historical data shows that there is significant write latency coupling between bankgroup2 and bankgroup5 under high load write scenarios. The system inputs parameters such as bank group information, tREFI=7.8μs, and minimum write command interval tWTR_L=4cycles into the bank dependency graph generator to construct a DAG containing weighted edges. The topological sorting outputs a priority sequence of [bg0, bg2, bg5, bg1, ...]. A refresh window of approximately 975ns is allocated to each bankgroup according to the refresh cycle constraint. Historical latency and error rate data are divided into 8 time-series data blocks. The dynamic scheduling window algorithm rearranges the blocks under priority and time-series window constraints. In the initially generated sequence fragments, bg2 and bg5 have activation conflicts due to window overlap. The conflict verification module triggers window adjustment, shifting the bg5 window 200ns to the right and rescheduling it. The final optimized test sequence completes all write and refresh operations within 12μs without any timing violations and successfully reproduces the refreshmiss failure that occurred occasionally at high temperatures.

[0071] In one embodiment, a dynamic mapping relationship is formed between historical write refresh parameters and optimized test sequences to obtain historical parameter-sequence dynamic mapping data. Test principle data and test process data of the test equipment for the target DDR5 memory module are acquired. Based on the historical parameter-sequence dynamic mapping data, test principle data, and test process data, a test sequence optimization platform for the test equipment for the target DDR5 memory module is constructed. Specifically: The optimized test sequences generated under different historical write-refresh parameters are associated with the corresponding historical write-refresh parameters to establish a parameter-sequence dynamic mapping table, thus obtaining historical parameter-sequence dynamic mapping data.

[0072] The parameter-sequence dynamic mapping table can be a data table that structurally associates different historical write-refresh parameters with their corresponding generated optimized test sequences. It can be used to achieve a traceable and queryable mapping from the parameter space to the test strategy space, supporting adaptive test sequence generation. In this embodiment, the parameter-sequence dynamic mapping table can be constructed by indexing historical write-refresh parameters as keys and corresponding optimized test sequences as values.

[0073] By associating optimized test sequences generated under different historical write-refresh parameters with their corresponding historical write-refresh parameters, a dynamic parameter-sequence mapping table is established to obtain historical parameter-sequence dynamic mapping data. This can be achieved by structurally pairing and storing multiple sets of historical write-refresh parameters and their corresponding optimized test sequences. Furthermore, this operation can replace the previous unstructured association method by forming a searchable and generalizable parameter-policy mapping foundation, thereby improving mapping accuracy and query efficiency.

[0074] Obtain test principle data and test process data of the test equipment on the target DDR5 memory module.

[0075] A virtual timing simulation model of DDR5 memory and test equipment is constructed. Based on the test principle data, bank grouping constraints and refresh cycle limits are applied to the virtual timing simulation model. The virtual data channel between the test equipment and DDR5 memory is configured to generate a timing interaction simulation environment between the test equipment and DDR5 memory.

[0076] The virtual timing simulation model of DDR5 memory and test equipment can be a software simulation system that models the internal timing behavior of DDR5 memory and its interaction with the test equipment. It can be used to verify the timing compliance and resource scheduling efficiency of test sequences without relying on physical hardware. In an exemplary embodiment, the virtual timing simulation model of DDR5 memory and test equipment can be constructed as a state machine or event-driven model based on the DDR5 JEDEC specification and timing parameters. Bank group constraints can be a modeling expression of the concurrent access rules of DDR5 bankgroups, used to ensure that command scheduling during simulation conforms to the parallel access restrictions of the DDR5 bankgroup architecture. For example, bank group constraints can include, but are not limited to, one or more of the following: bank mutual exclusion activation rules within the same bankgroup, cross-bankgroup parallel activation permission rules, and bankgroup precharge and activation timing isolation rules.

[0077] The refresh cycle limit can be a constraint on the maximum interval and scheduling window of DDR5 refresh operations. It can be used to prevent violations of critical refresh timing sequences such as tREFI during simulation, ensuring data reliability. The virtual data channel can be a logical component that simulates the command, address, and data signal transmission paths between the test device and DDR5 memory in the simulation environment. It can be used to reproduce the communication latency and bandwidth limitations in real-world testing, improving simulation fidelity. In a specific embodiment, the virtual data channel may include, but is not limited to, a command bus virtual channel, an address bus virtual channel, and a data bus virtual channel.

[0078] The timing interactive simulation environment can be a complete simulation runtime environment integrating virtual timing simulation models, bank grouping constraints, refresh cycle limits, and virtual data channels. It can be used to support the dynamic verification and evaluation of test sequences in high-fidelity DDR5-test device interaction scenarios. Furthermore, the timing interactive simulation environment can receive historical parameter-sequence dynamic mapping data and test principle data as training inputs, and output optimized platform capabilities. Constructing a virtual timing simulation model of DDR5 memory and test equipment can be based on the DDR5 protocol specification and test equipment interface characteristics, establishing simulation logic for command scheduling, state transitions, and timing responses. Further, this operation can be achieved by using a Discrete Event System (DES) to model the triggering and completion events of each command, or by using a Finite State Machine (FSM) to describe the state transition process of DDR5 memory cells. This allows the test sequence to obtain an executable virtual verification environment, avoiding direct trial and error on physical devices.

[0079] Applying bank grouping constraints and refresh cycle limits to the virtual timing simulation model based on test principle data can be achieved by injecting DDR5 architecture constraints into the simulation model as rules or parameters, restricting illegal command combinations and timing arrangements. For example, this operation can be implemented by embedding a bankgroup concurrency check module in the simulation scheduler, or by dynamically verifying the legality of the refresh interval through a timing constraint solver. This improves the simulation model's ability to reproduce the unique behavior of the DDR5 architecture and enhances the legality guarantee of the test sequence. Configuring the virtual data channel between the test equipment and DDR5 memory generates a timing interaction simulation environment between the test equipment and DDR5 memory. This can be achieved by establishing virtual transmission paths for command, address, and data signals in the simulation model and setting their latency and bandwidth characteristics. Furthermore, this operation can be achieved by using a FIFO queue to simulate bus arbitration and transmission delay, or by introducing a noise model to simulate the impact of signal integrity degradation on timing. This allows for the construction of a high-fidelity interactive environment, making the simulation results closer to actual test behavior.

[0080] Based on historical parameter-sequence dynamic mapping data and test principle data, the timing interactive simulation environment is iteratively trained and parameters are optimized to obtain the test sequence optimization platform for the test equipment on the target DDR5 memory module.

[0081] Based on historical parameter-sequence dynamic mapping data and test principle data, iterative training and parameter tuning are performed on the timing interactive simulation environment to obtain a test sequence optimization platform for the target DDR5 memory module. This can be achieved by using historical mapping data as training samples, repeatedly executing and evaluating sequence performance in the simulation environment, and adjusting the internal parameters of the model or the strategy generation logic. In a specific embodiment, this operation can be achieved by using a reinforcement learning framework to optimize the policy network with fault detection rate and test efficiency as reward signals, or by adjusting the timing relaxation parameters in the simulation model through Bayesian optimization to match the actual test performance. This allows the test sequence optimization platform to have self-learning and adaptive capabilities, enabling it to generate highly optimized test schemes for different operating conditions.

[0082] For example, in the scenario of testing DDR5 mobile chips under voltage offset conditions, the parallel test sequence optimization method for DDR5 memory write refresh operations in this embodiment can be used to verify the stability of the mobile platform DDR5 chip under a low voltage of 1.05V. The test sequence optimization platform first retrieves historical optimized sequences under similar voltages from the parameter-sequence dynamic mapping table; then, it loads the sequence in the timing interactive simulation environment and applies four bank-group constraints and a tREFI=3.9μs refresh cycle limit; the virtual data channel simulates the effect of a 15% increase in command bus latency under low voltage; the simulation operation found that the original sequence had a tRCD violation after continuous activation of bank2, and the platform automatically inserted NOP padding and rearranged subsequent commands; after three rounds of iterative training, the generated new sequence achieved zero timing conflicts and covered all high-risk row addresses in the simulation; the predictive optimized test sequence was sent to the ATE device and successfully detected an intermittent write failure fault caused by word line driver weakening, while the traditional static sequence missed the detection because it was not adapted to low voltage timing.

[0083] In one embodiment, the test principle data includes the bank grouping architecture of DDR5 memory, refresh command timing specifications, write operation voltage threshold, bank conflict avoidance mechanism, and data link protocol between the test equipment and DDR5 memory.

[0084] The DDR5 memory bank grouping architecture can be an organizational structure that divides physical banks into several logical bankgroups to support higher parallel access. It can serve as the basic granular unit for test sequence scheduling, guiding the concurrent arrangement and resource isolation strategies of bank-level commands. In an exemplary embodiment, the DDR5 memory bank grouping architecture can dynamically map the correspondence between logical bankgroups and physical banks, taking into account the test platform's requirements for concurrent activation of multiple banks. Furthermore, the DDR5 memory bank grouping architecture can be a foundational structure that works in conjunction with other objects, such as bank conflict avoidance mechanisms, to define the isolation boundaries of command scheduling.

[0085] The refresh command timing specification can be a set of timing parameters and constraint rules related to DDR5 refresh operations defined in the JEDEC standard. It can be used to ensure that the insertion timing and interval of refresh commands in the test sequence meet data retention reliability requirements. In one specific embodiment, the refresh command timing specification can be obtained by parsing the JEDEC DDR5 standard document and embedded into the timing verification module of the test sequence generation engine. Furthermore, the refresh command timing specification can be a timing constraint basis that works in conjunction with the write operation voltage threshold and bank conflict avoidance mechanism, used to coordinate the timing window between refresh operations, data writing, and bank activation. For example, the refresh command timing specification may include, but is not limited to, row refresh period tREFI constraints, refresh burst interval tRFC constraints, and self-refresh exit recovery timing tXS constraints.

[0086] The write operation voltage threshold can be the boundary voltage condition for maintaining stable write operations of DDR5 memory under different supply voltages. It can be used as a basis for adjusting write strength and timing margin under voltage offset conditions in test sequences. In this embodiment, the write operation voltage threshold can be obtained through voltage scan experiments or device model simulation and used as an input parameter for dynamically adjusting the write enable window in the test sequence. Furthermore, the write operation voltage threshold can be an electrical boundary condition that works in conjunction with refresh command timing specifications and data link protocols to maintain signal integrity and timing compliance under low voltage or overpressure stress. For example, the write operation voltage threshold can include, but is not limited to, the nominal voltage write threshold, the low voltage tolerance write threshold, and the overpressure stress write threshold.

[0087] Bank conflict avoidance mechanisms can be arbitration and scheduling rules in the DDR5 memory controller or protocol used to prevent command conflicts within the same bank or bankgroup. These rules can be used to avoid state conflicts caused by consecutive activations, precharges, or writes to the same bank, improving the legitimacy of test sequences. In one exemplary embodiment, the bank conflict avoidance mechanism can implement mutual exclusion checks for bank activation, precharge, and write commands through state machine modeling. Furthermore, the bank conflict avoidance mechanism can be scheduling logic tightly coupled to the DDR5 memory's bank grouping architecture, used to isolate command pipelines in concurrent access across multiple bankgroups.

[0088] The data link protocol between the test equipment and the DDR5 memory can be an agreement on the transmission format, clock alignment, and handshake rules for command, address, and data signals between the test equipment and the DDR5 memory module. This agreement can be used to ensure consistency between the simulation environment and physical testing at the signal interaction level, improving the fidelity of virtual timing simulation. In this embodiment, the data link protocol between the test equipment and the DDR5 memory can verify the signal phase and clock alignment status in real time through a protocol parser. Furthermore, the data link protocol between the test equipment and the DDR5 memory can be an interface layer specification that works in conjunction with write operation voltage thresholds and refresh command timing specifications to maintain link stability under voltage fluctuations or timing compression conditions. For example, the data link protocol between the test equipment and the DDR5 memory can include, but is not limited to, command bus encoding and sampling protocols, address phase alignment protocols, and data strobe (DQS) training and calibration protocols.

[0089] In one embodiment, the current operating parameter data of the target DDR5 memory module is obtained, and the current operating parameter data is imported into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module to obtain a predicted optimization test sequence, specifically: Obtain data on the impact of temperature changes on bank timing parameters of the target DDR5 memory module, and obtain data on the correlation between operating voltage fluctuations and refresh error rate; The data on the impact of temperature changes on bank timing parameters can be quantitative data describing the variation patterns of bank-level operational timing parameters (such as tRCD, tRP, and tRC) of the target DDR5 memory module under different temperature conditions. This data can be used to provide a temperature-timing mapping basis for virtual timing simulation, supporting the accurate calculation of bank timing offsets. In an exemplary embodiment, the data on the impact of temperature changes on bank timing parameters can be generated by performing a stepped temperature stress test on the target DDR5 memory module in a temperature-controlled environment and recording the timing response. Furthermore, the data on the impact of temperature changes on bank timing parameters can include, but is not limited to, one or more of the following: activation to read / write latency offset, precharge cycle offset, and row activation cycle offset.

[0090] The correlation data between operating voltage fluctuations and refresh error rate can be statistical or functional data reflecting the trend of refresh error rate changes when the supply voltage deviates from the nominal value. This data can be used to assess the impact of voltage disturbances on data retention reliability and support dynamic adjustments to refresh strategies. For example, the correlation data between operating voltage fluctuations and refresh error rate can be obtained by performing refresh stress tests under a controllable voltage source, combined with ECC verification or bit error scanning to statistically analyze the error rate distribution.

[0091] Obtaining data on the impact of temperature changes on bank timing parameters of the target DDR5 memory module can be achieved by applying different temperature points to the target DDR5 memory module in a controlled temperature chamber and measuring the changes in key timing parameters of each bankgroup. Furthermore, this operation can be implemented through stepped temperature increases and real-time parameter sampling, thereby establishing a temperature-timing physical mapping model to support subsequent offset calculations. Obtaining data on the correlation between operating voltage fluctuations and refresh error rate can be achieved by performing intensive refresh tests under different supply voltages and counting the number of data errors caused by refresh failures per unit time. Furthermore, this operation can be implemented through voltage step scanning combined with a bit-level error detection mechanism, thereby constructing a voltage-refresh reliability correlation model to evaluate refresh adequacy under voltage disturbances.

[0092] Obtain the current operating parameter data of the target DDR5 memory module, use the current operating parameter data as the real-time test parameter data of the test device on the target DDR5 memory module, import the real-time test parameter data into the test sequence optimization platform, perform virtual timing simulation on the current write latency and refresh error rate of the target DDR5 memory module, and obtain the initial predicted test sequence; The real-time test parameter data can be a set of instantaneous configuration parameters that can be directly used as the current operating parameter data when the test equipment executes the test. This can be used to ensure that the virtual simulation is consistent with the actual test environment and improve the feasibility of the predicted sequence. The current write latency can be the expected write operation completion time of the target DDR5 memory module under the current operating parameter conditions. It can be used as a key output indicator of virtual timing simulation to evaluate the feasibility of the initial predicted test sequence. The refresh error rate can be the expected refresh failure probability of the target DDR5 memory module under the current operating parameter conditions. It can be used to measure the sufficiency and safety boundary of refresh operations in the test sequence. The initial predicted test sequence can be an uncompensated and corrected test command sequence generated for the first time by virtual timing simulation based on the real-time test parameter data. It can be used as a benchmark input for dynamic adjustment, reflecting the original scheduling scheme without considering physical offsets.

[0093] Using the current operating parameter data as real-time test parameter data for the target DDR5 memory module can be achieved by directly binding the collected current operating parameters to the environment configuration parameters in the test execution context. Furthermore, this operation can be implemented through a parameter injection interface or hot-loading of configuration files, thereby ensuring consistency between the simulated and actual test environments and improving the effectiveness of predictions.

[0094] Real-time test parameter data is imported into the test sequence optimization platform to perform virtual timing simulation on the current write latency and refresh error rate of the target DDR5 memory module, obtaining an initial predicted test sequence. This can be achieved by loading real-time parameters into the test sequence optimization platform, driving the timing simulation engine to deduce the command execution path and output the preliminary sequence. Furthermore, this operation can be further refined by using event-driven simulation to deduce the bank state machine cycle by cycle, or by using a timing constraint solver to generate a sequence implementation that satisfies basic constraints within the feasible solution space, thereby generating an initial test plan that closely approximates the current operating conditions.

[0095] Obtain the current operating temperature and voltage data of the target DDR5 memory module, determine the bank timing offset based on the current operating temperature and voltage data, and calculate the timing compensation coefficient based on the bank timing offset and related data. The current operating temperature data can be the actual temperature value or range of the target DDR5 memory module just before the test, and can be used to calculate the timing parameter drift caused by thermal effects. The current operating voltage data can be the actual supply voltage value of the target DDR5 memory module just before the test, and can be used to evaluate the comprehensive impact of voltage deviation on refresh reliability and timing margin. The bank timing offset can be the offset of bank-level key timing parameters relative to their nominal values ​​caused by the current operating temperature and voltage, and can be used to quantify the impact of environmental disturbances on memory timing behavior, providing a basis for compensation. In a specific embodiment, the bank timing offset may include, but is not limited to, activation to read / write latency offset, precharge cycle offset, row activation cycle offset, etc. The associated data can refer to the aforementioned "associated data of operating voltage fluctuations on refresh error rate," and can be used to support refresh reliability modeling in timing compensation coefficient calculation, transforming voltage disturbances into correction factors for the refresh strategy. The timing compensation coefficient can be a proportion or increment factor used to adjust the timing interval of the test sequence, calculated based on the bank timing offset and associated data. It can be used to dynamically correct the initial prediction test sequence to offset the timing margin loss caused by the environment. In an exemplary embodiment, the timing compensation coefficient can be obtained by mapping the offset to the compensation value through a lookup table or interpolation function, or by iterative optimization through an error feedback model.

[0096] Obtaining the current operating temperature and voltage data of the target DDR5 memory module can be achieved by reading real-time environmental parameters through onboard temperature sensors and voltage monitoring circuitry. Furthermore, this operation can be implemented by polling the sensor registers via I2C or SMBus bus, thus providing physical input for bank timing offset calculations.

[0097] Determining the bank time series offset based on current operating temperature and voltage data can be achieved by querying data on the impact of temperature changes on bank time series parameters and interpolating the current temperature to obtain the time series offset value for each bank group. Furthermore, this operation can be implemented by estimating the offset between discrete temperature points using linear interpolation, or by directly outputting the offset from a pre-trained regression model, thereby quantifying the specific impact of environmental disturbances on time series behavior.

[0098] The timing compensation coefficient is calculated based on the bank timing offset and associated data. This can be achieved by combining the timing offset with voltage-refresh error rate correlation data to calculate the required timing margin or refresh density adjustment factor. Furthermore, this operation can be implemented by converting the offset into command interval increments to form additive compensation coefficients, or by back-calculating the required refresh frequency based on the error rate threshold to form multiplicative compensation coefficients. This allows for the generation of quantization correction parameters applicable to sequence adjustment.

[0099] The initial prediction test sequence is dynamically adjusted based on the timing compensation coefficient. The adjusted prediction test sequence is then matched and verified with the historical write latency data and historical refresh error rate data of the target DDR5 memory module under normal and fault conditions. Abnormal bank groups and conflict risk levels of the target DDR5 memory module are identified to obtain the prediction optimization test sequence.

[0100] The adjusted predicted test sequence can be an intermediate test sequence obtained by dynamically correcting the initial predicted test sequence using timing compensation coefficients. This allows for better alignment with current physical conditions and provides higher timing compliance and fault induction capabilities. Abnormal bank groups are those identified during the matching verification process as having significantly higher write latency or refresh error rates than normal. These can be used to locate potential fault areas and guide the focused allocation of test resources. In one specific embodiment, abnormal bank groups may include, but are not limited to, high-leakage bank groups, refresh counter failure bank groups, and activation circuit aging bank groups. The conflict risk level is the probability level of inter-bank access conflicts or refresh omissions assessed based on the matching results of the adjusted sequence and historical data. This can be used to quantify the safety margin of the test sequence and support the screening and optimization of the final sequence. For example, conflict risk levels may include low risk (no historical conflict pattern matching), medium risk (partial reproduction of historical error patterns), and high risk (matching known fault sequence characteristics).

[0101] The initial prediction test sequence is dynamically adjusted based on the timing compensation coefficient. This can be achieved by inserting delays, extending command intervals, or adding refresh commands to the initial sequence to meet compensation requirements. Furthermore, this operation can be implemented by inserting NOP commands between bank activation and write operations to extend the tRCD, or by dynamically adjusting the refresh command insertion frequency at the bankgroup granularity. This improves the timing compliance and fault-inducing capability of the sequence under current operating conditions.

[0102] The adjusted predicted test sequence is matched and verified with historical write latency data and historical refresh error rate data of the target DDR5 memory module under normal and fault conditions. This can be achieved by comparing the expected behavioral characteristics of the adjusted sequence (such as latency distribution and refresh density) with the historical multi-state dataset. Furthermore, this operation can be implemented by using Euclidean distance to measure feature vector similarity or by using anomaly detection models (such as IsolationForest) to identify matching fault modes, thereby identifying potential abnormal regions and assessing conflict risks.

[0103] Identifying abnormal bank groups and conflict risk levels of the target DDR5 memory module yields a predictive and optimized test sequence. This can be achieved by marking high-risk bankgroups based on matching verification results and filtering or enhancing test operations according to the conflict risk level, ultimately outputting the final sequence. Furthermore, this operation can be implemented by adding targeted stress test subsequences to high-risk bankgroups or by using sparse testing for low-risk areas to reduce overhead, thereby generating a final test scheme that combines high coverage with low redundancy.

[0104] For example, in the scenario of reliability testing of automotive DDR5 memory under unstable voltage conditions, the parallel test sequence optimization method for DDR5 memory write refresh operations in this embodiment can be as follows: In a simulated automotive power fluctuation scenario, the test equipment detects that the current operating voltage of the target DDR5 memory module is 1.05V (lower than the nominal 1.1V) and the temperature is 70℃. The system calls the pre-stored voltage-refresh error rate correlation data and finds that the refresh error rate increases by 3 times under this voltage; at the same time, based on the temperature-timing impact data, the tRC offset of bank2 is calculated to be +8ns. The test sequence optimization platform first generates an initial predicted test sequence, and then inserts additional delays between bank2-related operations based on the timing compensation coefficient, and increases the refresh density for bank2. When the adjusted sequence is matched with historical fault data, it is found that its behavior characteristics are highly similar to the "early row leakage" pattern. The system marks the bankgroup where bank2 is located as a high-risk abnormal group, and adds high-frequency refresh and post-write read verification operations to the final predicted optimized test sequence, successfully screening out potential early failure units before mass production.

[0105] In one embodiment, the actual test plan for the target DDR5 memory module is determined by the test equipment based on the predicted and optimized test sequence, specifically as follows: Based on the predicted and optimized test sequence, if the conflict risk level is low, the number of bank group tests and refresh command tests of the target DDR5 memory module by the test equipment will be reduced. If the conflict risk level is medium or high, the test bank group range of the test equipment for the target DDR5 memory module is determined according to the abnormal bank group identifier and the conflict risk level. The test timing window and test bandwidth weight of each bank group are allocated based on the bank group priority matrix to obtain the actual test plan of the test equipment for the target DDR5 memory module.

[0106] The conflict risk level can be a risk assessment level based on the possibility of potential timing conflicts, refresh omissions, or bank resource contention in the predicted and optimized test sequence. It can be used as a basis for test resource allocation decisions, driving a dynamic trade-off between coverage depth and efficiency in the test scheme. In this embodiment, the conflict risk level can include, but is not limited to, one or more of low risk, medium risk, and high risk. The abnormal bank group identifier can be a unique identifier for a bank group that may have row leakage, activation failure, or refresh anomalies, identified during the predicted and optimized test sequence analysis. It can be used to accurately locate memory regions that require enhanced testing, avoiding resource waste caused by full coverage. For example, the abnormal bank group identifier can be generated by matching historical refresh error rate data with abnormal patterns in the current virtual timing simulation results.

[0107] The bank group priority matrix can be a pre-constructed weight structure used to characterize the test importance ranking of different bank groups under specific failure modes or operating conditions. It can be used to guide the allocation of test resources towards high-risk or high-value bank groups. In an exemplary embodiment, the bank group priority matrix can be generated offline based on historical failure distribution statistics and DDR5 physical layout characteristics. Furthermore, the bank group priority matrix can include, but is not limited to, one or more of the following: a priority matrix based on aging sensitivity, a priority matrix based on temperature gradient response, and a priority matrix based on voltage fluctuation robustness.

[0108] The test bank group scope can be a subset of bank groups whose test operations are to be executed, defined by the abnormal bank group identifier, in medium-to-high-risk scenarios. This can be used to narrow the test scope to high-risk areas and improve fault detection efficiency. The test timing window can be the time interval allocated to a specific bank group within the test sequence where commands can be executed. This can be used to ensure that high-priority bank groups receive sufficient and compliant scheduling opportunities, avoiding test failures due to resource contention. The test bandwidth weight can be the proportion of data channel usage or command transmission frequency weight allocated to different bank groups in parallel testing. This can be used to adjust the test intensity of each bank group per unit time, achieving on-demand resource allocation.

[0109] If the conflict risk level is low, the number of bank group tests and the frequency of refresh command tests for the target DDR5 memory module by the testing equipment are reduced. This can be achieved by automatically reducing the number of bank groups participating in the test and the number of refresh commands per unit time when the overall conflict probability is determined to be below a threshold by virtual timing simulation of the predicted optimized test sequence. Furthermore, this operation can be achieved by sampling only one representative bank from each bank group or by extending the refresh command interval to 90% of the specification limit to reduce the frequency. This can significantly reduce testing overhead and energy consumption while ensuring basic functional verification.

[0110] If the conflict risk level is medium or high, the test bank group range for the target DDR5 memory module is determined based on the abnormal bank group identifier and the conflict risk level. This can be achieved by defining a high-risk area based on the abnormal bank group identifier and expanding the test range to adjacent or related bank groups in combination with the risk level. In one specific embodiment, this operation can be implemented by including the abnormal bank and all banks in the same group when the risk is high, or by testing only the abnormal bank and physically adjacent banks when the risk is medium, thereby achieving focused coverage of the fault area and improving the detection rate of boundary defects.

[0111] Assigning test timing windows and test bandwidth weights to each bank group based on the bank group priority matrix can be achieved by querying the bank group priority matrix and assigning differentiated time slice lengths and command emission densities to bank groups with different priorities. For example, this operation can be implemented by allowing high-priority bank groups to obtain exclusive activation windows for multiple consecutive tCK cycles, or by allowing low-priority bank groups to share the remaining bandwidth using an interleaved insertion method. This allows for optimization of resource allocation within a limited test time and enhances the testing intensity in key areas.

[0112] For example, in the scenario of DDR5 client memory reliability screening under voltage offset conditions, the parallel test sequence optimization method for DDR5 memory write refresh operations in this embodiment can be as follows: In the 1.05V low-voltage stress test, virtual timing simulation identifies a refresh delay accumulation trend in bank 5 of bankgroup2, and the conflict risk level is determined to be high risk, and it is marked as an abnormal bank group. Based on this, the system limits the test bank group range to all four banks of group2, and queries the bank group priority matrix. This matrix assigns the highest weight to group2 because historical data shows that group2 is prone to row leakage under low voltage. The platform then allocates continuous test timing windows to group2 and sets its test bandwidth weight to twice that of other groups; at the same time, the other three bank groups, due to their low risk level, only perform single-bank sampling tests and reduce the refresh frequency by 30%. Finally, without increasing the total test time, two early row hold failure defects were successfully captured.

[0113] Furthermore, to achieve the above objectives, the present invention also provides a parallel test sequence optimization system for DDR5 memory write refresh operations, the system comprising: The data acquisition module is used to acquire historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working and fault conditions through the test equipment, and to perform conflict detection and redundancy elimination on the historical write latency data and historical refresh error rate data. The modeling and rearrangement module is used to analyze the bank grouping structure, refresh cycle constraints and write command dependencies of the target DDR5 memory module based on the historical write refresh parameters, generate a bank-level parallel test sequence optimization model, and rearrange the historical write latency data and historical refresh error rate data according to the bank-level parallel test sequence optimization model to obtain an optimized test sequence. The platform construction module is used to form a dynamic mapping relationship between the historical write refresh parameters and the optimized test sequence to obtain historical parameter-sequence dynamic mapping data, acquire the test principle data and test process data of the test equipment for the target DDR5 memory module, and construct the test sequence optimization platform of the test equipment for the target DDR5 memory module based on the historical parameter-sequence dynamic mapping data, test principle data and test process data. The simulation prediction module is used to obtain the current operating parameter data of the target DDR5 memory module, import the current operating parameter data into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module, and obtain the prediction optimization test sequence; The scheme generation module is used to determine the actual test scheme of the test equipment for the target DDR5 memory module based on the predicted optimized test sequence.

[0114] Other embodiments or specific implementations of the parallel test sequence optimization system for DDR5 memory write refresh operation described in this invention can be found in the above-described method embodiments, and will not be repeated here.

[0115] Furthermore, to achieve the above objectives, the present invention also provides a parallel test sequence optimization device for DDR5 memory write refresh operations. The device includes: a memory, a processor, and a parallel test sequence optimization program for DDR5 memory write refresh operations stored on the memory and executable on the processor. The parallel test sequence optimization program for DDR5 memory write refresh operations is configured to implement the steps of the parallel test sequence optimization method for DDR5 memory write refresh operations as described above.

[0116] Furthermore, to achieve the above objectives, the present invention also provides a medium storing a parallel test sequence optimization program for DDR5 memory write refresh operations, wherein when the parallel test sequence optimization program for DDR5 memory write refresh operations is executed by a processor, the program implements the steps of the parallel test sequence optimization method for DDR5 memory write refresh operations as described above.

[0117] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A method for optimizing parallel test sequences for DDR5 memory write-refresh operations, characterized in that, The method includes: The test equipment is used to obtain the historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working conditions and fault conditions. Conflict detection and redundancy elimination are performed on the historical write latency data and historical refresh error rate data. Based on the historical write refresh parameters, the bank grouping structure, refresh cycle constraints, and write command dependencies of the target DDR5 memory module are analyzed to generate a bank-level parallel test sequence optimization model. The historical write latency data and historical refresh error rate data are rearranged according to the bank-level parallel test sequence optimization model to obtain the optimized test sequence. The historical write refresh parameters are dynamically mapped to the optimized test sequence to obtain historical parameter-sequence dynamic mapping data. The test principle data and test process data of the test equipment for the target DDR5 memory module are obtained. Based on the historical parameter-sequence dynamic mapping data, test principle data and test process data, the test sequence optimization platform of the test equipment for the target DDR5 memory module is constructed. Obtain the current operating parameter data of the target DDR5 memory module, import the current operating parameter data into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module, and obtain a predicted optimization test sequence; The actual test plan for the target DDR5 memory module is determined based on the predicted and optimized test sequence.

2. The parallel test sequence optimization method for DDR5 memory write refresh operations as described in claim 1, characterized in that, The process involves acquiring historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal and fault conditions using testing equipment, and performing conflict detection and redundancy elimination on the historical write latency data and historical refresh error rate data. The test equipment was used to obtain the historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working conditions and under different fault types. The historical write refresh parameters, historical write latency data, and historical refresh error rate data under different fault types were labeled with fault modes. Multiple bank conflict detection algorithms are pre-set and imported into the test device, and the conflict recognition threshold for each algorithm is determined; A bank access timing diagram is drawn for the historical write latency data and historical refresh error rate data. The bank activation conflict window and refresh command overlap area are calculated based on the bank access timing diagram. The conflict signal position is identified based on the bank activation conflict window and refresh command overlap area. Sequence segments are extracted from the conflict signal position in the bank access timing diagram to determine the command conflict type in the historical write latency data and historical refresh error rate data. Based on the command conflict type and the conflict identification threshold of each algorithm, a conflict elimination strategy is determined for historical write delay data and historical refresh error rate data. Based on the conflict elimination strategy, redundant commands are removed and sequences are compressed for historical write delay data and historical refresh error rate data.

3. The parallel test sequence optimization method for DDR5 memory write refresh operations as described in claim 1, characterized in that, Based on the historical write refresh parameters, the bank grouping structure, refresh cycle constraints, and write command dependencies of the target DDR5 memory module are analyzed to generate a bank-level parallel test sequence optimization model. The historical write latency data and historical refresh error rate data are then rearranged according to this model to obtain an optimized test sequence. Specifically: The bank grouping information, refresh cycle parameters, and write command timing constraints in the historical write refresh parameters are input into the bank dependency graph generator to construct a directed acyclic graph of bank dependencies. The nodes of the directed acyclic graph of bank dependencies represent bank groups, and the edges represent command dependency weights. Based on the directed acyclic graph of the bank dependencies, a topology sorting algorithm is used to determine the parallel execution priority sequence of bank groups, and the timing window of each bank group is calculated according to the refresh cycle constraints in the DDR5 specification. The historical write delay data and historical refresh error rate data are divided into M time-series data blocks according to bank grouping. The dynamic scheduling window algorithm is applied to the M time-series data blocks to rearrange the time-series data blocks according to the parallel execution priority sequence and the time-series window, generating conflict-free parallel test sequence fragments. The parallel test sequence segments are subjected to conflict verification. If a bank activation conflict exists, the scheduling window size is adjusted and the sequence is rearranged until the DDR5 refresh timing requirements are met, thus obtaining an optimized test sequence.

4. The parallel test sequence optimization method for DDR5 memory write refresh operations as described in claim 1, characterized in that, The process involves establishing a dynamic mapping relationship between the historical write refresh parameters and the optimized test sequence to obtain historical parameter-sequence dynamic mapping data. This is followed by acquiring test principle data and test process data for the target DDR5 memory module from the test equipment. Based on this historical parameter-sequence dynamic mapping data, test principle data, and test process data, a test sequence optimization platform for the target DDR5 memory module is constructed. Specifically: The optimized test sequences generated under different historical write-refresh parameters are associated with the corresponding historical write-refresh parameters to establish a parameter-sequence dynamic mapping table and obtain historical parameter-sequence dynamic mapping data. Obtain test principle data and test process data of the test equipment on the target DDR5 memory module; A virtual timing simulation model of DDR5 memory and test equipment is constructed. Based on the test principle data, bank grouping constraints and refresh cycle limits are applied to the virtual timing simulation model. The virtual data channel between the test equipment and DDR5 memory is configured to generate a timing interaction simulation environment between the test equipment and DDR5 memory. Based on the historical parameter-sequence dynamic mapping data and test principle data, the timing interactive simulation environment is iteratively trained and the parameters are tuned to obtain the test sequence optimization platform for the test equipment on the target DDR5 memory module.

5. The parallel test sequence optimization method for DDR5 memory write refresh operations as described in claim 4, characterized in that, The test principle data includes the bank grouping architecture of DDR5 memory, refresh command timing specifications, write operation voltage threshold, bank conflict avoidance mechanism, and data link protocol between the test equipment and DDR5 memory.

6. The parallel test sequence optimization method for DDR5 memory write refresh operations as described in claim 1, characterized in that, The process of obtaining the current operating parameter data of the target DDR5 memory module and importing it into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module to obtain a predicted optimization test sequence is as follows: Obtain data on the impact of temperature changes on bank timing parameters of the target DDR5 memory module, and obtain data on the correlation between operating voltage fluctuations and refresh error rate; The current operating parameter data of the target DDR5 memory module is obtained, and the current operating parameter data is used as the real-time test parameter data of the test device on the target DDR5 memory module. The real-time test parameter data is imported into the test sequence optimization platform to perform virtual timing simulation on the current write latency and refresh error rate of the target DDR5 memory module to obtain the initial predicted test sequence. Obtain the current operating temperature data and current operating voltage data of the target DDR5 memory module, determine the bank timing offset based on the current operating temperature data and current operating voltage data, and calculate the timing compensation coefficient based on the bank timing offset and associated data; The initial prediction test sequence is dynamically adjusted according to the time-series compensation coefficient; The adjusted predictive test sequence is matched and verified with the historical write latency data and historical refresh error rate data of the target DDR5 memory module under normal working and fault conditions. Abnormal bank groups and conflict risk levels of the target DDR5 memory module are identified to obtain the predictive optimized test sequence.

7. The parallel test sequence optimization method for DDR5 memory write refresh operations as described in claim 1, characterized in that, The step of determining the actual test plan for the target DDR5 memory module using the test equipment based on the predicted and optimized test sequence is as follows: Based on the predicted and optimized test sequence, if the conflict risk level is low, the number of bank group tests and the frequency of refresh command tests on the target DDR5 memory module by the test equipment will be reduced. If the conflict risk level is medium or high, the test bank group range of the test equipment for the target DDR5 memory module is determined according to the abnormal bank group identifier and the conflict risk level. The test timing window and test bandwidth weight of each bank group are allocated based on the bank group priority matrix to obtain the actual test plan of the test equipment for the target DDR5 memory module.

8. A parallel test sequence optimization system for DDR5 memory write refresh operations, characterized in that, The system includes: The data acquisition module is used to acquire historical write refresh parameters, historical write latency data, and historical refresh error rate data of the target DDR5 memory module under normal working and fault conditions through the test equipment, and to perform conflict detection and redundancy elimination on the historical write latency data and historical refresh error rate data. The modeling and rearrangement module is used to analyze the bank grouping structure, refresh cycle constraints and write command dependencies of the target DDR5 memory module based on the historical write refresh parameters, generate a bank-level parallel test sequence optimization model, and rearrange the historical write latency data and historical refresh error rate data according to the bank-level parallel test sequence optimization model to obtain an optimized test sequence. The platform construction module is used to form a dynamic mapping relationship between the historical write refresh parameters and the optimized test sequence to obtain historical parameter-sequence dynamic mapping data, acquire the test principle data and test process data of the test equipment for the target DDR5 memory module, and construct the test sequence optimization platform of the test equipment for the target DDR5 memory module based on the historical parameter-sequence dynamic mapping data, test principle data and test process data. The simulation prediction module is used to obtain the current operating parameter data of the target DDR5 memory module, import the current operating parameter data into the test sequence optimization platform to perform virtual timing simulation on the target DDR5 memory module, and obtain the prediction optimization test sequence; The scheme generation module is used to determine the actual test scheme of the test equipment for the target DDR5 memory module based on the predicted optimized test sequence.

9. A parallel test sequence optimization device for DDR5 memory write refresh operations, characterized in that, The device includes: a memory, a processor, and a parallel test sequence optimization program for DDR5 memory write refresh operations stored on the memory and executable on the processor, the parallel test sequence optimization program for DDR5 memory write refresh operations being configured to implement the steps of the parallel test sequence optimization method for DDR5 memory write refresh operations as described in any one of claims 1 to 7.

10. A medium, characterized in that, The medium stores a parallel test sequence optimization program for DDR5 memory write-refresh operations. When the processor executes the parallel test sequence optimization program for DDR5 memory write-refresh operations, it implements the steps of the parallel test sequence optimization method for DDR5 memory write-refresh operations as described in any one of claims 1 to 7.

Images