Defect screening method, controller, medium and product

Abstract

The invention provides a defect screening method, a controller, a medium and a product, applied to the technical field of electronic chips and applied to a defect screening system.The method comprises the steps that first feature data and a refresh time parameter of a to-be-tested chip are obtained; writing the first feature data into the to-be-tested chip to obtain the to-be-tested chip with the written feature data; modifying and adjusting the refresh time parameter of the chip to be tested to obtain a refresh configuration parameter; testing the to-be-tested chip according to the refresh configuration parameter to obtain second feature data; and performing comparison according to the first feature data and the second feature data to obtain a comparison result, and performing defect screening according to the comparison result. According to the method and the device, the comparison result can be obtained by comparing the second feature data obtained by testing the to-be-tested chip after the refresh time parameter is modified and adjusted with the written first feature data, and defect screening is performed according to the comparison result, so that defect screening of the storage chip is realized, and the product quality is improved.

Description

Technical Field

[0001] This application relates to the field of electronic chip technology, and in particular to a defect screening method, controller, medium, and product. Background Technology

[0002] In related technologies, some defects are inevitably introduced during the production and manufacturing of DRAM memory chips. Therefore, a key technology in its testing is to screen out damaged or potentially damaged memory cells through testing and mark their corresponding DRAM memory chips as defective products.

[0003] The current method involves reading and writing to the address space of the DRAM chip and comparing the read data to determine if there are any damaged memory cells. However, this method is prone to omissions, resulting in some defects not being effectively detected and defective products reaching end users. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a defect screening method, controller, medium, and product, designed to achieve defect screening of memory chips, thereby improving product quality.

[0005] In a first aspect, embodiments of this application provide a defect screening method applied to a defect screening system. The defect screening system includes a test board and a chip under test (DUT). The test board is connected to the DUT and is used to perform defect testing on the DUT. The method includes: Acquire the first feature data and the refresh time parameter of the chip under test; The first feature data is written into the chip under test to obtain the chip under test with the feature data written in it. The refresh time parameter of the chip under test is modified and adjusted to obtain the refresh configuration parameter; The chip under test is tested according to the refresh configuration parameters to obtain the second feature data; The first feature data and the second feature data are compared to obtain a comparison result, which is then used to screen for defects.

[0006] According to some embodiments of this application, the defect screening system further includes a heating device for heating the chip under test, and the method further includes: The chip under test is heated by the heating device.

[0007] According to some embodiments of this application, the step of modifying and adjusting the refresh time parameter of the chip under test to obtain refresh configuration parameters includes: Obtain the current temperature of the chip under test; The refresh time parameter is modified and adjusted according to the current temperature to obtain the refresh configuration parameter.

[0008] According to some embodiments of this application, the step of modifying and adjusting the refresh time parameter based on the current temperature to obtain the refresh configuration parameter includes: When the current temperature is within the first temperature range, the refresh time parameter is modified and adjusted to the first time parameter, and the first time parameter is used as the refresh configuration parameter; When the current temperature is within the second temperature range, the refresh time parameter is modified and adjusted to the second time parameter, and the second time parameter is used as the refresh configuration parameter; When the current temperature is within the third temperature range, the refresh time parameter is modified and adjusted to the third time parameter, and the third time parameter is used as the refresh configuration parameter.

[0009] According to some embodiments of this application, the step of comparing the first feature data and the second feature data to obtain a comparison result, and then using the comparison result for defect screening, includes: The number of error bits is obtained by performing an XOR operation on the first feature data and the second feature data. Defect screening is performed based on the number of error bits.

[0010] According to some embodiments of this application, the defect screening based on the number of error bits includes: When the number of error bits is less than or equal to the first threshold, it is determined that the chip under test has no defects; When the number of error bits is greater than the second threshold, it is determined that the chip under test has a hard defect.

[0011] According to some embodiments of this application, the method further includes: Decode the address of the second feature data; If the address decoding of the second feature data is incorrect, it is determined that the chip under test has a systemic defect.

[0012] Secondly, embodiments of this application provide a controller, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the defect screening method described in the first aspect when running the computer program.

[0013] Thirdly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions for performing the defect screening method as described in the first aspect above.

[0014] Fourthly, embodiments of this application provide a computer program product, including a computer program or computer instructions, wherein the computer program or computer instructions are stored in a computer-readable storage medium, a processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, causing the computer device to perform the defect screening method as described in the first aspect above.

[0015] According to the technical solution of the embodiments of this application, at least the following beneficial effects are achieved: This application proposes a defect screening method, controller, medium, and product, applied in the field of electronic chip technology, and applied to a defect screening system. The defect screening system includes a test board and a chip under test (DUT). The test board is connected to the DUT and is used to perform defect testing on the DUT. The method includes: acquiring first feature data and refresh time parameters of the DUT; writing the first feature data into the DUT to obtain a DUT with written feature data; modifying and adjusting the refresh time parameters of the DUT to obtain refresh configuration parameters; testing the DUT according to the refresh configuration parameters to obtain second feature data; comparing the first feature data and the second feature data to obtain a comparison result, and performing defect screening based on the comparison result. Because this application can compare the second feature data obtained by testing the DUT with the first feature data after modifying and adjusting the refresh time parameters with the written first feature data to obtain a comparison result, and perform defect screening based on the comparison result, it can achieve defect screening of memory chips and improve product quality.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0018] Figure 1 This is a schematic diagram of the structure of a defect screening system provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a defect screening system provided in another embodiment of this application; Figure 3 This is a flowchart of a defect screening method provided in one embodiment of this application; Figure 4 yes Figure 3 The flowchart of a sub-step of step S130 is shown below; Figure 5 yes Figure 3 The flowchart of a sub-step of step S150 is shown below; Figure 6 This is a flowchart of a defect screening method provided in an overall embodiment of this application; Figure 7 This is a flowchart of a defect screening method provided in another overall embodiment of this application; Figure 8 This is a schematic diagram of a controller for performing a defect screening method according to an embodiment of this application. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0022] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0023] In some cases, defects are inevitably introduced during the manufacturing of DRAM memory chips. Therefore, a key technology in its testing is to screen out damaged or potentially damaged memory cells through testing and mark their corresponding DRAM memory chips as defective products.

[0024] The current method involves reading and writing to the address space of the DRAM chip and comparing the read data to determine if there are any damaged memory cells. However, this method is prone to omissions, resulting in some defects not being effectively detected and defective products reaching end users.

[0025] Based on the above, this application proposes a defect screening method, controller, medium, and product, aiming to achieve defect screening of memory chips, thereby improving product quality.

[0026] The various embodiments of the defect screening system of this application will be further described below with reference to the accompanying drawings.

[0027] like Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of the structure of a defect screening system provided in one embodiment of this application; Figure 2 This is a schematic diagram of the defect screening system provided in another embodiment of this application.

[0028] In one embodiment, the defect screening system includes a test board 100 and a chip under test 200. The test board 100 is connected to the chip under test 200 and is used to perform defect testing on the chip under test 200.

[0029] Understandably, the defect screening system also includes a heating device 300 for heating the chip 200 to be tested.

[0030] Understandably, the test board 100 includes a power module and a test controller SOC.

[0031] Understandably, this application uses a test board 100 to connect to the chip under test 200, thereby enabling the execution of corresponding software algorithms. The external heating device 300 is used to heat the chip under test 200 separately, taking advantage of the different characteristics exhibited by the chip under test 200 at high temperatures, which is more conducive to the effective functioning of the software algorithms.

[0032] Based on the defect screening system of the above embodiments, the following are various embodiments of the defect screening method of this application.

[0033] like Figure 3 As shown, Figure 3 This is a flowchart of a defect screening method provided in one embodiment of this application; the defect screening method may include, but is not limited to, steps S110, S120, S130, S140 and S150.

[0034] Step S110: Obtain the first feature data and the refresh time parameter of the chip under test; Step S120: Write the first feature data into the chip under test to obtain the chip under test with the feature data written. Step S130: Modify and adjust the refresh time parameters of the chip under test to obtain refresh configuration parameters; Step S140: Test the chip under test according to the refresh configuration parameters to obtain the second feature data; Step S150: Compare the first feature data and the second feature data to obtain the comparison results, and then use the comparison results to screen for defects.

[0035] In one embodiment, first feature data and refresh time parameters of the chip under test (DUT) are obtained; the first feature data is written to the DUT to obtain a DUT with written feature data; the refresh time parameters of the DUT are modified and adjusted to obtain refresh configuration parameters; the DUT is tested according to the refresh configuration parameters to obtain second feature data; the first feature data and the second feature data are compared to obtain a comparison result, which is used for defect screening. Because this application can compare the second feature data obtained by testing the DUT with the modified refresh time parameters with the written first feature data to obtain a comparison result, and then use the comparison result for defect screening, it achieves defect screening of memory chips and improves product quality.

[0036] It is understandable that, due to the influence of the manufacturing process, the actual refresh interval required for different memory cells of the chip under test is different, with some being longer and others shorter. Although the protocol specifies the interval for automatic refresh time, theoretically, chips with a refresh interval longer than the specified interval are considered good products. However, exceptions occur in actual engineering applications. Therefore, this application obtains refresh configuration parameters by modifying and adjusting the refresh time parameters of the chip under test, which can accelerate the screening process and improve efficiency when testing the chip under test.

[0037] It is understandable that refreshing configuration parameters is related to the specific chip product model under test and the type of test board.

[0038] It is understandable that when the chip under test has its automatic refresh function enabled, heating the chip under test with a heating device can speed up the refresh of configuration parameters, thereby accelerating the screening process and improving efficiency.

[0039] In addition, such as Figure 4 As shown, Figure 4 yes Figure 3 The flowchart of a sub-step of step S130 is shown; step S130 may include, but is not limited to, steps S210 and S220.

[0040] Step S210: Obtain the current temperature of the chip under test; Step S220: Modify and adjust the refresh time parameter according to the current temperature to obtain the refresh configuration parameter.

[0041] It is understandable that when the chip under test has its automatic refresh function enabled, heating the chip under test with a heating device can speed up the refresh of configuration parameters, thereby accelerating the screening process and improving efficiency.

[0042] It is understood that the refresh configuration parameters of the chip under test are related to the current temperature, and this application embodiment does not specifically limit them.

[0043] Understandably, if the current temperature is within the first temperature range, the refresh time parameter is modified and adjusted to the first time parameter, and the first time parameter is used as the refresh configuration parameter; if the current temperature is within the second temperature range, the refresh time parameter is modified and adjusted to the second time parameter, and the second time parameter is used as the refresh configuration parameter; if the current temperature is within the third temperature range, the refresh time parameter is modified and adjusted to the third time parameter, and the third time parameter is used as the refresh configuration parameter.

[0044] It is understood that the aforementioned first temperature range can be a high temperature range, and can be set according to actual conditions. This application embodiment does not specifically limit it.

[0045] It is understood that the second temperature range mentioned above can be a normal temperature range, and can be set according to the actual situation. This application embodiment does not specifically limit it.

[0046] It is understood that the aforementioned third temperature range can be a low temperature range, and can be set according to actual conditions. This application embodiment does not specifically limit it.

[0047] It is understood that the refresh configuration parameters corresponding to normal temperature, high temperature and low temperature can be set according to actual needs, and this application embodiment does not impose specific limitations on them.

[0048] In addition, such as Figure 5 As shown, Figure 5 yes Figure 3 The flowchart shows a sub-step of step S150; step S150 may include, but is not limited to, steps S310 and S320.

[0049] Step S310: Perform an XOR operation on the first feature data and the second feature data to obtain the number of error bits; Step S320: Screen defects based on the number of error bits.

[0050] It is understandable that if the number of error bits is less than or equal to the first threshold, the chip under test has no defects; if the number of error bits is greater than the second threshold, it indicates that the chip under test has a hard defect; thus, defect screening of the chip under test is achieved through the first feature data and the second feature data.

[0051] It is understandable that this application will also perform address decoding on the second feature data. If the address decoding of the second feature data is incorrect, it indicates that the chip under test has a systemic defect.

[0052] Based on the defect screening methods of the above embodiments, the following presents an overall embodiment of the defect screening method of this application.

[0053] like Figure 6 As shown, Figure 6 This is a flowchart of a defect screening method provided in an overall embodiment of this application; Using a dedicated software algorithm, we write our custom data, such as 0xff00ff00 or other first feature data containing feature numbers. Then, through the host computer software, we send the refresh time parameter that we need to modify to the test controller SOC, which then executes the action to adjust the refresh time parameter. After the modification is completed, and after a certain delay, the data is read back to determine if there are any defects.

[0054] In addition, such as Figure 7 As shown, Figure 7 This is a flowchart of a defect screening method provided in another overall embodiment of this application.

[0055] This application utilizes the high temperature of the heating device to accelerate the refresh time parameter refresh process, thereby speeding up the screening process and improving efficiency.

[0056] Taking LPDDR4 chips as an example, the protocol specifies an automatic refresh interval of 32ms, meaning that a full-space automatic refresh operation must be completed every 32ms. This behavior is performed automatically in the background after the LPDDR4 automatic refresh function is enabled. Under high temperatures, this interval will become 16ms or 8ms.

[0057] If the automatic refresh function is disabled, data loss will inevitably occur over time, leading to anomalies. By comparing and analyzing the performance of different chips at different temperatures, the pattern of the required automatic refresh time for DRAM chips can be derived. The changes at room temperature and high / low temperatures are not linear and each has its own pattern, but generally speaking, as the temperature increases, the required automatic refresh interval becomes shorter and shorter.

[0058] By using data derived from theoretical and practical analysis, some parameters can be obtained to effectively test the interval of automatic refresh time.

[0059] Traditional testing methods cannot effectively detect such defects because the automatic refresh function runs in the background.

[0060] Using a heating device can shorten testing time and improve efficiency.

[0061] It is worth noting that this application, through a heating device and a specially developed algorithm, can solve the problems of omission and misplacement that occur in current methods, effectively improving the coverage of defect screening and enhancing product quality.

[0062] Based on the defect screening methods of the above embodiments, the following presents various embodiments of the controller, computer-readable storage medium, and computer program product of this application.

[0063] like Figure 8 As shown, Figure 8 This is a schematic diagram of a controller for performing a defect screening method according to an embodiment of this application. The controller 700 implemented in this application includes: a processor 710, a memory 720, and a computer program stored in the memory 720 and executable on the processor 710, wherein... Figure 8 The example uses a processor 710 and a memory 720.

[0064] The processor 710 and memory 720 can be connected via a bus or other means. Figure 8 Taking the example of a connection between China and Israel via a bus.

[0065] Memory 720, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory 720 may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory 720 may optionally include remotely located memories 720 relative to processor 710, which can be connected to controller 700 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0066] Those skilled in the art will understand that Figure 8 The device structure shown does not constitute a limitation on the controller 700 and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0067] exist Figure 8In the controller 700 shown, the processor 710 can be used to call the control program stored in the memory 720 to implement the defect screening method described above. Specifically, the non-transitory software program and instructions required to implement the defect screening method of the above embodiment are stored in the memory 720, and when executed by the processor 710, the defect screening method of the above embodiment is executed.

[0068] It is worth noting that since the controller 700 of this application embodiment can execute the defect screening method of any of the above embodiments, the specific implementation method and technical effect of the controller 700 of this application embodiment can refer to the specific implementation method and technical effect of the defect screening method of any of the above embodiments.

[0069] Furthermore, one embodiment of this application provides a computer-readable storage medium storing computer-executable instructions for performing the defect screening method described above. Exemplarily, the above-described method is executed... Figures 3 to 7 The methods and steps in the text.

[0070] It is worth noting that, since the computer-readable storage medium of this application embodiment can execute the defect screening method of any of the above embodiments, the specific implementation and technical effects of the computer-readable storage medium of this application embodiment can be referred to the specific implementation and technical effects of the defect screening method of any of the above embodiments.

[0071] Furthermore, one embodiment of this application also provides a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. A processor of a computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform the defect screening method described above. Exemplarily, the above-described method is performed... Figures 3 to 7 The methods and steps in the text.

[0072] It is worth noting that, since the computer program product of this application embodiment can execute the defect screening method of any of the above embodiments, the specific implementation method and technical effect of the computer program product of this application embodiment can refer to the specific implementation method and technical effect of the defect screening method of any of the above embodiments.

[0073] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0074] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0075] In the several embodiments provided in this application, it should be understood that the disclosed systems, instruments, and methods can be implemented in other ways. For example, the instrument embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between instruments or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0076] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0077] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A defect screening method, characterized in that, An application is made in a defect screening system, the defect screening system including a test board and a chip under test (DUT), the test board being connected to the DUT, the test board being used to perform defect testing on the DUT, the method including: Acquire the first feature data and the refresh time parameter of the chip under test; The first feature data is written into the chip under test to obtain the chip under test with the feature data written in it. The refresh time parameter of the chip under test is modified and adjusted to obtain the refresh configuration parameter; The chip under test is tested according to the refresh configuration parameters to obtain the second feature data; The first feature data and the second feature data are compared to obtain a comparison result, which is then used to screen for defects.

2. The method according to claim 1, characterized in that, The defect screening system further includes a heating device for heating the chip under test, and the method further includes: The chip under test is heated by the heating device.

3. The method according to claim 2, characterized in that, The step of modifying and adjusting the refresh time parameter of the chip under test to obtain refresh configuration parameters includes: Obtain the current temperature of the chip under test; The refresh time parameter is modified and adjusted according to the current temperature to obtain the refresh configuration parameter.

4. The method according to claim 3, characterized in that, The step of modifying and adjusting the refresh time parameter according to the current temperature to obtain the refresh configuration parameters includes: When the current temperature is within the first temperature range, the refresh time parameter is modified and adjusted to the first time parameter, and the first time parameter is used as the refresh configuration parameter; When the current temperature is within the second temperature range, the refresh time parameter is modified and adjusted to the second time parameter, and the second time parameter is used as the refresh configuration parameter; When the current temperature is within the third temperature range, the refresh time parameter is modified and adjusted to the third time parameter, and the third time parameter is used as the refresh configuration parameter.

5. The method according to claim 1, characterized in that, The step of comparing the first feature data and the second feature data to obtain a comparison result, and then using the comparison result to perform defect screening, includes: The number of error bits is obtained by performing an XOR operation on the first feature data and the second feature data. Defect screening is performed based on the number of error bits.

6. The method according to claim 5, characterized in that, The defect screening based on the number of error bits includes: When the number of error bits is less than or equal to the first threshold, it is determined that the chip under test has no defects; When the number of error bits is greater than the second threshold, it is determined that the chip under test has a hard defect.

7. The method according to claim 1, characterized in that, The method further includes: Decode the address of the second feature data; If the address decoding of the second feature data is incorrect, it is determined that the chip under test has a systemic defect.

8. A controller, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, performs the defect screening method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: The device stores computer-executable instructions for performing the defect screening method as described in any one of claims 1 to 7.

10. A computer program product, comprising a computer program or computer instructions, characterized in that, The computer program or the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer program or the computer instructions from the computer-readable storage medium and executes the computer program or the computer instructions, causing the computer device to perform the defect screening method as described in any one of claims 1 to 7.

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