Grid-controlled semiconductor depletion layer modulation vacuum variable capacitor and preparation method thereof

Abstract

The invention relates to the technical field of variable capacitors, and discloses a grid-controlled semiconductor depletion layer modulation vacuum variable capacitor and a preparation method thereof, and the capacitor comprises an upper electrode which is made of high-purity oxygen-free copper and has a rounding edge structure; the lower electrode is made of oxygen-free copper and also serves as a mechanical support and a heat sink; the vacuum insulating layer is arranged between the upper electrode and the lower electrode; the semiconductor layer is N-type monocrystalline silicon, the thickness of the semiconductor layer is 200 micrometers, the resistivity of the semiconductor layer is 4-6, and impurity concentration of the semiconductor layer is 4-6. According to the invention, the high-voltage-withstanding vacuum gap capacitor and the semiconductor depletion layer capacitor based on MOS gate voltage regulation and control are connected in series and integrated, so that the single device has high-voltage insulation and rapid electric regulation capabilities at the same time creatively; the capacitance value can be continuously and accurately adjusted in the order of tens of nanoseconds to microseconds only by applying a small-amplitude low-voltage signal.

Description

Technical Field

[0001] This invention relates to the field of variable capacitor technology, and in particular to a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor and its fabrication method. Background Technology

[0002] Currently, there are two main technical approaches in the field of high voltage adjustable capacitors: mechanical vacuum variable capacitors have the advantages of high voltage resistance and high power, but their capacitance adjustment depends on mechanical drive, which has problems such as slow response speed (more than milliseconds), mechanical wear, limited lifespan, and difficulty in integrating into automated control. On the other hand, although varactor diodes based on semiconductor PN junctions can achieve fast voltage adjustment (nanosecond level), their inherent voltage withstand capability is low (usually below 100 volts), and there is an inherent contradiction between the capacitor tuning range and the voltage withstand capability, which completely fails to meet the needs of high voltage application scenarios of several kilovolts. Summary of the Invention

[0003] This invention provides a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor and its fabrication method to solve existing technical problems, thereby addressing the issues of slow response in traditional mechanical vacuum variable capacitors and insufficient voltage withstand capability of semiconductor varactor diodes.

[0004] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor, comprising: The upper electrode is made of high-purity oxygen-free copper and has a rounded edge structure; The lower electrode is made of oxygen-free copper and serves as both a mechanical support and a heat sink. A vacuum insulation layer is disposed between the upper and lower electrodes, and the vacuum gap is... for ; The semiconductor layer is made of N-type single-crystal silicon, with a thickness of 200 μm and a resistivity of 4-6. impurity concentration ; The gate oxide layer, located above the semiconductor layer, is thermally grown SiO2 with a thickness of [missing information]. ; The gate, located above the gate oxide layer, is a ring-shaped aluminum electrode with an inner diameter of 15 mm and an outer diameter of 25 mm. The ceramic shell is made of 95% Made of ceramic, used for hermetic sealing; A high voltage is applied between the upper electrode and the lower electrode. (DC voltage), a control voltage is applied between the gate and the lower electrode. (DC voltage), by changing the control voltage Modulation semiconductor depletion layer width To achieve the overall Continuous electronic adjustment of capacitors; The total capacitance Vacuum gap capacitor With semiconductor depletion layer capacitance They are connected in series and satisfy the following formula: ; And there are: , ; In the above formula, A is the effective area between the upper and lower electrodes. ; The capacitor has a capacitance tuning range of 44pF to 77pF, a tuning ratio of 1.75:1, and a maximum energy storage of 0.96mJ.

[0005] Furthermore, the edge rounding radius of the upper electrode is 2.0 mm, the effective diameter is 35.7 mm, and the thickness is 1.0 mm.

[0006] Furthermore, the semiconductor layer in A strong inversion layer is formed on the lower surface under the action of the action, which is equivalent to a metal electrode. The thin-film resistance of the inversion layer is .

[0007] Furthermore, the vacuum degree of the vacuum gap on the vacuum insulation layer is better than... Average electric field strength Maximum electric field strength .

[0008] Furthermore, the gate is modulated with respect to the depletion layer width via a MOS structure. The response time is determined by the dielectric relaxation time, and the theoretical electronic speed is in the range of nanoseconds to microseconds.

[0009] A method for fabricating a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor specifically includes: S1. Semiconductor substrate preparation: N-type single-crystal silicon wafers are used, and the substrates undergo cleaning and surface quality control. S2. Front-side MOS structure fabrication, including dry oxygen thermal growth of gate oxide layer, aluminum evaporation and photolithography to form ring gate, and annealing; S3. Backside metallization and treatment, including thinning and polishing, ion implantation to form an ohmic contact layer, evaporation of a Ti / Pt / Au composite metal layer and annealing; S4. Upper electrode preparation: oxygen-free copper is used to process a disk electrode with rounded edges, and the surface is polished and plated with nickel. S5. Ceramic shell preparation, including processing alumina ceramic rings and end-face metallization treatment; S6. Precision assembly and vacuum packaging: using precision gaskets to control the vacuum gap, employing brazing technology for hermetic sealing, and maintaining high vacuum through getter.

[0010] Furthermore, the vacuum gap This is achieved using precision ceramic or metal gaskets, with the gasket thickness tolerance controlled within [specific tolerance range]. Within this range, the parallelism is better than .

[0011] Furthermore, the brazing employs... or Eutectic brazing is performed in a vacuum or reducing atmosphere, and the vacuum level of the cavity after brazing is better than that of other materials. .

[0012] Furthermore, the thickness of the gate oxide layer is The material was grown at 1050℃ for 30 minutes using a dry oxygen thermal growth process, with thickness uniformity controlled within a certain range. Within.

[0013] Furthermore, all internal components undergo ultra-clean treatment before assembly, with surface particle sizes larger than [missing information]. The number of particles is less than 10 per piece, and the cleanliness of the assembly environment is not lower than ISO 5 level.

[0014] This invention provides a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor and its fabrication method. Compared with the prior art, the advantages achieved by this method are: 1. This invention creatively integrates a high-voltage vacuum gap capacitor with a semiconductor depletion layer capacitor based on MOS gate voltage regulation in series, achieving both high-voltage insulation and rapid voltage adjustment capabilities within a single device. This structure enables the device to withstand thousands of volts of DC high voltage while continuously and precisely adjusting the capacitance value within tens of nanoseconds to microseconds by applying only a small low-voltage signal. This effectively solves the inherent technical contradiction between the slow response of traditional mechanical vacuum variable capacitors and the insufficient voltage withstand capability of semiconductor varactor diodes, thus broadening the application boundaries of variable capacitor technology in high-voltage and high-frequency fields.

[0015] 2. This invention benefits from the rounded edge design of the upper electrode and the high-vacuum insulating medium, which significantly improves the electric field distribution at the electrode edge and controls the maximum field strength within a safe threshold. Combined with the low-outgassing oxygen-free copper electrode and hermetic ceramic encapsulation, this ensures the insulation reliability and stability of the device under long-term high-voltage operation, effectively suppressing the risks of field emission and gas breakdown, and providing a guarantee for the device's long-term operation in harsh environments.

[0016] 3. The present invention utilizes the strong inversion layer induced on the semiconductor surface by the high-voltage main circuit as an equivalent electrode, enabling capacitance modulation to no longer rely on the slow generation and recombination process of carriers, but to be achieved through the multi-carrier response mechanism of controlling the depletion layer width by the gate voltage. This principle endows capacitance tuning with theoretically high-speed response characteristics, and the tuning process is continuous, smooth, and free from mechanical wear, greatly enhancing the service life, adjustment accuracy, and dynamic performance of the device.

[0017] 4. The precision preparation method supporting the present invention forms a complete and controllable manufacturing process from semiconductor technology, gap control, vacuum packaging to clean environment management. By accurately controlling key process parameters, such as the vacuum gap tolerance, gate oxide thickness uniformity, and the final cavity vacuum degree, it ensures that each device can reproduce the designed electrical performance and insulation index, laying a solid process foundation for the engineering mass production and practical application of this high-performance device. Brief Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of the present invention.

[0019] In the figure: 1. Upper electrode; 2. Lower electrode; 3. Ceramic shell; 4. Semiconductor layer; 5. Gate oxide layer; 6. Gate electrode; 7. Vacuum insulation layer. Detailed Embodiment

[0020] To make the technical solution of the present invention clearer, the following further elaborates on the present invention in detail with reference to the accompanying drawings and specific embodiments.

[0021] To make the technical solution of the present invention clearer, the following further elaborates on the present invention in detail with reference to the accompanying drawings and specific embodiments. <着

[0022] Embodiment 1 As Figure 1 shown, a gate-controlled semiconductor depletion layer modulation vacuum variable capacitor, whose core structure is as Figure 1 shown, includes an upper electrode 1, a lower electrode 2, a ceramic shell 3, a semiconductor layer 4, a gate oxide layer 5, a gate electrode 6, and a vacuum insulation layer 7.

[0023] The device design of this embodiment is based on rigorous theoretical calculations and multi-physics field simulations. The specific key parameters and design bases are as follows: 1. Electrical and geometric specifications: Operating voltage: The high voltage applied between the upper electrode 1 and the lower electrode 2 in the main circuit is 5.0 kV (DC voltage). This voltage value ensures high energy storage capacity while providing sufficient safety margin for vacuum gap insulation.

[0024] Control voltage: The control voltage applied in the control loop, i.e., between gate 6 and common lower electrode 2. The voltage is 0V to -20V DC. This is the standard MOS gate voltage range, ensuring safety, reliability, and ease of driving.

[0025] Capacitor resonance: by changing Total capacitance of the device It can be continuously electrically adjusted within the range of 44pF to 77pF, with a tuning ratio of 1.75:1. This data is extracted and verified based on electromagnetic simulation software (such as ANSYS Q3D).

[0026] Maximum energy storage: The maximum energy storage of the device at its maximum capacitance (77pF) and rated operating voltage (5kV). The value is 0.96 mJ, and its calculation formula is: .

[0027] Electrodes and gap: The effective area A between the upper electrode 1 and the lower electrode 2 is... (Corresponding to an effective diameter of 35.7 mm for the circular electrode). The vacuum gap between the two. The tolerance is 100.0 pm, controlled by precision gaskets, within [specific tolerance range]. Within this range. This gap determines the fixed capacitor. The core parameters of insulation strength.

[0028] Upper electrode optimization: The upper electrode 1 is made of high-purity oxygen-free copper, and its edges are rounded with a radius of 2.0 mm. This design effectively suppresses edge electric field concentration. Simulation verification shows that it can reduce the maximum electric field intensity. Controlled The following values ​​are significantly lower than the vacuum gas breakdown value, ensuring high-voltage insulation safety (average electric field strength). ).

[0029] 2. Semiconductor and MOS structures: Semiconductor layer 4: Made of N-type single-crystal silicon, with a thickness of 200 μm and a resistivity of 4-6. (corresponding doping concentration) This thickness is much greater than the maximum depletion layer width (approximately 10 μm), which prevents penetration during operation.

[0030] Gate oxide layer 5: A thermally grown silicon dioxide (SiO2) layer with a thickness of [insert thickness here]. The wavelength is 50.0 nm, and the uniformity is controlled at... Within this range. This thickness provides good insulation while ensuring sufficient gate control capability.

[0031] Gate 6: A ring-shaped aluminum electrode, defined by photolithography, with an inner diameter of 15mm, an outer diameter of 25mm, and a thickness of approximately 0.5um. The shape design ensures uniform control of the gate voltage on the semiconductor surface potential.

[0032] Working mechanism: When After application, a strong inversion layer forms on the semiconductor surface due to the strong electric field, and the charge on this thin layer can be as low as [value missing]. This can be equivalent to a metal electrode, forming a parallel-plate capacitor with the upper electrode 1 using a vacuum gap as the dielectric, together with the upper electrode 1. Simultaneously, the applied grid voltage... Modulating the width of the depletion layer in the semiconductor bulk using MOS structure Due to the total capacitance It is a vacuum capacitor With depletion layer capacitance The series connection thus changes It can be continuously adjusted This modulation process depends on the redistribution of majority carriers, and the response speed is determined by the dielectric relaxation time (approximately...). According to the calculation, the theoretical speed regulation can reach the nanosecond to microsecond level.

[0033] 3. Encapsulation and insulation Ceramic housing 3: Made of 95% alumina ceramic, providing mechanical support and enabling gas-tight encapsulation.

[0034] Vacuum insulation layer 7: After encapsulation, the vacuum level inside the cavity is better than... This is to eliminate gas discharge and ensure reliable insulation under high voltage.

[0035] The innovation of this embodiment lies in electrically connecting a high-voltage-resistant vacuum dielectric with a rapidly adjustable semiconductor MOS structure and structurally integrating them. The principle is as follows: in the high-voltage main circuit (between the upper and lower electrodes), a vacuum gap is used to withstand a high electric field (average 50 MV / m) and achieve insulation. Simultaneously, this high voltage induces a strong inversion layer on the semiconductor surface, serving as an equivalent upper electrode. In the low-voltage control circuit (between the gate and lower electrode), the MOS gate voltage is used to precisely modulate the width of the semiconductor depletion layer, thereby changing the depletion layer capacitance value connected in series with the vacuum capacitor, achieving continuous electrical adjustment of the total capacitance. The advantages of this design are that it simultaneously achieves high-voltage withstand (5 kV), rapid electrical adjustment (nanosecond to microsecond level), and continuous adjustability (44-77 pF), resolving the technical contradictions of slow adjustment speed in traditional mechanical vacuum variable capacitors and the low voltage withstand capability of semiconductor varactor diodes, which prevent their use in high-voltage applications.

[0036] Example 2 The fabrication method of the device in this embodiment covers the following key steps to ensure device performance and reliability: Step 1: Semiconductor substrate preparation Double-sided polished N-type monocrystalline silicon wafers with a diameter of 100mm, a thickness of 200±10μm, and a resistivity of 4-6Ω·cm are selected. After standard RCA cleaning, the surface is ensured to be clean, with a warpage of <20μm and fewer than 10 surface particles (>0.3μm) per wafer.

[0037] Step 2: Fabrication of the front-side MOS structure Gate oxidation: A SiO2 layer is thermally grown in a dry oxygen atmosphere at 1050°C for about 30 minutes to form a gate oxide layer with a thickness of 50 nm and a uniformity of ±2 nm.

[0038] Gate formation: An aluminum film is deposited by electron beam evaporation, followed by photolithography and etching to form the specified ring gate pattern.

[0039] Annealing: during the formation of gas ( Annealing at 450°C for 30 minutes optimizes the Al / SiO2 interface properties.

[0040] Step 3, Backside Metallization and Processing The back side of the silicon wafer is thinned and polished to the target thickness.

[0041] Through ion implantation (e.g.) (or diffusion formation) Layers are used to prepare ohmic contacts.

[0042] Electron beam evaporation deposits a Ti / Pt / Au (50 / 100 / 300nm) composite metal layer, followed by rapid thermal annealing (400°C, 60s) to form a low-resistance ohmic contact, which will be connected to the lower electrode 2.

[0043] Step 4: Electrode and shell preparation Upper electrode 1: It is made of oxygen-free copper and precision machined into a disc with a 2.0mm rounded edge. The surface is polished to a roughness Ra<0.05μm and then electroplated with a 2-3μm nickel layer to prevent oxidation.

[0044] Lower electrode 2: Oxygen-free copper is also used as the substrate, serving as both mechanical support and heat sink.

[0045] Ceramic shell 3: Grind the end face of the 95% alumina ceramic ring to a parallelism of <5μm and metallize it (such as electroplating nickel after printing and sintering a molybdenum-manganese layer) to prepare for brazing.

[0046] Step 5: Precision assembly and vacuum packaging Gap control: A 100.0 μm thick ceramic or metal pad is placed on the lower electrode 2 to precisely set the vacuum gap. The gasket thickness tolerance is controlled within... Within this range, the parallelism is better than .

[0047] Assembly: The processed semiconductor wafer (face up), the pad, and the upper electrode 1 are stacked in the center and placed inside the ceramic shell.

[0048] Hermetically sealed packaging: Using AgCu28 or AuSn20 eutectic alloy, encapsulation is performed in a high-vacuum or reducing atmosphere needle furnace. The vacuum level of the cavity after brazing must be superior to [previous standard]. .

[0049] Cleanliness control: All internal components undergo ultra-clean treatment before assembly, and the cleanliness of the assembly environment is not lower than ISO 5 level to prevent particulate contamination from causing field emission.

[0050] Testing and Performance Verification After packaging, the device performance can be verified through the following tests: 1. Insulation test: Apply 5kV (DC voltage) between A and B; the leakage current should be less than 1nA (insulation resistance >5). ).

[0051] 2. Capacitance-Voltage (CV) Characteristic Test: Fixed ,scanning Measurements from 0V to -20V at a frequency of 1MHz A qualified device should exhibit a smooth CV curve, with the capacitance value continuously adjustable within the range of 44pF to 77pF.

[0052] Reliability verification: It can perform tests such as high temperature and high humidity storage (85℃ / 85%RH), temperature cycling (-55℃ to +125℃) and high voltage aging to ensure the long-term stability of the device.

[0053] Application Examples This capacitor can be used in applications requiring high voltage and fast capacitor tuning, such as: Automatic impedance matching network for high-voltage resonant power supplies. Utilizing as an adjustable energy storage element in a pulse forming network (PFN). A tunable element in a high-frequency high-voltage filter circuit.

[0054] When using it, a stable 0 to -20V adjustable low voltage source must be provided to the gate, and a series current-limiting resistor should be considered in the high voltage main circuit.

[0055] The innovation of this embodiment lies in providing a repeatable and high-precision fabrication and packaging process for the aforementioned high-performance devices. Its implementation principle involves using precision spacers (controlling...) Vacuum gap tolerance in Internal), dry oxygen thermal growth gate oxide (50 nm ± 2 nm), ultra-high vacuum brazing encapsulation (vacuum degree better than...) And ultra-clean control throughout the entire process (particles > 0.3). The combination of key processes (less than 10 pieces / piece, ISO 5 environmental standard) ensures the internal interface quality, insulation strength, capacitance consistency, and long-term reliability of the device. The advantage of this fabrication method is that it transforms high-performance, high-reliability electrical designs into manufacturable engineering prototypes. Strict process control points guarantee the stability and lifespan of the device under actual high-voltage operating environments, laying the foundation for industrialization.

[0056] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A gate-controlled semiconductor depletion layer modulated vacuum variable capacitor, characterized in that, include: The upper electrode (1) is made of high-purity oxygen-free copper and has a rounded edge structure; The lower electrode (2) is made of oxygen-free copper and serves as both a mechanical support and a heat sink. A vacuum insulating layer (7) is disposed between the upper electrode (1) and the lower electrode (2), and a vacuum gap is formed. for ; Semiconductor layer (4) is N-type single crystal silicon with a thickness of 200 μm and a resistivity of 4-6. impurity concentration ; The gate oxide layer (5), located above the semiconductor layer (4), is thermally grown SiO2 with a thickness of [missing information]. ; The gate (6) is located above the gate oxide layer (5) and is a ring aluminum electrode with an inner diameter of 15 mm and an outer diameter of 25 mm. The ceramic shell (3) is made of 95% Made of ceramic, used for hermetic sealing; A high voltage is applied between the upper electrode (1) and the lower electrode (2). A control voltage is applied between the gate (6) and the lower electrode (2). By changing the control voltage Modulation semiconductor depletion layer width To achieve the overall Continuous electronic adjustment of capacitors; The total capacitance Vacuum gap capacitor With semiconductor depletion layer capacitance They are connected in series and satisfy the following formula: ； And there are: ， ； In the above formula, A is the effective area between the upper electrode (1) and the lower electrode (2). ; The capacitor has a capacitance tuning range of 44pF to 77pF, a tuning ratio of 1.75:1, and a maximum energy storage of 0.96mJ.

2. The gate-controlled semiconductor depletion layer modulated vacuum variable capacitor according to claim 1, characterized in that: The upper electrode (1) has an edge rounding radius of 2.0 mm, an effective diameter of 35.7 mm, and a thickness of 1.0 mm.

3. The gate-controlled semiconductor depletion layer modulated vacuum variable capacitor according to claim 1, characterized in that: The semiconductor layer (4) is in A strong inversion layer is formed on the lower surface under the action of the action, which is equivalent to a metal electrode. The thin-film resistance of the inversion layer is .

4. The gate-controlled semiconductor depletion layer modulated vacuum variable capacitor according to claim 1, characterized in that: The vacuum level of the vacuum gap on the vacuum insulation layer (7) is better than Average electric field strength Maximum electric field strength .

5. The gate-controlled semiconductor depletion layer modulated vacuum variable capacitor according to claim 1, characterized in that: The gate (6) modulates the depletion layer width through a MOS structure. The response time is determined by the dielectric relaxation time, and the theoretical electronic speed is in the range of nanoseconds to microseconds.

6. A method for fabricating a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor, characterized in that, The gate-controlled semiconductor depletion layer modulated vacuum variable capacitor, applicable to any one of claims 1-5, is prepared by a method comprising: S1. Semiconductor substrate preparation: N-type single-crystal silicon wafers are used, and the substrates undergo cleaning and surface quality control. S2, Front-side MOS structure fabrication, including dry oxygen thermal growth of gate oxide layer (5), aluminum vapor deposition and photolithography to form ring gate (6), annealing; S3. Backside metallization and treatment, including thinning and polishing, ion implantation to form an ohmic contact layer, evaporation of a Ti / Pt / Au composite metal layer and annealing; S4. Preparation of the upper electrode (1): The upper electrode is made of oxygen-free copper and processed into a disc electrode with rounded edges. The surface is polished and plated with nickel. S5, Ceramic shell (3) preparation, including processing alumina ceramic ring and end face metallization treatment; S6. Precision assembly and vacuum packaging: using precision gaskets to control the vacuum gap, employing brazing technology for hermetic sealing, and maintaining high vacuum through getter.

7. The method for fabricating a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor according to claim 6, characterized in that: The vacuum gap This is achieved using precision ceramic or metal gaskets, with the gasket thickness tolerance controlled within [specific tolerance range]. Within this range, the parallelism is better than .

8. The method for fabricating a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor according to claim 6, characterized in that: The brazing is employed or Eutectic brazing is performed in a vacuum or reducing atmosphere, and the vacuum level of the cavity after brazing is better than that of other materials. .

9. The method for fabricating a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor according to claim 6, characterized in that: The thickness of the gate oxide layer (5) is The material was grown at 1050℃ for 30 minutes using a dry oxygen thermal growth process, with thickness uniformity controlled within a certain range. Within.

10. The method for fabricating a gate-controlled semiconductor depletion layer modulated vacuum variable capacitor according to claim 6, characterized in that: All internal components undergo ultra-clean treatment before assembly, with surface particle sizes greater than [missing value]. The number of particles is less than 10 per piece, and the cleanliness of the assembly environment is not lower than ISO 5 level.

Images