Semiconductor structure and manufacturing method thereof

Abstract

A method of fabricating a semiconductor structure includes providing a substrate on which a shallow trench isolation structure and a first active region are formed, where a top surface of the shallow trench isolation structure is higher than a top surface of the substrate in the first active region, performing an etching step, the method includes etching the first active region to remove a portion of the shallow trench isolation structure such that the top surface of the shallow trench isolation structure is lower than the top surface of the substrate of the first active region, and performing a doping step on the first active region after the etching step.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to an improved method for manufacturing planar transistors, which can effectively improve the performance of planar transistors. Background Technology

[0002] With the rapid development of technology, the demands for performance and functionality in electronic products are constantly increasing, which is driving semiconductor technology forward. In order to accommodate more transistors on a limited chip area and achieve higher computing power and lower power consumption, the design of semiconductor components has gradually shifted from traditional planar structures to three-dimensional structures.

[0003] Planar transistors have always been a crucial component in the semiconductor industry. Their simple structure, relatively easy fabrication process, and high cost-effectiveness have led to their widespread use in various electronic products. Planar transistors are primarily used in 28nm and 22nm manufacturing processes. However, as semiconductor manufacturing processes continue to shrink and transistor sizes become increasingly smaller, the physical limitations of planar transistors are gradually becoming apparent. When manufacturing processes reach 17nm, 14nm, and even more advanced nodes, planar transistors face challenges in controlling leakage current and maintaining performance.

[0004] The FinFET (Fin Field-Effect Transistor) has emerged to address this need. FinFETs employ a three-dimensional structure, where the transistor's channel protrudes from the substrate, and the gate surrounds three sides of the channel. This allows for better gate control, effectively reducing leakage current and improving transistor performance. The advent of FinFETs has enabled the continuous miniaturization of semiconductor manufacturing processes, laying the foundation for the development of high-performance chips.

[0005] Although FinFETs play a crucial role in advanced manufacturing processes, planar transistors have not been completely replaced. Planar transistors offer advantages such as simple structure and ease of fabrication, and are therefore still widely used in mid-range components with lower performance requirements. Furthermore, in certain specialized applications, such as power management chips, planar transistors still possess advantages. Summary of the Invention

[0006] The present invention provides a method for fabricating a semiconductor structure, comprising providing a substrate on which a shallow trench isolation structure and a first active region are formed, wherein a top surface of the shallow trench isolation structure is higher than a top surface of the substrate in the first active region, performing an etching step to remove a portion of the shallow trench isolation structure so that the top surface of the shallow trench isolation structure is lower than the top surface of the substrate in the first active region, and performing a doping step on the first active region after the etching step.

[0007] The present invention also provides a semiconductor structure comprising a substrate having a first active region thereon, a shallow trench isolation structure located on the substrate and surrounding the first active region, wherein a top surface of the shallow trench isolation structure is lower than a top surface of the substrate of the first active region, and a height difference between the top surface of the shallow trench isolation structure and the top surface of the first active region is defined as H1, wherein H1 is between 2 nanometers and 10 nanometers.

[0008] The key feature of this invention is that planar transistors remain a primary application element in mid-range semiconductor manufacturing processes such as 22nm and 28nm. In the fabrication of planar transistors, this invention employs an additional etching process to slightly lower the surface of the shallow trench isolation structure, causing the originally planar active region to exhibit a fin-like protrusion, thereby improving transistor performance. However, unlike conventional fin transistors, the improved planar transistor of this invention does not require multiple additional fabrication processes to form a planar transistor with a protruding active region. The planar transistor of this invention is suitable for mid-range semiconductor manufacturing processes such as 22nm and 28nm, offering advantages such as ease of fabrication and simple structure. Simultaneously, due to the protruding active region, the transistor exhibits higher performance. Attached Figure Description

[0009] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0010] Figures 1 to 5 This is a cross-sectional schematic diagram of a semiconductor structure formed according to an embodiment of the present invention.

[0011] Figure 6 These are schematic diagrams of a semiconductor structure and a finned transistor, respectively, according to the present invention.

[0012] Symbol Explanation

[0013] 10: Padding layer

[0014] 12: Insulation layer

[0015] 14: Oxide layer

[0016] 16: Nitrided layer

[0017] 18: Gap

[0018] 20: Gap

[0019] 21: Gate dielectric layer

[0020] 22: Gate conductive layer

[0021] 23: Gate dielectric layer

[0022] 24: Gate conductive layer

[0023] AA: Active (Active) Region

[0024] AA1: First Active Zone

[0025] AA2: Second Active Zone

[0026] D1: Depth

[0027] F: Fin-like structure

[0028] H1: Height

[0029] G1: Gate structure

[0030] G2: Gate structure

[0031] G3: Gate structure

[0032] G4: Gate structure

[0033] L1: Length

[0034] L2: Length

[0035] NW: N-type doped region

[0036] PW: P-type doped region

[0037] P1: Wet etching step

[0038] P2: Doping step

[0039] RC1: Rounded corner structure

[0040] RC2: Rounded corner structure

[0041] S: Base

[0042] STI: Shallow Trench Separation Structure

[0043] W1: Width

[0044] W2: Width Detailed Implementation

[0045] To enable those skilled in the art to further understand the present invention, preferred embodiments of the invention are described below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings.

[0046] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0047] Although the present invention uses terms such as first, second, third, etc., to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0048] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, such as within 10%, 5%, 3%, 2%, 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate, meaning that the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0049] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0050] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0051] Please refer to Figures 1 to 5 , Figures 1 to 5A schematic cross-sectional view of a semiconductor structure formed according to an embodiment of the present invention is shown. Firstly, as follows... Figure 1 As shown, a substrate S is provided, which may be, for example, a silicon substrate, but is not limited thereto. A first active region AA1 and a second active region AA2 are defined on the substrate S. A shallow trench isolation structure STI is included between the first active region AA1 and the second active region AA2. The shallow trench isolation structure STI comprises a bottom pad layer 10 and an upper insulating layer 12. In this embodiment, the material of the pad layer 10 and the insulating layer 12 is, for example, silicon oxide, but the invention is not limited thereto. The pad layer 10 mainly serves to block ion diffusion and stabilize stress. In other embodiments of the invention, the pad layer 10 may be omitted, and the insulating layer 12 may be directly formed in the substrate S; such variations are also within the scope of the invention.

[0052] In this embodiment, an oxide layer 14 and a nitride layer 16 are formed on the surface of the substrate S. After the oxide layer 14 and the nitride layer 16 are formed on the surface of the substrate S, one or more etching steps are performed to form a groove (not shown) in the nitride layer 16, the oxide layer 14, and the substrate S. Then, material layers constituting the pad layer 10 and the insulating layer 12, such as a silicon nitride material layer and a silicon oxide material layer, are filled into the groove. Subsequently, a planarization step (e.g., chemical mechanical polishing) is used to remove the excess silicon nitride material layer and silicon oxide material layer, and the remaining material layers are defined as the pad layer 10 and the insulating layer 12. Figure 1 As shown, after the planarization step, the top surfaces of the nitrided layer 16, the liner layer 10, and the insulating layer 12 are aligned with each other in the horizontal direction.

[0053] In this context, the first active region AA1 and the second active region AA2, as defined herein, will respectively form the gates of transistors in subsequent steps. The first active region AA1 and the second active region AA2 can be doped with different ions to form different types of transistors. For example, P-type ions and N-type ions can be doped into the first active region AA1 and the second active region AA2 respectively to form P-type and N-type doped regions. After the gates are subsequently formed in the first active region AA1 and the second active region AA2 respectively, different types of transistors can be formed in the two regions. For example, the first active region AA1 contains a P-type doped region, thus forming an N-type transistor, and the second active region AA2 contains an N-type doped region, thus forming a P-type transistor. It is worth noting that the above embodiment is only one example of the present invention. In other embodiments of the present invention, the same type of doped regions can also be included on both sides of the shallow trench isolation structure STI, forming transistors of the same type. Such variations are also within the scope of the present invention.

[0054] Next, as Figure 2 and Figure 3 As shown, after the planarization step is completed, a wet etching step is performed. Wet etching step P1 is, for example, a buffered oxide etching (BOE), in which the device is immersed in a mixed solution of hydrofluoric acid (HF) and ammonium fluoride (NH4F). The main function of BOE is to etch the silicon oxide layer. It is worth noting that wet etching step P1 does not require an additional photomask; instead, it isotropically etches the silicon oxide layer of the entire semiconductor structure. During wet etching step P1, the insulating layer 12 and oxide layer 14, composed of silicon oxide, are the main etching targets, and therefore the pad layer 10, insulating layer 12, and oxide layer 14 are removed relatively quickly. Additionally, the silicon nitride layer 16, made of silicon nitride, may also be partially removed. Furthermore, since silicon oxide is removed faster than silicon nitride during wet etching step P1, oxide layer 14 is more easily removed, resulting in gaps 18 and 20 in oxide layer 14 located between the substrate S and the nitride layer 16.

[0055] Then as Figure 3 and Figure 4 As shown, the nitride layer 16 and oxide layer 14 on the surface of the substrate S are removed by one or more etching steps. Next, one or more doping steps P2 are performed to dope the first active region AA1 and the second active region AA2 respectively, forming doped regions in the first active region AA1 and the second active region AA2. The doped regions in the first active region AA1 and the second active region AA2 can be of the same or different types. For example, in this embodiment, boron ions are doped in the first active region AA1, and phosphorus ions or arsenic ions are doped in the second active region AA2, forming a P-type doped region PW in the substrate S of the first active region AA1 and an N-type doped region NW in the substrate of the second active region AA2. The P-type doped region PW and the N-type doped region NW can be considered as a first active region and a second active region, respectively. In subsequent steps, gate structures will be formed on the first active region and the second active region to constitute a transistor. As mentioned above, the present invention does not limit the types of doped regions formed by the first active region AA1 and the second active region AA2 shown herein, that is, they can be adjusted according to actual needs.

[0056] It is also worth noting that, Figures 2 to 4In the fabrication process, etching parameters or ion doping parameters can be selectively adjusted to create rounded corner structures RC1 and RC2 at the interface between the P-type doped region (PW) or N-type doped region (NW) and the shallow trench isolation (STI) structure. Rounded corner structures RC1 and RC2 help reduce leakage current in subsequently formed transistors, thereby improving the quality of the semiconductor structure. However, this invention does not limit the formation of rounded corner structures RC1 and RC2; therefore, in other embodiments of this invention, the semiconductor structure may not include rounded corner structures RC1 and RC2, and such variations are also within the scope of this invention.

[0057] It is also worth noting that, Figure 2 After wet etching step P1, the top surface of the shallow trench isolation structure STI will drop below the top surface of the substrate S, and then... Figure 4 In the steps shown, the substrate S is doped. That is, the top surfaces of the P-type doped region PW (the first active region AA1) and the N-type doped region NW (the second active region AA2) will be higher than the top surface of the shallow trench isolation structure STI. However, in this invention, the height difference between the top surface of the P-type doped region PW or the N-type doped region NW and the top surface of the shallow trench isolation structure STI is limited to a certain range. More specifically, the height difference between the top surface of the P-type doped region PW or the N-type doped region NW and the top surface of the shallow trench isolation structure STI is defined as H1, and the depth of the shallow trench isolation structure STI is defined as D1 (that is, the vertical length from the top surface to the bottom surface of the shallow trench isolation structure STI as seen in the cross-sectional view). In this invention, the height H1 is approximately 10 nanometers or less, and the depth D1 is approximately 200 nanometers or less. More specifically, in this embodiment, the height H1 is only about 4 nanometers. In other words, relative to the depth D1 of the shallow trench isolation structure (STI), the height H1 of the active regions (i.e., the P-type doped region PW and the N-type doped region NW) protruding above the top surface of the STI is relatively small. For example, in this embodiment, the ratio of height H1 to depth D1 is approximately less than 0.05 (i.e., 10 / 200), but the present invention is not limited thereto.

[0058] Then as Figure 5As shown, gate structures G1 and G2 are formed on the surfaces of the P-type doped region PW and the N-type doped region NW, respectively. After the formation of gate structures G1 and G2, two transistors of different types are formed in the first active region AA1 and the second active region AA2, respectively. Gate structure G1 includes a gate dielectric layer 21 and a gate conductive layer 23, and gate structure G2 includes a gate dielectric layer 22 and a gate conductive layer 24. The gate dielectric layer 21 and gate dielectric layer 22 may contain a stacked structure of materials such as silicon oxide, a high dielectric constant layer, and a work function metal layer. The gate conductive layer 23 and gate conductive layer 24 may contain polysilicon or conductive metal layers. Since the steps for forming the gate structure and the material characteristics of the gate structure are prior art in this field, they will not be described in detail here. Furthermore, in the actual fabrication process, the first active region AA1 (P-type doped region PW) or the second active region AA2 (N-type doped region NW) is surrounded by a shallow trench isolation structure (STI). Gate structures G1 and G2 span the first and second active regions AA1 and AA2, respectively. Therefore, gate structures G1 and G2 are actually located not only on the surfaces of the P-type doped region PW and the N-type doped region NW, but also on a portion of the shallow trench isolation structure (STI). This can be explained by the following... Figure 6 It's even more obvious now.

[0059] It is worth noting that although the active region protruding from the shallow trench isolation structure (STI) is formed in this invention, the fabrication process of this invention is still classified as a planar transistor. More specifically, the fabrication process of forming the transistor within the first active region AA1 or the second active region AA2 in this invention is mostly the same as the fabrication process of a planar transistor, and differs significantly from the steps of forming a typical fin transistor (FinFET). Generally, in the fabrication process of a fin transistor, in order to form a fin structure, multiple photomasks are usually required to perform multiple photolithography and etching steps on the substrate, including forming a sacrificial layer and spacers, removing the sacrificial layer, performing a sidewall pattern transfer (SIT) step to transfer the pattern to the stacked material layer and the substrate, filling with insulating material, and performing back etching, etc. In the steps of this invention, multiple complex photomasks are not required to form a fin structure. This invention is mainly applicable to fabrication processes of 22 nanometers (e.g., 22 nanometers, 28 nanometers, etc.) and above, that is, to improve the structure of planar transistors in fabrication processes of 22 nanometers and above. As mentioned earlier, in fabrication processes above 22 nanometers, due to the lower precision requirements for components, most transistors are still planar transistors. In the foregoing description of this invention... Figure 1The active regions (i.e., the first active region AA1 and the second active region AA2) and the shallow trench isolation structure STI are defined, and then the gate structures G1 and G2 are formed on the active regions. However, unlike existing planar transistors, an additional wet etching step P1 is performed in the fabrication process (e.g., ... Figure 2 Therefore, the top surface of the shallow trench isolation structure (STI) is slightly lowered, and the active region protrudes from the surface of the shallow trench isolation structure (STI). However, even though the semiconductor structure of the present invention has a protruding active region, it still falls into the category of planar transistors, and the protruding active region of the semiconductor structure of the present invention is structurally significantly different from that of a typical fin structure.

[0060] To more clearly illustrate the differences between the structure of the present invention and the finned transistor, Figure 6 A schematic diagram of a semiconductor structure and a schematic diagram of a finned transistor of the present invention are shown respectively. Figure 6 As shown, the left side illustrates the structural diagram of the semiconductor structure of the present invention, while the right side illustrates the structural diagram of a finned transistor. As shown in the left-side structure, the gate structure G3 spans the active region AA and the shallow trench isolation structure STI to form the transistor. Due to etching, the top surface of the shallow trench isolation structure STI in this invention is slightly lowered, causing the active region AA (i.e., the aforementioned P-type doped region PW or N-type doped region NW) to protrude from the top surface of the shallow trench isolation structure STI. However, the height difference H1 between the top surface of the shallow trench isolation structure STI and the top surface of the active region AA (please refer to...) Figure 2 The height (H1) is only about 10 nanometers. In contrast, Figure 6 In the structure on the right, the gate structure G4 spans the fin structure F and the shallow trench isolation structure STI to form a transistor. However, the height H3 of the fin structure is usually below 40 nanometers, but usually significantly exceeds 10 nanometers. Therefore, the height of the protruding active region of the present invention is significantly lower than the height of a typical fin structure.

[0061] On the other hand, since the structure of this invention is an improvement on the planar transistor structure, the size of the active region AA will be significantly different from the size of the fin structure when viewed from a top view. For example... Figure 6 The active region AA has a length L1 of approximately 25 nanometers and a width W1 of approximately 250 nanometers, resulting in a length-to-width ratio greater than 0.1 (i.e., 25 / 250). However, the length L2 of the fin structure F will be significantly smaller than the length L1 of the active region AA. For example, in a typical 14-nanometer fabrication process, with the same width W2 of 250 nanometers, the length L2 of the fin structure F is only about 10 nanometers. Therefore, for the fin structure F, the length-to-width ratio L2 will be significantly less than 0.1. Consequently, from a top-view perspective, the size of the active region AA of this invention will also be significantly different from the size of the fin structure F.

[0062] This invention involves lowering the top surface of the shallow trench isolation (STI) structure of a planar transistor through a wet etching step P1 before forming the gate structure (e.g. Figure 5 The gate structures G1, G2, or Figure 6 The gate structure (G3) spans the top surface of the active region AA and the sidewalls on both sides of the active region. This increases the channel width of the planar transistor and correspondingly improves its performance. According to the applicant's experimental results, the improved planar transistor of this invention, compared with existing planar transistors (i.e., planar transistors that do not perform additional etching steps to lower the top surface of the shallow trench isolation structure STI), has an approximately 20% increase in turn-off current (Ioff), an approximately 12% decrease in leakage current, and an approximately 20% decrease in drive voltage when the transistor is applied to SRAM. Therefore, this invention, based on the existing planar transistor fabrication process, performs additional etching steps on the shallow trench isolation structure STI without the need for additional photomasks, effectively improving the performance of planar transistors.

[0063] Based on the above description and accompanying drawings, the present invention provides a method for fabricating a semiconductor structure, comprising providing a substrate S, forming a shallow trench isolation structure STI on the substrate S, and defining a first active region AA1, wherein a top surface of the shallow trench isolation structure STI is higher than a top surface of the substrate S of the first active region AA1 (e.g., ...). Figure 1 Before the wet etching step P1, the top surface of the shallow trench isolation structure STI is higher than the surface of the substrate S of the first active region AA1. An etching step P1 is then performed to remove a portion of the shallow trench isolation structure STI, making the top surface of the shallow trench isolation structure STI lower than the top surface of the substrate S of the first active region AA1 (e.g., ...). Figure 2 ), and after the etching step, a doping step is performed on the first active region (e.g. Figure 4 Doping step P2).

[0064] In some embodiments of the present invention, after the etching step, a height difference between the top surface of the shallow trench isolation structure STI and the top surface of the first active region AA1 is defined as H1, wherein H1 is between 2 nanometers and 10 nanometers.

[0065] In some embodiments of the invention, a depth of the shallow trench isolation structure STI is defined as D1 after the etching step, wherein the ratio of H1 to D1 is less than 0.05.

[0066] In some embodiments of the present invention, the length of the first active region AA1 is defined as L1 and the width is defined as W1, as viewed from a top view, wherein the width W1 is less than 250 nanometers.

[0067] In some embodiments of the present invention, the ratio of length L1 to width W1 is greater than 0.1.

[0068] In some embodiments of the present invention, an oxide layer 14 and a nitride layer 16 are formed on the first active region AA1, wherein the nitride layer 16 is stacked on the oxide layer 14.

[0069] In some embodiments of the present invention, during the etching step, etching step P1 removes a portion of the oxide layer 14, such that the width of the oxide layer 14 is smaller than the width of the nitride layer 16 (e.g., ...). Figure 2 As shown, notches 18 and 20 are formed in oxide layer 14.

[0070] In some embodiments of the present invention, after etching step P1, oxide layer 14 and nitride layer 16 are completely removed before doping step P2 is performed.

[0071] In some embodiments of the invention, the top surface of the shallow trench isolation structure STI is horizontally aligned with a top surface of the nitride layer 16 prior to the etching step (e.g., ...). Figure 1 ).

[0072] In some embodiments of the present invention, the junction of the first active region AA1 and the shallow trench isolation structure STI includes a rounded corner structure (e.g., Figure 4 (RC1 shown).

[0073] In some embodiments of the present invention, after the doping step P2, a first gate structure G1 is further formed on the first active region and a portion of the shallow trench isolation structure. The bottom surface of the first gate structure G1 in contact with the first active region AA1 is defined as a first bottom surface, and the bottom surface of the first gate structure G1 in contact with the shallow trench isolation structure STI is defined as a second bottom surface. The height difference between the first bottom surface and the second bottom surface in a vertical direction is within 10 nanometers (see reference). Figure 6 or Figure 2 (height H1 in the middle).

[0074] In some embodiments of the present invention, the etching step includes a wet etching step, which includes a buffered oxide etch (BOE) etching step.

[0075] In some embodiments of the present invention, a second active region AA2 is defined on the substrate S, wherein the shallow trench isolation structure STI is located between the first active region AA1 and the second active region AA2.

[0076] In some embodiments of the present invention, the doping step P2 further includes performing doping steps P2 on the first active region and the second active region respectively, so as to dope the first active region and the second active region with ions of different conductivity types respectively.

[0077] The present invention further provides a semiconductor structure comprising a substrate S, wherein a first active region AA1 is included on the substrate S, and a shallow trench isolation structure STI is located on the substrate S and surrounding the first active region AA1, wherein a top surface of the shallow trench isolation structure STI is lower than a top surface of the substrate of the first active region AA1, and a height difference between the top surface of the shallow trench isolation structure STI and the top surface of the first active region AA1 is defined as H1, wherein H1 is between 2 nanometers and 10 nanometers.

[0078] In some embodiments of the present invention, a depth of the shallow trench isolation structure STI is defined as D1, wherein the ratio of H1 to D1 is less than 0.1.

[0079] In some embodiments of the present invention, wherein, viewed from a top view, the first active region AA1 has a length defined as L1 and a width defined as W1, wherein the width W1 is less than 250 nanometers and wherein the ratio of the length L1 to the width W1 is greater than 0.1.

[0080] In some embodiments of the present invention, a rounded corner structure RC1 is included at the junction of the first active region AA1 and the shallow trench isolation structure STI.

[0081] In some embodiments of the present invention, a first gate structure G1 is located on a first active region AA1 and a portion of a shallow trench isolation structure AA1, wherein the bottom surface of the first gate structure G1 in contact with the first active region AA1 is defined as a first bottom surface, and the bottom surface of the first gate structure G1 in contact with the shallow trench isolation structure is defined as a second bottom surface, wherein the height difference between the first bottom surface and the second bottom surface in a vertical direction is within 10 nanometers.

[0082] In some embodiments of the present invention, a second active region AA2 is further included, wherein the shallow trench isolation structure STI is located between the first active region AA1 and the second active region AA2, and the first active region AA1 and the second active region AA2 are respectively doped with ions of different conductivity types.

[0083] The key feature of this invention is that planar transistors remain a primary application element in mid-range semiconductor manufacturing processes such as 22nm and 28nm. In the fabrication of planar transistors, this invention employs an additional etching process to slightly lower the surface of the shallow trench isolation structure, causing the originally planar active region to exhibit a fin-like protrusion, thereby improving transistor performance. However, unlike conventional fin transistors, the improved planar transistor of this invention does not require multiple additional fabrication processes to form a planar transistor with a protruding active region. The planar transistor of this invention is suitable for mid-range semiconductor manufacturing processes such as 22nm and 28nm, offering advantages such as ease of fabrication and simple structure. Simultaneously, due to the protruding active region, the transistor exhibits higher performance.

[0084] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for fabricating a semiconductor structure, comprising: A substrate is provided on which a shallow trench isolation structure and a first active region are formed, wherein the top surface of the shallow trench isolation structure is higher than the top surface of the substrate in the first active region; An etching step is performed to remove a portion of the shallow trench isolation structure, such that the top surface of the shallow trench isolation structure is lower than the top surface of the substrate of the first active region; as well as After the etching step, the first active region is subjected to a doping step.

2. The method for fabricating a semiconductor structure as claimed in claim 1, wherein after the etching step, the height difference between the top surface of the shallow trench isolation structure and the top surface of the first active region is defined as H1, wherein H1 is between 2 nanometers and 10 nanometers.

3. The method for fabricating a semiconductor structure as described in claim 2, wherein after the etching step, the depth of the shallow trench isolation structure is defined as D1, wherein the ratio of H1 to D1 is less than 0.

05.

4. The method for fabricating a semiconductor structure as described in claim 1, wherein, from a top view, the length of the first active region is defined as L1 and the width is defined as W1, wherein the width W1 is less than 250 nanometers.

5. The method for fabricating a semiconductor structure as described in claim 4, wherein the ratio of the length L1 to the width W1 is greater than 0.

1.

6. The method for fabricating a semiconductor structure as claimed in claim 1, further comprising forming an oxide layer and a nitride layer on the first active region, the nitride layer being stacked on the oxide layer.

7. The method for fabricating a semiconductor structure as claimed in claim 6, wherein in the etching step, a portion of the oxide layer is removed simultaneously, such that the width of the oxide layer is smaller than the width of the nitride layer.

8. The method for fabricating a semiconductor structure as described in claim 6, wherein after the etching step, the oxide layer and the nitride layer are completely removed before the doping step is performed.

9. The method of fabricating a semiconductor structure as claimed in claim 6, wherein, prior to the etching step, the top surface of the shallow trench isolation structure is aligned with the top surface of the nitride layer in the horizontal direction.

10. The method for fabricating a semiconductor structure as claimed in claim 1, wherein the junction between the first active region and the shallow trench isolation structure includes a rounded corner structure.

11. The method for fabricating a semiconductor structure as claimed in claim 1, wherein after the doping step, it further comprises forming a first gate structure on the first active region and a portion of the shallow trench isolation structure, wherein the bottom surface of the first gate structure in contact with the first active region is defined as a first bottom surface, and the bottom surface of the first gate structure in contact with the shallow trench isolation structure is defined as a second bottom surface, wherein the height difference between the first bottom surface and the second bottom surface in the vertical direction is within 10 nanometers.

12. The method for fabricating a semiconductor structure as claimed in claim 1, wherein the etching step includes a wet etching step, and the wet etching step includes a buffered oxide etch (BOE) etching step.

13. The method of fabricating a semiconductor structure as claimed in claim 1, further comprising forming a second active region located in the substrate, wherein the shallow trench isolation structure is located between the first active region and the second active region.

14. The method for fabricating a semiconductor structure as claimed in claim 13, wherein the doping step further includes performing doping steps on the first active region and the second active region respectively, so as to dope the first active region and the second active region with ions of different conductivity types respectively.

15. A semiconductor structure comprising: A substrate containing a first active region; A shallow trench isolation structure is located on the substrate and around the first active region, wherein a top surface of the shallow trench isolation structure is lower than the top surface of the substrate of the first active region, and the height difference between the top surface of the shallow trench isolation structure and the top surface of the first active region is defined as H1, wherein H1 is between 2 nanometers and 10 nanometers.

16. The semiconductor structure of claim 15, wherein the depth of the shallow trench isolation structure is defined as D1, and the ratio of H1 to D1 is less than 0.

1.

17. The semiconductor structure of claim 15, wherein, viewed from a top view, the length of the first active region is defined as L1 and the width as W1, wherein the width W1 is less than 250 nanometers, and wherein the ratio of the length L1 to the width W1 is greater than 0.

1.

18. The semiconductor structure of claim 15, wherein the junction between the first active region and the shallow trench isolation structure includes a rounded corner structure.

19. The semiconductor structure of claim 15, further comprising a first gate structure located on the first active region and a portion of the shallow trench isolation structure, wherein the bottom surface of the first gate structure in contact with the first active region is defined as a first bottom surface, and the bottom surface of the first gate structure in contact with the shallow trench isolation structure is defined as a second bottom surface, wherein the height difference between the first bottom surface and the second bottom surface in the vertical direction is within 10 nanometers.

20. The semiconductor structure of claim 15, further comprising a second active region, wherein the shallow trench isolation structure is located between the first active region and the second active region, and the first active region and the second active region are respectively doped with ions of different conductivity types.

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