Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a semiconductor substrate, and a drift layer and a source doped region are sequentially formed on the surface of the semiconductor substrate; the plurality of grooves extend along the x direction, penetrate through the source doped region and extend into the drift layer; a plurality of gate connection regions respectively wrapping the bottoms and partial side walls of the plurality of grooves; and the plurality of grid electrode doping regions extend along the y direction, are positioned below the grid electrode connecting regions and cover part of the grid electrode connecting regions, and the y direction is perpendicular to the x direction. The invention provides a solution for more effectively reducing the on-resistance of the silicon carbide power device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the development of power semiconductors, many mechanical electrical devices or components have been replaced by solutions implemented with power semiconductor chips, such as solid-state circuit breakers and safety relays. These components are generally normally open, meaning that to minimize power loss, the primary requirement for power semiconductor chips is the lowest possible on-resistance. Currently, in high-voltage applications, power semiconductor chips made with wide-bandgap semiconductors are becoming increasingly common, with silicon carbide (SiC) becoming the market mainstream due to its process compatibility with silicon. However, the material cost of SiC is still tens or even hundreds of times higher than that of silicon. The aforementioned requirement for low on-resistance implies a large chip area, which poses a cost challenge to SiC components in terms of chip count per wafer and yield.

[0003] Therefore, it is necessary to provide a more effective solution to reduce the on-resistance of silicon carbide power devices. Summary of the Invention

[0004] The purpose of this invention is to provide a more effective solution for reducing the on-resistance of silicon carbide power devices.

[0005] One aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate, wherein a drift layer and a source doped region are sequentially formed on the surface of the semiconductor substrate; a plurality of trenches extending along the x-direction and penetrating through the source doped region to the drift layer; a plurality of gate connection regions respectively covering the bottom and part of the sidewalls of the plurality of trenches; and a plurality of gate doped regions extending along the y-direction and located below the gate connection regions and covering part of the gate connection regions, wherein the y-direction and the x-direction are perpendicular to each other.

[0006] In some embodiments of this application, the semiconductor structure further includes: a first current diffusion layer located between the source doped region and the gate doped region, wherein the top surface of the first current diffusion layer is connected to the source doped region and the bottom surface of the first current diffusion layer is connected to the gate doped region.

[0007] In some embodiments of this application, the semiconductor structure further includes: a second current diffusion layer located between the semiconductor substrate and the gate doped region, wherein the top surface of the second current diffusion layer is connected to the gate doped region.

[0008] In some embodiments of this application, the gate connection region and the gate doped region are formed by the same ion implantation process.

[0009] In some embodiments of this application, a gate silicide is formed in the trench, and the bottom and sidewalls of the gate silicide are completely covered by the gate connection region.

[0010] In some embodiments of this application, the top surface of the gate silicide is formed with an interlayer dielectric layer that fills the trench and extends partially over the source doped region.

[0011] Another aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a drift layer and a source doped region are sequentially formed on the surface of the semiconductor substrate; forming a plurality of trenches, wherein the plurality of trenches extend along the x-direction and penetrate the source doped region to the drift layer; forming a plurality of gate connection regions, wherein the plurality of gate connection regions respectively cover the bottom and part of the sidewalls of the plurality of trenches; and forming a plurality of gate doped regions, wherein the plurality of gate doped regions extend along the y-direction and are located below the gate connection regions and cover part of the gate connection regions, wherein the y-direction and the x-direction are perpendicular to each other.

[0012] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a first current diffusion layer, wherein the first current diffusion layer is located between the source doped region and the gate doped region, the top surface of the first current diffusion layer is connected to the source doped region, and the bottom surface of the first current diffusion layer is connected to the gate doped region.

[0013] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a second current diffusion layer, the second current diffusion layer being located between the semiconductor substrate and the gate doped region, and the top surface of the second current diffusion layer being connected to the gate doped region.

[0014] In some embodiments of this application, the gate connection region and the gate doped region are formed by the same ion implantation process.

[0015] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a gate silicide in the trench, wherein the bottom and sidewalls of the gate silicide are completely covered by the gate connection region.

[0016] In some embodiments of this application, the method of forming the semiconductor structure further includes: forming an interlayer dielectric layer on the top surface of the gate silicide that fills the trench and extends partially above the source doped region.

[0017] This application provides a semiconductor structure and a method for forming the same, offering a more effective solution for reducing the on-resistance of silicon carbide power devices. Attached Figure Description

[0018] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0019] in:

[0020] Figures 1 to 6 This is a schematic diagram of the semiconductor structure described in some embodiments of this application;

[0021] Figure 7 This is a schematic diagram of the semiconductor structure described in other embodiments of this application;

[0022] Figure 8 This is a schematic diagram of the semiconductor structure described in other embodiments of this application. Detailed Implementation

[0023] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0024] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0025] Figures 1 to 6 This is a schematic diagram of the semiconductor structure described in some embodiments of this application.

[0026] in, Figures 1 to 6 The coordinates have x, y, and z axes in the same Cartesian coordinate system to represent orientation. Specifically, Figure 1 A three-dimensional structural view of a portion of the semiconductor structure after it has been removed; Figure 2 The image shows a cross-sectional view of the semiconductor structure on the yz plane at the center point of the gate doped region 104. Figure 3 This is a cross-sectional view of the semiconductor structure located at the center of channel 106 in the yz plane; Figure 4 This is a cross-sectional view of the semiconductor structure at the center point of trench 100a in the xz plane; Figure 5 This is a cross-sectional view of the semiconductor structure on the xz plane located at the center point of platform 100b; Figure 6This is a cross-sectional view of the semiconductor structure located at the center point of the gate connection region 105 in the xy plane. The method for forming the semiconductor structure 100 according to the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0027] Some embodiments of this application provide a semiconductor structure 100, see reference Figures 1 to 6 As shown, the system includes: a semiconductor substrate 101, on which a drift layer 102 and a source doped region 103 are sequentially formed; a plurality of trenches 100a extending along the x-direction and penetrating the source doped region 103 into the drift layer 102; a plurality of gate connection regions 105 respectively covering the bottom and part of the sidewalls of the plurality of trenches 100a; and a plurality of gate doped regions 104 extending along the y-direction and located below and covering part of the gate connection regions 105, wherein the y-direction and the x-direction are perpendicular to each other. Specifically, the y-direction and the x-direction correspond to the y-axis and x-axis in the figure, respectively.

[0028] In some embodiments of this application, the semiconductor substrate 101 is made of any one or more of silicon carbide, silicon, gallium nitride, gallium oxide, and aluminum nitride. The thickness of the semiconductor substrate 101 is 10 to 500 micrometers. The semiconductor substrate 101 may contain, for example, N-type doped ions, such as nitrogen and phosphorus. The doping concentration of the semiconductor substrate 101 is 1 x 10⁻⁶. 17 Up to 1x10 21 Atoms per cubic centimeter.

[0029] In some embodiments of this application, the material of the drift layer 102 is the same as that of the semiconductor substrate 101. The doping type of the drift layer 102 is the same as that of the semiconductor substrate 101. The drift layer 102 may contain, for example, N-type dopant ions, such as nitrogen or phosphorus. The doping concentration of the drift layer 102 is 1 x 10⁻⁶. 14 Up to 5x10 16 Atoms per cubic centimeter. The thickness of the drift layer 102 is 0.5 to 100 micrometers.

[0030] In some embodiments of this application, the material of the source doped region 103 is the same as that of the semiconductor substrate 101. The doping type of the source doped region 103 is the same as that of the semiconductor substrate 101. The source doped region 103 may contain, for example, N-type doped ions, such as nitrogen or phosphorus. The doping concentration of the source doped region 103 is 1 x 10⁻⁶. 18 Up to 1x10 21 Atoms per cubic centimeter. The thickness of the source doped region 103 is 0.1 to 1 micrometer.

[0031] In some embodiments of this application, a source silicide 111 is further formed on the surface of the source doped region 103 to reduce the contact resistance of the source doped region 103. The material of the source silicide 111 includes any one or more of nickel silicide and titanium silicide. The thickness of the source silicide 111 is 0.1 to 1 micrometer.

[0032] In some embodiments of this application, the depth of the trench 100a is 0.1 to 5 micrometers.

[0033] In some embodiments of this application, the area between adjacent trenches 100a is a platform 100b. The depth of the platform 100b is 0.1 to 5 micrometers.

[0034] In some embodiments of this application, a gate silicide 112 is formed in the trench 100a, and the bottom and sidewalls of the gate silicide 112 are completely covered by the gate connection region 105. The material of the gate silicide 112 includes any one or more of nickel silicide and titanium silicide. The thickness of the gate silicide 112 is 0.1 to 1 micrometer.

[0035] In some embodiments of this application, the top surface of the gate silicide 112 is formed with an interlayer dielectric layer 113 that fills the trench 100a and extends partially above the source doped region 103. The material of the interlayer dielectric layer 113 includes any one or more of silicon dioxide, doped silicon dioxide, and silicon nitride. The thickness of the interlayer dielectric layer 113 is 0.1 to 1 micrometer.

[0036] In some embodiments of this application, a source metal layer 114 electrically connected to the source silicide 111 is further formed on the surfaces of the source silicide 111 and the interlayer dielectric layer 113. The material of the source metal layer 114 includes any one or more of aluminum, copper, silver, gold, nickel, titanium, platinum, and palladium. The thickness of the source metal layer 114 is 1 to 10 micrometers.

[0037] In some embodiments of this application, the material of the gate doped region 104 is the same as that of the semiconductor substrate 101. The doping type of the gate doped region 104 is opposite to that of the semiconductor substrate 101. The gate doped region 104 may contain, for example, p-type doped ions, such as boron or aluminum. The doping concentration of the gate doped region 104 is 1 x 10⁻⁶. 17 Up to 1x10 21 Atoms per cubic centimeter. The depth of the gate doped region 104 (the distance from the top surface to the bottom surface of the gate doped region 104) is 0.1 to 5 micrometers.

[0038] In some embodiments of this application, the region between adjacent gate doped regions 104 in the x-direction is a channel 106. The width of the channel 106 in the x-direction is 0.1 to 5 micrometers.

[0039] In some embodiments of this application, the material of the gate connection region 105 is the same as that of the semiconductor substrate 101. The doping type of the gate connection region 105 is the same as that of the gate doping region 104. The gate connection region 105 may contain, for example, p-type doped ions, such as boron or aluminum. The doping concentration of the gate connection region 105 is 1 x 10⁻⁶. 17 Up to 1x10 21 Atoms per cubic centimeter. The depth of the gate connection region 105 (the distance from the top surface to the bottom surface of the gate connection region 105) is 0.1 to 5 micrometers.

[0040] In some embodiments of this application, a drain metal layer 115 is further formed on the back side of the semiconductor substrate 101. The material of the drain metal layer 115 includes any one or more of aluminum, copper, silver, gold, nickel, titanium, platinum, and palladium. The thickness of the drain metal layer 115 is 0.1 to 10 micrometers.

[0041] The semiconductor structure provided in this application belongs to a junction field-effect transistor (JFET). In a typical trench JFET implementation, the gate doped region is formed on the side of the trench, while the channels are located between the gate doped regions in the platform. A disadvantage of this typical implementation is that the cell spacing of the transistor, i.e., the repetition period between each channel, is linked to the trench spacing, thus being limited by the trench etching process capability. Furthermore, since the resistivity of the device is positively correlated with the cell spacing, this typical implementation is not conducive to reducing the device's resistivity. In addition, since each cell contains a trench, the area occupied by the trench cannot be used for conduction, resulting in a low channel area ratio. In other words, the conduction efficiency per unit area of ​​the chip is low, which also hinders the reduction of the device's resistivity.

[0042] In the semiconductor structure design provided in this application, the arrangement direction of the gate doped regions is perpendicular to the arrangement direction of the trenches. A cell consists of one gate doped region and one channel region. The cell does not contain trenches, which greatly reduces the cell pitch compared to conventional implementations and increases the proportion of the channel region in the cell, significantly increasing the conduction efficiency per unit area of ​​the chip. Moreover, the cell pitch is no longer linked to the trench pitch, meaning that the cell pitch is no longer limited by the critical dimensions of the trench etching process, but depends on the critical dimensions of the ion implantation process. The critical dimensions of the trench etching process are mainly limited by the aspect ratio of the trench, making it difficult to significantly reduce them at the same trench depth. However, the critical dimensions of the ion implantation process can currently be further reduced through various methods, such as channel implantation, multiple epitaxy, and new hard mask materials. Making the cell pitch independent of the trench pitch will facilitate the iterative reduction of the cell pitch. Since the trenches and their associated regions—the gate connection region and the gate silicide—only provide cell gate interconnection and do not participate in source-drain current conduction, the structural design provided in this application can be tailored to application switching requirements, especially for normally open applications such as circuit breaker applications, where the requirements for device switching speed and loss are low. In such cases, the trench spacing can be increased to minimize the number of trenches, thereby achieving higher chip area conduction efficiency and lower device resistivity. In terms of design flexibility, this is superior to the implementation of general trench junction field-effect transistors.

[0043] Figure 7 This is a schematic diagram of the semiconductor structure 200 described in other embodiments of this application. It should be noted that, for the sake of brevity, Figure 7 In the semiconductor structure 200 shown, and Figure 1 The same or similar contents in the semiconductor structure 100 shown will not be described in detail; only the different contents will be described.

[0044] refer to Figure 7 As shown, in some embodiments of this application, compared to Figure 1 The semiconductor structure 100 shown further includes a first current diffusion layer 207 located between the source doped region 203 and the gate doped region 204. The top surface of the first current diffusion layer 207 is connected to the source doped region 203, and the bottom surface of the first current diffusion layer 207 is connected to the gate doped region 204.

[0045] In some embodiments of this application, the material of the first current diffusion layer 207 is the same as that of the semiconductor substrate 201. The first current diffusion layer 207 may contain, for example, N-type dopant ions, such as nitrogen or phosphorus. The doping concentration of the first current diffusion layer 207 is 1 x 10⁻⁶. 17 Up to 1x10 20Atoms per cubic centimeter. The thickness of the first current diffusion layer 207 is 0.1 to 5 micrometers.

[0046] Continue to refer to Figure 7 As shown, in some embodiments of this application, compared to Figure 1 The semiconductor structure 100 shown further includes a second current diffusion layer 208 located between the semiconductor substrate 201 and the gate doped region 204, with the top surface of the second current diffusion layer 208 connected to the gate doped region 204.

[0047] In some embodiments of this application, the material of the second current diffusion layer 208 is the same as that of the semiconductor substrate 201. The second current diffusion layer 208 may contain, for example, N-type dopant ions, such as nitrogen or phosphorus. The doping concentration of the second current diffusion layer 208 is 1 x 10⁻⁶. 17 Up to 5x10 20 Atoms per cubic centimeter. The thickness of the second current diffusion layer 208 is 0.5 to 5 micrometers.

[0048] exist Figure 7 In the embodiment shown, the drift layer 202 at the entrance of channel 206 is further provided with a first current diffusion layer 207, and the drift layer 202 at the exit of channel 206 is further provided with a second current diffusion layer 208, so as to reduce the diffusion resistance caused by the increased current path length when the current enters and leaves channel 206 due to the need to bypass the gate doped region 204.

[0049] Figure 8 This is a schematic diagram of the semiconductor structure described in other embodiments of this application. It should be noted that, for the sake of brevity, Figure 8 In the semiconductor structure 300 shown, and Figure 1 The same or similar contents in the semiconductor structure 100 shown will not be described in detail; only the different contents will be described.

[0050] refer to Figure 8 As shown, in some embodiments of this application, compared to Figure 1 The semiconductor structure 100 shown has a gate connection region 305 and a gate doped region 304 formed by the same ion implantation process. Therefore, the gate connection region 305 and the gate doped region 304 have the same depth and the same doping concentration.

[0051] exist Figure 8 In the illustrated embodiment, the gate connection region 305 and the gate doped region 304 are formed by ion implantation after the same photolithography, which eliminates one photolithography step, helps to reduce production time, improve productivity and yield, reduce photoresist material costs, and reduce overall production costs.

[0052] This application provides a semiconductor structure that offers a more effective solution for reducing the on-resistance of silicon carbide power devices.

[0053] This application also provides a method for forming a semiconductor structure, see reference. Figure 1 As shown, the method includes: providing a semiconductor substrate 101, on which a drift layer 102 and a source doped region 103 are sequentially formed; forming a plurality of trenches 100a, which extend along the x-direction and penetrate the source doped region 103 to the drift layer 102; forming a plurality of gate connection regions 105, which respectively cover the bottom and part of the sidewalls of the plurality of trenches 100a; forming a plurality of gate doped regions 104, which extend along the y-direction and are located below the gate connection regions 105 and cover part of the gate connection regions 105, wherein the y-direction and the x-direction are perpendicular to each other.

[0054] It should be noted that the focus of this application is on the semiconductor structure, and the specific process for forming the semiconductor structure can be selected from suitable processes well known to those skilled in the art, and will not be elaborated further. For example, a suitable ion implantation process can be selected to form the gate connection region 105 and the gate doped region 104.

[0055] In some embodiments of this application, the method of forming the semiconductor structure further includes: forming a gate silicide 112 in the trench 100a, wherein the bottom and sidewalls of the gate silicide 112 are completely covered by the gate connection region 105.

[0056] In some embodiments of this application, the method of forming the semiconductor structure further includes: forming an interlayer dielectric layer 113 on the top surface of the gate silicide 112 that fills the trench 100a and extends partially above the source doped region 103.

[0057] In some embodiments of this application, reference is made to Figure 7 As shown, the method for forming the semiconductor structure further includes: forming a first current diffusion layer 207, wherein the first current diffusion layer 207 is located between the source doped region 203 and the gate doped region 204, the top surface of the first current diffusion layer 207 is connected to the source doped region 203, and the bottom surface of the first current diffusion layer 207 is connected to the gate doped region 204.

[0058] In some embodiments of this application, reference is made to Figure 7As shown, the method for forming the semiconductor structure further includes: forming a second current diffusion layer 208, the second current diffusion layer 208 being located between the semiconductor substrate 201 and the gate doped region 204, and the top surface of the second current diffusion layer 208 being connected to the gate doped region 204.

[0059] refer to Figure 8 As shown, in some embodiments of this application, the gate connection region 305 and the gate doped region 304 are formed by the same ion implantation process.

[0060] This application provides a semiconductor structure and a method for forming the same, offering a more effective solution for reducing the on-resistance of silicon carbide power devices.

[0061] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0062] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "comprise," or "including" as used in this application specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0063] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0064] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that, include: A semiconductor substrate, wherein a drift layer and a source doped region are sequentially formed on the surface of the semiconductor substrate; Several trenches extend along the x-direction and penetrate the source doped region into the drift layer; Several gate connection regions respectively cover the bottom and part of the sidewalls of the several trenches; Several gate doped regions extend along the y-direction and are located below and partially cover the gate connection region, wherein the y-direction and the x-direction are perpendicular to each other.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first current diffusion layer is located between the source doped region and the gate doped region. The top surface of the first current diffusion layer is connected to the source doped region, and the bottom surface of the first current diffusion layer is connected to the gate doped region.

3. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second current diffusion layer is located between the semiconductor substrate and the gate doped region, and the top surface of the second current diffusion layer is connected to the gate doped region.

4. The semiconductor structure as described in claim 1, characterized in that, The gate connection region and the gate doped region are formed by the same ion implantation process.

5. The semiconductor structure as described in claim 1, characterized in that, A gate silicide is formed in the trench, and the bottom and sidewalls of the gate silicide are completely covered by the gate connection region.

6. The semiconductor structure as described in claim 5, characterized in that, The top surface of the gate silicide has an interlayer dielectric layer that fills the trench and extends partially above the source doped region.

7. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, wherein a drift layer and a source doped region are sequentially formed on the surface of the semiconductor substrate; A plurality of trenches are formed, the plurality of trenches extending along the x-direction and penetrating the source doped region into the drift layer; A plurality of gate connection regions are formed, wherein the plurality of gate connection regions respectively cover the bottom and part of the sidewalls of the plurality of trenches; A plurality of gate doped regions are formed, the plurality of gate doped regions extending along the y-direction and located below the gate connection region and covering part of the gate connection region, the y-direction and the x-direction being perpendicular to each other.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: A first current diffusion layer is formed, which is located between the source doped region and the gate doped region. The top surface of the first current diffusion layer is connected to the source doped region, and the bottom surface of the first current diffusion layer is connected to the gate doped region.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: A second current diffusion layer is formed, which is located between the semiconductor substrate and the gate doped region, and the top surface of the second current diffusion layer is connected to the gate doped region.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The gate connection region and the gate doped region are formed by the same ion implantation process.

11. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: A gate silicide is formed in the trench, and the bottom and sidewalls of the gate silicide are completely covered by the gate connection region.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, Also includes: An interlayer dielectric layer is formed on the top surface of the gate silicide to fill the trench and partially extend above the source doped region.

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