Array substrate and display device

Abstract

The invention provides an array substrate and a display device, and belongs to the technical field of display. The array substrate comprises a substrate body, pixel units arranged on the substrate body, a first test line, a first test terminal, a gating circuit, a plurality of first bonding pads arranged side by side in the first direction, a plurality of second bonding pads arranged side by side in the first direction, a plurality of third bonding pads arranged side by side in the first direction and an electrostatic discharge structure. The first bonding pad, the gating circuit and the second bonding pad are all located in the first sub-binding area, the first bonding pad is closer to the display area than the second bonding pad, and the gating circuit is arranged between the first bonding pad and the second bonding pad; the third bonding pad is located in the second sub-binding area; the first bonding pad and the second bonding pad are configured to be in binding connection with the driving chip; the first test terminal is located in the wiring area; the two ends of the first test line penetrate through the first sub-binding area, extend to the wiring area and are electrically connected with the first test terminal; at least one end of the first test line is electrically connected with the electrostatic discharge structure.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to an array substrate and a display device. Background Technology

[0002] During the manufacturing and use of display products, internal static electricity is inevitably generated. This static electricity accumulates inside the product, such as at the tips of metal traces. Once it accumulates to a certain level, it will generate a large instantaneous discharge, which is electrostatic discharge (ESD), also known as tip discharge. This can cause irreversible damage such as short circuits in metal traces and burn-out of devices, seriously affecting product yield. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide an array substrate and a display device.

[0004] In a first aspect, the technical solution adopted to solve the technical problem of this disclosure is an array substrate having a display area and a bonding area located on one side of the display area; the bonding area includes a first sub-bonding area, a second sub-bonding area located on the side of the first sub-bonding area away from the display area, and a wiring area surrounding the first sub-bonding area and the second sub-bonding area;

[0005] The array substrate includes a substrate, pixel units disposed on the substrate, a first test line, a first test terminal, a gating circuit, a plurality of first pads arranged side by side along a first direction, a plurality of second pads arranged side by side along the first direction, a plurality of third pads arranged side by side along the first direction, and an electrostatic discharge structure; the pixel units are located in the display area;

[0006] The first pad, the gating circuit, and the second pad are all located in the first sub-bonding area, and the first pad is closer to the display area than the second pad. The gating circuit is disposed between the first pad and the second pad. The third pad is located in the second sub-bonding area.

[0007] The first pad and the second pad are both configured to be bonded to the driver chip; the third pad is configured to be bonded to the flexible circuit board.

[0008] The first test terminal is located in the wiring area; both ends of the first test wire pass through the first sub-binding area and extend to the wiring area, and are electrically connected to the first test terminal;

[0009] At least one end of the first test lead is electrically connected to the electrostatic discharge structure.

[0010] In some embodiments, the array substrate further includes a peripheral region surrounding the display area, and a fan-out region disposed between the peripheral region and the bonding region;

[0011] The array substrate further includes a second test terminal, a second test line, a plurality of touch electrode lines extending along a second direction, and touch leads electrically connected to the touch electrode lines; the second test terminal is located in the trace area; both ends of the second test line pass through a first sub-bonding area and extend to the trace area; both ends of the touch electrode lines pass through the display area and extend to the peripheral area; the touch leads pass through the fan-out area, with one end extending to the peripheral area and electrically connected to the touch electrode line, and the other end extending to the first sub-bonding area and electrically connected to the first pad; the second direction intersects with the first direction;

[0012] The selection circuit includes a switching transistor that corresponds to each of the touch leads; the first electrode of the switching transistor is electrically connected to the first pad connected to the corresponding touch lead, the second electrode is electrically connected to the first test line, and the control electrode is electrically connected to the second test line.

[0013] In some embodiments, the array substrate includes a common electrode bus located in the peripheral area and surrounding the display area, and a first common lead extending from the peripheral area to the wiring area; the common electrode bus includes two first sub-segments extending in a first direction and arranged opposite to each other, and two second sub-segments extending in a second direction and arranged opposite to each other; the first sub-segments and the second sub-segments are connected end to end in sequence;

[0014] The two ends of the first segment near the first sub-binding area are electrically connected to the first ends of the two first common leads respectively; the second end of the first common lead is electrically connected to one end of the first test lead;

[0015] The first common lead, the first sub-segment, and the second sub-segment are multiplexed as at least a portion of the electrostatic discharge structure.

[0016] In some embodiments, the first common lead and the first test lead are disposed on the same layer and connected as a single structure.

[0017] In some embodiments, for at least one first common lead, the second end of the first common lead and one end of the first test lead are both electrically connected to the same first test terminal.

[0018] In some embodiments, the array substrate further includes a first adapter line located in the wiring area;

[0019] The first common lead is on the same layer as the first test lead and is spaced apart from it.

[0020] The first test lead is on a different layer from the first adapter cable; the first test lead is electrically connected to the first common lead through the first adapter cable.

[0021] The first adapter cable is reused as another part of the electrostatic discharge structure.

[0022] In some embodiments, the array substrate further includes a third test terminal located in the wiring area;

[0023] For at least one first common lead, the second end of the first common lead and the first end of the first adapter wire are both electrically connected to the same third test terminal, and the second end of the first adapter wire and one end of the first test lead are both electrically connected to the same first test terminal.

[0024] In some embodiments, the array substrate further includes a driver chip and a common pad located in the first sub-bonding region;

[0025] The common pad, the plurality of first pads, and the plurality of second pads are respectively bonded and connected to the driver chip; the common pad and the first pads are arranged side by side along the first direction;

[0026] The first test line is spaced apart from the second pad; during normal display, the switching transistor is turned off, the driver chip provides a second operating voltage to the touch electrode line through the first pad, and provides a first reference voltage to the common electrode bus through the common pad, so as to load the first reference voltage onto the first test line.

[0027] In some embodiments, the second operating voltage and the first reference voltage are the same.

[0028] In some embodiments, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate.

[0029] The first test line, the second test line, the common electrode bus, the first common lead, and the control electrode of the switching transistor are all located in the first conductive layer;

[0030] The touch electrode line, the touch lead, and the first and second electrodes of the switching transistor are all located in the second conductive layer;

[0031] The first adapter line is located on the third conductive layer; at least a portion of the film layers of the first test terminal, the second test terminal, the third test terminal, the first pad, the second pad, the third pad, and the common pad are located on the third conductive layer.

[0032] In some embodiments, the electrostatic discharge structure includes at least one redundant pad located in the second sub-bonding region, and a second adapter cable located in the routing region and corresponding one-to-one with the redundant pad;

[0033] The first test line includes a first test segment located in the first sub-binding area and a second test segment located in the routing area;

[0034] For any of the redundant pads, the first end of the redundant pad is electrically connected to the second test segment via the corresponding second adapter cable, and the second end of the redundant pad is floating.

[0035] In some embodiments, the electrostatic discharge structure includes at least one redundant pad located in the first sub-bonding region, and a second adapter cable located in the first sub-bonding region and corresponding one-to-one with the redundant pad;

[0036] The first test line includes a first test segment located in the first sub-binding area and a second test segment located in the routing area;

[0037] For any of the redundant pads, the first end of the redundant pad is electrically connected to the second test segment via the corresponding second adapter cable, and the second end of the redundant pad is floating.

[0038] In some embodiments, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate.

[0039] The first test line, the second test line, and the control electrode of the switching transistor are located in the first conductive layer;

[0040] The touch electrode line, the touch lead, and the first and second electrodes of the switching transistor are all located in the second conductive layer;

[0041] The second adapter cable is located in the third conductive layer; at least a portion of the film layer of the first test terminal, the second test terminal, the first pad, the second pad, the third pad, and the redundant pad is located in the third conductive layer.

[0042] In some embodiments, the electrostatic discharge structure includes a plurality of protrusions located in the first sub-binding region, the protrusions being integrally connected to the first test line and protruding along the side away from the switching transistor.

[0043] In some embodiments, the first test line includes, in addition to its two ends, a first connection node located in the middle region and electrically connected to the second electrode of the switching transistor;

[0044] In the extension direction of the first test line, the protrusion is provided between adjacent first connection nodes.

[0045] In some embodiments, the electrostatic discharge structure is located in the trace area, with one end of the electrostatic discharge structure electrically connected to the first test line and the other end extending to the edge of the trace area.

[0046] In some embodiments, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate.

[0047] The first test line, the second test line, and the control electrode of the switching transistor are all located in the first conductive layer;

[0048] The touch electrode line, the touch lead, and the first and second electrodes of the switching transistor are all located in the second conductive layer;

[0049] The electrostatic discharge structure is located in the third conductive layer; at least a portion of the film layer of the first test terminal, the second test terminal, the first pad, the second pad, and the third pad is located in the third conductive layer.

[0050] In some embodiments, the linewidth of the electrostatic discharge structure is greater than the linewidth of the first test line.

[0051] In some embodiments, the array substrate further includes a flexible circuit board and a fourth pad located in the second sub-bonding area, and a third adapter line located in the wiring area;

[0052] The fourth pad is bonded to the flexible circuit board, and the fourth pad is electrically connected to the portion of the first test line located in the first sub-bonding area via the third adapter cable;

[0053] During the normal display phase, the switching transistor is turned off, and the flexible circuit board provides a first reference voltage to the first test line through the fourth pad to load the first test line with the first reference voltage.

[0054] In some embodiments, the array substrate further includes a driver chip located in the first sub-binding region;

[0055] Multiple first pads and multiple second pads are respectively bonded and connected to the driver chip;

[0056] During the normal display phase, the switching transistor is turned off, and the driver chip provides a second operating voltage to the touch electrode line through the first pad.

[0057] In some embodiments, the array substrate further includes a flexible circuit board and a fourth pad located in the second sub-bonding area, a fifth pad located in the first sub-bonding area, a third adapter line located in the trace area, and a fourth adapter line located in the first sub-bonding area; the fifth pad and the second pad are arranged side by side along the second direction;

[0058] The fourth pad is bonded to the flexible circuit board, the fourth pad is electrically connected to the fifth pad through the third adapter cable, and the fifth pad is electrically connected to the portion of the first test line located in the first sub-bonding area through the fourth adapter cable;

[0059] During the normal display phase, the switching transistor is turned off, and the flexible circuit board provides a first reference voltage to the first test line through the fourth and fifth pads.

[0060] In some embodiments, the array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate.

[0061] The first test line, the second test line, the third adapter line, and the control electrode of the switching transistor are all located in the first conductive layer;

[0062] The touch electrode line, the touch lead, and the first and second electrodes of the switching transistor are all located in the second conductive layer;

[0063] The fourth adapter line is located in the third conductive layer; at least a portion of the film layer of the first pad, the second pad, the third pad, the fourth pad, and the fifth pad is located in the third conductive layer.

[0064] In some embodiments, the second operating voltage and the first reference voltage are the same.

[0065] Secondly, embodiments of this disclosure also provide a display device, including an array substrate as described in any one of the first aspects. Attached Figure Description

[0066] Figure 1 This is a wiring diagram of the touch test line in an existing display product;

[0067] Figure 2 A schematic diagram of the array substrate provided in Example 1 of the embodiments of this disclosure;

[0068] Figure 3 A schematic diagram illustrating a connection relationship between the first common lead and the first test lead provided in an embodiment of this disclosure;

[0069] Figure 4A schematic diagram of the array substrate provided in Example 2 of the embodiments of this disclosure;

[0070] Figure 5 A schematic diagram illustrating another connection relationship between the first common lead and the first test lead provided in an embodiment of this disclosure;

[0071] Figure 6 This is a schematic diagram of the film layer stacking of the array substrate under Example 1 provided in the embodiments of this disclosure;

[0072] Figure 7 This is a schematic diagram of the film layer stacking of the array substrate under Example 2 provided in the embodiments of this disclosure;

[0073] Figure 8 A schematic diagram of the array substrate provided in Example 3 of the embodiments of this disclosure;

[0074] Figure 9 for Figure 8 A magnified view of the middle pad structure;

[0075] Figure 10 This is a schematic diagram of the film layer stacking of the array substrate under Example 3 provided in the embodiments of this disclosure;

[0076] Figure 11 A schematic diagram illustrating the connection relationship between redundant pads and the second adapter cable provided in an embodiment of this disclosure;

[0077] Figure 12 This is a schematic diagram showing the connection relationship between the third adapter cable and the fourth adapter cable provided in an embodiment of this disclosure;

[0078] Figure 13a A schematic diagram of the array substrate provided in Example 4 of the embodiments of this disclosure;

[0079] Figure 13b A schematic diagram of the array substrate provided in Example 5 of the embodiments of this disclosure;

[0080] Figure 14 A schematic diagram of the array substrate provided in Example 6 of the embodiments of this disclosure;

[0081] Figure 15 A schematic diagram of the array substrate provided in Example 7 of the embodiments of this disclosure;

[0082] Figure 16 This is a schematic diagram of the film layer stacking of the array substrate under Example 7 provided in the embodiments of this disclosure;

[0083] Figure 17 A schematic diagram illustrating the connection relationship between the peripheral AT wiring and the fifth adapter cable provided in this embodiment of the disclosure;

[0084] Figure 18This is a wiring diagram of the second test line provided in an embodiment of the present disclosure;

[0085] Figure 19 A schematic diagram illustrating the connection relationship between the sixth pad and the sixth adapter cable provided in an embodiment of this disclosure;

[0086] Figure 20 A schematic diagram illustrating the electrical connection relationship of a fourth pad provided in an embodiment of this disclosure;

[0087] Figure 21 This is a schematic diagram illustrating another electrical connection relationship of the fourth pad provided in an embodiment of this disclosure. Detailed Implementation

[0088] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0089] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0090] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0091] In the embodiments disclosed herein, the first direction X, the second direction Y, and the third direction Z intersect each other in pairs. In this disclosure, the first direction X and the second direction Y are perpendicular to each other in the plane where the base is located, the first direction X is a horizontal direction (or the extension direction of the gate line), the second direction Y is a vertical direction (or the extension direction of the data line), and the third direction Z is a vertical direction that is perpendicular to the plane where the base is located. However, this does not constitute a limitation on this disclosure.

[0092] In the embodiments of this disclosure, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same mask to form a single patterning process. Depending on the specific pattern, the sequential patterning process may include multiple exposure, development, or etching processes, and the specific pattern formed in the same layer may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0093] Before introducing the specific structure of the array substrate disclosed herein, the application scenarios and circuit structure of the array substrate provided herein will be described in detail. The array substrate disclosed herein can be applied to liquid crystal displays, that is, it is a liquid crystal array substrate.

[0094] The transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In the embodiments of this disclosure and the following description, to distinguish the source and drain of the transistor, one of them is called the first electrode, the other is called the second electrode, and the gate is called the control electrode. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. An N-type thin-film transistor refers to a thin-film transistor with N-type ion doping in the active layer; a P-type thin-film transistor refers to a thin-film transistor with P-type ion doping in the active layer. The operating level signal of an N-type thin-film transistor is a high-level signal; the operating level signal of a P-type thin-film transistor is a low-level signal.

[0095] In related technologies, performance testing is often incorporated into the manufacturing process of display products to improve product yield. For example, before IC bonding, external equipment is used to provide test signals to the internal circuitry of the array substrate via test lines. The performance test results are determined by judging whether the product can light up normally. However, in the design of the array substrate, its internal circuitry is complex. When the introduced test lines have long traces, ESD is prone to occur at their ends, which can easily lead to irreversible damage such as short circuits in metal traces and device burnout, seriously affecting product yield.

[0096] Figure 1 This is a wiring diagram of touch test lines in existing display products. In related technologies, such as... Figure 1 As shown, the display product has a display area AA, a terminal side (Data Pad, DP) located vertically below the display area AA, and a non-terminal side (Data Pad Opposite, DPO) located vertically above the display area AA. The display product includes a substrate 1, touch electrode lines Tx, touch test lines Tx_Test, and test terminals CT pads. During the testing phase of the display product manufacturing process, the switch circuit SW is turned on, and external devices are connected through the test terminals CT pads, providing a common signal (Vcom) to the touch test lines Tx_Test. The touch test lines Tx_Test transmit the common signal (Vcom) and provide it to the touch electrode lines Tx through the switch circuit SW in the on state.

[0097] During the normal display phase of the product, the switching circuit SW is off. At this time, a reference ground signal (GND) is provided to the touch test line Tx Test through the input terminal In of the driver chip (IC) using a flexible printed circuit board (FPC). Simultaneously, the driver chip (IC) is turned on, providing a common signal (Vcom) to the touch electrode line Tx through the output terminal Out of the driver chip (IC).

[0098] like Figure 1 As shown, the touch test line Tx_Test spans the entire array substrate and is electrically connected to the input terminal In of the driver chip (IC). The input terminal In is electrically connected to the FPC PIN of the flexible printed circuit board (FPC). The FPC PIN is like the tip of a long wire, which easily accumulates charge. ESD can easily occur in many process stages such as cutting, bonding, and transportation, resulting in irreversible damage such as short circuits in metal traces and device burnout, seriously affecting product yield.

[0099] In view of this, embodiments of the present disclosure provide an array substrate that substantially eliminates one or more of the problems caused by limitations and defects in related technologies.

[0100] Figure 2 This is a schematic diagram of the array substrate provided in Example 1 of the embodiments of this disclosure, as shown below. Figure 2 As shown, the array substrate has a display area AA and a bonding area BB located on one side of the display area AA; the bonding area BB includes a first sub-bonding area BB1, a second sub-bonding area BB2 located on the side of the first sub-bonding area BB1 away from the display area AA, and a trace area BB3 surrounding the first sub-bonding area BB1 and the second sub-bonding area BB2. The array substrate includes a substrate 1, pixel units (not shown in the figure) disposed on the substrate 1, a first test line 2, a first test terminal 31, a gating circuit 4, a plurality of first pads 51 arranged side by side along a first direction X, a plurality of second pads 52 arranged side by side along the first direction X, a plurality of third pads 53 arranged side by side along the first direction X, and an electrostatic discharge structure 6. The substrate 1 may be made of, but is not limited to, polyimide (PI), polyethylene naphthalene-2,6-dicarboxylate (PEN), polyethylene terephthalate (PET), colorless polyimide (CPI), thermoplastic polyurethane (TUP), or ultrathin glass (UTG). The substrate 11 may also be made of a rigid, transparent material such as glass, which can effectively support other film layers on it. In practical applications, appropriate materials can be selected according to actual needs. For example, the substrate 1 may be a single-layer structure or a multi-layer structure. In a multi-layer substrate 1, inorganic thin films can be added between the layers to act as buffer layers. The buffer layer material may be one or more layers of amorphous silicon (a-Si), silicon nitride (SiNx), or silicon oxide (SiOx).

[0101] The pixel unit is located in the display area AA; the first pad 51, the gating circuit 4, and the second pad 52 are all located in the first sub-bonding area BB1, with the first pad 51 being closer to the display area AA than the second pad 52. The gating circuit 4 is located between the first pad 51 and the second pad 52; the third pad 53 is located in the second sub-bonding area BB2. The first pad 51 and the second pad 52 are both configured to be bonded to a driver chip (not shown in the figure); the third pad 53 is configured to be bonded to a flexible circuit board (not shown in the figure). Specifically, the second pad 52 is electrically connected to the input pin of the driver chip, the first pad 51 is electrically connected to the output pin of the driver chip, and the third pad 53 is electrically connected to the output pin of the flexible circuit board.

[0102] The first test terminal 31 is located in the wiring area BB3; both ends of the first test line 2 pass through the first sub-binding area BB1 and extend to the wiring area BB3, and are electrically connected to the first test terminal 31; when the gating circuit 4 is in the on state, it provides a first operating voltage to the first test line 2 through the first test terminal 31 to test the display and / or touch functions of the display area AA. The first test terminal 31 is a contact pad. Here, an external testing device is needed to connect to the first test terminal 31 and provide the first operating voltage to the first test line 2 through the first test terminal 31. At this time, the gating circuit 4 is in the on state, so the first operating voltage can be transmitted through the gating circuit 4 to the structure under test located in the display area AA, such as a touch electrode or data line, to test whether the pixel unit lights up normally.

[0103] At least one end of the first test line 2 is electrically connected to the electrostatic discharge structure 6 for dispersing static electricity on the first test line 2.

[0104] For ease of understanding, this disclosure uses the first test line 2 as an example of the touch electrode line Tx. In some embodiments, the array substrate further includes a peripheral region CC surrounding the display area AA, and a fan-out region DD disposed between the peripheral region CC and the bonding area BB. Figure 2 As shown, the array substrate also includes a second test terminal 32, a second test line 7, a plurality of touch electrode lines Tx extending along the second direction Y, and touch leads 8 electrically connected to the touch electrode lines Tx. The touch electrode lines Tx and touch leads 8 are arranged in a one-to-one correspondence. The touch electrode lines Tx are electrically connected to touch electrodes (not shown in the figure), and the touch electrode lines Tx and touch electrodes can be arranged one-to-one or one-to-many. The second test terminal 32 is located in the wiring area BB3; both ends of the second test line 7 pass through the first sub-binding area BB1 and extend to the wiring area BB3, and at least one end is electrically connected to the second test terminal 32; for example, the second test terminal 32 includes two terminals, and both ends of the second test line 7 are electrically connected to the second test terminal 32 to receive control signals using the second test terminal 32.

[0105] The two ends of the touch electrode line Tx extend through the display area AA to the peripheral area CC. The touch lead 8 is a fan-out trace, passing through the fan-out area DD. One end of the touch lead 8 extends to the peripheral area CC and is electrically connected to the touch electrode line Tx, while the other end extends to the first sub-bonding area BB1 and is electrically connected to the first pad 51. The touch lead 8 and the first pad 51 are arranged in a one-to-one correspondence. The second direction Y is arranged to intersect with the first direction X, for example, the second direction Y is arranged perpendicular to the first direction X.

[0106] During the testing phase of the array substrate fabrication process, the driver chip is not bonded; during the normal display phase, the array substrate is bonded with the driver chip.

[0107] The selection circuit 4 includes a switching transistor 41 corresponding to each touch lead 8; multiple switching transistors 41 are arranged side by side along the first direction X. The first terminal S of the switching transistor 41 is electrically connected to the first pad 51 connected to the corresponding touch lead 8, the second terminal D is electrically connected to the first test line 2, and the control terminal G is electrically connected to the second test line 7.

[0108] This disclosure describes an embodiment using an N-type thin-film transistor as an example of a switching transistor 41, but this disclosure is not limited to N-type thin-film transistors. Here, an external testing device is required to connect to the second test terminal 32, through which a control signal is provided to the second test line 7. The second test line 7 is electrically connected to the control electrode of the switching transistor 41. In response to receiving the control signal, the control electrode of the switching transistor 41 conducts when the control signal is high. The first test line 2 is electrically connected to the second electrode of the switching transistor 41. The first operating voltage is transmitted to the touch lead 8 through the conducting switching transistor 41, and then to the touch electrode line Tx electrically connected to the touch lead 8. Under these conditions, the pixel unit is tested to ensure it illuminates normally.

[0109] The main extension direction of the first test line 2 and the main extension direction of the second test line 7 are both the first direction X. The orthogonal projection of the first test line 2 and the second test line 7 on the substrate 1 can span the orthogonal projection of the extension lines of all touch electrode lines Tx on the substrate 1.

[0110] like Figure 2 As shown, the first test line 2 is a long trace. The electrostatic discharge structure 6 is electrically connected to the first test line 2, allowing the electrostatic discharge structure 6 to release static electricity on the first test line 2, preventing ESD from occurring on the first test line 2 and affecting product yield.

[0111] The specific structure of electrostatic discharge structure 6 is described in detail below with different embodiments.

[0112] In some embodiments, such as Figure 2As shown, the array substrate includes a common electrode bus 9 located in the peripheral area CC and surrounding the display area AA, and a first common lead 101 extending from the peripheral area CC to the wiring area BB3. The common electrode bus 9 includes two first sub-segments 91 extending along a first direction X and arranged opposite each other, and two second sub-segments 92 extending along a second direction Y and arranged opposite each other. The first sub-segments 91 and the second sub-segments 92 are connected end to end. The two ends of a first sub-segment 91 near the first sub-binding area BB1 are electrically connected to the first ends of the two first common leads 101, respectively. The second end of the first common lead 101 is electrically connected to one end of the first test line 2. The first common lead 101, the first sub-segment 91 and the second sub-segment 92 are multiplexed as at least a part of the electrostatic discharge structure 6. The first common lead 101 is used to conduct static electricity on the first test line 2 into the first sub-segment 91 and the second sub-segment 92, and the first sub-segment 91 and the second sub-segment 92 are used to disperse the static electricity to achieve electrostatic discharge.

[0113] During the testing phase of the array substrate, a first operating voltage is provided to the first test line 2. At this time, since the first test line 2 is electrically connected to the first common lead 101, the first common lead 101 is also connected to the first operating voltage, thereby connecting the common electrode bus 9 to the first operating voltage. Optionally, the first operating voltage is a common voltage (Vcom), for example, -3V; the common electrode bus 9 can provide a common voltage (Vcom) to the redundant touch electrode lines (Tx_dummy).

[0114] The array substrate also includes a second common lead 102 and a common pad 50 corresponding to the second common lead 102. The second common lead 102 passes through the fan-out region DD, with one end extending to the peripheral region CC and electrically connected to the common electrode bus 9, and the other end extending to the first sub-bonding region BB1 and electrically connected to the common pad 50.

[0115] During the normal display phase of the array substrate, the driver chip is bonded, and a first reference voltage is provided to the common electrode bus 9 through the common pad 50. At this time, since the common electrode bus 9 is electrically connected to the first test line 2 through the first common lead 101, the first test line 2 is also connected to the first reference voltage. Optionally, the first reference voltage is a common voltage (Vcom), for example, -3V; the common electrode bus 9 can provide a common voltage (Vcom) to the redundant touch electrode line (Tx_dummy).

[0116] Optionally, the line width of the common electrode bus 9 is greater than the line width of the first test line 2, which is beneficial for dispersing static charge.

[0117] Optionally, the line width of the second segment 92, which is in direct contact with the first common lead 101, is greater than the line width of the first test line 2.

[0118] Optionally, the line width of the first common lead 101 is greater than the line width of the first test lead 2.

[0119] Figure 3 This is a schematic diagram illustrating a connection relationship between the first common lead 101 and the first test lead 2 provided in an embodiment of this disclosure. In one possible implementation, as... Figure 3 As shown, the first common lead 101 and the first test lead 2 can be arranged on the same layer and connected as an integral structure, which can quickly guide the static electricity on the first test lead 2 into the common electrode bus 9 through the first common lead 101 connected to it, so as to disperse the charge.

[0120] like Figure 2 As shown, for at least one first common lead 101, the second end of the first common lead 101 and one end of the first test line 2 are both electrically connected to the same first test terminal 31.

[0121] For example, the array substrate has two first test terminals 31, which are electrically connected to the two ends of the first test line 2, respectively.

[0122] For example, the array substrate has a first test terminal 31 that is electrically connected to one end of the first test line 2.

[0123] Figure 4 A schematic diagram of the array substrate provided in Example 2 of the embodiments of this disclosure; Figure 5 This is a schematic diagram illustrating another connection relationship between the first common lead 101 and the first test lead 2 provided in an embodiment of this disclosure. In another possible implementation, such as... Figure 4 and Figure 5 As shown, the array substrate also includes a first adapter line 111 located in the wiring area BB3; the first common lead 101 is on the same layer as the first test line 2 and is spaced apart; the first test line 2 is on a different layer from the first adapter line 111; the first test line 2 is electrically connected to the first common lead 101 through the first adapter line 111; the first common lead 101, the first sub-segment 91 and the second sub-segment 92 are multiplexed as part of the electrostatic discharge structure 6, and the first adapter line 111 is multiplexed as another part of the electrostatic discharge structure 6.

[0124] For example, the first adapter cable 111 includes two cables, one of which has a first end electrically connected to the second end of a first common lead 101 and the second end of the first adapter cable 111 electrically connected to one end (first end A) of the first test line 2; the other cable has a first end electrically connected to the second end of another first common lead 101 and the second end of the first adapter cable 111 electrically connected to the other end (second end B) of the first test line 2.

[0125] like Figure 4As shown, the array substrate also includes a third test terminal 33 located in the trace area BB3; for example, the first test terminal 31, the second test terminal 32, and the third test terminal 33 are arranged side by side along the first direction X, and the third test terminal 33 is located on the side of the first test terminal 31 away from the second test terminal 32. For at least one first common lead 101, the second end of the first common lead 101 and the first end of the first adapter wire 111 are both electrically connected to the same third test terminal 33, and the second end of the first adapter wire 111 and one end of the first test line 2 are both electrically connected to the same first test terminal 31.

[0126] For example, the array substrate has two first test terminals 31, which are electrically connected to the two ends of the first test line 2, respectively.

[0127] For example, the array substrate has a first test terminal 31 that is electrically connected to one end of the first test line 2.

[0128] In this embodiment, the first common lead 101 and the first test lead 2 are arranged on the same layer and are bridging each other through the first adapter wire 111 on different layers. The two first common leads 101, the first adapter wire 111, the first sub-segment 91 and the second sub-segment 92 are reused as the electrostatic discharge structure 6. The electrostatic charge on the first test lead 2 is conducted into the first sub-segment 91 and the second sub-segment 92 by using the electrically connected first adapter wire 111 and the first common lead 101, and the electrostatic charge is dispersed by the first sub-segment 91 and the second sub-segment 92 to achieve electrostatic discharge.

[0129] Compared to the array substrate in Example 2, the array substrate in Example 1 saves the third test terminal 33. During the testing phase of the array substrate, the first test terminal 31 is used to simultaneously power the common electrode bus 9 and the first test line 2, saving wiring space.

[0130] In some embodiments, such as Figure 2 or Figure 4 As shown, the first test line 2 and the second pad 52 are spaced apart.

[0131] Examples 1 and 2 avoid the adverse effects of ESD by simply adjusting the connection structure of the first test line 2, such as breaking the connection between the first test line 2 and the second pad 52, and forming an electrostatic ring by connecting the first test line 2 and the first common lead 101.

[0132] In some embodiments, for example 1 and example 2 above, such as Figure 2 or Figure 4As shown, the array substrate also includes a driver chip (not shown in the figure) located in the first sub-bonding area BB1 and a common pad 50; the common pad 50, a plurality of first pads 51 and a plurality of second pads 52 are respectively bonded to the driver chip; the common pad 50 and the first pads 51 are arranged side by side along the first direction X, and the common pad 50 is located on the side of the first pad 51 near the edge of the first sub-bonding area BB1.

[0133] like Figure 2 or Figure 4 As shown, the first test line 2 and the second pad 52 are spaced apart; during the normal display phase, the switching transistor 41 is turned off, and the driver chip provides a second working voltage to the touch electrode line Tx through the first pad 51, and provides a first reference voltage to the common electrode bus 9 through the common pad 50, so as to load the first reference voltage onto the first test line 2.

[0134] In this embodiment, the first test line 2 is disconnected from the second pad 52, compared to... Figure 1 In the existing structure shown, during the normal display phase, the reference ground signal is no longer provided through the flexible circuit board. Instead, the first reference voltage is provided to the first test line 2 through the common pad 50, with the help of the second common lead 102 and the first common lead 101.

[0135] Optionally, the first reference voltage ranges from -3V to 0V. For example, the first reference voltage is the ground voltage (0V) or the common voltage (-3V).

[0136] In some embodiments, the first operating voltage and the second operating voltage are the same. For example, both the first operating voltage and the second operating voltage are common voltages.

[0137] In some embodiments, the second operating voltage and the first reference voltage are the same and are both common voltages, such as -3V. During the normal display phase of the product, compared to providing a reference ground signal to the first test line 2 in related technologies, this disclosure uses the same second operating voltage and the first reference voltage, both being common voltages. This eliminates the voltage difference between the source and drain of the switching transistor 41 during its off-state, reducing touch noise and improving the stability of the common signal of the touch electrode line Tx, which is beneficial for identifying the user's actual touch position.

[0138] In some embodiments, the first operating voltage, the second operating voltage, and the first reference voltage are the same, for example, all of them are common voltages.

[0139] Figure 6 This is a schematic diagram of the film layer stacking of the array substrate provided in Example 1 of this disclosure. In some embodiments, for Example 1, such as Figure 6As shown, the array substrate includes a first conductive layer 01, a second conductive layer 02, and a third conductive layer 03 sequentially disposed along a direction away from the substrate 1. The first test line 2, the second test line 7, the common electrode bus 9, the first common lead 101, and the control electrode G of the switching transistor 41 are all located on the first conductive layer 01. The touch electrode line Tx, the touch lead 8, and the first electrode S and the second electrode D of the switching transistor 41 are all located on the second conductive layer 02. At least a portion of the film layers of the first test terminal 31, the second test terminal 32, the first pad 51, the second pad 52, the third pad 53, and the common pad 50 are located on the third conductive layer 03. The connection terminals of the first test terminal 31, the second test terminal 32, the first pad 51, the second pad 52, the third pad 53, and the common pad 50 are located on the third conductive layer 03.

[0140] For example, the first test terminal 31, the second test terminal 32, the first pad 51, the second pad 52, the third pad 53, and the common pad 50 all include a multi-layer connection structure. The connection ends of the first test terminal 31 and the second test terminal 32 are connected to external testing equipment. The connection ends of the first pad 51, the second pad 52, and the common pad 50 are bonding ends for bonding to the driver chip. The connection end of the third pad 53 is a bonding end for bonding to the flexible circuit board. The connection ends are located at the top layer of the multi-layer connection structure, that is, at the third conductive layer 03. The connection end of the first test terminal 31 located at the third conductive layer 03 can be transferred through a first overlap portion (not shown in the figure) located at the second conductive layer 02 and then electrically connected to the first test line 2. Similarly, the connection end of the second test terminal 32 located at the third conductive layer 03 can be transferred through a second overlap portion (not shown in the figure) located at the second conductive layer 02 and then electrically connected to the second test line 7. The connection end of the common pad 50 located on the third conductive layer 03 can be connected to the second common lead 102 located on the first conductive layer 01 via the third overlap portion (not shown in the figure) located on the second conductive layer 02. The connection end of the second pad 52 located on the third conductive layer 03 can be connected to the first connection portion 521 located on the first conductive layer 01 via the fourth overlap portion (not shown in the figure) located on the second conductive layer 02; the connection end of the third pad 53 located on the third conductive layer 03 can be connected to the second connection portion 531 located on the first conductive layer 01 via the fifth overlap portion (not shown in the figure) located on the second conductive layer 02.

[0141] Figure 7 This is a schematic diagram of the film layer stacking of the array substrate under Example 2 provided in this disclosure. In some embodiments, for Example 1, such as Figure 7As shown, the array substrate includes a first conductive layer 01, a second conductive layer 02, and a third conductive layer 03 sequentially disposed along a direction away from the substrate 1; wherein, the first test line 2, the second test line 7, the common electrode bus 9, the first common lead 101, and the control electrode G of the switching transistor 41 are all located in the first conductive layer 01; the touch electrode line Tx, the touch lead 8, and the first electrode S and the second electrode D of the switching transistor 41 are all located in the second conductive layer 02; the first adapter line 111 is located in the third conductive layer 03; at least a portion of the film layer (connection terminal) of the first test terminal 31, the second test terminal 32, the third test terminal 33, the first pad 51, the second pad 52, the third pad 53, and the common pad 50 is located in the third conductive layer 03.

[0142] It should be noted that, Figure 6 and Figure 7 The membrane stacking structure shown only represents the stacking relationship of each membrane layer, not the actual position and size.

[0143] For example, the third test terminal 33 includes a multi-layer connection structure. The connection end is located on the top layer, namely the third conductive layer 03. The connection end of the third test terminal 33 located on the third conductive layer 03 can be transferred through the sixth overlap (not shown in the figure) located on the second conductive layer 02, and then electrically connected to the first common lead 101 located on the first conductive layer 01.

[0144] For example 1, such as Figure 6 As shown, the first test line 2 and the first common lead 101 are both located on the first conductive layer 01 and are connected as a single structure, and are electrically connected to the common electrode bus 9 to discharge the electrostatic charge on the first test line 2.

[0145] For example 2, such as Figure 7 As shown, the first test line 2 and the first common lead 101 are both located on the first conductive layer 01 and are spaced apart; the first test line 2 and the first common lead 101 are connected by a first adapter wire 111 located on the second conductive layer 02. The first test terminal 31, the third test terminal 33 and the first adapter wire 111 are all located on the third conductive layer 03; the first test terminal 31, the first adapter wire 111 and the third test terminal 33 are connected as a single structure.

[0146] Optionally, the second common lead 102 is located in the first conductive layer 01 and is integrated with the common electrode bus 9.

[0147] like Figure 6As shown, a gate insulating layer GI is also included between the first conductive layer 01 and the second conductive layer 02. A first passivation layer PVX1, a planarization layer PLN, and a second passivation layer PVX2 are also sequentially disposed along the direction away from the substrate 1 between the second conductive layer 02 and the third conductive layer 03. The first test line 2 is electrically connected to the second electrode D of the switching transistor 41 through a first via V1 penetrating the gate insulating layer GI; the first electrode S of the switching transistor 41 is disposed on the same layer as the touch lead 8, and the two are connected as a single structure. For example, the first pad 51 can be electrically connected to the first pad 51 through a second via (not shown in the figure) sequentially penetrating the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2, or the first pad 51 can be electrically connected to the touch lead 8 through a third via V3 sequentially penetrating the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2; the touch lead 8 is disposed on the same layer as the touch electrode line Tx, and the two are connected as a single structure. The common pad 50 is electrically connected to the second common lead 102 via a fourth via V4 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2. The first test terminal 31 is electrically connected to the first test line 2 via a fifth via V5 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2. The second test terminal 32 is electrically connected to the second test line 7 via a sixth via V6 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2.

[0148] like Figure 7 As shown, the first test terminal 31 is electrically connected to the first test line 2 through a fifth via V5 that sequentially passes through the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2. The third test terminal 32 is electrically connected to the first common lead 101 through a seventh via V7 that sequentially passes through the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2.

[0149] The materials of the first passivation layer PVX1 and the second passivation layer PVX2 can be the same, including organic and / or inorganic materials. Organic passivation materials include polyimides; inorganic passivation materials include silicon oxides (e.g., silicon dioxide SiO2) and silicon nitrides (e.g., trisilicon tetranitride Si3N4). The material of the planarization layer PLN can include, but is not limited to, one or more combinations of resin materials such as acrylic, polyimide, epoxy resin, polyester, photoresist, polyacrylate, polyamide, and siloxane; or elastic materials such as urethane and thermoplastic polyurethane (TPU).

[0150] For example 1 above, in the relevant products (such as...) Figure 1Based on the above, only one mask of the first conductive layer 01 needs to be changed to connect the first test line 2 and the first common lead 101 into a single structure, and to break the connection between the first test line 2 and the second pad 52. Therefore, the setting of the electrostatic discharge structure 6 disclosed herein will not affect the process of the entire manufacturing process. Only the mask of the first conductive layer 01 needs to be changed, and the impact on the product manufacturing stage is low.

[0151] For example 2 above, in the relevant products (such as...) Figure 1 Based on the above, it is necessary to change one mask of the first conductive layer 01 and one mask of the third conductive layer 03. Specifically, changing the mask of the first conductive layer 01 breaks the connection between the first test line 2 and the second pad 52; changing the mask of the second conductive layer 02 allows the first test line 2 and the first common lead 101 to be connected through the first cross-layer adapter 111. Therefore, the setting of the electrostatic discharge structure 6 disclosed herein will not affect the process of the entire manufacturing process; only some masks need to be changed, resulting in a low impact on the product manufacturing stage.

[0152] Figure 8 This is a schematic diagram of the array substrate provided in Example 3 of the embodiments of this disclosure. Figure 9 for Figure 8 A partially enlarged view of the pad structure. In some embodiments, such as... Figure 8 and Figure 9 As shown, the array substrate also includes at least one redundant pad 56 located in the second sub-bonding area BB2, and a second adapter line 112 located in the routing area BB3 and corresponding to the redundant pad 56. The first test line 2 includes a first test segment 21 located in the first sub-bonding area BB1 and a second test segment 22 located in the routing area BB3; for any redundant pad 56, the first end of the redundant pad 56 is electrically connected to the second test segment 22 through the corresponding second adapter line 112, and the second end of the redundant pad 56 is floating.

[0153] Optionally, such as Figure 9As shown, there are multiple first sub-binding areas BB1, and these multiple first sub-binding areas BB1 are arranged side by side along the first direction X. There are multiple second sub-binding areas BB2, and these multiple second sub-binding areas BB2 are arranged side by side with the first direction X, and each second sub-binding area BB2 corresponds to a first sub-binding area BB1. There are multiple first test segments 21, each located in a different first sub-binding area BB1; there are multiple second test segments 22, each connected to both ends of the first test segment 21. For any second test segment 22, it is electrically connected to at least one second adapter line 112, and static electricity is released through redundant pads 56, thereby dispersing the tip charge on a single fourth pad 54. During the testing phase, the second end of the fourth pad 54 is floating, and the first end is electrically connected to the first test segment 21; during the normal display phase, the fourth pad 54 is bonded to the flexible circuit board to provide a first reference voltage for the first test line 2.

[0154] Taking two first sub-binding regions BB1 as an example, the first test segment 21 includes two segments; the second test segment 22 includes three segments. The second test segment 22, located at the end of the first test line 2, is electrically connected to a redundant pad 56 via a second adapter cable 112. The connection node between the second adapter cable 112 and the second test segment 22 is the second connection node N2. Here, the redundant pad 56 connected to the second adapter cable 112 is the one closest to the second connection node N2. The closer to the second connection node N2, the shorter the second adapter cable 112, and the lower the ESD risk. Simultaneously, the redundant pad 56 disperses the tip charge on the single fourth pad 54, further reducing the ESD risk. The second test segment 22, located between two adjacent first test segments 21, is electrically connected to two redundant pads 56 via two second adapter wires 112. One of the second adapter wires 112 is adjacent to a first sub-bonding area BB1 at the second connection node N2 of the second test segment 22 and is electrically connected to the nearest redundant pad 56. The other second adapter wire 112 is adjacent to another first sub-bonding area BB1 at the second connection node N2 of the second test segment 22 and is electrically connected to the nearest redundant pad 56.

[0155] Optionally, the bonding area BB includes a first sub-bonding area BB1 and a second sub-bonding area BB2. The first test line 2 includes a first test segment 21 located in the first sub-bonding area and a second test segment 22 located in the second sub-bonding area BB2. There are two second test segments 22, which are respectively connected to the two ends of the first test segment 21. For any second test segment 22, it is electrically connected to at least one second adapter line 112 and discharges static electricity through the nearest redundant pad 56, thereby dispersing the tip charge on the single fourth pad 54.

[0156] Figure 10This is a schematic diagram of the film layer stacking of the array substrate under Example 3 provided for embodiments of this disclosure. In some embodiments, such as Figure 10 As shown, the array substrate includes a first conductive layer 01, a second conductive layer 02, and a third conductive layer 03 sequentially disposed along a direction away from the substrate 1; wherein, the first test line 2, the second test line 7, and the control electrode G of the switching transistor 41 are located in the first conductive layer 01; the touch electrode line Tx, the touch lead 8, and the first electrode S and the second electrode D of the switching transistor 41 are all located in the second conductive layer 02; the second adapter line 112 is located in the third conductive layer 03; at least a portion of the film layers of the first test terminal 31 (not shown in the figure), the second test terminal 32, the fourth test terminal 34, the first pad 51, the second pad 52 (not shown in the figure), the third pad 53 (not shown in the figure), and the redundant pad 56 are located in the third conductive layer 03.

[0157] It should be noted that, Figure 10 The membrane stacking structure shown only represents the stacking relationship of each membrane layer, not the actual position and size.

[0158] For example, the redundant pad 56 includes a multi-layer connection structure, wherein the discharge end is located on the top layer, i.e., the third conductive layer 03. The discharge end of the redundant pad 56 located on the third conductive layer 03 can be transferred through a seventh overlap (not shown) located on the second conductive layer 02, and then electrically connected to the second adapter wire 112 located on the first conductive layer 01. The fourth test terminal 34 includes a multi-layer connection structure, wherein the connection end is located on the top layer, i.e., the third conductive layer 03. The connection end of the fourth test terminal 34 located on the third conductive layer 03 can be transferred through an eighth overlap (not shown) located on the second conductive layer 02, and then electrically connected to the first common lead 101 located on the first conductive layer 01.

[0159] Figure 11 This is a schematic diagram illustrating the connection relationship between the redundant pads and the second adapter cable provided in an embodiment of this disclosure, as shown below. Figure 11 As shown, the first test line 2 is a long trace; the second adapter line 112 includes a first adapter segment 1121 and a second adapter segment 1122 connected to the first adapter segment 1121. The first adapter segment 1121 is located in the third conductive layer 03, and the second adapter segment 1122 is located in the first conductive layer 01. The first test line 2 (second test segment 22) and the second adapter segment 1122 are on the same layer but spaced apart. The second test segment 22 and the second adapter segment 1122 are connected across layers via the first adapter segment 1121. Figure 10 and Figure 11As shown, the second test segment 22 is electrically connected to the first transition segment 1121 through an eighth via V8 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2; the first transition segment 1121 is electrically connected to the second transition segment 1122 through a ninth via V9 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2; and the second transition segment 1122 is electrically connected to the redundant pad 56 through a tenth via V10 that sequentially penetrates the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2.

[0160] In this embodiment, the second transition segment 1122 and the first test line 2 of the same layer are disconnected and are bridged by the first transition segment 1121 of different layers to avoid ESD of long traces of the same layer. Especially in the product manufacturing stage, the disconnection of the second transition segment 1122 and the first test line 2 in the first conductive layer 01 can reduce the ESD risk before the formation of the third conductive layer 03.

[0161] like Figure 8 As shown, the array substrate includes a common electrode bus 9 located in the peripheral area CC and surrounding the display area AA, a first common lead 101 extending from the peripheral area CC to the wiring area BB3, and a fourth test terminal 34 located in the wiring area BB3. The common electrode bus 9 includes two first sub-segments 91 extending along a first direction X and arranged opposite each other, and two second sub-segments 92 extending along a second direction Y and arranged opposite each other. The first sub-segments 91 and the second sub-segments 92 are connected end to end. The two ends of a first sub-segment 91 near the first sub-bonding area BB1 are electrically connected to the first ends of the two first common leads 101, respectively; the second ends of the first common leads 101 are electrically connected to the fourth test terminal 34. The fourth test terminal 34 is configured to provide a common voltage, such as -3V, to the common electrode bus 9 through an external power supply device during the testing phase. The array substrate also includes a second common lead 102 and a common pad 50 corresponding to the second common lead 102. The second common lead 102 passes through the fan-out area DD, with one end extending to the peripheral area CC and electrically connected to the common electrode bus 9, and the other end extending to the first sub-bonding area BB1 and electrically connected to the common pad 50. The common pad 50 is configured to bond the driver chip during normal display, and to provide a common voltage, such as -3V, to the common electrode bus 9 through the common pad 50.

[0162] like Figure 10 As shown, the common electrode bus 9, the first common lead 101, and the second common lead 102 are all located on the first conductive layer 01; the fourth test terminal 34 and the common pad 50 are located on the third conductive layer 03. The common electrode bus 9, the first common lead 101, and the second common lead 102 are connected as a single structure.

[0163] Figure 12 This is a schematic diagram illustrating the connection relationship between the third adapter cable 113 and the fourth adapter cable 114 provided in an embodiment of this disclosure. Figure 8 and Figure 12 As shown, the array substrate also includes a fourth pad 54 located in the second sub-bonding area BB2, a fifth pad 55 located in the first sub-bonding area BB1, a third adapter wire 113 located in the trace area BB3, and a fourth adapter wire 114 located in the first sub-bonding area BB1. The fifth pad 55 and the second pad 52 are arranged side by side along the second direction Y. The fourth pad 54 is configured to be bonded to the flexible circuit board, and the fourth pad 54 is electrically connected to the fifth pad 55 through the third adapter wire 113. The fifth pad 55 is electrically connected to the first test segment 21 through the fourth adapter wire 114.

[0164] like Figure 10 and Figure 12 As shown, the fourth adapter line 114 is located in the third conductive layer 03. The third adapter line 113 is located in the first conductive layer 01 or the second conductive layer 02; at least a portion of the film layer in the fourth pad 54 and the fifth pad 55 is located in the third conductive layer 03. The bonding ends in both the fourth pad 54 and the fifth pad 55 are located in the third conductive layer 03.

[0165] Optionally, such as Figure 10 and Figure 12 As shown, the third adapter cable 113 includes two layers of metal traces stacked together, located in the first conductive layer 01 and the second conductive layer 02, respectively.

[0166] Figure 13a This is a schematic diagram of the array substrate in Example 4 provided in the embodiments of this disclosure. Figure 13b This is a schematic diagram of the array substrate provided in Example 5, which is an embodiment of this disclosure. In some embodiments, such as Figure 13a As shown, the electrostatic discharge structure 6 includes at least one redundant pad 56 located in the first sub-bonding area BB1, and a second adapter cable 112 located in the first sub-bonding area BB1 and corresponding one-to-one with the redundant pad 56. The first test line 2 includes a first test segment 21 located in the first sub-bonding area BB1 and a second test segment 22 located in the trace area BB3; for any redundant pad 56, the first end of the redundant pad 56 is electrically connected to the second test segment 22 through the corresponding second adapter cable 112, and the second end of the redundant pad 56 is floating.

[0167] The difference between Example 4 and Example 5 and Example 3 is that ESD risk is reduced by setting redundant pads 56 in the first sub-binding area BB1 to disperse the tip charge of the single fourth pad 54.

[0168] Optionally, such as Figure 13aAs shown, redundant pad 56 and first pad 51 are arranged side by side along the first direction X. The redundant pad 56 is closer to the edge of the first sub-bonding area BB1 than the first pad 51 arranged side by side. For example, it is closer to the first edge of the first sub-bonding area BB1 that is arranged opposite to it along the first direction X.

[0169] Optionally, such as Figure 13b As shown, redundant pad 56 and second pad 52 are arranged side by side along the first direction X. The redundant pad 56 is closer to the edge of the first sub-bonding area BB1 than the second pad 52 arranged side by side. For example, it is closer to the first edge of the first sub-bonding area BB1 that is arranged opposite to it along the first direction X.

[0170] Optionally, the redundant pad 56 is closer to the first edge than the common pad 50.

[0171] It should be noted that the other membrane structures in Examples 4 and 5 can be found in the description of Example 3, and the repeated parts will not be repeated.

[0172] Figure 14 This is a schematic diagram of the array substrate provided in Example 6, which is an embodiment of this disclosure. In some embodiments, such as Figure 14 As shown, the electrostatic discharge structure 6 includes a plurality of protrusions 13 located in the first sub-bonding region BB1, the plurality of protrusions 13 being connected to the side of the first test line 2 away from the switching transistor 41. Optionally, the protrusions 13 are integrally connected to the first test line 2 and protrude along the side away from the switching transistor 41. The protrusions 13 are located in the first conductive layer 01.

[0173] Optionally, such as Figure 14 As shown, the first test line 2, in addition to its two ends, also includes a first connection node located in the middle region and electrically connected to the second electrode D of the switching transistor 41; in the extension direction of the first test line 2, a protrusion 13 is provided between adjacent first connection nodes. The protrusions 13 are distributed on the first test line 2 to disperse the charge on the first test line 2, thereby reducing the ESD risk.

[0174] Optionally, the electrostatic discharge structure 6 also includes a plurality of protrusions 13 located in the trace area BB3, the plurality of protrusions 13 being connected to the side of the first test line 2 away from the switching transistor 41.

[0175] It should be noted that other membrane structures in Example 6 can be found in the description of Example 3, and repeated parts will not be repeated.

[0176] Figure 15 A schematic diagram of the array substrate provided in Example 7 of this disclosure. In some embodiments, such as Figure 15As shown, the electrostatic discharge structure 6 is located in the trace area BB3. One end of the electrostatic discharge structure 6 is electrically connected to the first test line 2, and the other end extends to the edge of the trace area BB3 to release static electricity to the periphery of the array substrate.

[0177] In some embodiments, such as Figure 15 As shown, the array substrate also includes a cutting area EE located in the peripheral area CC away from the display area AA, and an outer perimeter area FF located in the cutting area EE away from the peripheral area CC; the electrostatic discharge structure 6 is located in the outer perimeter area FF and extends along the second direction Y; the array substrate also includes a conductive line 60 located in the outer perimeter area FF and extending along the second direction Y and a fifth adapter line 115 located in the cutting area EE; the electrostatic discharge structure 6 is located in the wiring area BB3, and one end is electrically connected to the first test line 2, and the other end extends to the edge of the wiring area BB3 and is connected to one end of the fifth adapter line 115, and the other end of the fifth adapter line 115 is electrically connected to the middle area of ​​the conductive line 60.

[0178] The conductive line 60 is a wide trace extending from the DPO side to the DP side of the array substrate. In this embodiment, the static electricity on the first test line 2 located in the bonding area BB is conducted to the conductive line 60 located in the peripheral area FF through the electrostatic discharge structure 6 and the fifth adapter line 115 to disperse the charge, thereby reducing the risk of ESD during many process stages such as cutting, bonding, and transportation of the product.

[0179] Optionally, the line width of the conductive line 60 is greater than the line width of the first test line 2; and / or, the line width of the electrostatic discharge structure 6 is greater than the line width of the first test line 2, to facilitate the release of static electricity.

[0180] Optionally, the two ends of the conductive wire 60 are floating.

[0181] Optionally, the electrostatic discharge structure 6 and the fifth adapter cable 115 are connected as a single unit.

[0182] It should be noted that, since array factories need to perform functional checks and screenings on the array substrates throughout the entire manufacturing process, it is necessary to set traces (hereinafter referred to as peripheral AT traces) on the array substrates to transmit array detection signals, in order to confirm whether the array substrates can function properly. It is important to emphasize that in the prior art, the peripheral AT traces themselves serve as test lines, electrically connecting to the structure under test, and are not connected to the first test line 2 in this disclosure. However, this disclosure reuses the peripheral AT traces as an electrostatic discharge structure 6 electrically connected to the first test line 2. While releasing static electricity on the long traces (first test line 2), it does not affect the overall fabrication process; only the mask of the third conductive layer 03 needs to be changed, resulting in minimal impact on the product fabrication stage.

[0183] Optionally, one end of the external AT trace is electrically connected to the fifth test terminal 35, and the other end is floating.

[0184] It should be noted that the array substrate disclosed herein can have its peripheral region FF structure bent to the backlight side before leaving the factory, or used as a bezel for a display device. Alternatively, the array substrate can be cut, with the structure located in the peripheral region FF cut off along the cutting area EE.

[0185] Figure 16 A schematic diagram of the film layer stacking of the array substrate provided in Example 7 of this disclosure. In some embodiments, such as Figure 16 As shown, the array substrate includes a first conductive layer 01, a second conductive layer 02, and a third conductive layer 03 sequentially disposed along a direction away from the substrate 1; the first test line 2, the second test line 7, the common electrode bus 9, the first common lead 101, the second common lead 102, the conductive line 60, and the control electrode G of the switching transistor 41 are all located in the first conductive layer 01; the touch electrode line Tx, the touch lead 8, the third adapter line 113, and the first electrode S and the second electrode D of the switching transistor 41 are all located in the second conductive layer 02; the fourth adapter line 114, the fifth adapter line 115, and the electrostatic discharge structure 6 are all located in the third conductive layer 03; at least a portion of the film layers of the first test terminal 31, the second test terminal 32, the fourth test terminal 34, the common pad 50, the first pad 51, the second pad 52 (not shown in the figure), the third pad 53 (not shown in the figure), the fourth pad 54, and the fifth pad 55 are located in the third conductive layer 03.

[0186] Figure 17 This is a schematic diagram illustrating the connection relationship between the peripheral AT wiring and the fifth adapter cable 115 provided in an embodiment of this disclosure, as shown below. Figure 16 and Figure 17 As shown, one end of the first test line 2 is electrically connected to the first test terminal 31 through the fifth via V5, which passes through the gate insulating layer GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2 in sequence; the first test terminal 31 and the fifth adapter line 115 are connected as an integral structure; the fifth adapter line 115 passes through the routing area BB3, through the cutting area EE and extends to the peripheral area FF, and is electrically connected to the peripheral AT trace (static discharge structure 6) through the eleventh via V11, which passes through the gate insulating line GI, the first passivation layer PVX1, the planarization layer PLN, and the second passivation layer PVX2 in sequence.

[0187] In this embodiment, the first test line 2 and the peripheral AT trace are connected by the fifth adapter cable 115 to prevent the first test line 2 and / or the peripheral AT trace from being corroded when they extend to the cutting area EE.

[0188] In some embodiments, for examples 3 to 7 above, the array substrate further includes a driver chip and a common pad 50 located in the first sub-bonding area BB1; the common pad 50, a plurality of first pads 51 and a plurality of second pads 52 are respectively bonded and connected to the driver chip; the common pad 50 and the first pads 51 are arranged side by side along the first direction X, and are located on the side of the first pad 51 near the edge of the first sub-bonding area BB1.

[0189] like Figure 8 , Figure 13a , Figure 13b , Figure 14 or Figure 15 As shown, during the normal display phase, the switching transistor 41 is turned off, and the driver chip provides a second operating voltage to the touch electrode line Tx through the first pad 51 and provides a first reference voltage to the common electrode bus 9 through the common pad 50, so as to load the first reference voltage onto the first test line 2.

[0190] Optionally, the second operating voltage is the same as the first reference voltage, and both are common voltages, such as -3V.

[0191] In some embodiments, the array substrate further includes a flexible circuit board located in the second sub-bonding region BB2. A fourth pad 54 is bonded to the flexible circuit board and electrically connected to a fifth pad 55 via a third adapter cable 113. The fifth pad 55 is electrically connected to the first test segment 21 via a fourth adapter cable 114.

[0192] like Figure 8 , Figure 13a , Figure 13b , Figure 14 or Figure 15 As shown, during the normal display phase, the switching transistor 41 is turned off, and the flexible circuit board provides a first reference voltage to the first test line 2 through the fourth pad 54 and the fifth pad 55.

[0193] Optionally, the second operating voltage and the first reference voltage are the same and are both common voltages, such as -3V. This way, there is no voltage difference between the source and drain of the switching transistor 41 during the off phase, reducing touch noise and thus improving the stability of the common signal of the touch electrode line Tx, which is beneficial for identifying the user's actual touch position.

[0194] Figure 18 This is a wiring diagram of the second test line provided in an embodiment of this disclosure. Optionally, as shown... Figure 18 As shown, the array substrate also includes a sixth adapter wire 116 located in the trace area BB3 and a sixth pad 57 located in the second sub-bonding area BB2; the second test line 7 is electrically connected to the sixth pad 57 via the sixth adapter wire 116. The sixth pad 57 is configured to be bonded to the flexible circuit board.

[0195] During the normal display phase, the flexible circuit board provides a low-level signal to the second test line 7 through the sixth pad 57 to control the switching transistor 41 to turn off; at the same time, the flexible circuit board provides a first reference voltage to the first test line 2 through the fourth pad 54 and the fifth pad 55.

[0196] Figure 19 This is a schematic diagram illustrating the connection relationship between the sixth pad and the sixth adapter line provided in an embodiment of this disclosure. Optionally, the sixth adapter line 116 includes a third adapter segment 1161 and a fourth adapter segment 1162 electrically connected to the third adapter segment 1161. The third adapter segment 1161 is located in the third conductive layer 03, and the fourth adapter segment 1162 is located in the first conductive layer 01. The second test line 7 and the fourth adapter segment 1162 are in the same layer but spaced apart. The second test line 7 and the fourth adapter segment are connected across layers 1162 through the third adapter segment 1161, avoiding ESD of the long trace (second test line 7) in the same layer. Especially during the product manufacturing stage, the fourth adapter segment 1162 and the second test line 7 are disconnected in the first conductive layer 01, which can reduce the ESD risk before the formation of the third conductive layer 03.

[0197] In some embodiments, for examples 3-7 above, the array substrate further includes a flexible circuit board located in the second sub-bonding region BB2. The flexible circuit board is bonded to a fourth pad 54, which is electrically connected to the first test segment 21 via a third adapter cable 113. During normal display, the switching transistor 41 is turned off, and the flexible circuit board provides a first reference voltage to the first test line 2 via the fourth pad 54 to load the first reference voltage onto the first test line 2.

[0198] Taking Example 3 as an example, optionally, the fourth pad 54 can be a redundant pad 56 located in the second sub-bonding area BB2. Optionally, the fourth pad 54 is different from the redundant pad 56. The fourth pad 54 is located in the middle area of ​​the second sub-bonding area BB2 and is adjacent to the third pad 53.

[0199] Figure 20 A schematic diagram of the electrical connection relationship of a fourth pad 54 provided in an embodiment of this disclosure is shown below. Figure 20 As shown, a redundant pad 56 located in the second sub-bonding area BB2 is multiplexed as a fourth pad 54, which is used to disperse charge during the testing phase and bonded to the flexible circuit board during the normal display phase to provide a first reference voltage to the first test line 2.

[0200] Figure 21 A schematic diagram illustrating another electrical connection relationship of the fourth pad 54 provided in an embodiment of this disclosure, as shown below. Figure 21As shown, the fourth pad 54 differs from the redundant pad 56; during the normal display phase, the fourth pad 54 is bonded to the flexible circuit board to provide a first reference voltage to the first test line 2. During the testing phase, the first end of the fourth pad 54 is electrically connected to the first test line 2, and the second end is floating.

[0201] Similarly, the structural relationship between the flexible circuit board and the fourth pad 54 in this embodiment also applies to Examples 4 to 7, and the repeated parts will not be described again.

[0202] This disclosure also provides a display device comprising the array substrate of any of the above embodiments. The display device can be, for example, any product with a display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are readily understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0203] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. An array substrate having a display area and a bonding area located on one side of the display area; the bonding area includes a first sub-bonding area, a second sub-bonding area located on the side of the first sub-bonding area away from the display area, and a wiring area surrounding the first sub-bonding area and the second sub-bonding area; The array substrate includes a substrate, pixel units disposed on the substrate, a first test line, a first test terminal, a gating circuit, a plurality of first pads arranged side by side along a first direction, a plurality of second pads arranged side by side along the first direction, a plurality of third pads arranged side by side along the first direction, and an electrostatic discharge structure; the pixel units are located in the display area; The first pad, the gating circuit, and the second pad are all located in the first sub-bonding area, and the first pad is closer to the display area than the second pad. The gating circuit is disposed between the first pad and the second pad. The third pad is located in the second sub-bonding area. The first pad and the second pad are both configured to be bonded to the driver chip; the third pad is configured to be bonded to the flexible circuit board. The first test terminal is located in the wiring area; both ends of the first test wire pass through the first sub-binding area and extend to the wiring area, and are electrically connected to the first test terminal; At least one end of the first test lead is electrically connected to the electrostatic discharge structure.

2. The array substrate according to claim 1, wherein, The array substrate further includes a peripheral area surrounding the display area, and a fan-out area disposed between the peripheral area and the bonding area; The array substrate further includes a second test terminal, a second test line, a plurality of touch electrode lines extending along a second direction, and touch leads electrically connected to the touch electrode lines; the second test terminal is located in the trace area; both ends of the second test line pass through a first sub-bonding area and extend to the trace area; both ends of the touch electrode lines pass through the display area and extend to the peripheral area; the touch leads pass through the fan-out area, with one end extending to the peripheral area and electrically connected to the touch electrode line, and the other end extending to the first sub-bonding area and electrically connected to the first pad; the second direction intersects with the first direction; The selection circuit includes a switching transistor that corresponds to each of the touch leads; the first electrode of the switching transistor is electrically connected to the first pad connected to the corresponding touch lead, the second electrode is electrically connected to the first test line, and the control electrode is electrically connected to the second test line.

3. The array substrate according to claim 2, wherein, The array substrate includes a common electrode bus located in the peripheral area and surrounding the display area, and a first common lead extending from the peripheral area to the wiring area; the common electrode bus includes two first sub-segments extending in a first direction and arranged opposite to each other, and two second sub-segments extending in a second direction and arranged opposite to each other; the first sub-segments and the second sub-segments are connected end to end in sequence; The two ends of the first segment near the first sub-binding area are electrically connected to the first ends of the two first common leads respectively; the second end of the first common lead is electrically connected to one end of the first test lead; The first common lead, the first sub-segment, and the second sub-segment are multiplexed as at least a portion of the electrostatic discharge structure.

4. The array substrate according to claim 3, wherein, The first common lead and the first test lead are arranged in the same layer and connected as a single structure.

5. The array substrate according to claim 3 or 4, wherein, For at least one of the first common leads, the second end of the first common lead and one end of the first test lead are both electrically connected to the same first test terminal.

6. The array substrate according to claim 3, wherein, The array substrate also includes a first adapter cable located in the wiring area; The first common lead is on the same layer as the first test lead and is spaced apart from it. The first test lead is on a different layer from the first adapter cable; the first test lead is electrically connected to the first common lead through the first adapter cable. The first adapter cable is reused as another part of the electrostatic discharge structure.

7. The array substrate according to claim 6, wherein, The array substrate also includes a third test terminal located in the wiring area; For at least one first common lead, the second end of the first common lead and the first end of the first adapter wire are both electrically connected to the same third test terminal, and the second end of the first adapter wire and one end of the first test lead are both electrically connected to the same first test terminal.

8. The array substrate according to claim 4 or 6, wherein, The array substrate also includes a driver chip and a common pad located in the first sub-bonding region; The common pad, the plurality of first pads, and the plurality of second pads are respectively bonded and connected to the driver chip; the common pad and the first pads are arranged side by side along the first direction; The first test line is spaced apart from the second pad; during normal display, the switching transistor is turned off, the driver chip provides a second operating voltage to the touch electrode line through the first pad, and provides a first reference voltage to the common electrode bus through the common pad, so as to load the first reference voltage onto the first test line.

9. The array substrate according to claim 8, wherein, The second operating voltage is the same as the first reference voltage.

10. The array substrate according to claim 4 or 6, wherein, The array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate. The first test line, the second test line, the common electrode bus, the first common lead, and the control electrode of the switching transistor are all located in the first conductive layer; The touch electrode line, the touch lead, and the first and second electrodes of the switching transistor are all located in the second conductive layer; The first adapter line is located on the third conductive layer; at least a portion of the film layers of the first test terminal, the second test terminal, the third test terminal, the first pad, the second pad, the third pad, and the common pad are located on the third conductive layer.

11. The array substrate according to claim 2, wherein, The electrostatic discharge structure includes at least one redundant pad located in the second sub-bonding area, and a second adapter cable located in the routing area and corresponding one-to-one with the redundant pad; The first test line includes a first test segment located in the first sub-binding area and a second test segment located in the routing area; For any of the redundant pads, the first end of the redundant pad is electrically connected to the second test segment via the corresponding second adapter cable, and the second end of the redundant pad is floating.

12. The array substrate according to claim 2, wherein, The electrostatic discharge structure includes at least one redundant pad located in the first sub-bonding area, and a second adapter cable located in the first sub-bonding area and corresponding one-to-one with the redundant pad; The first test line includes a first test segment located in the first sub-binding area and a second test segment located in the routing area; For any of the redundant pads, the first end of the redundant pad is electrically connected to the second test segment via the corresponding second adapter cable, and the second end of the redundant pad is floating.

13. The array substrate according to claim 11 or 12, wherein, The array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate. The first test line, the second test line, and the control electrode of the switching transistor are located in the first conductive layer; The touch electrode line, the touch lead, and the first and second electrodes of the switching transistor are all located in the second conductive layer; The second adapter cable is located in the third conductive layer; at least a portion of the film layer of the first test terminal, the second test terminal, the first pad, the second pad, the third pad, and the redundant pad is located in the third conductive layer.

14. The array substrate according to claim 2, wherein, The electrostatic discharge structure includes a plurality of protrusions located in the first sub-binding region. The protrusions are connected to the first test line as an integral structure and protrude along the side away from the switching transistor.

15. The array substrate according to claim 14, wherein, In addition to its two ends, the first test line also includes a first connection node located in the middle region and electrically connected to the second electrode of the switching transistor; In the extension direction of the first test line, the protrusion is provided between adjacent first connection nodes.

16. The array substrate according to claim 2, wherein, The electrostatic discharge structure is located in the wiring area, with one end of the electrostatic discharge structure electrically connected to the first test line and the other end extending to the edge of the wiring area.

17. The array substrate according to claim 16, wherein, The array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate. The first test line, the second test line, and the control electrode of the switching transistor are all located in the first conductive layer; The touch electrode line, the touch lead, and the first and second electrodes of the switching transistor are all located in the second conductive layer; The electrostatic discharge structure is located in the third conductive layer; at least a portion of the film layers of the first test terminal, the second test terminal, the first pad, the second pad, and the third pad are all located in the third conductive layer.

18. The array substrate according to claim 16 or 17, wherein, The linewidth of the electrostatic discharge structure is greater than the linewidth of the first test line.

19. The array substrate according to claim 11, 12, 14 or 16, wherein, The array substrate also includes a flexible circuit board and a fourth pad located in the second sub-bonding area, and a third adapter cable located in the wiring area; The fourth pad is bonded to the flexible circuit board, and the fourth pad is electrically connected to the portion of the first test line located in the first sub-bonding area via the third adapter cable; During the normal display phase, the switching transistor is turned off, and the flexible circuit board provides a first reference voltage to the first test line through the fourth pad to load the first test line with the first reference voltage.

20. The array substrate according to claim 11, 12, 14 or 16, wherein, The array substrate also includes a driver chip located in the first sub-binding region; Multiple first pads and multiple second pads are respectively bonded and connected to the driver chip; During the normal display phase, the switching transistor is turned off, and the driver chip provides a second operating voltage to the touch electrode line through the first pad.

21. The array substrate according to claim 20, wherein, The array substrate further includes a flexible circuit board and a fourth pad located in the second sub-bonding area, a fifth pad located in the first sub-bonding area, a third adapter line located in the wiring area, and a fourth adapter line located in the first sub-bonding area; the fifth pad and the second pad are arranged side by side along the second direction; The fourth pad is bonded to the flexible circuit board, the fourth pad is electrically connected to the fifth pad through the third adapter cable, and the fifth pad is electrically connected to the portion of the first test line located in the first sub-bonding area through the fourth adapter cable; During the normal display phase, the switching transistor is turned off, and the flexible circuit board provides a first reference voltage to the first test line through the fourth and fifth pads.

22. The array substrate according to claim 21, wherein, The array substrate includes a first conductive layer, a second conductive layer, and a third conductive layer disposed sequentially along a direction away from the substrate. The first test line, the second test line, the third adapter line, and the control electrode of the switching transistor are all located in the first conductive layer; The touch electrode line, the touch lead, and the first and second electrodes of the switching transistor are all located in the second conductive layer; The fourth adapter line is located in the third conductive layer; at least a portion of the film layer of the first pad, the second pad, the third pad, the fourth pad, and the fifth pad is located in the third conductive layer.

23. The array substrate according to claim 22, wherein, The second operating voltage is the same as the first reference voltage.

24. A display device, wherein, Includes the array substrate as described in any one of claims 1 to 23.

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