Semiconductor device and memory device

Abstract

The invention relates to a semiconductor device and a memory device. A semiconductor device according to an embodiment of the present disclosure includes: a protection region; the chip area is surrounded by the protection area; and a circuit structure including bond pads coupled in series in the chip region. A semiconductor device according to an embodiment of the present disclosure includes: a chip region; chip protectors surrounding the chip region and spaced apart from each other; and a circuit structure including bond pads coupled in series between the chip guards.

Description

Technical Field

[0001] Various embodiments of this disclosure generally relate to semiconductor devices, and more specifically, to semiconductor devices including test circuitry configured to detect whether bonding has been achieved in a wafer bonding structure. Background Technology

[0002] Multiple chip regions can be formed on a semiconductor substrate using semiconductor integration processes. These multiple chip regions can be separated from each other by scribe lines. Multiple semiconductor chips can be manufactured by separating these multiple chip regions through a dicing process.

[0003] Since there are limitations to increasing the integration density of three-dimensional non-volatile memory devices that stack memory cells vertically on a substrate, methods have been proposed to form more circuitry within a limited chip area. For example, a wafer bonding structure has been proposed that bonds a first wafer on which peripheral circuitry is formed to a second wafer on which memory cells are formed. Summary of the Invention

[0004] According to one embodiment, a semiconductor device may include: a protective region; a chip region surrounded by the protective region; and a circuit structure including bonding pads connected in series in the chip region.

[0005] According to one embodiment, a semiconductor device may include: a chip region; chip guards surrounding the chip region and spaced apart from each other; and a circuit structure including bonding pads connected in series between the chip guards.

[0006] According to one embodiment, a semiconductor device may include: a lower structure including peripheral circuitry; an upper structure stacked above the lower structure and including a memory cell array; a lower bonding pad exposed on an upper surface of the lower structure; upper bonding pads exposed on a lower surface of the upper structure and respectively contacting the lower bonding pads; and test electrodes connected in the upper structure to one or more of the upper bonding pads, wherein the upper bonding pads and the lower bonding pads are connected in series to form an electrical path.

[0007] According to one embodiment, a semiconductor device may include: an upper structure stacked over a lower structure and including a memory cell array; a first lower bonding pad exposed on an upper surface of the lower structure; a first upper bonding pad exposed on a lower surface of the upper structure and respectively contacting the first lower bonding pad; and test electrodes coupled in the upper structure to one or more of the first upper bonding pads, wherein the first upper bonding pads and the first lower bonding pads are connected in series to form an electrical path, and wherein the electrical path surrounds the memory cell array. Attached Figure Description

[0008] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure;

[0009] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a diagram illustrating the structure of a semiconductor device according to a first embodiment of the present disclosure;

[0010] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure;

[0011] Figure 4A , Figure 4B , Figure 4C and Figure 4D These are diagrams illustrating various embodiments related to the first embodiment of this disclosure;

[0012] Figure 5A , Figure 5B and Figure 5C This is a diagram showing the structure of a semiconductor device according to a second embodiment of the present disclosure;

[0013] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E and Figure 6F This is a diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present disclosure;

[0014] Figure 7A , Figure 7B , Figure 7C and Figure 7D These are diagrams illustrating various embodiments related to the second embodiment of this disclosure;

[0015] Figure 8A , Figure 8B , Figure 8C and Figure 8D This is a diagram illustrating a memory device including a circuit structure according to an embodiment of the present disclosure;

[0016] Figure 9 This is a diagram illustrating a memory card system employing a memory device according to an embodiment of the present disclosure; and

[0017] Figure 10 This is a diagram illustrating a solid-state drive (SSD) system for a memory device applied according to an embodiment of the present disclosure. Detailed Implementation

[0018] The specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure can be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein. It should be understood that when an element or layer is referred to as being "on," "connected to," or "linked to" another element or layer, that element or layer may be directly on, directly connected to, or directly linked to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being "directly on," "directly connected to," or "directly linked to" another element or layer, there are no intermediate elements or layers. Terms such as "first" and "second" are used to distinguish various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, a first element may be named a second element, while in another example, a second element may be named a first element. Terms such as “top,” “above,” “upper,” “side,” “upper part,” “lower part,” “row,” “column,” “inner,” “outer,” and other terms that suggest relative spatial relationships or directions are used for the purpose of description or reference to the accompanying drawings only, and not to limit in any other way. Cross-shading throughout the drawings indicates corresponding or similar areas between the drawings, and does not indicate material associated with those areas.

[0019] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can realize the technical spirit of the invention.

[0020] Various embodiments of this disclosure relate to a semiconductor device that can more easily detect whether bonding pads are bonded to each other.

[0021] Figure 1 This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0022] Semiconductor devices may include a structure STR. For example, a structure STR may include a substrate (e.g., a silicon wafer, a SiGe wafer, or an SOI wafer) and a material pattern formed on the substrate.

[0023] Reference Figure 1 The structure STR can include a chip region CHA, a protective region GDA, and a scribing region SLA. For example, the structure STR can include a chip region CHA, a protective region GDA surrounding the chip region CHA, and a scribing region SLA surrounding the protective region GDA.

[0024] Semiconductor chips can be formed in chip regions CHAs. Chip regions CHAs can be arranged along the X and Y directions. Each of the semiconductor chips can be formed by semiconductor integration processes performed on the chip regions CHAs. For example, when the semiconductor chips formed in the chip regions CHAs include a memory cell array, the semiconductor device can be a memory device. In a single structure STR, the semiconductor chips formed in the respective chip regions CHAs can be substantially identical. After the semiconductor integration process is completed on the substrate, the structure STR can be separated into chip regions CHAs, such that each of the chip regions CHAs is separated into the shape of a semiconductor chip.

[0025] Each of the protective regions GDAs may be adjacent to each of the chip regions CHAs. Each of the protective regions GDAs may surround each of the chip regions CHAs. For example, the protective regions GDAs may be formed within a predetermined distance from the boundary of the chip regions CHAs. When the chip regions CHAs have a rectangular shape in a plan view, the protective regions GDAs may have a hollow rectangular shape in a plan view to surround the chip regions CHAs. The side surfaces of the chip regions CHAs and the inner surfaces of the protective regions GDAs may contact each other. As used herein with respect to parameters, the term "predetermined" (such as a predetermined distance, predetermined thickness, or predetermined range) means that the value of the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0026] Chip protectors can be formed within the protected region GDA. In one embodiment, the chip protector can prevent or mitigate the penetration of moisture or oxygen from the outside of the chip region CHA into the chip region CHA. Furthermore, in one embodiment, the chip protector can reduce die-to-die interference during the packaging process performed after the chip region CHA has been divided into the corresponding semiconductor chips. Reference will be made below. Figure 2B , Figure 2C , Figure 5B and Figure 5C Describe the shape of the chip's protective component.

[0027] The circuit structure can be located in the chip region CHA or the guard region GDA. The circuit structure can be used as a test circuit to detect whether bonding has been achieved in a semiconductor device with a wafer bonding structure. See below for further details. Figures 2A to 2D , Figures 4A to 4D , Figures 5A to 5C and Figures 7A to 7D To describe the location and shape of the circuit structure.

[0028] The scribing trace area (SLA) can be located outside the chip region (CHA) and the guard region (GDA). For example, the scribing trace area (SLA) can be located between the chip regions (CHA). Furthermore, the scribing trace area (SLA) can surround the guard region (GDA). After the semiconductor integration process is completed, the scribing trace area (SLA) can be cut during the dicing process to separate the semiconductor chip. Because the structure STR is cut along the scribing trace area (SLA), the chip regions (CHA) can be separated from each other. Each separated semiconductor chip can include a chip region (CHA) and a guard region (GDA) surrounding a chip region (CHA). Various methods can be used to cut the structure STR, such as sawing processes using blades, laser processes utilizing lasers, or stealth scribing processes. In one embodiment, electrical test patterns, process monitoring patterns, and alignment keys can be set in the scribing trace area (SLA).

[0029] exist Figure 1 For ease of description, six chip regions CHA are shown in this disclosure, but the scope of this disclosure is not limited thereto. For example, the structure STR may include seven or more chip regions CHA. In this disclosure, for ease of description, the chip regions CHA, the guard region GDA, and the scribing region SLA are shown as separate from each other, but the chip regions CHA, the guard region GDA, and the scribing region SLA may not be physically separated from each other, but may be continuously connected to each other. For example, the boundaries of the chip regions CHA, the guard region GDA, and the scribing region SLA may not be clearly visible. Furthermore, the positions of the chip regions CHA, the guard region GDA, and the scribing region SLA in the structure STR may be randomly determined. In this disclosure, the chip regions CHA, the guard region GDA, and the scribing region SLA may refer to spaces in the structure STR whose horizontal extent is limited to a predetermined range, rather than areas in the substrate.

[0030] Figures 2A to 2D This is a diagram illustrating the structure of a semiconductor device according to a first embodiment of the present disclosure. Figure 2A This is a plan view of the layout of a semiconductor device according to the first embodiment of the present disclosure. Figure 2B It is along Figure 2A A cross-sectional view taken from line A-A'. Figure 2C It is along Figure 2A A cross-sectional view taken from the B-B' line. Figure 2D It is along Figure 2A A cross-sectional view taken from line C-C'.

[0031] Reference Figure 2A A first chip protector GD1 and a second chip protector GD2 can be formed within a protected region GDA. The protected region GDA may include the first chip protector GD1, the second chip protector GD2, and a region located between the first chip protector GD1 and the second chip protector GD2. A chip region CHA may be surrounded by the first chip protector GD1. For example, in a plan view, the first chip protector GD1 may have a rectangular shape extending along the boundary of the chip region CHA. A scribing area SLA may be located outside the second chip protector GD2. For example, the second chip protector GD2 may have a rectangular shape in a plan view, the area of ​​which is larger than the area of ​​the rectangular shape of the first chip protector GD1.

[0032] The test circuit region (TCR) may be located within the chip region CHA. The TCR may be adjacent to the guard region GDA within the chip region CHA. The TCR may extend along the boundary of the chip region CHA. The TCR may extend along at least three of the four side surfaces of the chip region CHA. For example, the chip region CHA may include a first region containing the center of the chip region CHA and a second region surrounding the first region, and the TCR may be located in the second region of the chip region CHA. The TCR may surround the first region of the chip region CHA. The TCR may have a rectangular shape in a plan view, with some portions of it broken.

[0033] Reference Figure 2B The semiconductor device may include a lower structure STR1 and an upper structure STR2 situated above the lower structure STR1. The upper structure STR2 may be positioned relative to the lower structure STR1 along the Z-direction. The upper structure STR2 may be stacked on top of the lower structure STR1. The lower surface of the upper structure STR2 may contact the upper surface of the lower structure STR1. The lower structure STR1 and the upper structure STR2 may contact each other on a bonding surface BS. The lower structure STR1 and the upper structure STR2 may be bonded to each other on the bonding surface BS. The upper structure STR2 may be bonded to the lower structure STR1 using a wafer bonding method.

[0034] The lower structure STR1 may include a substrate SUB. The substrate SUB can extend from the chip region CHA to the protection region GDA. The substrate SUB can extend in both the X and Y directions. For example, the substrate SUB can be a silicon wafer substrate, a SiGe wafer substrate, or an SOI wafer substrate, etc.

[0035] The substrate SUB may include a first well region PW and a first active region PA. The first well region PW and the first active region PA may be regions of the substrate SUB implanted with a first type of impurity. The amount of impurity contained in the first active region PA may be greater than the amount of impurity contained in the first well region PW. The first type of impurity may include elements of Group 13. For example, the first type of impurity may include boron (B) or indium (In).

[0036] The first well region PW and the first active region PA can be located within the protection region GDA. The first well region PW and the first active region PA can extend in the horizontal direction. For example, the first well region PW and the first active region PA located in the X direction relative to the chip region CHA can extend in the Y direction. In one embodiment, a portion of the first well region PW can extend into the chip region CHA.

[0037] The upper structure STR2 may not include any substrate. See below for reference. Figure 3D and Figure 3E The description does not include the upper structure STR2 of any substrate.

[0038] The lower structure STR1 may include a lower bonding pad (LBD) exposed on its upper surface. The lower bonding pad (LBD) may be located within the chip region CHA and the guard region GDA. The lower bonding pad (LBD) may include a conductive material. For example, the lower bonding pad (LBD) may include copper (Cu).

[0039] The lower structure STR1 may include a lower insulating layer LIL. The lower insulating layer LIL may be located above the substrate SUB. The lower insulating layer LIL may be located between the lower bonding pads LBD. The lower bonding pads LBD can be separated from each other by the lower insulating layer LIL. The lower insulating layer LIL may include an insulating layer (e.g., an oxide layer).

[0040] The upper structure STR2 may include an upper bonding pad UBD exposed on its lower surface. The upper bonding pad UBD may be located within the chip region CHA and the guard region GDA. The upper bonding pad UBD may include a conductive material. The upper bonding pad UBD may include the same material as the lower bonding pad LBD. For example, the upper bonding pad UBD may include copper (Cu).

[0041] The upper bonding pad UBD can contact the lower bonding pad LBD. The upper bonding pad UBD and the lower bonding pad LBD can contact each other on the bonding surface BS. The upper bonding pad UBD and the lower bonding pad LBD can be electrically connected to each other. The upper bonding pad UBD and the lower bonding pad LBD can be bonded to each other. The lower bonding pad LBD can overlap with the upper bonding pad UBD. Alternatively, the upper bonding pad UBD can overlap with the lower bonding pad LBD.

[0042] The upper structure STR2 may include an upper insulating layer UIL. The upper insulating layer UIL may be located between the upper bonding pads UBD. The upper bonding pads UBD can be separated from each other by the upper insulating layer UIL. The upper insulating layer UIL may include an insulating layer (e.g., an oxide layer).

[0043] The upper insulating layer UIL can contact the lower insulating layer LIL. The upper insulating layer UIL and the lower insulating layer LIL can contact each other on the bonding surface BS. The upper insulating layer UIL and the lower insulating layer LIL can be bonded to each other.

[0044] The first chip protector GD1 and the second chip protector GD2 can be located within the protected region GDA. Each of the first chip protector GD1 and the second chip protector GD2 can extend in the Z-direction. Each of the first chip protector GD1 and the second chip protector GD2 can extend in the Z-direction within the lower structure STR1. Furthermore, each of the first chip protector GD1 and the second chip protector GD2 can extend in the Z-direction within the upper structure STR2. In one embodiment, each of the first chip protector GD1 and the second chip protector GD2 can have a shape extending in the Z-direction to prevent or mitigate the penetration of moisture or oxygen from the outside of the chip region CHA into the chip region CHA.

[0045] The first chip protector GD1 and the second chip protector GD2 can extend in the horizontal direction. For example, the portion of the first chip protector GD1 located in the X direction relative to the chip region CHA can extend in the Y direction. The first chip protector GD1 can extend in the direction extending from the side surface of the chip region CHA. The second chip protector GD2 can extend in the direction extending from the first chip protector GD1.

[0046] Each of the first chip protection component GD1 and the second chip protection component GD2 may include a first well region PW and a first active region PA in the substrate SUB. The first well region PW in the first chip protection component GD1 and the first well region PW in the second chip protection component GD2 may be connected to each other. In another embodiment, the first well region PW in the first chip protection component GD1 and the first well region PW in the second chip protection component GD2 may be separated from each other. Furthermore, each of the first chip protection component GD1 and the second chip protection component GD2 may include a lower bonding pad LBD in the protection region GDA. Each of the first chip protection component GD1 and the second chip protection component GD2 may include a first lower plug LP1, a first lower line LL1, a second lower plug LP2, a second lower line LL2, a third lower plug LP3, a third lower line LL3, and a lower bonding contact LBC located between the first active region PA and the lower bonding pad LBD. The first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, and the lower bonding contact LBC can be sequentially arranged above the first active area PA along the Z direction. The first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be surrounded by the lower insulating layer LIL.

[0047] Each of the first chip protector GD1 and the second chip protector GD2 may include an upper bonding pad UBD in the protected area GDA. Each of the first chip protector GD1 and the second chip protector GD2 may include an upper bonding contact UBC, a first upper line UL1, an upper plug UP, and a second upper line UL2 located above the upper bonding pad UBD. The upper bonding contact UBC, the first upper line UL1, the upper plug UP, and the second upper line UL2 may be sequentially arranged above the upper bonding pad UBD along the Z direction. The upper bonding pad UBD, the upper bonding contact UBC, the first upper line UL1, the upper plug UP, and the second upper line UL2 may be surrounded by an upper insulating layer UIL. The second upper line UL2 included in the first chip protector GD1 and the second upper line UL2 included in the second chip protector GD2 may be connected to each other. In one embodiment, the second upper line UL2 included in the first chip protector GD1 and the second upper line UL2 included in the second chip protector GD2 may be separated from each other.

[0048] The circuit structure CS can be located within the test circuit region TCR. (See also...) Figure 2A and Figure 2BThe circuit structure CS can extend along the interface between the chip region CHA and the guard region GDA. For example, the chip region CHA can have a rectangular shape in the plan view, and the circuit structure CS can have a shape corresponding to a portion of the rectangular shape. Although Figure 2A and Figure 2B Not shown, but the chip region CHA may include a first region and a second region, the first region including the center of the chip region CHA, and the second region surrounding the first region. A circuit structure CS may be disposed in the second region of the chip region CHA. Furthermore, a memory cell array may be disposed in the first region of the chip region CHA. The circuit structure CS may be disposed between the memory cell array and the guard region GDA. The circuit structure CS may surround the memory cell array. The following will refer to... Figures 8A to 8D Describe the positional relationship between the memory cell array and the circuit structure CS.

[0049] Return to reference Figure 2B The circuit structure CS may include bonding pads (e.g., upper bonding pad UBD and lower bonding pad LBD) in the chip region CHA. The circuit structure CS may include upper bonding pads UBD and lower bonding pads LBD disposed in the chip region CHA. The upper bonding pads UBD included in the circuit structure CS may overlap with the lower bonding pads LBD included in the circuit structure CS in a one-to-one manner. Upper bonding pads UBD and lower bonding pads LBD that are in contact with each other may be referred to as a bonding pad group. The circuit structure CS may include bonding pad groups arranged along the X and Y directions in the chip region CHA. For example, a bonding pad group may be... Figure 2B Arranged in rows along the X direction.

[0050] The bonding pads included in the circuit structure CS (e.g., upper bonding pad UBD and lower bonding pad LBD) can be connected in series. The upper bonding pad UBD and lower bonding pad LBD included in the circuit structure CS can be electrically connected to each other.

[0051] The lower structure STR1 may include lower bonding contacts LBC, each contacting a corresponding one of the lower bonding pads LBD. Each of the lower bonding contacts LBC may contact the lower surface of each of the lower bonding pads LBD. The lower bonding contacts LBC may be electrically connected to the lower bonding pads LBD. The lower bonding contacts LBC may include a conductive material. The lower structure STR1 may include a third lower line LL3, each connecting at least two of the lower bonding contacts LBC. In the test circuit region TCR, each of the third lower lines LL3 may contact the lower surfaces of at least two lower bonding contacts LBC. In the test circuit region TCR, the third lower lines LL3 may electrically connect adjacent lower bonding contacts LBC to each other. The third lower lines LL3 may include a conductive material.

[0052] The upper structure STR2 may include upper bonding contacts UBC, each contacting a corresponding one of the upper bonding pads UBD. Each upper bonding contact UBC may contact the upper surface of each of the upper bonding pads UBD. The upper bonding contacts UBC may be electrically connected to the upper bonding pads UBD. The upper bonding contacts UBC may include a conductive material. The upper structure STR2 may include first upper lines UL1, each connecting at least two of the upper bonding contacts UBC. In the test circuit region TCR, each of the first upper lines UL1 may contact the upper surfaces of at least two upper bonding contacts UBC. In the test circuit region TCR, the first upper lines UL1 may electrically connect adjacent upper bonding contacts UBC to each other. The first upper lines UL1 may include a conductive material.

[0053] Reference Figure 2B The third lower line LL3, lower bonding contact LBC, lower bonding pad LBD, upper bonding pad UBD, upper bonding contact UBC, and first upper line UL1 included in the circuit structure CS can be connected in series with each other. The third lower line LL3, lower bonding contact LBC, lower bonding pad LBD, upper bonding pad UBD, upper bonding contact UBC, and first upper line UL1 included in the circuit structure CS can be connected in a chain-like manner.

[0054] Reference Figure 2C The circuit structure CS may include a test electrode TE. The test electrode TE may be located in the chip region CHA. The test electrode TE may be located in the upper structure STR2. The test electrode TE may be located at a level corresponding to the second upper line UL2. The test electrode TE may be connected to the first upper line UL1 via the upper plug UP. The test electrode TE may be connected to a portion of the first upper line UL1 included in the circuit structure CS.

[0055] Reference Figure 2D The circuit structure CS may include an upper bonding pad UBD and a lower bonding pad LBD connected in series. The upper bonding pad UBD and lower bonding pad LBD included in the circuit structure CS may be connected in series to form an electrical path. The upper bonding pad UBD and lower bonding pad LBD included in the circuit structure CS may form a single electrical path that electrically connects the test electrode TE.

[0056] In the lower bonding pads (LBDs) included in the circuit structure CS, adjacent lower bonding pads (LBDs) can be electrically connected to each other via a single third lower line (LL3) or via a single first upper line (UL1). For example, adjacent lower bonding pads (LBDs) can be electrically connected to each other via a lower bonding contact (LBC), a third lower line (LL3), and another lower bonding contact (LBC). Alternatively, adjacent lower bonding pads (LBDs) can be electrically connected to each other via an upper bonding pad (UBD), an upper bonding contact (UBC), a first upper line (UL1), another upper bonding contact (UBC), and another upper bonding pad (UBD).

[0057] Furthermore, among the upper bonding pads UBD included in the circuit structure CS, adjacent upper bonding pads UBD can be electrically connected to each other via a single third lower line LL3 or via a single first upper line UL1. For example, adjacent upper bonding pads UBD can be electrically connected to each other via an upper bonding contact UBC, a first upper line UL1, and another upper bonding contact UBC. Alternatively, adjacent upper bonding pads UBD can be electrically connected to each other via a lower bonding pad LBD, a lower bonding contact LBC, a third lower line LL3, another lower bonding contact LBC, and another lower bonding pad LBD.

[0058] In the lower bonding pads (LBDs) included in the circuit structure CS, non-adjacent lower bonding pads (LBDs) can be electrically connected to each other through at least one lower bonding pad (LBD) and at least one upper bonding pad (UBD). For example, non-adjacent lower bonding pads (LBDs) can be electrically connected to each other through an upper bonding pad (UBD), an upper bonding contact (UBC), a first upper line (UL1), another upper bonding contact (UBC), another upper bonding pad (UBD), a lower bonding pad (LBD), a lower bonding contact (LBC), a third lower line (LL3), and another lower bonding contact (LBC).

[0059] Furthermore, among the upper bonding pads UBD included in the circuit structure CS, upper bonding pads UBD that are not adjacent to each other can be electrically connected to each other through at least one lower bonding pad LBD and at least one upper bonding pad UBD. For example, upper bonding pads UBD that are not adjacent to each other can be electrically connected to each other through an upper bonding contact UBC, a first upper line UL1, another upper bonding contact UBC, an upper bonding pad UBD, a lower bonding pad LBD, a lower bonding contact LBC, a third lower line LL3, another lower bonding contact LBC, and another lower bonding pad LBD.

[0060] In one embodiment, a semiconductor device according to an embodiment of the present disclosure can use test electrodes TE to obtain information about whether the lower structure STR1 and the upper structure STR2 are bonded to each other. For example, the semiconductor device can apply a test voltage to one of the test electrodes TE and can identify whether a test voltage is detected through the remaining test electrodes TE. In one embodiment, when the lower structure STR1 and the upper structure STR2 are bonded to each other, test current can flow between the test electrodes TE because the upper bonding pads UBD included in the circuit structure CS are in contact with the lower bonding pads LBD. When the lower structure STR1 and the upper structure STR2 are not bonded to each other, for example, when delamination occurs, test current may not flow between the test electrodes TE because at least a portion of the upper bonding pads UBD included in the circuit structure CS is not in contact with the lower bonding pads LBD. Therefore, in one embodiment, the semiconductor device can test whether the upper structure STR2 and the lower structure STR1 are bonded to each other by determining whether a test voltage is detected through the test electrodes TE.

[0061] According to one embodiment of this disclosure, the circuit structure CS may not include any other structures (e.g., cell plugs) besides the bonding pads UBD and LBD and the structures for connecting the bonding pads UBD and LBD to each other (e.g., bonding contacts UBC and LBC and lines LL3 and UL1). For example, the circuit structure CS according to an embodiment of this disclosure may include only the minimum components used as a test circuit. Therefore, when information about whether bonding has been achieved is obtained by utilizing the circuit structure CS according to an embodiment of this disclosure, the influence of other potential defects in the structure STR is mitigated, and thus the occurrence of delamination can be detected. Furthermore, the test circuit according to an embodiment of this disclosure can be used in the later testing stages (e.g., quality testing) of various testing stages (e.g., wafer testing, packaging testing, quality testing) included in the semiconductor device manufacturing process. Therefore, in one embodiment, defects can be detected regardless of whether the defects occur at any stage of the semiconductor device manufacturing process. That is, according to one embodiment of this disclosure, by improving the structure of the circuit structure CS used as a test circuit, it is easier to detect whether the bonding pads UBD and LBD are bonded to each other.

[0062] Figures 3A to 3E This is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. Figures 3A to 3E Each corresponds to Figure 2A The A-A' cross section.

[0063] Reference Figure 3A The first well region PW and the first active region PA can be formed in the substrate SUB. The first well region PW and the first active region PA can be formed in the guard region GDA. The first well region PW and the first active region PA can surround the chip region CHA. The first well region PW and the first active region PA can be formed by an implantation process that implants a first type of impurity into the substrate SUB. For example, a first type of impurity can be implanted into a portion of the substrate SUB to form the first well region PW, and the first type of impurity can be additionally implanted into a portion of the first well region PW to form the first active region PA.

[0064] Reference Figure 3BThe first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be formed above the substrate SUB. The first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be formed in the protection region GDA. The third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be formed in the chip region CHA. The first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be surrounded by a lower insulating layer LIL.

[0065] For example, after forming a first insulating layer with a predetermined thickness, a portion of the first insulating layer can be etched. A first lower plug LP1 can be formed in the etched portion of the first insulating layer. Subsequently, after forming a second insulating layer covering the first lower plug LP1, a portion of the second insulating layer can be etched. Subsequently, a first lower line LL1 can be formed in the etched portion of the second insulating layer. In the same method as described above, the lower line and the lower plug can be formed in the Z direction. The substrate SUB, the lower insulating layer LIL, the first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be referred to as the lower structure STR1.

[0066] Reference Figure 3C The upper structure STR2 can be formed above the sacrificial substrate SSUB. The upper structure STR2 may include a first upper plug UP1, a first upper line UL1, an upper bonding contact UBC, and an upper bonding pad UBD. The first upper plug UP1, the first upper line UL1, the upper bonding contact UBC, and the upper bonding pad UBD can be formed in the protective region GDA. The first upper line UL1, the upper bonding contact UBC, and the upper bonding pad UBD can be formed in the chip region CHA. The first upper plug UP1, the first upper line UL1, the upper bonding contact UBC, and the upper bonding pad UBD can be surrounded by a first upper insulating layer UIL1. The upper bonding pad UBD can be exposed on the upper surface of the upper structure STR2. Although... Figure 3C It is not shown in the diagram, but the memory cell array can be formed in the chip area CHA.

[0067] Reference Figure 3DThe upper structure STR2 can be flipped and stacked on top of the lower structure STR1. Because the upper structure STR2 is flipped, the upper bonding pad UBD can be exposed on the lower surface of the upper structure STR2.

[0068] Reference Figure 3E The sacrificial substrate SSUB can be removed. For example, the sacrificial substrate SSUB can be selectively etched using an anisotropic dry etching process. Because the sacrificial substrate SSUB is removed, the first upper insulating layer UIL1 and the first upper plug UP1 can be exposed to the outside.

[0069] Subsequently, a second upper insulating layer UIL2 can be formed above the first upper insulating layer UIL1, and a second upper plug UP2 can be formed above the first upper plug UP1. Furthermore, a second upper line UL2 can be formed above the second upper plug UP2. Although Figure 3E Not shown in the diagram, but when the second upper line UL2 is formed, it can be formed simultaneously. Figure 2C The test electrode TE in the text. The terms "simultaneously" and "at the same time" used in this document to describe processes mean that the processes occur over overlapping time intervals. For example, if a first process occurs within a first time interval, and a second process simultaneously occurs within a second time interval, then the first and second intervals at least partially overlap, resulting in a time when both the first and second processes occur simultaneously.

[0070] The first well region PW, first active region PA, first lower plug LP1, first lower line LL1, second lower plug LP2, second lower line LL2, third lower plug LP3, third lower line LL3, lower bonding contact LBC, lower bonding pad LBD, upper bonding pad UBD, upper bonding contact UBC, first upper line UL1, first upper plug UP1, second upper plug UP2, and second upper line UL2 located in the protection region GDA can form the first chip protection component GD1 and the second chip protection component GD2. The third lower line LL3, lower bonding contact LBC, lower bonding pad LBD, upper bonding pad UBD, upper bonding contact UBC, and first upper line UL1 located in the chip region CHA (e.g., the test circuit region TCR) can form the circuit structure CS. It can be understood that the first upper plug UP1 and the second upper plug UP2 are included... Figure 2B The upper plug UP is included in the middle. This can be understood as the first upper insulating layer UIL1 and the second upper insulating layer UIL2 being included within... Figure 2B In the upper insulating layer UIL.

[0071] Figures 4A to 4D The diagram illustrates various embodiments related to the first embodiment of this disclosure. Figures 4A to 4D Each corresponds to Figure 2AThe C-C' cross section. Figures 4A to 4D It shows that, in addition to being relative to Figures 2A to 2D Various embodiments other than the first embodiment shown. In conjunction with... Figures 4A to 4D The omission or simplification has been referenced. Figures 2A to 2D A detailed description of the configuration.

[0072] Reference Figures 4A to 4D The circuit structure CS may include an upper bonding pad UBD and a lower bonding pad LBD connected in series. The upper bonding pad UBD and lower bonding pad LBD included in the circuit structure CS may be connected in series to form an electrical path. The upper bonding pad UBD and lower bonding pad LBD included in the circuit structure CS may form a single electrical path that electrically connects the test electrode TE. Figures 4A to 4D In the middle, it will be shown with Figure 2D Other chain structures that differ from the chain structure shown.

[0073] Reference Figure 4A The circuit structure CS may include a lower bonding pad LBD, an upper bonding pad UBD, an upper bonding contact UBC, and a first upper line UL1, all connected in series. The lower bonding pad LBD, upper bonding pad UBD, upper bonding contact UBC, and first upper line UL1 included in the circuit structure CS may be connected to each other in a chain-like manner. Figure 2D Compared to the structure shown, the lower bonding contact LBC and the third lower line LL3 that connect the lower bonding pad LBD can be omitted.

[0074] In the lower bonding pads (LBDs) included in the circuit structure CS, adjacent lower bonding pads (LBDs) can be electrically connected to each other via a single first upper line (UL1). For example, adjacent lower bonding pads (LBDs) can be electrically connected to each other via an upper bonding pad (UBD), an upper bonding contact (UBC), a first upper line (UL1), another upper bonding pad (UBD), and another upper bonding contact (UBC).

[0075] Furthermore, among the upper bonding pads UBD included in the circuit structure CS, adjacent upper bonding pads UBD can be electrically connected to each other via a single first upper line UL1. For example, adjacent upper bonding pads UBD can be electrically connected to each other via an upper bonding contact UBC, a first upper line UL1, and another upper bonding contact UBC.

[0076] Among the lower bonding pads (LBDs) included in the circuit structure CS, non-adjacent lower bonding pads (LBDs) can be electrically connected to each other through at least one lower bonding pad (LBD) and at least one upper bonding pad (UBD). Furthermore, among the upper bonding pads (UBDs) included in the circuit structure CS, non-adjacent upper bonding pads (UBDs) can be electrically connected to each other through at least one lower bonding pad (LBD) and at least one upper bonding pad (UBD).

[0077] Reference Figure 4B The circuit structure CS may include a third lower line LL3, a lower bonding contact LBC, a lower bonding pad LBD, and an upper bonding pad UBD connected in series. The third lower line LL3, lower bonding contact LBC, lower bonding pad LBD, and upper bonding pad UBD included in the circuit structure CS may be interconnected in a chain-like manner. Figure 2D Compared to the structure shown, the upper bonding contact UBC and the first upper line UL1, which connect the upper bonding pads UBD to each other, can be omitted.

[0078] In the lower bonding pads (LBDs) included in the circuit structure CS, adjacent lower bonding pads (LBDs) can be electrically connected to each other via a single third lower line (LL3). For example, adjacent lower bonding pads (LBDs) can be electrically connected to each other via a lower bonding contact (LBC), a third lower line (LL3), and another lower bonding contact (LBC).

[0079] Furthermore, among the upper bonding pads UBD included in the circuit structure CS, adjacent upper bonding pads UBD can be electrically connected to each other via a single third lower line LL3. For example, adjacent upper bonding pads UBD can be connected to each other via a lower bonding pad LBD, a lower bonding contact LBC, a third lower line LL3, another lower bonding contact LBC, and another lower bonding pad LBD.

[0080] Among the lower bonding pads (LBDs) included in the circuit structure CS, non-adjacent lower bonding pads (LBDs) can be electrically connected to each other through at least one lower bonding pad (LBD) and at least one upper bonding pad (UBD). Furthermore, among the upper bonding pads (UBDs) included in the circuit structure CS, non-adjacent upper bonding pads (UBDs) can be electrically connected to each other through at least one lower bonding pad (LBD) and at least one upper bonding pad (UBD).

[0081] Reference Figure 4CAt least a portion of each of the upper bonding pads UBD may not overlap with the lower bonding pads LBD. The lower bonding pads LBD may have a shorter length in the horizontal direction than the upper bonding pads UBD. Two lower bonding pads LBD may contact one upper bonding pad UBD. The upper bonding pads UBD can electrically connect the two lower bonding pads LBD.

[0082] In the lower bonding pads (LBDs) included in the circuit structure CS, adjacent lower bonding pads (LBDs) can be electrically connected to each other via a single third lower line (LL3) or via a single upper bonding pad (UBD). For example, adjacent lower bonding pads (LBDs) can be electrically connected to each other via a lower bonding contact (LBC), a third lower line (LL3), and another lower bonding contact (LBC). Alternatively, adjacent lower bonding pads (LBDs) can be electrically connected to each other via one of the upper bonding pads (UBDs).

[0083] Furthermore, among the upper bonding pads UBD included in the circuit structure CS, adjacent upper bonding pads UBD can be electrically connected to each other via a single third lower line LL3. For example, adjacent upper bonding pads UBD can be electrically connected to each other via a lower bonding pad LBD, a lower bonding contact LBC, a third lower line LL3, another lower bonding contact LBC, and another lower bonding pad LBD.

[0084] In the lower bonding pads (LBDs) included in the circuit structure CS, lower bonding pads (LBDs) that are not adjacent to each other can be electrically connected to each other through at least one lower bonding pad (LBD) and at least one upper bonding pad (UBD). For example, lower bonding pads (LBDs) that are not adjacent to each other can be electrically connected to each other through an upper bonding pad (UBD), a lower bonding pad (LBD), a lower bonding contact (LBC), a third lower line (LL3), and another lower bonding contact (LBC).

[0085] Furthermore, among the upper bonding pads UBD included in the circuit structure CS, upper bonding pads UBD that are not adjacent to each other can be electrically connected to each other through at least one lower bonding pad LBD and at least one upper bonding pad UBD. For example, upper bonding pads UBD that are not adjacent to each other can be electrically connected to each other through a lower bonding pad LBD, a lower bonding contact LBC, a third lower line LL3, another lower bonding contact LBC, another lower bonding pad LBD, an upper bonding pad UBD, another lower bonding pad LBD, another lower bonding contact LBC, another third lower line LL3, another lower bonding contact LBC, and another lower bonding pad LBD.

[0086] and Figure 4CIn a different implementation, each of the lower bonding pads (LBD) can have a greater length in the horizontal direction than each of the upper bonding pads (UBD). For example, the upper bonding contact (UBC) and the first upper line (UL1) can be chained together in the circuit structure (CS) instead of the lower bonding contact (LBC) and the third lower line (LL3).

[0087] Reference Figure 4D The circuit structure CS may include upper bonding pads UBD and lower bonding pads LBD connected in a chain structure. A portion of each of the upper bonding pads UBD may not overlap with the lower bonding pads LBD. Similarly, a portion of each of the lower bonding pads LBD may not overlap with the upper bonding pads UBD.

[0088] In the lower bonding pads (LBDs) included in the circuit structure CS, adjacent lower bonding pads (LBDs) can be electrically connected to each other via a single upper bonding pad (UBD). Furthermore, in the upper bonding pads (UBDs) included in the circuit structure CS, adjacent upper bonding pads (UBDs) can be electrically connected to each other via a single lower bonding pad (LBD).

[0089] Among the lower bonding pads (LBDs) included in the circuit structure CS, lower bonding pads (LBDs) that are not adjacent to each other can be electrically connected to each other through at least one lower bonding pad (LBD) and at least one upper bonding pad (UBD). For example, lower bonding pads (LBDs) that are not adjacent to each other can be electrically connected to each other through two or more upper bonding pads (UBD) and one or more lower bonding pads (LBDs).

[0090] Furthermore, among the upper bonding pads UBD included in the circuit structure CS, upper bonding pads UBD that are not adjacent to each other can be electrically connected to each other through at least one lower bonding pad LBD and at least one upper bonding pad UBD. For example, upper bonding pads UBD that are not adjacent to each other can be electrically connected to each other through two or more lower bonding pads LBD and one or more upper bonding pads UBD.

[0091] Besides relative to Figures 4A to 4D In addition to the circuit structure CS shown, various embodiments of the series connection of the bonding pads UBD and LBD can also be included within the scope of this disclosure.

[0092] Figures 5A to 5C This is a diagram showing the structure of a semiconductor device according to a second embodiment of the present disclosure. Figure 5A This is a plan view of the layout of a semiconductor device according to the second embodiment of the present disclosure. Figure 5B It shows along Figure 5A The cross section intercepted by line D-D'. Figure 5C It shows along Figure 5A The cross section intercepted by line E-E'.

[0093] Figures 5A to 5C It shows the relationship with relative to Figures 2A to 2D The second embodiment differs from the first embodiment shown. (Combined) Figures 5A to 5C The omission or simplification has been referenced. Figures 2A to 2D A detailed description of the configuration.

[0094] Reference Figure 5A The first chip protection component GD1 and the second chip protection component GD2 may surround the chip region CHA. The first chip protection component GD1 and the second chip protection component GD2 may be spaced apart from each other. For example, the first chip protection component GD1 may surround the chip region CHA, and the second chip protection component GD2 may surround both the chip region CHA and the first chip protection component GD1.

[0095] The test circuit region TCR can be located within the chip region CHA. At least a portion of the test circuit region TCR can be located between the first chip protection component GD1 and the second chip protection component GD2. The test circuit region TCR can extend in the direction in which the first chip protection component GD1 and the second chip protection component GD2 extend.

[0096] The test circuit region (TCR) can extend into the chip region (CHA). At least a portion of the test circuit region (TCR) can be located within the chip region (CHA). This portion of the test circuit region (TCR) can overlap with the first chip protection element (GD1).

[0097] Reference Figure 5A and Figure 5B The circuit structure CS may include bonding pads UBD and LBD located between the first chip protector GD1 and the second chip protector GD2. A portion of the bonding pads UBD and LBD included in the circuit structure CS may be disposed within a protector region GDA. Within the protector region GDA, the bonding pads UBD and LBD included in the circuit structure CS may be arranged along the space between the first chip protector GD1 and the second chip protector GD2. For example, each of the upper bonding pad UBD and the lower bonding pad LBD included in the circuit structure CS may be disposed along the direction extending from the first chip protector GD1 and the second chip protector GD2.

[0098] The circuit structure CS may include a test electrode TE. The test electrode TE may be located in the chip region CHA. For example, the test electrode TE may be located in the chip region CHA, so that the circuit structure CS can be used as a test circuit.

[0099] The circuit structure CS may include an electrical path that electrically connects the bonding pads UBD and LBD in the guard region GDA to the test electrode TE in the chip region CHA. The circuit structure CS may include a second active region NA, a second well region NW, and a third well region DW. The second well region NW and the second active region NA may be regions of the substrate SUB in which a second type of impurity has been implanted. The amount of impurity contained in the second active region NA may be greater than the amount of impurity contained in the second well region NW. The second type of impurity may include elements of Group 15. For example, the second type of impurity may include phosphorus (P). The third well region DW may be a region in the substrate SUB in which the second type of impurity is implanted. The third well region DW may be formed deeper than the first well region PW. For example, as Figure 5B As shown, the third well region DW can be formed at a greater depth than the first well region PW in the opposite direction of Z. In one embodiment, the circuit structure CS includes a second active region NA, a second well region NW, and a third well region DW having a greater depth than the first well region PW in the substrate SUB. For example, the circuit structure CS includes a second active region NA, a second well region NW, and a third well region DW having a greater depth than the first well region PW in the opposite direction of Z. Therefore, the second well regions NW can be electrically connected to each other via the third well region DW at the lower part of the first well region PW included in the first chip guard GD1. In the guard region GDA, the upper bonding pad UBD and the lower bonding pad LBD included in the circuit structure CS can be electrically connected to the test electrode TE via the third well region DW.

[0100] The third well region DW can extend from the protection region GDA into the chip region CHA. A portion of the third well region DW can be located within the protection region GDA. Another portion of the third well region DW can be located within the chip region CHA. The third well region DW can be located below the first chip protection component GD1. Therefore, the circuit structure CS can overlap with the first chip protection component GD1.

[0101] The isolation structure IS can be located between the first well region PW and the second well region NW. The isolation structure IS can include insulating material filled in the substrate SUB. The first well region PW and the second well region NW can be insulated from each other by the isolation structure IS.

[0102] In the protected area GDA, the circuit structure CS may include a lower bonding contact LBC, a third lower line LL3, a third lower plug LP3, a second lower line LL2, a second lower plug LP2, a first lower line LL1, and a first lower plug LP1, connecting the lower bonding pad LBD to the second active area NA. Furthermore, in the chip area CHA, the circuit structure CS may include a first lower plug LP1, a first lower line LL1, a second lower plug LP2, a second lower line LL2, a third lower plug LP3, a third lower line LL3, a lower bonding contact LBC, a lower bonding pad LBD, an upper bonding pad UBD, an upper bonding contact UBC, a first upper line UL1, and an upper plug UP, connecting the second active area NA to the test electrode TE.

[0103] Reference Figure 5C The circuit structure CS may include bonding pads UBD and LBD connected in series within the protection region GDA. The circuit structure CS may also include bonding pads UBD and LBD connected in series between the first chip protection component GD1 and the second chip protection component GD2. Within the protection region GDA, the circuit structure CS may include a first upper line UL1, an upper bonding contact UBC, an upper bonding pad UBD, a lower bonding pad LBD, a lower bonding contact LBC, and a third lower line LL3 connected in series. Within the protection region GDA, the first upper line UL1, the upper bonding contact UBC, the upper bonding pad UBD, the lower bonding pad LBD, the lower bonding contact LBC, and the third lower line LL3 may be continuously connected to each other. (See reference...) Figure 2D The described connection relationships between the first upper line UL1, upper bonding contact UBC, upper bonding pad UBD, lower bonding pad LBD, lower bonding contact LBC, and third lower line LL3 in the circuit structure CS can be similarly applied. Figure 5C In addition to being located in the protected area GDA.

[0104] According to a second embodiment of this disclosure, by placing a portion of the circuit structure CS between the first chip protector GD1 and the second chip protector GD2, the timing for detecting whether the bonding pads UBD and LBD are bonded to each other can be set differently. For example, in the various testing stages included in the manufacturing process of a semiconductor device, the occurrence of delamination can be detected not only in later testing stages but also in earlier testing stages.

[0105] Figures 6A to 6F This is a diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present disclosure. Figure 6A and Figures 6C to 6F Each corresponds to Figure 5A The E-E' cross section. Figure 6B It shows Figure 6A The cross-section.

[0106] Combination Figures 6A to 6F The omission or simplification has been referenced. Figures 3A to 3E A detailed description of the configuration.

[0107] Reference Figure 6A and Figure 6B A first well region PW, a first active region PA, a second well region NW, a second active region NA, and a third well region DW can be formed in a substrate SUB. The first well region PW and the first active region PA can be formed in a guard region GDA. The first well region PW and the first active region PA can surround a chip region CHA. A portion of the second well region NW can be formed in the guard region GDA, and another portion of the second well region NW can be formed in the chip region CHA. Each of the second active regions NA can overlap with each of the second well regions NW. Each of the third well regions DW can extend from the guard region GDA toward the chip region CHA.

[0108] The first well region PW and the first active region PA can be formed by an implantation process that implants a first type of impurity into the substrate SUB. For example, the first type of impurity can be implanted into a portion of the substrate SUB to form the first well region PW, and the first type of impurity can be additionally implanted into a portion of the first well region PW to form the first active region PA.

[0109] The second well region NW and the second active region NA can be formed by an implantation process that implants a second type of impurity into the substrate SUB. For example, the second type of impurity can be implanted into a portion of the substrate SUB to form the second well region NW, and the second type of impurity can be additionally implanted into a portion of the second well region NW to form the second active region NA.

[0110] The third well region (DW) can be formed by an implantation process that implants a second type of impurity into the substrate (SUB). The third well region (DW) can be formed deeper than the first well region (PW) and the second well region (NW). In the implantation process for forming the third well region (DW), impurities can be implanted into the third well region (DW) at a higher voltage than the implantation process for forming the first well region (PW) and the second well region (NW).

[0111] The formation order of the first well region PW, the first active region PA, the second well region NW, and the third well region DW can vary. For example, the first well region PW and the second well region NW can be formed after the third well region DW. In another example, the third well region DW can be formed after the first well region PW, the second well region NW, the first active region PA, and the second active region NA.

[0112] An isolation structure IS can be formed in a substrate SUB. The isolation structure IS can separate the first well region PW and the second well region NW from each other. For example, the isolation structure IS can be formed by filling an insulating material into a space where a portion of the substrate SUB has been removed. The isolation structure IS can be formed using various processes other than those described above. The isolation structure IS can be formed before or after forming the first well region PW, the second well region NW, the third well region DW, the first active region PA, and the second active region NA.

[0113] exist Figure 6B In the diagram, the first well regions PW are shown as being separated from each other, but the scope of this disclosure is not limited thereto. For example, as Figure 3A As shown, the first well regions PW can extend from each other. In other words, the first well region PW included in the first chip protection component GD1 and the first well region PW included in the second chip protection component GD2 can be separated from or connected to each other.

[0114] Reference Figure 6C The first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be formed above the substrate SUB. The first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be formed above the first active region PA and the second active region NA. The third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be formed in the protective region GDA. The first lower plug LP1, the first lower line LL1, the second lower plug LP2, the second lower line LL2, the third lower plug LP3, the third lower line LL3, the lower bonding contact LBC, and the lower bonding pad LBD can be surrounded by a lower insulating layer LIL.

[0115] Reference Figure 6D The upper structure STR2 can be formed above the sacrificial substrate SSUB. The upper structure STR2 may include a first upper plug UP1, a first upper line UL1, an upper bonding contact UBC, and an upper bonding pad UBD. The first upper plug UP1, the first upper line UL1, the upper bonding contact UBC, and the upper bonding pad UBD may be surrounded by a first upper insulating layer UIL1. The upper bonding pad UBD may be exposed on the upper surface of the upper structure STR2. Although... Figure 6D It is not shown in the diagram, but the memory cell array can be formed in the chip area CHA.

[0116] Reference Figure 6EThe upper structure STR2 can be flipped and stacked on top of the lower structure STR1. Because the upper structure STR2 is flipped, the upper bonding pad UBD can be exposed on the lower surface of the upper structure STR2.

[0117] Reference Figure 6F The sacrificial substrate SSUB can be removed. Subsequently, a second upper insulating layer UIL2 can be formed above the first upper insulating layer UIL1, and a second upper plug UP2 can be formed above the first upper plug UP1. Furthermore, a second upper line UL2 and a test electrode TE can be formed above the second upper plug UP2.

[0118] Figures 7A to 7D The diagram illustrates various embodiments related to the second embodiment of this disclosure. Figures 7A to 7D Each corresponds to Figure 5A The E-E' cross section. Figures 7A to 7D It shows that, in addition to being relative to Figures 5A to 5C Various embodiments other than the second embodiment shown. In conjunction with... Figures 7A to 7D The omission or simplification has been referenced. Figures 5A to 5C A detailed description of the configuration.

[0119] Reference Figures 7A to 7D The circuit structure CS may include an upper bonding pad UBD and a lower bonding pad LBD connected in series. The upper bonding pad UBD and lower bonding pad LBD included in the circuit structure CS may be connected in series to form an electrical path. The upper bonding pad UBD and lower bonding pad LBD included in the circuit structure CS may form a single electrical path that electrically connects the test electrode TE. Figures 7A to 7D It shows the relationship with Figure 5C Other chain structures that differ from the chain structure shown.

[0120] Reference Figure 7A The circuit structure CS may include a lower bonding pad LBD, an upper bonding pad UBD, an upper bonding contact UBC, and a first upper line UL1 connected in series. The lower bonding pad LBD, upper bonding pad UBD, upper bonding contact UBC, and first upper line UL1 included in the circuit structure CS may be chained together. Figure 4A Compared to the structure shown, except that the bonding pads UBD and LBD are located in the protection region GDA instead of the chip region CHA, the bonding pads UBD and LBD can have the same chain structure. Therefore, Figure 4A The specific connection structure of the bonding pads UBD and LBD shown can also be applied to Figure 7A .

[0121] Reference Figure 7BThe circuit structure CS may include a third lower line LL3, a lower bonding contact LBC, a lower bonding pad LBD, and an upper bonding pad UBD connected in series. The third lower line LL3, lower bonding contact LBC, lower bonding pad LBD, and upper bonding pad UBD included in the circuit structure CS may be interconnected in a chain-like manner. Figure 4B Compared to the structure shown, except that the bonding pads UBD and LBD are located in the protection region GDA instead of the chip region CHA, the bonding pads UBD and LBD can have the same chain structure. Therefore, Figure 4B The specific connection structure of the bonding pads UBD and LBD shown can also be applied to Figure 7B .

[0122] Reference Figure 7C At least a portion of each of the upper bonding pads (UBD) may not overlap with a lower bonding pad (LBD). Each of the lower bonding pads (LBD) may have a shorter horizontal length than each of the upper bonding pads (UBD). Two lower bonding pads (UBD) may contact one upper bonding pad (UBD). The upper bonding pad (UBD) can electrically connect the two lower bonding pads (UBD). Figure 4C Compared to the structure shown, except that the bonding pads UBD and LBD are located in the protection region GDA instead of the chip region CHA, the bonding pads UBD and LBD can have the same chain structure. Therefore, Figure 4C The specific connection structure of the bonding pads UBD and LBD shown can also be applied to Figure 7C .

[0123] Reference Figure 7D The circuit structure CS may include upper bonding pads UBD and lower bonding pads LBD connected in a chain structure. At least a portion of each of the upper bonding pads UBD may not overlap with the lower bonding pads LBD. Similarly, at least a portion of each of the lower bonding pads LBD may not overlap with the upper bonding pads UBD. Figure 4D Compared to the structure shown, except that the bonding pads UBD and LBD are located in the protection region GDA instead of the chip region CHA, the bonding pads UBD and LBD can have the same chain structure. Therefore, Figure 4D The specific connection structure of the bonding pads UBD and LBD shown can also be applied to Figure 7D .

[0124] Besides relative to Figures 7A to 7D In addition to the circuit structure CS shown, various embodiments of the series connection of the bonding pads UBD and LBD can also be included within the scope of this disclosure.

[0125] Figures 8A to 8DThis is a diagram illustrating a memory device including a circuit structure CS according to an embodiment of the present disclosure.

[0126] Figure 8A and Figure 8B A diagram of a memory device including a circuit structure CS according to a first embodiment of the present disclosure is shown. Figure 8C and Figure 8D A diagram of a memory device including a circuit structure CS according to a second embodiment of the present disclosure is shown.

[0127] Combination Figures 8A to 8D The omission or simplification has been referenced. Figures 2A to 7D A detailed description of the configuration.

[0128] Reference Figure 8A and Figure 8C The memory cell array can be formed in the chip area CHA. Cell plugs (CPL), contacts (CT), and peripheral circuit contacts (PCT) can be located in the chip area CHA. Figure 8A and Figure 8C Only a portion of the memory cell array included in the memory device is shown. Therefore, the number, location, and shape of the memory cell array are not limited to the scope of this disclosure and are not limited thereto. Figure 8A and Figure 8C The contents are shown in the figure. In one embodiment, the memory cell array may include a stacked structure, a conductive layer CD, an interlayer insulating layer IIL, cell plugs CPL, contacts CT, and a source layer SL. For example, the memory cell array may include: a stacked structure comprising alternating layers of conductive layers CD and interlayer insulating layers IIL; cell plugs CPL extending through the stacked structure; contacts CT, each connected to a conductive layer CD; and a source layer SL contacting the cell plugs CPL above the stacked structure.

[0129] Figure 8B It shows along Figure 8A The cross section intercepted by line F-F'. Figure 8D It shows along Figure 8C The cross section cut by line G-G'.

[0130] Reference Figure 8B and Figure 8DThe upper structure STR2 may include conductive layers CD and interlayer insulating layers IIL alternately stacked in the chip region CHA. The conductive layers CD and IIL may be alternately arranged in the Z direction. The conductive layers CD and IIL may have a stepped structure. As the conductive layer CD is located at the top of the conductive layers CD, the conductive layer CD may have a greater length in the X direction. The upper structure STR2 may include a source layer SL covering the conductive layers CD and IIL. The source layer SL may be located in the Z direction relative to the conductive layers CD and IIL. The upper structure STR2 may include cell plugs CPL penetrating the conductive layers CD and IIL. Each of the cell plugs CPL may extend in the Z direction. The cell plugs CPL may extend into the source layer SL. Each of the cell plugs CPL may have a width that narrows towards the top. The upper structure STR2 may have contacts CT respectively connected to the conductive layers CD. The contacts CT may respectively contact the conductive layers CD forming the stepped structure. The upper structure STR2 may include peripheral circuit contacts (PCTs). The peripheral circuit contacts (PCTs) may be spaced apart from the conductive layer CD.

[0131] The cell plug CPL can be connected to the substrate SUB via the cell contact CC, the first upper plug UP1, the first upper line UL1, the upper bonding contact UBC, the upper bonding pad UBD, the lower bonding pad LBD, the lower bonding contact LBC, the third lower line LL3, the third lower plug LP3, the second lower line LL2, the second lower plug LP2, the first lower line LL1, and the first lower plug LP1. Although Figure 8B and Figure 8D Although not shown, the cell plug CPL can be electrically connected to the transistor formed in and above the substrate SUB. The contact CT can be connected to the upper bonding pad UBD via the first upper line UL1 and the upper bonding contact UBC. The contact CT can be electrically connected to the lower structure STR1 via the upper bonding pad UBD and the lower bonding pad LBD. Although... Figure 8B and Figure 8DAlthough not shown, the contact CT can be electrically connected to control circuitry (e.g., a transmission transistor) formed in the lower structure STR1. The source layer SL can be connected to the second upper line UL2 via the second upper plug UP2. The peripheral circuit contact PCT can be connected to the second upper line UL2. The peripheral circuit contact PCT can be connected to the substrate SUB via the first upper line UL1, the upper bonding contact UBC, the upper bonding pad UBD, the lower bonding pad LBD, the lower bonding contact LBC, the third lower line LL3, the third lower plug LP3, the second lower line LL2, the second lower plug LP2, the first lower line LL1, and the first lower plug LP1. The peripheral circuit contact PCT can be connected to peripheral circuitry included in the lower structure STR1. For example, although not shown, the peripheral circuit contact PCT can be electrically connected to transistors formed in and above the substrate SUB.

[0132] According to the first and second embodiments of this disclosure, the circuit structure CS can be configured around components required for the operation of the memory device, such as a stacked structure of cell plugs CPL, contacts CT, peripheral circuit contacts PCT, conductive layer CD, and interlayer insulating layer IIL, and a source layer SL. Furthermore, the test electrode TE of the circuit structure CS can be located further away in the Z direction than the source layer SL, conductive layer CD, interlayer insulating layer IIL, cell plug CPL, and contacts CT. The upper bonding pad UBD and lower bonding pad LBD included in the circuit structure CS can be located further away in the opposite direction to the Z direction than the source layer SL, conductive layer CD, interlayer insulating layer IIL, cell plug CPL, and contacts CT.

[0133] Figure 9 This is a diagram illustrating a memory card system 3000 using a memory device according to an embodiment of the present disclosure.

[0134] Reference Figure 9 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0135] Controller 3100 can be coupled to memory device 3200. Controller 3100 can be configured to access memory device 3200. For example, controller 3100 can be configured to control programming, reading, or erasing operations of memory device 3200, or to control background operations. Controller 3100 can be configured to provide an interface between memory device 3200 and a host. Controller 3100 can be configured to drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0136] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, controller 3100 can be configured to communicate with external devices via at least one of the following communication protocols: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe. For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0137] The memory device 3200 may include a memory cell array containing multiple memory cells.

[0138] The controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and memory device 3200 can be integrated into a single semiconductor device to form a memory card, such as a PC card in the form of a PCMCIA card, a compact flash memory (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro or eMMC), a secure digital card (SD) card (SD, miniSD, microSD or SDHC), and a universal flash memory (UFS).

[0139] Figure 10 This is a diagram illustrating a solid-state drive (SSD) system 4000 to which an embodiment of the memory device according to the present disclosure is applied.

[0140] Reference Figure 10 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 through a signal connector 4001 and can receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0141] The controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from the host 4100. For example, the signals can be based on the interface between the host 4100 and the SSD 4200. For example, the signals can be defined through at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and NVMe interface.

[0142] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. The plurality of memory devices 4221 to 422n may communicate with the controller 4210 via channels CH1 to CHn.

[0143] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can receive power voltage from host 4100 and charge it using that power voltage. When the power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power voltage to SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be located on the motherboard and provide auxiliary power to SSD 4200.

[0144] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 can store data received from host 4100 or data received from multiple memory devices 4221 to 422n, or it can store metadata (e.g., a mapping table) of memory devices 4221 to 422n. Buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0145] According to embodiments of this disclosure, by improving the structure and layout of the test circuit, it is easier to detect whether the bonding pads are bonded to each other.

[0146] Cross-references to related applications

[0147] This application claims priority to Korean Patent Application No. 10-2024-0132989, filed with the Korean Intellectual Property Office on September 30, 2024, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: Protected area; A chip area, which is surrounded by the protective area; as well as A circuit structure comprising bonding pads connected in series in the chip region.

2. The semiconductor device of claim 1, further comprising an array of memory cells in the chip region. in, The circuit structure is disposed between the memory cell array and the protective region.

3. The semiconductor device according to claim 1, wherein, The chip region includes a first region and a second region, the first region including the center of the chip region, and the second region surrounding the first region. The circuit structure is located in the second region of the chip area.

4. The semiconductor device according to claim 1, wherein, The circuit structure extends along the interface between the chip region and the protective region.

5. The semiconductor device according to claim 1, wherein, The chip region has a generally rectangular shape, and The circuit structure has a shape corresponding to a portion of the generally rectangular shape.

6. The semiconductor device according to claim 1, in, The bonding pads include: Lower bonding pads, the lower bonding pads being exposed on the upper surface of the lower structure; and Upper bonding pads are exposed on the lower surface of the upper structure.

7. The semiconductor device according to claim 6, wherein, The lower bonding pads overlap with the upper bonding pads respectively.

8. The semiconductor device according to claim 6, wherein, The upper bonding pads overlap with the lower bonding pads respectively.

9. The semiconductor device according to claim 6, in, The lower structure includes: Lower bonding contacts, wherein the lower bonding contacts respectively contact the lower bonding pads; and The lower wires, each connecting to at least two of the lower engaging contacts, and The upper structure includes: Upper bonding contacts, wherein the upper bonding contacts respectively contact the upper bonding pads; and The upper line, each of which connects to at least two of the upper engagement contacts.

10. The semiconductor device according to claim 9, wherein, The circuit structure further includes the upper line, the upper bonding contact, the upper bonding pad, the lower bonding pad, the lower bonding contact, and the lower line connected in series.

11. The semiconductor device according to claim 10, wherein, The upper line, the upper bonding contact, the upper bonding pad, the lower bonding pad, the lower bonding contact, and the lower line are connected in a chain-like manner.

12. The semiconductor device according to claim 9, wherein, The circuit structure further includes test electrodes electrically connected to one or more of the upper lines.

13. The semiconductor device according to claim 12, wherein, Information about whether the lower structure and the upper structure are connected to each other is obtained through the test electrodes.

14. The semiconductor device according to claim 9, wherein, The circuit structure further includes the upper line, the upper bonding contact, the upper bonding pad, and the lower bonding pad connected in series.

15. The semiconductor device according to claim 14, wherein, The upper line, the upper bonding contact, the upper bonding pad, and the lower bonding pad are connected in a chain-like manner.

16. The semiconductor device according to claim 9, wherein, The circuit structure further includes the upper bonding pad, the lower bonding pad, the lower bonding contact, and the lower line connected in series.

17. The semiconductor device according to claim 16, wherein, The upper bonding pad, the lower bonding pad, the lower bonding contact, and the lower line are connected in a chain-like manner.

18. The semiconductor device according to claim 6, wherein, At least a portion of each of the upper bonding pads does not overlap with the lower bonding pad.

19. The semiconductor device according to claim 6, wherein, At least a portion of each of the lower bonding pads does not overlap with the upper bonding pad.

20. The semiconductor device according to claim 6, wherein, In the horizontal direction, the length of each of the lower bonding pads is different from the length of each of the upper bonding pads.

21. A semiconductor device, the semiconductor device comprising: Chip area; Chip protectors, the chip protectors surrounding the chip region and spaced apart from each other; as well as A circuit structure including bonding pads connected in series between the chip protection components.

22. The semiconductor device according to claim 21, wherein, The bonding pads are arranged along the direction in which the chip protection extends.

23. The semiconductor device according to claim 21, wherein, The circuit structure further includes test electrodes in the chip region.

24. The semiconductor device according to claim 23, in, The first chip protection component of the chip protection component surrounds the chip area, and The second chip protection component in the chip protection component surrounds the chip area and the first chip protection component.

25. The semiconductor device according to claim 24, wherein, A portion of the circuit structure overlaps with a portion of the first chip protective component.

26. The semiconductor device according to claim 24, in, The first chip protection component includes a first active region and a first well region in the substrate, and The circuit structure includes a second activation region, a second well region, and a third well region in the substrate, wherein the depth of the third well region is greater than the depth of the first well region.

27. The semiconductor device of claim 26, wherein, The bonding pad is electrically connected to the test electrode through the third well region.

28. The semiconductor device according to claim 21, in, The bonding pads include: Lower bonding pads, the lower bonding pads being exposed on the upper surface of the lower structure; and Upper bonding pads are exposed on the lower surface of the upper structure.

29. The semiconductor device according to claim 28, wherein, The lower bonding pad and the upper bonding pad overlap each other.

30. The semiconductor device according to claim 28, in, The lower structure includes: Lower bonding contacts, wherein the lower bonding contacts respectively contact the lower bonding pads; and The lower wires, each connecting to at least two of the lower engaging contacts, and The upper structure includes: Upper bonding contacts, wherein the upper bonding contacts respectively contact the upper bonding pads; and The upper line, each of which connects to at least two of the upper engagement contacts.

31. The semiconductor device according to claim 30, wherein, The circuit structure further includes the continuously connected upper line, upper bonding contact, upper bonding pad, lower bonding pad, lower bonding contact, and lower line.

32. The semiconductor device according to claim 30, wherein, The circuit structure further includes the continuously connected upper line, the upper bonding contact, the upper bonding pad, and the lower bonding pad.

33. The semiconductor device according to claim 30, wherein, The circuit structure further includes the upper bonding pad, the lower bonding pad, the lower bonding contact, and the lower line that are continuously connected.

34. The semiconductor device according to claim 30, wherein, At least a portion of each of the upper bonding pads does not overlap with the lower bonding pad.

35. The semiconductor device according to claim 30, wherein, At least a portion of each of the lower bonding pads does not overlap with the upper bonding pad.

36. A semiconductor device, the semiconductor device comprising: The lower structure includes peripheral circuitry; An upper structure, which is stacked on top of the lower structure and includes a memory cell array; The lower bonding pad is exposed on the upper surface of the lower structure; Upper bonding pads are exposed on the lower surface of the upper structure and respectively contact the lower bonding pads; as well as Test electrodes, wherein the test electrodes are connected in the upper structure to one or more of the upper bonding pads. The upper bonding pad and the lower bonding pad are connected in series to form an electrical path.

37. The semiconductor device according to claim 36, in, The lower structure further includes lower bonding contacts that respectively contact the lower bonding pads and lower lines connecting at least two of the lower bonding contacts. The upper structure further includes upper bonding contacts that respectively contact the upper bonding pads and upper lines that connect at least two of the upper bonding contacts.

38. The semiconductor device according to claim 37, wherein, Adjacent lower bonding pads are connected to each other via one of the lower lines or one of the upper lines.

39. The semiconductor device according to claim 37, wherein, Adjacent upper bonding pads are connected to each other via one of the lower lines or one of the upper lines.

40. The semiconductor device of claim 37, wherein, Adjacent lower bonding pads are connected to each other via one of the lower lines or one of the upper bonding pads.

41. The semiconductor device according to claim 37, wherein, Adjacent upper bonding pads are connected to each other via one of the lower bonding pads or one of the upper lines.

42. The semiconductor device according to claim 36, wherein, The non-adjacent lower bonding pads are electrically connected to each other by at least one lower bonding pad and at least one upper bonding pad.

43. The semiconductor device according to claim 36, wherein, The non-adjacent upper bonding pads are electrically connected to each other via at least one lower bonding pad and at least one upper bonding pad.

44. A memory device, the memory device comprising: The lower structure includes peripheral circuitry; An upper structure, which is stacked on top of the lower structure and includes a memory cell array; The first lower bonding pad is exposed on the upper surface of the lower structure; The first upper bonding pad is exposed on the lower surface of the upper structure and contacts the first lower bonding pad respectively; as well as Test electrodes, wherein the test electrodes are connected in the upper structure to one or more of the first upper bonding pads. The first upper bonding pad and the first lower bonding pad are connected in series to form an electrical path, and The electrical path surrounds the memory cell array.

45. The memory device according to claim 44, wherein, The memory cell array includes: A stacked structure comprising alternating layers of conductive layers and interlayer insulating layers; A unit plug that penetrates the stacked structure; Contacts, each of which is connected to the conductive layer; and A source layer that contacts the cell plug above the stacked structure.

46. ​​The memory device of claim 45, further comprising: The second upper bonding pad is connected to the unit plug and exposed on the lower surface of the upper structure. as well as The second lower bonding pad is exposed on the upper surface of the lower structure and contacts the second upper bonding pad.

47. The memory device of claim 45, further comprising: The third upper bonding pad is connected to the contact and exposed on the lower surface of the upper structure. as well as The third lower bonding pad is exposed on the upper surface of the lower structure and contacts the third upper bonding pad.

48. The memory device of claim 45, further comprising a peripheral circuit contact extending vertically in the upper structure and electrically connected to a peripheral circuit included in the lower structure.

49. The memory device of claim 48, further comprising: A fourth upper bonding pad is connected to the peripheral circuit contact and exposed on the lower surface of the upper structure. as well as A fourth lower bonding pad is exposed on the upper surface of the lower structure and contacts the fourth upper bonding pad.

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