Manufacturing method of back-illuminated image sensor and back-illuminated image sensor

Abstract

The invention discloses a manufacturing method of a back-illuminated image sensor and the back-illuminated image sensor, and the manufacturing method comprises the steps: providing a substrate which is provided with a front surface and a back surface which are opposite to each other; a metal interconnection layer is formed on the front surface of the substrate, and a contact hole is formed in the metal interconnection layer; etching from the back surface of the substrate to form a first through hole and a second through hole which penetrate through the substrate; the first through hole is coaxially aligned with the contact hole; each second through hole is located between two adjacent first through holes; the critical size of the second through hole is smaller than that of the first through hole; and conformally depositing an isolation material in the first through hole and the second through hole until the top of the second through hole is sealed. According to the invention, the problem of interlayer discharge of the TSV structure region is solved, the device is prevented from being burnt in the manufacturing process, and the product yield is improved.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a method for manufacturing a back-illuminated image sensor and the back-illuminated image sensor itself. Background Technology

[0002] With the development of semiconductor technology, back-illuminated image sensors are widely used due to their excellent photoelectric conversion efficiency and low noise characteristics. In the manufacturing process of back-illuminated image sensors, vertical interconnect structures such as through-silicon vias (TSVs) are usually required to achieve electrical connection between the front metal interconnect layer and the back metal layer of the chip.

[0003] However, extensive research has revealed the following drawbacks of existing back-illuminated image sensors: during the manufacturing process or device operation, charge can easily be conducted from the metal layer on the back of the substrate to the metal interconnect layer on the front of the substrate. Because the front of the substrate is in a floating state at certain stages of the process, this charge cannot be effectively transferred to the ground terminal, easily leading to charge accumulation at the contact points on the front of the substrate. This creates a potential difference with the adjacent TSV structure, easily resulting in interlayer discharge (or "arc discharge"). This interlayer discharge phenomenon generates instantaneous large currents and high heat, causing device performance degradation, increased dark current, increased white spots, and even directly burning out metal interconnects or damaging semiconductor junctions, severely impacting product yield.

[0004] The statements herein provide only background information in relation to this invention and do not necessarily constitute prior art. Summary of the Invention

[0005] The purpose of this invention is to provide a method for manufacturing a back-illuminated image sensor and a back-illuminated image sensor, so as to solve the problem of interlayer discharge caused by charge accumulation in the TSV structure region, avoid the device being burned out during the manufacturing process, and improve the product yield.

[0006] To achieve the above objectives, the present invention provides a method for manufacturing a back-illuminated image sensor, comprising: A substrate is provided, the substrate having opposing front and back sides; a metal interconnect layer is formed on the front side of the substrate, and contact holes are formed on the metal interconnect layer; A first through-hole and a second through-hole are etched through the back side of the substrate; the first through-hole is coaxially aligned with the contact hole; the second through-hole is located between two adjacent first through-holes; the critical dimension of the second through-hole is smaller than the critical dimension of the first through-hole; Conformal deposition of isolation material is performed in the first through-hole and the second through-hole until the top of the second through-hole is sealed.

[0007] Optionally, the first through-hole and the second through-hole are formed simultaneously by the same mask process.

[0008] Optionally, the method for forming the first through hole and the second through hole includes: A patterned mask layer is formed on the back side of the substrate. The mask layer has a plurality of first openings and second openings. The first openings define the etching positions of the first vias, and the second openings define the etching positions of the second vias.

[0009] Optionally, both the first through-hole and the second through-hole are annular structures surrounding the logic circuit area or pixel area.

[0010] Optionally, the manufacturing method further includes: Vertically etch the insulating material at the bottom of the first through hole until the contact hole is fully exposed; After depositing conductive material in the first through hole on the contact hole and on the back side of the substrate, a portion of the conductive material above the back side of the substrate is etched away to form a vertical interconnect structure electrically connected to the metal interconnect layer.

[0011] Optionally, the conductive material is either tungsten or copper.

[0012] Optionally, the method for depositing the conductive material includes any one of chemical vapor deposition, electroplating, or physical vapor deposition.

[0013] Optionally, a plurality of first shallow trenches and second shallow trenches are etched on the front side of the substrate, and the first shallow trenches and second shallow trenches are filled with an isolation material to form a first shallow trench isolation structure and a second shallow trench isolation structure; the first shallow trench isolation structure is coaxially aligned with the etching position of the first through hole, and the second shallow trench isolation structure is coaxially aligned with the etching position of the second through hole.

[0014] Optionally, the bottom of the first through hole formed by etching extends to the first shallow trench isolation structure, and the bottom of the second through hole extends to the second shallow trench isolation structure.

[0015] Optionally, the insulating material is any one or more of silicon oxide or silicon nitride.

[0016] Optionally, the method for depositing the isolation material includes either plasma-enhanced chemical vapor deposition or atomic layer deposition.

[0017] Accordingly, the present invention also provides a back-illuminated image sensor, which is formed by the manufacturing method described above.

[0018] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects: This invention forms a second via between adjacent first vias (i.e., conductive TSV structures), and fills the second via with an insulating material until the top of the second via is sealed, forming an isolation structure. This isolation structure acts as a potential isolation barrier, blocking the direct charge transfer path between adjacent conductive TSV structures, thereby effectively suppressing the risk of interlayer discharge. Furthermore, the critical dimension of the second via is smaller than that of the first via, allowing the top of the second via to be naturally sealed by the insulating material during deposition, thus enhancing the ability to isolate potential.

[0019] Furthermore, the first and second vias of the present invention are formed simultaneously using the same masking process, making them fully compatible with existing manufacturing processes and eliminating the need for additional etching steps or masks. Specifically, the present invention can simultaneously define the etching positions of the first and second vias by forming a patterned mask layer with different openings on the back side of the substrate, simplifying the process flow. Attached Figure Description

[0020] Figure 1A This is a partial cross-sectional schematic diagram of interlayer discharge phenomenon in a back-illuminated image sensor.

[0021] Figure 1B This is a planar schematic diagram of a sealing ring layout.

[0022] Figure 2 This is a flowchart of a method for manufacturing a back-illuminated image sensor according to the present invention.

[0023] Figure 3 This is a partial cross-sectional schematic diagram of a substrate for completing the front-side process of a substrate according to the present invention.

[0024] Figure 4 This is a partial cross-sectional schematic diagram of a substrate with a first through hole and a second through hole formed by etching according to the present invention.

[0025] Figure 5 This is a partial cross-sectional schematic diagram of a substrate with a patterned mask layer formed according to the present invention.

[0026] Figure 6 This is a partial cross-sectional schematic diagram of a substrate for completing the conformal deposition of isolation material according to the present invention.

[0027] Figure 7 This is a flowchart illustrating another method for manufacturing a back-illuminated image sensor according to the present invention.

[0028] Figure 8 This is a partial cross-sectional schematic diagram of a substrate with a patterned hard mask layer formed according to the present invention.

[0029] Figure 9 This is a partial cross-sectional schematic diagram of a substrate from which the isolation material at the bottom of the first through-hole has been removed by vertical etching, according to the present invention.

[0030] Figure 10 This is a partial cross-sectional schematic diagram of a substrate with a conductive material deposited on it, according to the present invention.

[0031] Figure 11 This is a partial cross-sectional schematic diagram of a substrate with a vertical interconnect structure formed according to the present invention.

[0032] Figure 12 This is a partial cross-sectional schematic diagram of a substrate for completing the front-side process of the substrate according to another method of the present invention.

[0033] Figure 13 This is a partial cross-sectional schematic diagram of another substrate of the present invention, in which a first through hole and a second through hole are formed by etching.

[0034] Figure 14 This is a partial cross-sectional schematic diagram of a substrate for completing another conformal deposition of isolation material according to the present invention.

[0035] Figure 15 This is a partial cross-sectional schematic diagram of a substrate from which the isolation material at the bottom of the first via has been removed by vertical etching, according to another embodiment of the present invention.

[0036] Figure 16 This is a partial cross-sectional schematic diagram of another substrate with a vertical interconnect structure according to the present invention.

[0037] Figure 17 This is a planar schematic diagram of a sealing ring layout according to the present invention.

[0038] Attached image labels: 1. Sealing ring; 2. Main chip; 3. TSV structure; Substrate 10, front side of substrate 11, back side of substrate 12; Contact hole 20; Metal interconnect layer 30; First through hole 40 (40'), second through hole 50 (50'), critical dimension CD1 of the first through hole, critical dimension CD2 of the second through hole, isolation dielectric layer 41 (41'), isolation structure 51; Mask layer 60, first opening 61, second opening 62; Hard mask layer 70; Metal layer 80; Vertical interconnect structure 90; First shallow trench isolation structure 111; Second shallow trench isolation structure 112 Chip functional area 100. Detailed Implementation

[0039] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the manufacturing method of a back-illuminated image sensor and the back-illuminated image sensor proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0040] The "critical dimension" mentioned in this article refers to the minimum dimension of the first or second through hole in the horizontal direction, which is the width of the first or second through hole.

[0041] In this document, a “TSV structure” includes a vertical via through a substrate, an insulating material covering the sidewalls of the vertical via, a conductive material filling the interior of the vertical via, a metal layer on the back side of the substrate corresponding to the vertical via, a contact hole located between the vertical via and a metal interconnect layer on the front side of the substrate corresponding to the vertical via, and a metal interconnect layer on the front side of the substrate corresponding to the vertical via.

[0042] As described in the background section, in existing back-illuminated image sensors, interlayer discharge in the TSV structure region severely affects device yield. Specifically, for example, Figure 1A A partial cross-sectional structure of a back-illuminated image sensor is shown. Figure 1B It shows Figure 1A The layout involves a TSV structure 3 with a ring-shaped structure forming a sealing ring 1 at the edge of the main chip 2. For example... Figure 1A As shown, charge is conducted through the metal layer 80 on the back side of the substrate to the metal interconnect layer 30 on the front side. Since the front-side chip is in a floating state, the charge cannot be effectively grounded, leading to charge accumulation at the contact hole 20. When a sufficiently large potential difference is formed between the accumulated charge at the contact hole 20 and the metal layer 80 on the back side of the adjacent TSV structure 3 substrate, and the substrate's insulation is insufficient to block this potential difference, an interlayer arc discharge will occur. It should be noted that... Figure 1A , Figure 1B This is just an example. Figure 1A , Figure 1B The image illustrates the interlayer discharge problem in the sealing ring 1 and main chip 2 regions. However, this interlayer discharge problem is not limited to the sealing ring 1 region of the image sensor, but is prevalent in any semiconductor device containing TSV structures 3. As long as there is a potential difference between adjacent TSV structures 3, they may face similar interlayer discharge risks.

[0043] To address the aforementioned technical problems, this invention provides a method for manufacturing a back-illuminated image sensor and the back-illuminated image sensor itself. A second via is added between adjacent conductive TSV structures (i.e., the location of the first via), and an insulating material is filled into the second via to form an isolation structure between adjacent first vias. This enhances the isolation capability of interlayer potential, thereby preventing the formation of discharge paths. Furthermore, the manufacturing direction of this invention is fully compatible with existing processes. No additional mask is required when etching the first and second vias, avoiding the introduction of additional photolithography steps or process adjustments, and significantly reducing production costs while improving device yield.

[0044] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0045] like Figure 2 As shown, the present invention provides a method for manufacturing a back-illuminated image sensor, comprising the following steps: Step 1, providing a substrate having a front side and a back side; a metal interconnect layer is formed on the front side of the substrate, and contact holes are formed on the metal interconnect layer.

[0046] The substrate 10 can be a substrate for a device wafer or a silicon substrate. In this embodiment, the substrate 10 is a silicon substrate. Contact holes 20 and metal interconnect layers 30 are formed on the front side 11 of the substrate 10 using conventional methods. Then, the substrate 10 is flipped so that the back side 12 faces upwards, resulting in a partial cross-sectional structure as shown below. Figure 3 As shown.

[0047] Step 2: Etch a first through-hole and a second through-hole through the substrate from the back side of the substrate; the first through-hole is coaxially aligned with the contact hole; the second through-hole is located between two adjacent first through-holes; the critical dimension of the second through-hole is smaller than the critical dimension of the first through-hole.

[0048] The partial cross-sectional structure of the substrate 10 formed in step 2 is as follows: Figure 4As shown. The second through hole 50 is located between two adjacent first through holes 40, and the first through holes 40 are coaxially aligned with the contact hole 20. That is, the second through hole 50 is located between the contact hole 20 and the adjacent first through hole 40. This allows the second through hole 50 to form an isolation structure between adjacent conductive TSV structures after being filled with insulating material and subsequent process steps, acting as a potential isolation barrier and effectively blocking the direct transfer path of charge between the contact hole 20 and the adjacent first through hole 40.

[0049] In some embodiments, the first via 40 and the second via 50 are formed simultaneously by the same masking process, making full use of existing process technology without adding an additional masking step, thus significantly reducing production costs while improving device yield. Simultaneously, simultaneous etching ensures the accuracy of the positional relationship between the first via 40 and the second via 50, avoiding structural failures that may be caused by multiple photolithography alignment errors. In these embodiments, the method for forming the first via 40 and the second via 50 includes: A patterned mask layer 60 is formed on the back surface 12 of the substrate. The mask layer 60 has a plurality of first openings 61 and second openings 62. The first openings 61 define the etching positions of the first vias 40, and the second openings 62 define the etching positions of the second vias 50. The resulting local cross-sectional structure is as follows: Figure 5 As shown.

[0050] The mask layer 60 can be made of silicon nitride, silicon oxide, or similar materials. A patterned mask layer 60 can be formed by spin-coating photoresist onto the surface of the deposited mask layer 60, followed by photolithography and etching processes. In this embodiment, the mask layer 60 is made of silicon oxide and has a thickness of at least 30 nm, preferably at least 50 nm, to ensure sufficient etching resistance during the etching process.

[0051] In some embodiments, an etching process, such as using a combination of gases like SF6 and C4F8, can be used to etch the substrate 10 below the first opening 61 and the second opening 62 through the substrate 10 in a single step, forming the first via 40 and the second via 50. Then, the patterned mask layer 60 is removed.

[0052] In some embodiments, the critical dimensions used in etching include a first critical dimension CD1 and a second critical dimension CD2. That is, the critical dimension of the first through-hole 40 formed by etching is CD1, and the critical dimension of the second through-hole 50 formed by etching is CD2. The relationship between CD2 and CD1 is: CD2 < CD1.

[0053] It should be noted that in some embodiments, the upper limit of the critical dimension CD2 of the second via 50 must meet the requirement of self-closing sealing under the subsequent conformal deposition process. Specifically, when the process conditions set the conformal deposition thickness of the isolation material to T, the critical dimension CD2 of the second via 50 should satisfy: CD2≤2T, to ensure that the isolation materials growing on the sidewalls of the second via 50 can naturally converge and close at the top during the subsequent conformal deposition process. For example, when the process conditions limit the thickness of the isolation material formed at the bottom and sidewalls of the first via 40 to 100nm, the critical dimension CD2 of the second via 50 should not be greater than 200nm, so that the top of the second via 50 will naturally close to form a seal through the conformal deposition process, thereby constructing a potential isolation barrier. In this case, the first via 40 may be closed or not, which is not limited by this invention.

[0054] Step 3: Conformally deposit isolation material in the first through hole and the second through hole until the top of the second through hole is sealed.

[0055] like Figure 6 As shown, because the critical dimension CD2 of the second through-hole 50 is small, in step 3 (the step of conformally depositing the isolation material), the top of the second through-hole 50 can be completely sealed by the isolation material to form an isolation structure 51. However, because the critical dimension CD1 of the first through-hole 40 is large, the deposited isolation material forms an isolation dielectric layer 41 at the bottom and sidewalls of the first through-hole 40. A cavity will still be retained inside the first through-hole 40 to allow for subsequent filling with conductive material to form an electrical connection.

[0056] The formed isolation structure 51 forms an effective potential isolation barrier between adjacent first through holes 40. When charge is conducted through the back metal layer and accumulates at the contact hole 20, the isolation structure 51 can effectively block the discharge path between adjacent first through holes 40, preventing interlayer discharge caused by excessive potential difference.

[0057] In some embodiments, the insulating material is any one or more of silicon oxide or silicon nitride.

[0058] In some embodiments, the method for depositing the insulating material includes either plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0059] It is important to emphasize that in this invention, a conformally deposited insulating material is required to seal the top of the second via 50 to prevent the subsequent penetration of conductive material. If the top of the second via 50 remains open, in subsequent processes, the second via 50 will also be filled with conductive material, just like the first via 40, thus losing its insulating function and failing to effectively block the charge migration path, thereby failing to solve the fundamental problem of interlayer discharge.

[0060] It should be noted that in this invention, when conformally depositing the isolation material, only the top of the second via 50 needs to be sealed, without requiring the middle portion of the second via to be completely filled. On one hand, from the perspective of the electrical isolation mechanism, once the top of the second via 50 is sealed with the isolation material, a continuous potential isolation barrier is constructed between adjacent conductive TSV structures, sufficient to block charge migration paths and achieve effective interlayer potential isolation. On the other hand, due to the difference in thermal expansion coefficients between the isolation material and the substrate 10, thermal stress will be generated during temperature changes. The presence of cavities or air gaps in the middle portion of the second via 50 helps to release stress, reducing the risk of cracking or peeling of the isolation material and improving the reliability of the isolation structure 51. Therefore, the process for depositing the isolation material does not require costly and complex high aspect ratio filling techniques; standard conformal deposition processes (e.g., PECVD or ALD) can meet the requirements.

[0061] In some embodiments, such as Figure 7 As shown, the manufacturing method of the present invention further includes: Step 4: Vertically etch the insulating material at the bottom of the first through hole until the contact hole is fully exposed.

[0062] After conformally depositing isolation material in the first via 40 and the second via 50, the isolation material at the bottom of the first via 40, i.e., the isolation material covering the contact hole 20, needs to be removed to rebuild the electrical connection path with the contact hole 20 below. In some embodiments, a patterned hard mask layer 70 can be formed on the back side 12 of the substrate, and then an etching process can be used to completely remove the isolation material at the bottom of the first via 40 until the top surface of the contact hole 20 below is fully exposed. The patterned hard mask layer 70 is formed in a similar manner to the aforementioned patterned mask layer 60. After spin-coating photoresist, the patterned hard mask layer 70 can be formed by photolithography and etching processes. The patterned hard mask layer 70 covers the second via area and the chip functional area, exposing only the bottom area of ​​the first via 40, such as... Figure 8 As shown. Then, using the patterned hard mask layer 70 as a mask, anisotropic etching is performed through an etching process to vertically etch the isolation material at the bottom of the first via 40 until the contact hole 20 is completely exposed; afterwards, the patterned hard mask layer 70 is removed, as shown. Figure 9 As shown.

[0063] In some embodiments, the thickness of the hard mask layer 70 is greater than or equal to 30 nm, preferably greater than or equal to 50 nm, to ensure that it has sufficient resistance to etching during the etching process.

[0064] Step 5: After depositing conductive material in the first through hole on the contact hole and above the back side of the substrate, etch away part of the conductive material above the back side of the substrate to form a vertical interconnect structure electrically connected to the metal interconnect layer.

[0065] like Figure 10 As shown, a conductive material is deposited on the back side 12 of the substrate, filling the first via 40 and covering the back side 12 to form a metal layer 80 for electrical connection with the metal interconnect layer 30 on the front side 11 of the substrate. Then, a patterned mask is used to define the back metal layer pattern, and a portion of the metal layer 80 is etched away to form a vertical interconnect structure 90 connecting the metal interconnect layer 30 on the front side 11 of the substrate, as shown. Figure 11 As shown. The metal layer 80 is used to form metal traces and / or metal grids.

[0066] During the deposition of conductive material, since the top of the second through hole 50 is sealed by the insulating material, the conductive material cannot enter the interior of the second through hole 50. Therefore, the insulating structure 51 remains in an insulating state and can perform the function of potential isolation.

[0067] In some embodiments, the conductive material is either tungsten or copper.

[0068] In some embodiments, the method for depositing the conductive material includes any one of chemical vapor deposition, electroplating, or physical vapor deposition.

[0069] In other embodiments of the present invention, in step 1 described above, before forming the contact hole 20 and the metal interconnect layer 30, the front side of the substrate 11 is etched to form a plurality of first shallow trenches and second shallow trenches. The first shallow trenches and second shallow trenches are filled with an insulating material to form a first shallow trench isolation structure 111 and a second shallow trench isolation structure 112. The first shallow trench isolation structure 111 is coaxially aligned with the contact hole 20 and simultaneously defines the etching positions of the contact hole 20 and the first via 40. The second shallow trench isolation structure 112 defines the etching position of the second via 50. In these embodiments, after completing the subsequent front side process of the substrate, the substrate 10 is flipped, resulting in a partial cross-sectional structure as shown below. Figure 12 As shown. Then, etching is performed from the back side 12 of the substrate, extending from the bottom of the first via 40' formed by the etching to the first shallow trench isolation structure 111, and the bottom of the second via 50' extends to the second shallow trench isolation structure 112, as shown. Figure 13As shown. During the etching process, the first shallow trench isolation structure 111 and the second shallow trench isolation structure 112 can serve as etching stop layers to control the etching depth of the first through hole 40' and the second through hole 50', preventing over-etching from damaging the contact hole 20. Subsequent steps are the same as steps 3 to 5 described above, and the resulting local cross-sectional structures are shown below. Figures 14-16 As shown; in step 4, as Figure 15 As shown, during vertical etching, it is necessary to etch away the isolation medium layer 41' formed by conformal deposition at the bottom of the first via 40' and a portion of the first shallow trench isolation structure 111 located below the first via 40'. That is, it is necessary to etch through a portion of the first shallow trench isolation structure 111 to fully expose the top surface of the contact hole 20. Optionally, in this invention, the second shallow trench isolation structure 112 may not be provided, and only the first shallow trench isolation structure 111 may be provided. In this case, the etching position of the second via 50' can be defined by other photolithographic alignment marks or process design.

[0070] As an example, the first shallow trench and the second shallow trench can be formed simultaneously using a conventional shallow trench isolation (STI) process. In a scenario where the substrate thickness is 1μm to 10μm, the depths of the first and second shallow trenches are 200nm to 400nm. The first and second shallow trenches are filled with silicon oxide, and their surfaces are planarized by chemical mechanical polishing to form the first shallow trench isolation structure 111 and the second shallow trench isolation structure 112.

[0071] In some embodiments, the first through-hole 40 (or the first through-hole 40') and the second through-hole 50 (or the second through-hole 50') are both annular structures, surrounding the chip functional area 100. After forming the vertical interconnect structure 90, a complete sealing ring layout is formed, as shown in the top view below. Figure 17 As shown. The chip functional area 100 includes a logic circuit area or a pixel area. When the first via 40 (or the first via 40') and the second via 50 (or the second via 50') surround the key functional area in a ring structure, a continuous potential isolation barrier can be formed at the edge of the area, providing comprehensive discharge protection for the chip functional area 100 and improving the yield during the device manufacturing process.

[0072] In summary, this invention forms an effective potential isolation barrier by setting a smaller critical second via between adjacent first vias (conductive TSV structures) and depositing isolation material within the second via until it is naturally sealed at the top. This blocks the charge transfer path between adjacent conductive TSV structures and significantly reduces the risk of interlayer discharge. Simultaneously, the first and second vias can be formed simultaneously using the same masking process. Different sized openings can be designed in a patterned mask layer on the back of the substrate to define the etching positions of both vias simultaneously, without requiring additional photomasks or process steps. This makes it fully compatible with existing manufacturing processes, solving the interlayer discharge problem while maintaining process simplicity and cost-effectiveness.

[0073] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0074] In the description of this invention, it should be understood that the terms "center," "height," "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0075] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0076] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0077] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for manufacturing a back-illuminated image sensor, characterized in that, include: A substrate is provided, the substrate having opposing front and back sides; A metal interconnect layer is formed on the front side of the substrate, and contact holes are formed on the metal interconnect layer; A first through-hole and a second through-hole are etched through the back side of the substrate; the first through-hole is coaxially aligned with the contact hole; the second through-hole is located between two adjacent first through-holes; the critical dimension of the second through-hole is smaller than the critical dimension of the first through-hole; Conformal deposition of isolation material is performed in the first through-hole and the second through-hole until the top of the second through-hole is sealed.

2. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The first through hole and the second through hole are formed simultaneously by the same mask process.

3. The method for manufacturing a back-illuminated image sensor as described in claim 2, characterized in that, The method for forming the first through hole and the second through hole includes: A patterned mask layer is formed on the back side of the substrate. The mask layer has a plurality of first openings and second openings. The first openings define the etching positions of the first vias, and the second openings define the etching positions of the second vias.

4. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, Both the first and second through holes are ring structures, surrounding the logic circuit area or pixel area.

5. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The manufacturing method further includes: Vertically etch the insulating material at the bottom of the first through hole until the contact hole is fully exposed; After depositing conductive material in the first through hole on the contact hole and on the back side of the substrate, a portion of the conductive material above the back side of the substrate is etched away to form a vertical interconnect structure electrically connected to the metal interconnect layer.

6. The method for manufacturing a back-illuminated image sensor as described in claim 5, characterized in that, The conductive material is either tungsten or copper.

7. The method for manufacturing a back-illuminated image sensor as described in claim 5, characterized in that, The method for depositing the conductive material includes any one of chemical vapor deposition, electroplating, or physical vapor deposition.

8. The method for manufacturing a back-illuminated image sensor as described in claim 1, characterized in that, The substrate has a plurality of first shallow trenches and second shallow trenches etched on its front side. The first shallow trenches and second shallow trenches are filled with isolation material to form a first shallow trench isolation structure and a second shallow trench isolation structure. The first shallow trench isolation structure is coaxially aligned with the etching position of the first through hole, and the second shallow trench isolation structure is coaxially aligned with the etching position of the second through hole.

9. The method for manufacturing a back-illuminated image sensor as described in claim 8, characterized in that, The bottom of the first through hole formed by etching extends to the first shallow trench isolation structure, and the bottom of the second through hole extends to the second shallow trench isolation structure.

10. The method for manufacturing a back-illuminated image sensor as described in claim 1 or 8, characterized in that, The insulating material is any one or more of silicon oxide or silicon nitride.

11. The method for manufacturing a back-illuminated image sensor as described in claim 1 or 8, characterized in that, The method for depositing the isolation material includes any one of plasma-enhanced chemical vapor deposition and atomic layer deposition.

12. A back-illuminated image sensor, characterized in that, Formed by the manufacturing method according to any one of claims 1 to 11.

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