LED epitaxial wafer and preparation method and application thereof

Abstract

The invention discloses an LED epitaxial wafer and a preparation method and application thereof. The LED epitaxial wafer comprises a substrate, a nucleation buffer lamination layer and an epitaxial structure layer, the nucleating buffer lamination layer comprises a graphic structure layer, a graphic covering layer and a top covering layer which are sequentially laminated along a selected direction; the graphic structure layer comprises a plurality of AlN graphic structures, and the height ratio of the adjacent AlN graphic structures is between 1.2 and 3; the pattern covering layer is a profiling pattern covering layer, and the pattern covering layer comprises an AlN layer, an Al-Si-N miscible layer and a SiN layer which are stacked in a circulating mode; the top covering layer is made of AlN and completely covers the pattern covering layer. According to the invention, by forming the plane differentiation and multi-layer composite microstructure, the relaxation between the crystal boundaries can well release the stress and enhance the lateral epitaxy capability, so that the dislocation is fully turned to realize self annihilation, the upward extension of the dislocation is avoided, and the crystal quality is improved.

Description

Technical Field

[0001] This invention relates to the field of nitride semiconductor technology, and more particularly to an LED epitaxial wafer, its preparation method and application. Background Technology

[0002] Wide bandgap nitride semiconductor materials possess excellent physical and chemical properties such as high breakdown field strength, high thermal conductivity, and fast electron saturation migration rate, and have attracted much attention due to their broad application prospects in blue-green LEDs, photodetectors, and high-temperature, high-frequency, and high-power devices.

[0003] Because nitride single-crystal materials are scarce in nature, and the growth of bulk single-crystal nitrides is extremely difficult, the growth of nitride materials mainly employs heteroepitaxial methods. Currently, the most mature epitaxial techniques for preparing nitride materials are all grown on heterogeneous substrates. Due to the lattice and thermal expansion mismatch between the substrate and the epitaxial layer, the grown crystal material has a high dislocation density and high stress, making it prone to warping and cracking. The lattice constants and thermal mismatch between different materials generate dislocations or defects that extend upwards with the growth of the epitaxial layer. These dislocations act as non-radiative recombination centers during device operation, affecting device efficiency. Simultaneously, they act as leakage channels, increasing leakage current and causing rapid device aging, impacting device efficiency and lifespan, thus limiting their application in the semiconductor electronics field. Furthermore, with the unprecedented development of high-end applications, there is a growing demand for reducing defects in the epitaxial layer, and existing processes are insufficient to meet these increasingly stringent requirements.

[0004] It is evident that reducing the dislocation density of heterogeneous materials such as sapphire during nitride epitaxial growth is of great significance for accelerating the industrial application of nitride materials. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide an LED epitaxial wafer, its preparation method and application.

[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes: In a first aspect, the present invention provides an LED epitaxial wafer, which includes a substrate, a nucleation buffer stack and an epitaxial structure layer sequentially stacked along a selected direction; The nucleation buffer stack includes a graphic structure layer, a graphic overlay layer, and a top overlay layer stacked sequentially along the selected direction; The graphic structure layer includes multiple AlN graphic structures, and the height ratio of adjacent AlN graphic structures is between 1.2 and 3. The patterned overlay layer conforms to the patterned structure layer, and the patterned overlay layer includes a cyclically stacked AlN layer, an Al-Si-N miscible layer, and a SiN layer; The top overlay layer is made of AlN and completely covers the graphic overlay layer.

[0007] Furthermore, the AlN graphic structure includes an adjacent first graphic structure and a second graphic structure, wherein the height of the first graphic structure is greater than that of the second graphic structure. The height of the first pattern structure is 100-500nm, and the lateral diameter of the first pattern structure is 200-1000nm.

[0008] Furthermore, in the patterned overlay layer, the AlN layer, the Al-Si-N miscible layer, and the SiN layer are cycled 2-6 times.

[0009] Furthermore, the thickness of the AlN layer is 5-15 nm; and / or, the thickness of the SiN layer is 2-10 nm.

[0010] Furthermore, the thickness of the top cover layer is 10-100 nm.

[0011] Furthermore, the epitaxial structure layer includes a nitride roughening layer and an undoped nitride layer stacked sequentially along a selected direction, wherein the nitride roughening layer covers the surface of the top capping layer, and the thickness of the nitride roughening layer is 100-500 nm.

[0012] Furthermore, the epitaxial structure layer further includes a first nitride layer, a nitride light-emitting layer, and a second nitride layer. The first nitride layer and the second nitride layer have opposite conductivity characteristics, and the first nitride layer, the nitride light-emitting layer, and the second nitride layer are stacked on the surface of the undoped nitride layer in the order of the selected direction.

[0013] Secondly, the present invention also provides a method for preparing an LED epitaxial wafer, comprising: Step ac is repeated on the substrate surface, with step a being performed once at the last time, to form a patterned structure layer: a. Perform the first N-stage thermal surface treatment at a temperature of 500-1000℃; b. Perform the first Al thermal surface treatment at a temperature of 500-1000℃; c. Annealing is performed at a temperature of 500-1000℃; After repeatedly executing step de on the surface of the graphic structure layer, step f is executed once to form a graphic overlay layer: d. Perform a second Al thermal surface treatment at a temperature of 500-1000℃; e. Perform Si hot surface treatment at a temperature of 500-1000℃; f. Perform a second N-stage thermal surface treatment; An epitaxial growth of AlN material is performed on the surface of the patterned cover layer to form a top cover layer; An epitaxial structure layer is formed by epitaxial growth on the surface of the top cover layer.

[0014] Furthermore, the pressure of the first N-heat surface treatment is less than the pressure of the second N-heat surface treatment.

[0015] Furthermore, the pressure of the first Al thermal surface treatment is less than the pressure of the second Al thermal surface treatment.

[0016] Furthermore, in step a, the time for the first N-thermal surface treatment is 5-40 seconds, and the pressure is 75-150 Torr.

[0017] Further, in step b, the first Al thermal surface treatment time is 10-60s, and the pressure is 100-300 Torr.

[0018] Furthermore, in step c, the annealing process takes 20-50 seconds and the pressure is 100-300 Torr.

[0019] Furthermore, in step d, the second Al thermal surface treatment time is 60-600s, and the pressure is 200-500 Torr.

[0020] Further, in step e, the Si thermal surface treatment time is 30-240s, and the pressure is 200-500 Torr.

[0021] Further, in step f, the second N-heat surface treatment time is 100-500s, the pressure is 200-500Torr, and the temperature is 1000-1090℃.

[0022] Furthermore, the temperature at which the top capping layer is grown is 1000-1090℃, and the thickness of the top capping layer is 10-100nm.

[0023] Furthermore, step ac is repeated 2-6 times.

[0024] Furthermore, the number of iterations for step de is 2-6.

[0025] Furthermore, prior to step a, the following is also included: The substrate is subjected to hydrogen surface heat treatment for 1-15 minutes at a temperature of 1050-1150℃ and a pressure of 100-300 Torr.

[0026] Further, the step of sequentially epitaxially growing an epitaxial structure layer on the surface of the top cover layer includes: A nitride roughening layer with a thickness of 100-500 nm is grown on the top cover layer at a temperature of 1000-1050℃. Under conditions of 900-1200℃, an undoped nitride layer with a thickness of 2-6 μm is formed on the nitride roughening layer; Under conditions of 900-1200℃, a doping concentration of 1×10⁻⁶ is grown on the undoped nitride layer. 18 -5×10 19 cm -3 The first nitride layer; A nitride luminescent layer is grown on the first nitride layer at a temperature of 650-950℃. Under conditions of 850-1050℃, a nitride light-emitting layer with a thickness of 50-300 nm and a doping concentration of 1×10⁻⁶ is grown on the nitride light-emitting layer. 19 -5×10 20 cm -3 The second nitride layer.

[0027] Thirdly, the present invention also provides a nitride semiconductor device comprising the above-described LED epitaxial wafer, or an LED epitaxial wafer prepared by the above-described method for preparing LED epitaxial wafers.

[0028] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention include at least the following: The technical solution provided by this invention utilizes a periodic cyclic process to alter the nucleation center distribution on the substrate surface through insufficient N-thermal surface treatment, forming a patterned structure with varying sizes and spacing. Combined with the incorporation of Si atoms in the patterned capping layer, compressive stress can be introduced at different heights in the longitudinal direction, allowing for gradual stress release. Furthermore, the mutual dissolution and diffusion between the AlN and SiN layers provides a lattice buffer during the cyclic process, preventing the increase in local defects in the epitaxial layer caused by stress abrupt changes. Simultaneously, the morphology of the size-differentiated distribution can be transferred to the nitride coarsening layer, forming coarsened microstructures of different sizes. The relaxation between grain boundaries effectively releases stress, strengthening the lateral epitaxy of the undoped nitride layer. This allows dislocations to fully turn and self-annihilate, preventing upward dislocation extension and significantly improving the crystal quality of at least the undoped nitride layer, providing a foundation for the fabrication of high-quality devices.

[0029] The above description is merely an overview of the technical solution of the present invention. In order to enable those skilled in the art to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described below in conjunction with detailed drawings. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the overall structure of an LED epitaxial wafer provided in a typical embodiment of the present invention; Figure 2 This is a schematic diagram of the specific structure of the nucleation buffer stack and nitride roughening layer in an LED epitaxial wafer provided in a typical embodiment of the present invention; Figure 3 This is a schematic diagram of the specific structure of the nucleation buffer stack in the LED epitaxial wafer provided in another typical embodiment of the present invention; Figure 4 These are the secondary ion mass spectrometry test results of the Al-Si-N miscible structure in the LED epitaxial wafer provided in Example 1; Figure 5 These are KOH molten alkali corrosion test images of the LED epitaxial wafer provided in Example 1; Figure 6 The image shows a KOH molten alkali corrosion test result of the LED epitaxial wafer provided in Comparative Example 1. Figure 7 The image shows the KOH molten alkali corrosion test result of the LED epitaxial wafer provided in Comparative Example 2; Figure 8 This is a KOH molten alkali corrosion test image of the LED epitaxial wafer provided in Comparative Example 3.

[0031] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Nucleation buffer stack; 3. Nitride roughening layer; 4. Undoped nitride layer; 5. n-type nitride layer; 6. Nitride luminescent layer; 7. p-type nitride layer; 21. Pattern structure layer; 22. Pattern cover layer; 221. AlN layer; 222. Al-Si-N miscible layer; 223. SiN layer; 23. Top cover layer. Detailed Implementation

[0032] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0033] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0034] Moreover, relational terms such as “first” and “second” are used merely to distinguish one component or method step from another that has the same name, and do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0035] This invention provides an LED epitaxial wafer, comprising a substrate, a nucleation buffer layer, and an epitaxial structure layer sequentially stacked along a selected direction; the nucleation buffer layer includes a patterned structure layer, a patterned cover layer, and a top cover layer sequentially stacked along the selected direction; the patterned structure layer includes multiple AlN patterned structures, and the height ratio of adjacent AlN patterned structures is between 1.2 and 3; the patterned cover layer is a contoured patterned cover layer, which includes a cyclically stacked AlN layer, an Al-Si-N mixed layer, and a SiN layer, wherein the Al-Si-N mixed layer is a film layer formed by mutual dissolution and diffusion between the AlN layer and the SiN layer; the top cover layer is made of AlN and completely covers the patterned cover layer.

[0036] In the above technical solution, AlN pattern structures of varying heights are first formed. The height difference between these AlN patterns allows for relaxation strain at polycrystalline interfaces during nitride growth, releasing stress. Simultaneously, the varying AlN heights enable the formation of more closed-loop dislocations at the top of the lower AlN islands during nitride growth, further facilitating stress release. Furthermore, the adjacent higher AlN islands enhance the lateral epitaxial growth of the nitride, improving the lateral epitaxial capability of the undoped nitride layer. This allows dislocations to fully turn and self-annihilate, preventing upward dislocation extension and ultimately improving the crystal quality of the undoped nitride layer.

[0037] The patterned capping layer formed between the AlN patterned structure and the top capping layer, featuring an AlN-SiN-AlN hybrid structure (i.e., cyclically stacked AlN layers, Al-Si-N mixed layers, and SiN layers), effectively releases stress through relaxation between grain boundaries in the hybrid structure. Furthermore, the Si atoms introduced by the AlN-SiN-AlN hybrid structure introduce compressive stress on the substrate surface. This avoids the cracking phenomenon caused by tensile stress in the patterned structure and buffer layer structure obtained through conventional epitaxial growth processes, and also prevents the increase in local defects in the epitaxial layer due to stress abrupt changes. In addition, the top capping layer avoids the phenomenon of uneven growth of the epitaxial structure layer caused by nucleation on the surface of the AlN-SiN-AlN hybrid structure.

[0038] In some implementations, the epitaxial structure layer includes a nitride roughening layer and an undoped nitride layer stacked sequentially along a selected direction. The nitride roughening layer covers the surface of the top capping layer, and the undoped nitride layer is epitaxially grown using the nitride roughening layer as a growth base.

[0039] Because the nitride roughening layer is grown on AlN patterned structures with varying spacing, it also forms roughening layer microstructures of different sizes. These microstructures can effectively release stress by utilizing relaxation between grain boundaries. Compared with traditional roughening processes, this further enhances the lateral epitaxy of the undoped nitride layer, allowing dislocations to fully turn and achieve self-annihilation, preventing dislocations from extending upwards and improving the crystal quality of the undoped nitride layer. Ultimately, this results in high-quality nitride roughening and undoped nitride layers.

[0040] In some implementations, the AlN pattern structure includes an adjacent first pattern structure and a second pattern structure, wherein the height of the first pattern structure is greater than that of the second pattern structure; the height of the first pattern structure is 100-500 nm, and the lateral diameter of the first pattern structure is 200-1000 nm.

[0041] In some implementations, the AlN and SiN layers in the pattern overlay are cycled 2-6 times.

[0042] In some implementations, the thickness of the AlN layer is 5-15 nm.

[0043] In some implementations, the thickness of the SiN layer is 2-10 nm.

[0044] In some implementations, the thickness of the top capping layer is 10-100 nm.

[0045] In some implementations, the thickness of the nitride roughening layer is 100-500 nm.

[0046] In some embodiments, the epitaxial structure layer further includes a first nitride layer, a nitride light-emitting layer, and a second nitride layer, the first nitride layer and the second nitride layer having opposite electrical conductivity characteristics, and the first nitride layer, the nitride light-emitting layer and the second nitride layer being stacked on the surface of the undoped nitride layer in a selected direction.

[0047] Correspondingly, a second aspect of the present invention also provides a method for preparing an LED epitaxial wafer, comprising the following steps: (1) Repeat step ac on the substrate surface and finally execute step a once to form a patterned structure layer: a. Perform N-type thermal surface treatment at a temperature of 500-1000℃.

[0048] b. Perform the first Al thermal surface treatment at a temperature of 500-1000℃.

[0049] c. Annealing is performed at a temperature of 500-1000℃.

[0050] (2) Repeat step de on the surface of the graphic structure layer, and then execute step f once to form a graphic overlay layer: d. Perform a second Al thermal surface treatment at a temperature of 500-1000℃.

[0051] e. Perform Si thermal surface treatment at a temperature of 500-1000℃.

[0052] f. Perform a second N-stage thermal surface treatment.

[0053] (3) Epitaxial growth of AlN material is performed on the surface of the patterned cover layer to form the top cover layer.

[0054] (4) An epitaxial structure layer is formed by epitaxial growth on the surface of the top cover layer.

[0055] In some implementations, in step a, the N-thermal surface treatment time is 5-40 seconds and the pressure is 75-150 Torr.

[0056] In some implementations, in step b, the first Al thermal surface treatment takes 10-60 seconds and is carried out at a pressure of 100-300 Torr.

[0057] In some implementations, in step c, the annealing process takes 20-50 seconds and is carried out at a pressure of 100-300 Torr.

[0058] In some implementations, in step d, the second Al thermal surface treatment takes 60-600 seconds and is carried out at a pressure of 200-500 Torr.

[0059] In some implementations, in step e, the Si thermal surface treatment time is 30-240 s and the pressure is 200-500 Torr.

[0060] In some implementations, in step f, the second N-type thermal surface treatment lasts for 100-500 seconds and the pressure is 200-500 Torr.

[0061] In the above technical solution, it is preferable to achieve better results by adjusting the gas pressure values ​​of different steps. Specifically, the first N-thermal surface treatment is performed at a relatively low pressure compared to the second N-thermal surface treatment, which can effectively improve the surface uniformity of the substrate that is not fully N-ized during the cycle (i.e., the surface energy between two adjacent pattern structures is different at the microscopic level, but the substrate surface is uniform at a larger scale), and improve the consistency of the substrate surface. The second N-thermal surface treatment is performed at a relatively high pressure compared to the first N-thermal surface treatment to ensure that the Al-Si-Al intersoluble diffusion structure is fully N-ized and avoid the formation of interstitial impurity atom distribution.

[0062] For example, the first Al thermal surface treatment is performed at a relatively low pressure compared to the second Al thermal surface treatment, which improves the migration ability of Al atoms on the substrate surface and can achieve higher surface distribution uniformity. On the other hand, the second Al thermal surface treatment is performed at a relatively high pressure compared to the first Al thermal surface treatment, which improves the adhesion ability of Al atoms on the patterned structure and can achieve a uniform Al atom layer distribution, thus promoting uniform coverage of the patterned overlay layer.

[0063] In some implementations, step ac is repeated 2-6 times; and / or step de is repeated 2-6 times.

[0064] In some embodiments, the above preparation method may further include the following step: subjecting the substrate to hydrogen surface heat treatment for 1-15 minutes at a temperature of 1050-1150°C and a pressure of 100-300 Torr.

[0065] For some typical examples of the above technical solutions, see Figures 1-3 As shown, the LED epitaxial wafer provided by the present invention includes a substrate 1, a nucleation buffer stack 2, a nitride roughening layer 3, an undoped nitride layer 4, an n-type nitride layer 5, a nitride light-emitting layer 6, and a p-type nitride layer 7. The nucleation buffer stack 2 includes a patterned structure layer 21, a patterned capping layer 22 (including a cyclically stacked AlN layer 221, an Al-Si-N mixed layer 222, and a SiN layer 223), and a top capping layer 23. The patterned structure layer 21 includes multiple AlN patterned structures of different sizes and spaced apart. The method for fabricating this LED epitaxial wafer includes the following steps: S1: Provide substrate 1.

[0066] Substrate 1 is used as a support for the film layer subsequently grown epitaxially.

[0067] S2: Growing a nucleation buffer stack 2 on substrate 1, including the following steps S21-S26: S21: Perform hydrogen surface heat treatment for 1-15 minutes at a temperature of 1050-1150℃.

[0068] This step is mainly used to remove impurities such as oxygen from the surface of substrate 1. It can be replaced by other various forms of substrate 1 surface cleaning treatment. This is only an exemplary implementation.

[0069] S22: Growth pattern structure layer 21, including: S221: Perform N-heat surface treatment for 5-40 seconds at a temperature of 500-1000℃.

[0070] Unlike traditional N-thermal surface treatment, this process incorporates periodic N-thermal surface treatment. A single N-thermal surface treatment of substrate 1 during the cycle is insufficient. The N-thermal surface treatment on the substrate 1 surface gradually accumulates during the cycle, resulting in different potential energy on the substrate 1 surface in each cycle. Step S222 forms an Al atom capping layer, and the annealing process in step S223 forms nucleation centers for Al atom distribution on the substrate 1 surface. After the initial treatment in the cycle, low-density Al atom nucleation centers can be formed on the substrate 1 surface. Al atoms will initially form low-density nucleation centers in specific regions. As the cycle progresses, the N-thermal surface treatment on the substrate 1 surface is strengthened to varying degrees during the cycle. Al atoms on the substrate 1 surface will form new Al atom nucleation centers in regions outside the nucleation centers of Al atoms that have already formed in the previous cycle. Thus, the positions of the Al nucleation centers on the substrate 1 surface are different during the cycle, resulting in a periodic interval distribution.

[0071] During the cycle, the Al atom capping layer formed by the N-thermal surface treatment in step S221 forms an AlN nucleation pattern structure with Al atoms as nucleation centers. During the periodic cycle, after the N-thermal surface treatment in step S221, the new AlN pattern structure will form a multi-AlN pattern structure distribution in the region between the multiple AlN pattern structures formed in the previous cycle, thereby forming multiple spaced AlN pattern structures on the surface of substrate 1. During the cycle, the Al atom capping layer covers the AlN pattern structure formed in the previous cycle. Finally, under the action of the N-thermal surface treatment, the pattern structure of the previous cycle is enlarged, and multiple spaced AlN pattern structures of different sizes are finally formed on the surface of substrate 1.

[0072] S222: Perform Al hot surface treatment for 10-60 seconds at a temperature of 500-1000℃.

[0073] An Al atom capping layer can be formed through step S222.

[0074] S223: Annealing at a temperature of 500-1000℃ for 20-50 seconds.

[0075] In step S223, the annealing process forms nucleation centers with Al atoms distributed on the surface of substrate 1. After the N-thermal surface treatment in step S221, a multi-AlN pattern structure distribution is formed. During the periodic cycle, after the N-thermal surface treatment in step S221, a multi-AlN pattern structure distribution is formed in the region between the multi-AlN pattern structures formed in the previous cycle. Finally, multiple spaced AlN pattern structures are formed on the surface of substrate 1.

[0076] S224: Repeat steps S221-S223 alternately 2-6 times.

[0077] S225: Perform N-heat surface treatment for 5-40 seconds at a temperature of 500-1000℃.

[0078] After step S225, AlN pattern structures with different heights are formed, resulting in different surface areas. Based on this, step S24 can utilize the different surface areas of the AlN pattern structures caused by the height difference to make the AlN-SiN-AlN mixed structure in the pattern cover layer 22 have different spatial distribution densities in the lateral and longitudinal directions, thereby effectively releasing the stress distribution in the nitride buffer layer.

[0079] The specific principle is as follows: This step forms AlN pattern structures of different heights. The height difference between the AlN pattern structures is used to release stress by relaxing the strain between polycrystalline interfaces during the growth of nucleation buffer stack 2. At the same time, the AlN pattern structures of different heights allow more closed-loop dislocations to form on the top of the lower AlN pattern structure during the growth of nucleation buffer stack 2, effectively releasing stress. Furthermore, the adjacent higher AlN pattern structures enhance the lateral epitaxial growth of nucleation buffer stack 2, further enhancing the lateral epitaxial growth of undoped nitride layer 4. This allows dislocations to fully turn and achieve self-annihilation, preventing dislocations from extending upwards and improving the crystal quality of undoped nitride layer 4, providing a high-quality foundation for the subsequent growth of functional layers.

[0080] S23: A patterned overlay layer 22 with a thickness of 20-200 nm is grown, including: S231: Perform Al hot surface treatment for 60-600s at a temperature of 500-1000℃.

[0081] S232: Perform Si hot surface treatment for 30-240s at a temperature of 500-1000℃.

[0082] S233: Repeat steps S231-S232 2-6 times.

[0083] S234: Perform N-heat surface treatment for 100-500s at a temperature of 1000-1090℃.

[0084] After N-thermal surface treatment, Al and Si are nitrided, transforming into AlN layer 221 and SiN layer 223 respectively. Furthermore, there is mutual diffusion between the multiple layers, forming an Al-Si-N miscible layer 222.

[0085] S24: The top capping layer 23 is grown at a temperature of 1000-1090℃.

[0086] A 10-100 nm thick AlN material layer is epitaxially grown using conventional processes as the top capping layer 23, for example, AlN material is epitaxially grown in the presence of Al and N sources.

[0087] By utilizing alternating cycles to form an Al-Si-Al intersoluble diffusion structure, and under the action of N thermal surface treatment, a patterned capping layer 22 with an AlN-SiN-AlN mixed structure is formed between the patterned structure layer 21 and the top capping layer 23. On the one hand, the relaxation between the grain boundaries of the mixed structure can effectively release stress; on the other hand, the AlN-SiN-AlN mixed structure introduces Si atoms to introduce compressive stress on the surface of the substrate 1, reducing the cracking phenomenon caused by the tensile stress of the epitaxial wafer. The setting of the top capping layer 23 avoids the phenomenon that the nitride coarsening layer 3 is difficult to grow uniformly due to the nucleation on the surface of the AlN-SiN-AlN mixed structure.

[0088] The AlN-SiN-AlN hybrid structure, from a microscopic perspective, is the Al-Si-N microstructure layer (i.e., Al-Si-N miscible layer 222) formed at the interface by the mutual diffusion of Al atomic layers and Si atomic layers during the second Al thermal surface treatment and Si thermal surface treatment, and the transition from the Al-Si-N microstructure layer to the AlN structure layer and SiN structure layer on both sides of the interface.

[0089] S3: A nitride roughening layer 3 with a thickness of 100-500 nm is grown on the top capping layer 23 at a temperature of 1000-1050℃.

[0090] The nitride roughening layer 3 formed in step S3 is distributed on the AlN pattern structure of different sizes. Therefore, the nitride roughening layer 3 will also form roughening layer microstructures of different sizes. This microstructure can effectively release stress by utilizing the relaxation between grain boundaries. Compared with the traditional roughening process, it further enhances the lateral epitaxy of the undoped nitride layer 4, allowing dislocations to turn fully and achieve self-annihilation, avoiding the upward extension of dislocations and improving the crystal quality of the undoped nitride layer 4.

[0091] Furthermore, since the growth process of the nitride roughening layer 3 is formed on AlN patterned structures with different spacings, it eliminates the need for thermal annealing of the nucleation centers on the substrate 1 surface before growth, unlike conventional roughening layer processes. Conventional thermal annealing suffers from temperature fluctuations, which can lead to significant variations in the distribution of nucleation centers and poor process repeatability. This invention utilizes AlN patterned structures with different spacings to grow the nitride roughening layer 3, eliminating the need for thermal annealing. This overcomes the aforementioned problems, ensures process stability, and improves product consistency and production yield.

[0092] S4: Under the condition of 900-1200℃, an undoped nitride layer 4 with a thickness of 2-6μm is formed on the nitride roughening layer 3.

[0093] S5: Under conditions of 900-1200℃, a doping concentration of 1×10⁻⁶ is grown on undoped nitride layer 4. 18 -5×10 19 cm -3 5. n-type nitride layer.

[0094] S6: Under conditions of 650-950℃, a nitride luminescent layer 6 is grown on the n-type nitride layer 5, including cyclically alternating steps S61-S62: S61: A nitride quantum well layer with a thickness of 0.5-5 nm is grown at a temperature of 650-850℃.

[0095] S62: A nitride quantum barrier layer with a thickness of 6-25 nm is grown on a nitride quantum well layer at a temperature of 700-950℃.

[0096] S7: Under conditions of 850-1050℃, a nitride emitting layer 6 with a thickness of 50-300 nm and a doping concentration of 1×10⁻⁶ is grown. 19 -5×10 20 cm -3 7. The p-type nitride layer.

[0097] It should be noted that steps S4-S7 above form the necessary components of the device structure exemplified in this invention. The growth process used can refer to existing conventional fabrication processes, but is not limited to them. The main inventive concept of this invention utilizes a high-quality nitride roughening layer 3 and an undoped nitride layer 4 for subsequent epitaxial growth. Even if other film layer structures are replaced, they should still fall within the scope of this invention.

[0098] In the above preparation method, by controlling the process conditions, the multiple AlN patterned structures can be made to have almost no gaps, completely covering the surface of substrate 1, such as... Figure 2 As shown, this method has the most significant effect on dislocation annihilation; of course, usually... Figure 3 As shown, there are gaps between multiple AlN pattern structures, exposing the surface of substrate 1 so that it has some contact with the pattern cover layer.

[0099] As an application of the technical solution of the present invention, a third aspect of the present invention also provides a nitride semiconductor device, which includes an LED epitaxial wafer provided or prepared by any of the above embodiments.

[0100] The technical solution of the present invention will be further described in detail below through several embodiments and in conjunction with the accompanying drawings. However, the selected embodiments are only for illustrating the present invention and do not limit the scope of the present invention.

[0101] Example 1 This embodiment uses MOCVD technology to fabricate LED epitaxial wafers on a 4-inch sapphire substrate, as detailed below: S1: Provides a sapphire growth substrate.

[0102] S2: Growing a nucleation buffer stack on the substrate, including the following steps: S21: Perform H2 heat treatment for 5 minutes at a temperature of 1085℃ and a pressure of 200 Torr.

[0103] S22: Growth pattern structure layer, including: S221: Under conditions of 650℃ and 110 Torr, NH3 is introduced for hot surface treatment for 15s.

[0104] S222: Under conditions of 650℃ and 200 Torr, TMAl is introduced for hot surface treatment for 30s.

[0105] S223: Stop the flow of TMA1 and perform annealing for 40 seconds at a temperature of 650°C and a pressure of 200 Torr.

[0106] S224: Repeat steps S221-S223 three times.

[0107] S225: Under conditions of 650℃ and 110 Torr, NH3 is introduced for heat treatment for 15s.

[0108] S23: Growth pattern overlay layer, including: S231: Under conditions of 950℃ and 350 Torr, TMAl is introduced for hot surface treatment for 200s.

[0109] S232: Under conditions of 950℃ and 350 Torr, SiH4 is introduced for hot surface treatment for 90s.

[0110] S233: Repeat steps S231-S232 three times.

[0111] S234: Heat treatment for 220s by introducing NH3 at a temperature of 1050℃ and a pressure of 350 Torr.

[0112] After this step, the obtained sample was tested using a secondary ion mass spectrometer, and the results are as follows: Figure 4As shown, the horizontal axis represents thickness, and the vertical axis represents concentration. From... Figure 4 It can be observed that Al and Si atoms diffuse between individual AlN and individual SiN layers, forming an Al-Si-N miscible structure.

[0113] S24: An AlN layer with a thickness of 50 nm is grown as the top capping layer.

[0114] S3: A nitride roughening layer with a thickness of 300 nm and made of GaN is grown on the top capping layer at a temperature of 1020℃.

[0115] S4: At a temperature of 1085℃, an undoped nitride layer with a thickness of 3μm and made of GaN is formed on the nitride roughening layer.

[0116] S5: Growing Si with a doping concentration of 5×10⁻⁶ on an undoped nitride layer at a temperature of 900-1200℃. 18 cm -3 The material is an n-type nitride layer of GaN.

[0117] S6: Repeat steps S61-S62 on the n-type nitride layer to obtain the nitride luminescent layer, including: S61: A quantum well layer with a thickness of 2.5 nm and made of InGaN is grown at a temperature of 750℃.

[0118] S62: A quantum barrier layer with a thickness of 12 nm and made of GaN is grown at a temperature of 850℃.

[0119] S7: At a temperature of 950℃, GaN with a thickness of 120nm and a doping concentration of 5×10⁻⁶ is grown on a nitride light-emitting layer. 19 cm -3 The p-type nitride layer.

[0120] At a temperature of 250℃, the surface of the LED epitaxial wafer was etched with KOH molten alkali for 1.5 minutes. The surface corrosion pits were tested using SEM, and the results were as follows: Figure 5 The test results are shown.

[0121] Comparative Example 1 This comparative example is largely the same as Example 1, with the main difference being that in step S22, instead of using a two-stage alternating thermal surface treatment method to grow the AlN patterned structure, a traditional epitaxial growth followed by annealing method is used to form the AlN patterned structure. The specific process conditions are as follows: S221: Under conditions of 560℃ and 500 torr, NH3 is introduced for hot surface treatment for 150s.

[0122] By executing S221, nitriding is achieved on the surface of the sapphire substrate.

[0123] S222: TMAl is introduced at a temperature of 560℃ and a pressure of 500 torr to form a low-temperature AlN layer with a thickness of 30nm.

[0124] S223: The low-temperature AlN layer is heat-treated for 120 seconds at a temperature of 1060℃ and a pressure of 200 torr.

[0125] The resulting AlN graphic structure does not exhibit a trend of highly differentiated distribution between adjacent structures, but rather tends to have an equal height distribution.

[0126] The surface of the LED epitaxial wafer was etched with KOH molten alkali for 1.5 min at 250℃, and the results were obtained by SEM testing. Figure 6 The test results shown indicate that, compared to Example 1, Comparative Example 1 has a higher density of corrosion pits, which suggests that the surface of the LED epitaxial wafer in Comparative Example 1 has a higher defect distribution.

[0127] Comparative Example 2 This comparative example is largely the same as Example 1, with the main difference being that step S23 is omitted and no graphic overlay layer is formed.

[0128] The surface of the LED epitaxial wafer was etched with KOH molten alkali for 1.5 minutes at 250℃, and the results were obtained by SEM testing. Figure 7 The test results shown indicate that, compared to Example 1, Comparative Example 2 has a higher density of corrosion pits, which suggests that the surface of the LED epitaxial wafer in Comparative Example 2 has a higher defect distribution.

[0129] Comparative Example 3 This comparative example is largely the same as Example 1, with the main difference being that step S232 is omitted and Si doping is not introduced into the patterned overlay layer.

[0130] The surface of the LED epitaxial wafer was etched with KOH molten alkali for 1.5 minutes at 250℃, and the results were obtained by SEM testing. Figure 8 The test results shown indicate that, compared to Example 1, Comparative Example 3 has a higher density of corrosion pits, which suggests that the surface of the LED epitaxial wafer in Comparative Example 3 has a higher defect distribution.

[0131] Example 2 This embodiment is largely the same as Embodiment 1, with the main difference being that the pressure in step S221 is adjusted to 350 Torr, the same as in step S235.

[0132] Example 3 This embodiment is largely the same as Embodiment 1, with the main difference being that the pressure in step S222 is adjusted to 350 Torr, the same as in step S231.

[0133] Example 4 This embodiment illustrates a process for preparing an LED epitaxial wafer, which is largely the same as in Embodiment 1, except that the process conditions in step S22 are different: S221: Under conditions of 550℃ and 120 Torr, NH3 is introduced for hot surface treatment for 15s.

[0134] S222: Under conditions of 515℃ and 275 Torr, TMAl is introduced for hot surface treatment for 55s.

[0135] S223: Stop the flow of TMA1 and perform annealing for 42 seconds at a temperature of 550°C and a pressure of 250 Torr.

[0136] The above process is repeated 5 times, eventually forming the following... Figure 3 The AlN patterned structure shown completely covers the patterned structure layer on the substrate surface. The difference from Example 1 is that the ratio of the flow rate of TMAl in step S222 to the flow rate of NH3 in step S221 is changed from 2.1 to 3.9.

[0137] Example 5 This embodiment is largely the same as Embodiment 1, with the main difference being the conditions for steps S1-S2: S1: Provides a sapphire growth substrate.

[0138] S2: Growing a nucleation buffer stack on the substrate, including the following steps: S21: Perform H2 heat treatment for 15 min at a temperature of 1050℃ and a pressure of 100 Torr.

[0139] S22: Growth pattern structure layer, including: S221: Under conditions of 500℃ and 150 Torr, NH3 is introduced for hot surface treatment for 40s.

[0140] S222: Under conditions of 1000℃ and 100 Torr, TMAl is introduced for hot surface treatment for 10s.

[0141] S223: Annealing is performed for 20 seconds at a temperature of 1000℃ and a pressure of 100 Torr.

[0142] S224: Repeat steps S221-S223 6 times.

[0143] S225: Under conditions of 500℃ and 150 Torr, NH3 is introduced for hot surface treatment for 40s.

[0144] S23: Growth pattern overlay layer, including: S231: Under conditions of 500℃, TMAl is introduced for hot surface treatment for 600s at a pressure of 200 Torr. S232: Under conditions of 500℃, SiH4 is introduced for hot surface treatment 240, and the pressure is 200 Torr; S233: Repeat steps S231-S232 twice.

[0145] S234: Heat treatment for 500s by introducing NH3 at a temperature of 1000℃ and a pressure of 200 Torr.

[0146] S24: An AlN layer with a thickness of 100 nm is grown as the top capping layer.

[0147] The remaining steps S3-S7 are consistent with those in Example 1, and will not be repeated here.

[0148] Example 6 This embodiment is largely the same as Embodiment 1, with the main difference being the conditions for steps S1-S2: S1: Provides a sapphire growth substrate.

[0149] S2: Growing a nucleation buffer stack on the substrate, including the following steps: S21: Perform H2 heat treatment for 1 min at a temperature of 1150℃ and a pressure of 300 Torr.

[0150] S22: Growth pattern structure layer, including: S221: Under conditions of 1000℃ and 75 Torr, NH3 is introduced for heat treatment for 5s.

[0151] S222: Under conditions of 500℃, TMAl is introduced for hot surface treatment for 60s at a pressure of 300 Torr. S223: Annealing at 500℃ for 50 seconds under a pressure of 300 Torr; S224: Repeat steps S221-S223 twice.

[0152] S225: Under conditions of 1000℃ and 75 Torr, NH3 is introduced for heat treatment for 5s.

[0153] S23: Growth pattern overlay layer, including: S231: Under conditions of 1000℃ and 500 Torr, TMAl is introduced for hot surface treatment for 60s.

[0154] S232: Under conditions of 1000℃, SiH4 is introduced for hot surface treatment for 30s at a pressure of 500 Torr. S233: Repeat steps S231-S232 6 times.

[0155] S234: Heat treatment for 100s by introducing NH3 at a temperature of 1100℃ and a pressure of 500 Torr.

[0156] S24: An AlN layer with a thickness of 10 nm is grown as the top capping layer.

[0157] The remaining steps S3-S7 are consistent with those in Example 1, and will not be repeated here.

[0158] Similar to Example 1, the above embodiments can achieve the fabrication of undoped nitride layers with low stress, low dislocation density, and high uniformity, providing a growth basis for the subsequent fabrication of high-performance devices.

[0159] The LED epitaxial wafers prepared in each embodiment and comparative example were tested, and the dislocation density, emission wavelength uniformity (WLD std), and luminous intensity (Lop) of the LED epitaxial wafers were obtained as shown below:

[0160] As can be seen in the table above, since the AlN pattern structure in Comparative Example 1 does not have a tendency for highly differentiated distribution between adjacent structures, but rather tends to be distributed at the same height, it is impossible for Si atoms in the patterned overlay layer to be incorporated at different heights in the longitudinal direction to introduce compressive stress, thus weakening the stress release effect. Furthermore, it is impossible to form a morphology with a differential size distribution, and the nitride coarsening layer cannot form coarsening microstructures of different sizes, reducing the lateral epitaxial effect of the heteronitride layer. This prevents dislocations from turning sufficiently to achieve self-annihilation, resulting in a high dislocation distribution in the nitride luminescent layer, leading to poor uniformity of emission wavelength and reduced luminescence intensity.

[0161] In Comparative Example 2, the absence of a patterned overlay layer also prevents the introduction of compressive stress at different heights in the longitudinal direction by incorporating Si atoms. Furthermore, it reduces the effect of the nitride roughening layer on the lateral epitaxial growth of the undoped nitride layer, resulting in a high dislocation distribution in the nitride emitting layer. This leads to poor uniformity of the emission wavelength and a decrease in luminescence intensity.

[0162] In Comparative Example 3, the stress-relieving effect brought about by the incorporation of Si atoms could not be utilized, resulting in a high dislocation distribution in the nitride luminescent layer, which led to poor uniformity of the emission wavelength and reduced luminescence intensity.

[0163] In Example 2, the increased nitriding pressure caused the formation of nucleation centers with relatively weak differential Al atom distribution on the substrate surface. This weakened the compressive stress introduced by the Si atoms in the patterned overlay layer at different heights in the longitudinal direction, thus reducing the stress release effect. Compared to Example 1, the patterned structure morphology formed has a lower degree of size differential distribution. At the same time, the surface uniformity of the device is also not as good as that of Example 1. Therefore, the device performance has decreased to a certain extent, but it is still significantly better than the other examples.

[0164] In Example 3, the reduced migration ability of Al atoms leads to a decrease in the uniformity of nucleation centers of Al atom distribution, resulting in a significant increase in the local dislocation density of the epitaxial layer. This leads to a high dislocation distribution in the nitride luminescent layer, resulting in a decrease in the uniformity of the emission wavelength and a reduction in the emission intensity compared to Example 1, but it is still significantly better than the other examples.

[0165] Based on the above embodiments and comparative examples, it is clear that the technical solution provided by the embodiments of the present invention, through a periodic cyclic process, utilizes insufficient N-thermal surface treatment to change the distribution of nucleation centers on the substrate surface, forming a patterned structure with different sizes of spaced distribution. Combined with the compressive stress introduced by Si doping in the patterned capping layer, the morphology of the size-differentiated distribution is transferred to the nitride coarsening layer to form coarsened microstructures of different sizes. The relaxation between grain boundaries can effectively release stress, strengthen the lateral epitaxy of the undoped nitride layer, and enable dislocations to fully turn and achieve self-annihilation, avoiding the upward extension of dislocations. This significantly improves the crystal quality of at least the undoped nitride layer, providing a foundation for the fabrication of high-quality devices.

[0166] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. An LED epitaxial wafer, characterized in that, It includes a substrate, a nucleation buffer stack, and an epitaxial structure layer stacked sequentially along a selected direction; The nucleation buffer stack includes a graphic structure layer, a graphic overlay layer, and a top overlay layer stacked sequentially along the selected direction; The graphic structure layer includes multiple AlN graphic structures, and the height ratio of adjacent AlN graphic structures is between 1.2 and 3. The patterned overlay layer conforms to the patterned structure layer, and the patterned overlay layer includes a cyclically stacked AlN layer, an Al-Si-N miscible layer, and a SiN layer; The top overlay layer is made of AlN and completely covers the graphic overlay layer.

2. The LED epitaxial wafer according to claim 1, characterized in that, The AlN graphic structure includes an adjacent first graphic structure and a second graphic structure, wherein the height of the first graphic structure is greater than that of the second graphic structure. The height of the first pattern structure is 100-500nm, and the lateral diameter of the first pattern structure is 200-1000nm.

3. The LED epitaxial wafer according to claim 1, characterized in that, In the patterned overlay layer, the AlN layer, the Al-Si-N miscible layer, and the SiN layer are cycled 2-6 times.

4. The LED epitaxial wafer according to claim 1 or 3, characterized in that, The thickness of the AlN layer is 5-15 nm; and / or, the thickness of the SiN layer is 2-10 nm; And / or, the thickness of the top cover layer is 10-100 nm; And / or, the epitaxial structure layer includes a nitride roughening layer and an undoped nitride layer stacked sequentially along a selected direction, the nitride roughening layer covering the surface of the top capping layer, and the thickness of the nitride roughening layer being 100-500 nm.

5. The LED epitaxial wafer according to claim 4, characterized in that, The epitaxial structure layer further includes a first nitride layer, a nitride light-emitting layer, and a second nitride layer. The first nitride layer and the second nitride layer have opposite conductivity characteristics, and the first nitride layer, the nitride light-emitting layer, and the second nitride layer are stacked on the surface of the undoped nitride layer in the selected direction.

6. A method for preparing an LED epitaxial wafer, characterized in that, include: Step ac is repeated on the substrate surface, with step a being performed once at the last time, to form a patterned structure layer: a. Perform the first N-stage thermal surface treatment at a temperature of 500-1000℃; b. Perform the first Al thermal surface treatment at a temperature of 500-1000℃; c. Annealing is performed at a temperature of 500-1000℃; After repeatedly executing step de on the surface of the graphic structure layer, step f is executed once to form a graphic overlay layer: d. Perform a second Al thermal surface treatment at a temperature of 500-1000℃; e. Perform Si hot surface treatment at a temperature of 500-1000℃; f. Perform a second N-stage thermal surface treatment; An epitaxial growth of AlN material is performed on the surface of the patterned cover layer to form a top cover layer; An epitaxial structure layer is formed by epitaxial growth on the surface of the top cover layer.

7. The preparation method according to claim 6, characterized in that, The pressure of the first N-type thermal surface treatment is less than the pressure of the second N-type thermal surface treatment; And / or, the pressure of the first Al thermal surface treatment is less than the pressure of the second Al thermal surface treatment.

8. The preparation method according to claim 6 or 7, characterized in that, In step a, the first N hot surface treatment time is 5-40s and the pressure is 75-150 Torr; and / or, in step b, the first Al hot surface treatment time is 10-60s and the pressure is 100-300 Torr; and / or, in step c, the annealing treatment time is 20-50s and the pressure is 100-300 Torr. And / or, in step d, the second Al thermal surface treatment time is 60-600s, and the pressure is 200-500Torr; and / or, in step e, the Si thermal surface treatment time is 30-240s, and the pressure is 200-500Torr; and / or, in step f, the second N thermal surface treatment time is 100-500s, the pressure is 200-500Torr, and the temperature is 1000-1090℃; And / or, the temperature at which the top capping layer is grown is 1000-1090°C, and the thickness of the top capping layer is 10-100 nm; And / or, step ac is repeated 2-6 times; And / or, the number of iterations for step de is 2-6.

9. The preparation method according to claim 6, characterized in that, Step a includes the following: The substrate is subjected to hydrogen surface heat treatment for 1-15 minutes at a temperature of 1050-1150℃ and a pressure of 100-300 Torr. And / or, the epitaxial structure layer formed sequentially on the surface of the top cover layer includes: A nitride roughening layer with a thickness of 100-500 nm is grown on the top cover layer at a temperature of 1000-1050℃. Under conditions of 900-1200℃, an undoped nitride layer with a thickness of 2-6 μm is formed on the nitride roughening layer; Under conditions of 900-1200℃, a doping concentration of 1×10⁻⁶ is grown on the undoped nitride layer. 18 -5×10 19 cm -3 The first nitride layer; A nitride luminescent layer is grown on the first nitride layer at a temperature of 650-950℃. Under conditions of 850-1050℃, a nitride light-emitting layer with a thickness of 50-300 nm and a doping concentration of 1×10⁻⁶ is grown on the nitride light-emitting layer. 19 -5×10 20 cm -3 The second nitride layer.

10. A nitride semiconductor device, characterized in that, Includes the LED epitaxial wafer as described in any one of claims 1-5, or an LED epitaxial wafer prepared by the method for preparing an LED epitaxial wafer as described in any one of claims 6-9.

Images