Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the forming method comprises the steps: providing a first wafer, the first wafer comprises a substrate and wiring structures located on the substrate, grooves are formed between the wiring structures, and the surfaces of the sides, away from the substrate, of the wiring structures and the surfaces of the inner walls of the grooves are provided with first protection layers; forming a first dielectric layer on the surface of one side, deviating from the substrate, of the first protective layer; first etching processing is carried out on the first dielectric layer until the first protective layer is exposed, a first recess is formed, and an opening, away from one side of the substrate, of the first recess has a first size; second etching processing is carried out on the first recess to form a second recess, an opening of one side, away from the substrate, of the second recess has a second size, and the second size is larger than the first size; and forming a second dielectric layer in the second recess and on the surface of one side, deviating from the wiring structure, of the first dielectric layer. The method can effectively inhibit the generation of holes in the formation process of the semiconductor structure, and improves the reliability of the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit technology, in order to meet the requirements of high performance, miniaturization and high integration, more and more devices are adopting three-dimensional integration or advanced packaging to achieve system integration. Typically, the wafer is first manufactured in a two-dimensional wafer fabrication plant (2D FAB) to complete the manufacturing of transistors and metal interconnect structures, and then enters a three-dimensional integration fabrication plant (3D FAB) as incoming wafers for subsequent processes such as three-dimensional stacking, packaging or interconnection.

[0003] In actual process flows, before implementing 3D stacking, packaging, or interconnect processes, a redistribution layer (RDL) is typically built on the wafer surface after the completion of 2D circuitry and metal wiring structures. This redistributes electrical signals and meets subsequent interconnect requirements. Since the redistribution layer usually uses thicker metal wiring to improve current carrying capacity and interconnect reliability, trench structures with significant depth and width variations inevitably form between the metal wiring. To meet the requirements of wafer surface flatness and structural integrity for subsequent 3D stacking, packaging, or interconnect processes, these trench structures need to be filled with dielectric material and planarized, thereby forming a continuous and flat interface for subsequent processes after the redistribution layer.

[0004] In the prior art, chemical vapor deposition (CVD) is commonly used for dielectric filling and planarization of the aforementioned trench structures. While this process has advantages such as low cost and mature technology, it is prone to forming voids within the dielectric layer during the deposition process when dealing with trench structures with significant depth and width variations. This can affect the stability of subsequent processes and the reliability of the semiconductor structure. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the same, which effectively suppresses the generation of voids during the semiconductor structure formation process and improves the reliability of the semiconductor structure.

[0006] To achieve the above objectives, according to a first aspect of this application, a method for forming a semiconductor structure is provided, comprising: A first wafer is provided, the first wafer including a substrate and wiring structures located on the substrate, trenches being formed between the wiring structures, and a first protective layer being provided on a side surface of the wiring structures facing away from the substrate and on the inner wall surface of the trenches. A first dielectric layer is formed on the side of the first protective layer facing away from the substrate; The first dielectric layer is etched until the first protective layer is exposed, and a first recess is formed in the first dielectric layer on the trench, wherein the opening of the first recess on the side opposite to the substrate has a first size. The first recess is subjected to a second etching process to form a second recess in the first dielectric layer on the trench. The opening of the second recess on the side opposite to the substrate has a second size, which is larger than the first size. A second dielectric layer is formed within the second recess and on the side of the first dielectric layer facing away from the wiring structure.

[0007] Optionally, the first etching process includes a dry etching process.

[0008] Optionally, the second etching process includes a wet etching process. Optionally, the material of the first dielectric layer includes silicon oxide, and the wet etching process uses diluted hydrofluoric acid for etching.

[0009] Optionally, the forming method further includes: After the second depression is formed and before the second dielectric layer is formed, the first dielectric layer and the second depression are cleaned to remove the residues generated by the wet etching.

[0010] Optionally, the cleaning process includes ultrasonic cavitation treatment and / or brush cleaning treatment.

[0011] Optionally, in a direction parallel to the substrate surface, the dimension between the inner sidewalls of the second recess tends to increase in the direction away from the substrate.

[0012] Optionally, the wiring structure includes: A first wiring group is formed on the substrate, comprising a plurality of first wirings; The second wiring group is formed on the side of the first wiring group away from the substrate and includes a plurality of second wirings, each of the second wirings being in contact with one of the first wirings. The size of the second wirings is larger than the size of the corresponding first wirings in both the direction parallel to the substrate surface and the direction perpendicular to the substrate surface.

[0013] Optionally, in a direction perpendicular to the substrate surface, the first dielectric layer has a third dimension between the side surface of the first wiring group away from the second wiring group and the side surface of the second wiring group facing the substrate, and the second wiring group has a fourth dimension between the side surface of the second wiring group away from the substrate and the side surface of the second wiring group facing the substrate, wherein the third dimension is not less than twice the fourth dimension.

[0014] Optionally, it further includes: performing a second planarization process on the second dielectric layer to form a third dielectric layer on the surface of the wiring structure facing away from the substrate.

[0015] According to a second aspect of this application, a semiconductor structure is provided, formed according to the semiconductor structure formation method described in any one of the preceding claims.

[0016] In this application, during the first etching process of the first dielectric layer, a first protective layer is used as a stop etching layer. This exposes and connects the gap space that might otherwise be sealed by the first dielectric layer and located inside the trench to the outside, thereby forming a first recess in the first dielectric layer on the trench. Based on this, a second etching process is further performed on the first recess to expand it into a second recess with a larger opening size, thereby reducing the aspect ratio of the second recess and improving the entry conditions for the dielectric material. Through this technical solution, when the second dielectric layer is subsequently formed in the second recess, the dielectric material can more fully enter the bottom of the second recess and achieve continuous and dense filling. This avoids the formation of voids inside the second dielectric layer due to the premature closure of the opening on the side of the second recess away from the substrate or the sidewalls of the second recess, thus improving the structural integrity of the subsequent process interface, the stability of the subsequent process, and the reliability of the semiconductor structure.

[0017] Meanwhile, since the first etching process has a clear etching stop interface, and the second etching process increases the process tolerance to different trench morphologies by expanding the opening size, this application can adapt to redistribution layer structures with different trench depths and linewidth distributions without relying on multiple filling and planarization cycles, thereby improving the versatility and applicability of semiconductor structure formation processes and helping to reduce process complexity and manufacturing costs.

[0018] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0020] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application; Figures 2 to 7A cross-sectional view of the semiconductor structure provided in the embodiments of this application during its formation process.

[0021] Explanation of reference numerals in the attached figures: 10. First wafer; 101. Substrate; 102. Wiring structure; 1021. First wiring group; 10211. First wiring; 1022. Second wiring group; 10221. Second wiring; 103. Trench; 104. First protective layer; 105. First insulating layer; 106. Second protective layer; 107. Second insulating layer; 108. Third protective layer; 109. Third insulating layer; 110. Conductive structure; 20. First dielectric layer; 201. Gap; 30. First depression; 40. Second depression; 50. Second dielectric layer; 60. Third dielectric layer. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0023] As described in the background art, in the semiconductor formation process, before performing three-dimensional stacking, packaging or interconnection processes on the wafer, it is usually necessary to build a redistribution layer (RDL) on the wafer surface after completing the two-dimensional circuit and metal wiring structure, so as to redistribute electrical signals and meet the subsequent interconnection requirements.

[0024] Because redistribution layers typically employ thicker metal traces to improve current carrying capacity and interconnect reliability, trench structures with significant depth and width variations inevitably form between these metal traces. To meet the requirements of subsequent 3D stacking, packaging, or interconnect processes for wafer surface flatness and structural integrity, these trench structures need to be dielectric-filled and planarized to create a continuous and flat interface for subsequent processes after the redistribution layer.

[0025] In some embodiments, chemical vapor deposition (CVD) is used to fill the trench structure with dielectric material. Since CVD is a surface reaction-driven deposition method, in trench structures with significant depth and width variations, the dielectric material tends to preferentially grow and prematurely seal in the upper and sidewall regions of the trench. However, the deposition rate is lower at the bottom of the trench due to limited reactant transport, resulting in unfilled sealed spaces within the trench. This ultimately leads to voids in the dielectric layer, affecting the stability of subsequent processes and the reliability of the semiconductor structure.

[0026] The voids left over from the filling and planarization process can lead to uneven stress distribution on the wafer, which can cause wafer warping or local structural failure, affecting the stability of subsequent 3D stacking and packaging processes and the long-term reliability of semiconductor structures.

[0027] To effectively suppress void formation during semiconductor structure formation and improve the stability of subsequent 3D stacking and packaging processes, as well as the long-term reliability of the semiconductor structure, a compensation process of alternating dielectric filling and chemical mechanical polishing is employed in some embodiments. However, due to significant differences in the trench depth, linewidth distribution, and morphology of redistribution layers across different wafers, the above method often requires repeated adjustments to the number of filling and polishing cycles and process parameters based on specific structural characteristics. This makes it difficult to form a standardized, reusable, and unified process flow, resulting in poor applicability. Furthermore, multiple cycles significantly increase the number of processes and material consumption, thereby increasing process complexity and manufacturing costs.

[0028] Therefore, in order to effectively suppress the generation of voids during semiconductor structure formation and improve the stability of subsequent three-dimensional stacking and packaging processes, as well as the long-term reliability of the semiconductor structure, this application discloses a method for forming a semiconductor structure.

[0029] Reference Figure 1 , Figure 1 A schematic flowchart of a method for forming a semiconductor structure provided in this application embodiment includes: Step S100: A first wafer is provided. The first wafer includes a substrate and wiring structures located on the substrate. Trenches are formed between the wiring structures. A first protective layer is provided on the side surface of the wiring structures facing away from the substrate and on the inner wall surface of the trenches. Step S200: A first dielectric layer is formed on the side of the first protective layer facing away from the substrate; Step S300: Perform a first etching process on the first dielectric layer until the first protective layer is exposed, and form a first recess in the first dielectric layer on the trench. The opening of the first recess on the side away from the substrate has a first size. Step S400: Perform a second etching process on the first recess to form a second recess in the first dielectric layer on the trench. The opening of the second recess on the side away from the substrate has a second size, which is larger than the first size. In step S500, a second dielectric layer is formed in the second recess and on the side of the first dielectric layer facing away from the wiring structure.

[0030] In this embodiment, during the first etching process of the first dielectric layer, a first protective layer is used as a stop etching layer. This exposes gaps that might otherwise be sealed by the first dielectric layer and located inside the trench, allowing them to communicate with the outside, thereby forming a first recess in the first dielectric layer on the trench. Based on this, a second etching process is further performed on the first recess to expand it into a second recess with a larger opening size, thereby reducing the aspect ratio of the second recess and improving the entry conditions for the dielectric material. Through this technical solution, when the second dielectric layer is subsequently formed within the second recess, the dielectric material can more fully enter the bottom of the second recess and achieve continuous and dense filling. This avoids the formation of voids inside the second dielectric layer due to premature closure of the opening on the side of the second recess away from the substrate or the sidewalls of the second recess, improving the stability of subsequent three-dimensional stacking and packaging processes and the long-term reliability of the semiconductor structure.

[0031] Meanwhile, since the first etching process has a clear etching stop interface, and the second etching process increases the process tolerance to different trench morphologies by expanding the opening size, the embodiments of this application can adapt to redistribution layer structures with different trench depths and linewidth distributions without relying on multiple filling and planarization cycles, thereby improving the versatility and applicability of semiconductor structure formation processes and helping to reduce process complexity and manufacturing costs.

[0032] refer to Figures 2 to 7 , Figures 2 to 7 This is a cross-sectional view of the semiconductor structure provided in the embodiment of this application during its formation process. The following will be combined with… Figure 1 and Figures 2 to 7 The formation process of the semiconductor structure provided in the embodiments of this application is described in detail.

[0033] Reference Figure 2 In this embodiment of the application, step S100 provides a first wafer 10, the first wafer 10 includes a substrate 101 and wiring structures 102 located on the substrate 101, trenches 103 are formed between the wiring structures 102, and a first protective layer 104 is provided on the side surface of the wiring structure 102 facing away from the substrate 101 and the inner wall surface of the trench 103.

[0034] In some embodiments, the wiring structure 102 includes a first wiring group 1021 and a second wiring group 1022. The first wiring group 1021 is formed on a substrate 101, and the second wiring group 1022 is formed on the side of the first wiring group 1021 facing away from the substrate 101. The first wiring group 1021 includes a plurality of first wirings 10211, and the second wiring group 1022 includes a plurality of second wirings 10221. Each second wiring 10221 is in contact with a first wiring 10211. The size of the second wiring 10221 is larger than the size of the corresponding first wiring 10211 in both directions parallel to the surface of the substrate 101 and directions perpendicular to the surface of the substrate 101.

[0035] The first wiring group 1021 is a metal interconnect structure completed in a two-dimensional wafer fabrication plant (2D FAB), and the second wiring group 1022 is a redistribution layer formed on the side of the metal interconnect structure away from the substrate 101.

[0036] In some embodiments, a first insulating layer 105 and a second protective layer 106 are sequentially formed between the first wiring group 1021 and the substrate 101. A second insulating layer 107 is formed to fill the spaces between adjacent first wiring groups 10211. A third protective layer 108 is formed on the surface of the first wiring group 10211 and the second insulating layer 107 facing away from the substrate 101. A third insulating layer 109 is formed on the surface of the third insulating layer 108 facing away from the substrate 101, and the second wiring group 1022 is formed on the surface of the third insulating layer 109 facing away from the substrate 101. Further, a conductive structure 110 is formed in the third insulating layer 109. The conductive structure 110 penetrates the third insulating layer 109 and is electrically connected to the first wiring group 10211 and the second wiring group 10221, respectively, to realize the electrical connection between the corresponding first wiring group 10211 and the second wiring group 10221.

[0037] In some embodiments, the first insulating layer 105, the second insulating layer 107, and the third insulating layer 109 are made of silicon oxide, and the first protective layer 104, the second protective layer 106, and the third protective layer 108 are made of silicon nitride. The first wiring 10211 is made of copper, the second wiring 10221 is made of aluminum, and the conductive structure 110 is made of aluminum.

[0038] In some embodiments, the conductive structure 110 can be formed by first patterning the third insulating layer 109 to form a conductive via, and then filling the conductive via with conductive material to form the conductive structure 110.

[0039] In some embodiments, the incoming wafers entering the 3D FAB have a first wiring group 1021 and a second wiring group 1022 pre-formed on them, and the side of the second wiring group 1022 facing away from the substrate 101 is covered with a first protective layer 104. The first wiring group 10211 and the second wiring group 10221 are electrically connected through a conductive structure 110. In this embodiment, the incoming wafer directly serves as the first wafer 10 for performing subsequent semiconductor structure formation processes.

[0040] Reference Figure 3 In this embodiment of the application, step S200 forms a first dielectric layer 20 on the side surface of the first protective layer 104 facing away from the substrate 101.

[0041] Since the second wiring 10221 in the second wiring structure 102 typically has a large thickness and the spacing between adjacent second wiring 10221 varies, some trenches 103 formed between adjacent second wiring 10221 may exhibit a high aspect ratio in local areas. In step S200, when the first dielectric layer 20 is formed on the first protective layer 104 located on the inner surface of the trench 103, due to the deposition mechanism, the dielectric material preferentially grows in the opening region and the sidewall region of the trench 103 on the side away from the substrate 101. As deposition continues, the dielectric layer in the opening region and the sidewall region gradually thickens and may close prematurely, causing local shrinkage or closure inside the trench 103. At the same time, due to the high aspect ratio of the trench 103, the diffusion and transport of reactants to the bottom of the trench 103 are restricted, resulting in a lower effective reactant concentration and a relatively smaller deposition rate at the bottom of the trench 103, making it difficult for the bottom of the trench 103 to be fully filled by the dielectric material before the opening closes. Therefore, the first dielectric layer 20 may have unfilled space in the area corresponding to the trench 103, forming gap 201.

[0042] In some embodiments, the first dielectric layer 20 is formed by a chemical vapor deposition (CVD) process, such as any one or a combination of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or high-density plasma-enhanced chemical vapor deposition (HDP-CVD). In some embodiments, the material of the first dielectric layer 20 includes silicon oxide (SiO2).

[0043] Furthermore, in some embodiments, in a first direction, the first dielectric layer 20 has a third dimension between the surface of the first wiring group 1022 facing away from the second wiring group 1022 and the surface of the second wiring group 1022 facing the substrate 101, and a fourth dimension between the surface of the second wiring group 1022 facing away from the substrate 101 and the surface of the second wiring group 1022 facing the substrate 101. The third dimension is not less than twice the fourth dimension. In other words, the thickness of the first dielectric layer 20 is not less than twice the thickness of the second wiring group 1022. The first direction is a direction perpendicular to the surface of the substrate 101.

[0044] With this configuration, when a relatively high aspect ratio trench 103 is formed between adjacent second wirings 10221, the thickness of the first dielectric layer 20 is not less than twice the thickness of the second wirings 10221, which is beneficial for forming a continuous and stable first dielectric layer 20 within the trench 103.

[0045] Reference Figure 4 In this embodiment of the application, step S300 performs a first etching process on the first dielectric layer 20 until the first protective layer 104 is exposed, and a first recess 30 is formed in the first dielectric layer 20 on the trench 103. The opening of the first recess 30 on the side opposite to the substrate 101 has a first size.

[0046] In some embodiments, the first etching process includes a dry etching process.

[0047] Dry etching has good etching directionality and controllability of etching endpoint. It can use the first protective layer 104 as the etching stop layer to etch the first dielectric layer 20 until the first protective layer 104 is exposed, thereby avoiding damage to the internal structure of the trench 103 or affecting the consistency of etching size due to lateral etching or over-etching.

[0048] Reference Figure 5 In this embodiment of the application, step S400 performs a second etching process on the first recess 30 to form a second recess 40 in the first dielectric layer 20 on the trench 103. The opening of the second recess 40 on the side away from the substrate 101 has a second size, which is larger than the first size.

[0049] During the aforementioned dry etching process, the etching reaction is primarily controlled by the ion bombardment direction in a plasma environment. The etching rate in the direction perpendicular to the substrate 101 plane is significantly higher than that in the direction parallel to the substrate 101 plane. This effectively suppresses the etching of the inner wall of the first recess 30. Therefore, the first recess 30 formed after the first etching process has a high inner wall verticality, and its inner wall morphology is relatively straight. Under these morphological conditions, if the dielectric material is directly filled into the first recess 30 to form the second dielectric layer 50, the dielectric material tends to preferentially grow on the side of the first recess 30 away from the substrate 101 or along with the inner wall of the first recess 30, resulting in premature sealing and thus forming an unfilled gap 201 again. Therefore, before forming the second dielectric layer 50, this embodiment of the application performs a second etching process on the first recess 30 to enlarge the opening size of the side of the first recess 30 facing away from the substrate 101, expanding it from the first recess 30 into the second recess 40. This reduces the aspect ratio of the second recess 40 and improves the transport conditions of the dielectric material. By increasing the opening size of the second recess 40, the dielectric material can more smoothly enter the bottom of the second recess 40 during subsequent deposition, which is beneficial for achieving continuous and dense dielectric filling, avoiding or suppressing the generation of voids, and improving the structural integrity and process stability of subsequent process interfaces.

[0050] In some embodiments, the second etching process includes a wet etching process. Because the wet etching process has isotropic etching characteristics, it can simultaneously etch the bottom wall of the first recess 30 and laterally etch the inner sidewall of the first recess 30 (lateral direction in this embodiment is parallel to the surface of the substrate 101), thereby effectively increasing the size of the opening on the side of the first recess 30 facing away from the substrate 101, thus reducing the aspect ratio of the formed second recess 40. Through the above etching method, the geometry of the second recess 40 is more conducive to the subsequent entry of dielectric material into the bottom of the second recess 40 and continuous filling, thereby reducing the risk of voids caused by premature closure of the opening on the side of the second recess 40 facing away from the substrate 101.

[0051] In some embodiments, after wet etching is performed on the first recess 30 to form the second recess 40, the dimension between the inner sidewalls of the second recess 40 tends to increase in the direction away from the substrate 101 in the direction parallel to the surface of the substrate 101. In other words, because wet etching simultaneously produces etching effects parallel to and perpendicular to the substrate 101 on the inner surface of the first recess 30, the inner sidewalls of the formed second recess 40 recede outward during the etching process, thereby gradually increasing the spacing between the inner sidewalls of the second recess 40 in the direction away from the substrate 101 in the direction parallel to the surface of the substrate 101. As a result, the second recess 40 exhibits a flared profile with a larger opening on the side away from the substrate 101 and a relatively narrower opening on the side closer to the substrate 101. By forming the above-mentioned flared profile structure, the aspect ratio of the second recess 40 can be reduced, making it easier for the subsequent dielectric material to enter the bottom region of the second recess 40 during the deposition process. This reduces the possibility that the dielectric material will prematurely close on the side of the second recess 40 away from the substrate 101, thereby facilitating continuous and dense filling of the second recess 40 and reducing the risk of void formation.

[0052] In some embodiments, the first dielectric layer 20 is made of silicon oxide, and the wet etching process uses diluted hydrofluoric acid for etching.

[0053] Diluted hydrofluoric acid has high etching selectivity for silicon oxide materials and the etching process has isotropic characteristics. Therefore, while etching the bottom wall of the first recess 30, it can produce a uniform etching effect on the side wall of the first recess 30, thereby effectively increasing the opening size of the side of the first recess 30 away from the substrate 101, so that the formed second recess 40 has a widened profile and reduces the aspect ratio of the second recess 40.

[0054] In addition, using diluted hydrofluoric acid as the etching medium can avoid morphology loss caused by over-etching and reduce etching or damage to adjacent metal wiring and other non-silicon oxide material layers, thereby improving the process stability and repeatability of the etching process.

[0055] Continue to refer to Figure 5 In some embodiments, after the second recess 40 is formed in step S400 and before the second dielectric layer 50 is formed in step S500, the semiconductor formation method further includes cleaning the first dielectric layer 20 and the second recess 40 to remove any residues generated by wet etching.

[0056] During wet etching, byproducts generated by the etching reaction and unreacted etching solution components may remain in the second recess 40. If these residues are not removed in time, they may affect the continuity of subsequent deposition of the second dielectric layer 50, or even form defects in the second recess 40.

[0057] In some embodiments, the cleaning process includes ultrasonic cleaning and brushing cleaning, which can be carried out individually or in combination.

[0058] Ultrasonic cleaning involves immersing the wafer in a cleaning solution and applying ultrasonic energy to the solution, creating a cavitation effect. This generates micro-impact forces on the surface of the first dielectric layer 20 and within the second recess 40, effectively peeling off and removing residues adhering to the inner wall of the second recess 40 and the surface of the first dielectric layer 20. Because the cavitation effect generated by the ultrasound can penetrate into the interior of the second recess 40, this ultrasonic cleaning process is beneficial for removing residues located at the bottom of the second recess 40, reducing the risk of discontinuities or defects in subsequent dielectric filling caused by residues.

[0059] The brushing cleaning process involves rotating a brush body to contact the surface of the first media layer 20 and the inner surface of the second recess 40, and using a cleaning solution to mechanically brush the surfaces of the first media layer 20 and the second recess 40 to remove residues adhering to them. This brushing cleaning process improves the removal efficiency of large particulate contaminants on the surfaces of the first media layer 20 and the second recess 40.

[0060] Reference Figure 6 In some embodiments, in step S500, a second dielectric layer 50 is formed in the second recess 40 and on the side surface of the first dielectric layer 20 opposite to the wiring structure 102.

[0061] In some embodiments, the second dielectric layer 50 and the first dielectric layer 20 are made of the same material to improve the compatibility of the interface between the first dielectric layer 20 and the second dielectric layer 50 and reduce the stress or adhesion risks introduced by the interface of different materials. Exemplarily, the material of the second dielectric layer 50 includes silicon oxide. In some embodiments, the second dielectric layer 50 is formed using a chemical vapor deposition process, such as any one or a combination of plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or high-density plasma-enhanced chemical vapor deposition (HDP-CVD), to achieve continuous filling of the second recess 40 and coverage of the surface of the first dielectric layer 20.

[0062] Reference Figure 7 In some embodiments, after the second dielectric layer 50 is formed in step S500, the semiconductor formation method further includes: performing a second planarization process on the second dielectric layer 50 to remove the excessively thick portion of the second dielectric layer 50 on the side of the wiring structure 102 away from the substrate 101 and obtain a flat surface to form a third dielectric layer 60 on the side of the wiring structure 102 away from the substrate 101.

[0063] The second planarization process can be chemical mechanical polishing or other planarization processes. This second planarization process ensures that the surface flatness of the formed third dielectric layer 60 meets the interface continuity and flatness requirements of subsequent interconnect, stacking, or packaging processes, further improving the stability of subsequent processes and the reliability of the semiconductor structure.

[0064] Reference Figure 7 This application also discloses a semiconductor structure formed according to any of the foregoing semiconductor structure formation methods.

[0065] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0066] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0067] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0068] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A first wafer is provided, the first wafer including a substrate and wiring structures located on the substrate, trenches being formed between the wiring structures, and a first protective layer being provided on a side surface of the wiring structures facing away from the substrate and on the inner wall surface of the trenches. A first dielectric layer is formed on the side of the first protective layer facing away from the substrate; The first dielectric layer is etched until the first protective layer is exposed, and a first recess is formed in the first dielectric layer on the trench, wherein the opening of the first recess on the side opposite to the substrate has a first size. The first recess is subjected to a second etching process to form a second recess in the first dielectric layer on the trench. The opening of the second recess on the side opposite to the substrate has a second size, which is larger than the first size. A second dielectric layer is formed within the second recess and on the side of the first dielectric layer facing away from the wiring structure.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first etching process includes a dry etching process.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The second etching process includes a wet etching process.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The first dielectric layer is made of silicon oxide, and the wet etching process uses diluted hydrofluoric acid for etching.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, The forming method further includes: After the second depression is formed and before the second dielectric layer is formed, the first dielectric layer and the second depression are cleaned to remove the residues generated by the wet etching.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The cleaning process includes ultrasonic cavitation treatment and / or brush cleaning treatment.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, In a direction parallel to the substrate surface, the dimension between the inner sidewalls of the second recess tends to increase in the direction away from the substrate.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The wiring structure includes: A first wiring group is formed on the substrate, comprising a plurality of first wirings; The second wiring group is formed on the side of the first wiring group away from the substrate and includes a plurality of second wirings, each of the second wirings being in contact with one of the first wirings. The size of the second wirings is larger than the size of the corresponding first wirings in both the direction parallel to the substrate surface and the direction perpendicular to the substrate surface.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, In a direction perpendicular to the substrate surface, the first dielectric layer has a third dimension between the side surface of the first wiring group away from the second wiring group and the side surface of the second wiring group facing the substrate, and the second wiring group has a fourth dimension between the side surface of the second wiring group away from the substrate and the side surface of the second wiring group facing the substrate, wherein the third dimension is not less than twice the fourth dimension.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: The second dielectric layer is subjected to a second planarization process to form a third dielectric layer on the surface of the wiring structure facing away from the substrate.

11. A semiconductor structure, characterized in that, The semiconductor structure is formed according to any one of claims 1 to 10.

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