Preparation method of chip packaging heat dissipation structure

Abstract

The invention relates to the technical field of chip packaging, in particular to a preparation method of a chip packaging heat dissipation structure, which is characterized in that a nanocrystalline ceramic base material is used as an outer frame main body, and a silver-palladium alloy electrode is embedded into a ceramic frame body through a low-temperature co-firing ceramic process to form an electrode structure with a gradient thermal expansion coefficient; the beneficial effects are that a nanocrystalline ceramic base material is used as an outer frame main body, a silver-palladium alloy electrode is embedded into a ceramic frame body through a low-temperature co-firing ceramic technology to form an electrode structure with a gradient thermal expansion coefficient, and a combination surface of a heat dissipation carrier seat and the ceramic frame body is coated with nanoscale glass slurry; gapless connection is achieved through the laser-assisted co-firing technology, and the heat conduction efficiency is improved to 20 W / m.K or above.

Description

Technical Field

[0001] This invention relates to the field of chip packaging, specifically to a method for preparing a heat dissipation structure for chip packaging. Background Technology

[0002] As chip performance continues to improve, its power consumption and heat generation are also increasing dramatically, placing higher demands on chip packaging heat dissipation structures. Traditional chip packaging heat dissipation structures have many shortcomings in terms of heat dissipation efficiency, thermal stress handling, signal transmission, vibration suppression, and electromagnetic shielding.

[0003] Currently, heat dissipation efficiency is insufficient to meet the needs of high-power chips, resulting in excessively high chip temperatures that affect performance and lifespan; thermal stress can easily cause microcracks in the packaging structure, increasing thermal resistance; signal transmission loss is relatively large, making it difficult to adapt to high-frequency signal transmission; the packaging structure has poor stability under vibration; electromagnetic interference problems affect the normal operation of the chip, etc.

[0004] Therefore, it is necessary to develop a novel method for fabricating chip packaging heat dissipation structures to solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a chip package heat dissipation structure to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for preparing a chip package heat dissipation structure, comprising the following steps: A nanocrystalline ceramic substrate is used as the outer frame, and a silver-palladium alloy electrode is embedded inside the ceramic frame through a low-temperature co-fired ceramic process to form an electrode structure with a gradient thermal expansion coefficient. The electrode is divided into a first part located inside the ceramic frame and a second part exposed outside. The surface of the second part is formed with anti-oxidation welding points through chemical nickel-palladium-gold plating process. At the same time, nano-scale glass paste is coated on the bonding surface between the heat sink and the ceramic frame. The seamless connection between the heat sink and the ceramic frame is achieved through laser-assisted co-firing technology, and the heat conduction efficiency is improved to more than 20W / m·K.

[0007] Preferably, the fabrication of the heat dissipation carrier includes: fabricating a microfin heat sink using a 5nm silicon process, with the fin surface covered with a boron nitride thin film using atomic layer deposition technology to form a superhydrophobic surface; constructing vertical liquid cooling channels using TSV through-hole technology, filling the channels with nanofluids, and achieving composite heat dissipation in conjunction with the microfin array, achieving a cooling capacity of 350W / cm². 2 A shape memory alloy spring is embedded in the bottom of the heat sink carrier. The spring deformation is controlled by electrical stimulation to dynamically adjust the contact pressure between the heat sink carrier and the chip. The contact thermal resistance fluctuation range is ≤0.05℃·cm. 2 / W.

[0008] Preferably, the method further includes: setting a bottom filler layer between the chip and the heat sink, using a self-healing polymer material to replace the traditional die bond; achieving a low-stress connection between the chip and the heat sink through a thermo-press bonding process, wherein the coefficient of thermal expansion of the self-healing polymer material is adjusted by molecular design to match the chip and the heat sink with a degree of ≤3ppm / ℃; when the encapsulation structure develops microcracks due to thermal stress, the microencapsulated repair agent ruptures at the crack and releases repair monomers, achieving self-healing of the crack through a free radical polymerization reaction, and the thermal resistance recovery rate after repair is ≥95%.

[0009] Preferably, the packaging structure further includes: a redistribution layer is prepared on the surface of the ceramic frame, using photosensitive polyimide as the dielectric layer, and a 12-layer stacked structure is achieved through negative photoresist patterning, Ti / Cu / Ni multilayer barrier layer deposition, electrochemical deposition of copper filling, and chemical mechanical polishing; the bonding accuracy is ≤0.5μm, the signal transmission loss is ≤0.3dB / cm, and it is suitable for high-frequency signal transmission above 40GHz; at the same time, a temperature sensor array is embedded in the RDL layer, and the chip temperature is monitored in real time through an embedded resistance temperature detector with a monitoring accuracy of ±0.1.

[0010] Preferably, the package includes a guide post fixed to the circuit board and a guide sleeve fixed to the heat dissipation unit; the guide post is made of carbon fiber reinforced composite material, and the inner wall of the guide sleeve is provided with a magnetic coating; the fit clearance between the guide post and the guide sleeve is optimized by finite element thermal simulation to ensure that the chip tilt angle is ≤0.05° within the temperature range of -55°C to 150°C; a piezoelectric ceramic sheet is embedded between the guide post and the guide sleeve, and the deformation of the piezoelectric ceramic sheet is controlled by electrical stimulation to achieve active vibration suppression of the packaging structure, with a vibration attenuation rate ≥80%.

[0011] Preferably, the fabrication of the heat dissipation unit includes: fabricating a heat spreader on the surface of the heat dissipation fins, using a sintered copper powder capillary structure, with the capillary pore size distribution precisely controlled by 3D printing technology, and the pore size range being 5-20μm; using a fluorinated liquid working fluid to achieve planar temperature uniformity; setting a phase change material array on the contact surface between the heat spreader and the chip, with the PCM using a paraffin / graphene composite material and a phase change latent heat ≥250J / g; embedding micro heating wires in the PCM array, and dynamically adjusting the phase change temperature of the PCM through a PID control algorithm to adapt to the heat dissipation requirements under different operating conditions.

[0012] Preferably, the method further includes: embedding a heat dissipation column array in the encapsulating colloid, wherein the heat dissipation columns are made of carbon nanotube-reinforced copper-based composite material, and heat dissipation channels surrounding the chip are formed by electrochemical deposition process; the ratio of heat dissipation column height to encapsulating colloid thickness is 1:1.5, and the area of ​​heat dissipation columns exposed on the surface of the encapsulating colloid accounts for ≥40%; at the same time, a superhydrophobic coating is prepared on the surface of the heat dissipation columns, and a fluorinated silane film is deposited by sol-gel method, with a contact angle ≥150° to prevent the increase in thermal resistance caused by water vapor condensation.

[0013] Preferably, the fabrication of the packaging structure further includes: using a C4 bump flip-mount process to prepare an array of solder balls with a diameter of 15-40μm on the functional surface of the chip, and forming a uniform tin layer on the surface of the solder balls through a chemical tin plating process; achieving interconnection between the chip and the redistribution layer through thermo-press bonding, with the bonding pressure precisely adjusted through a force feedback control system to ensure a bonding strength ≥30MPa; and applying an elastic sealant around the SoC, the sealant being a silicone rubber / nano silica composite material, which is rapidly cured through an ultraviolet light curing process to control the chip warpage ≤8μm, ensuring the reliability of the packaging structure under mechanical vibration.

[0014] Preferably, it also includes: integrating a co-packaged optical module in the packaging structure, realizing the co-packaging of the optical engine with the GPU and HBM through a two-dimensional planar glass waveguide scheme; embedding a single-mode waveguide in the molten glass panel using a thermal ion exchange process, with the refractive index of the waveguide core layer precisely controlled by doping with germanium, and the refractive index difference Δn≥0.5%; achieving 2048 optical connections, adapting to a 204.8Tb / s optical switching chip architecture; and preparing an anti-reflection coating on the waveguide surface by depositing an alumina thin film using atomic layer deposition technology.

[0015] Preferably, the package further includes: an electromagnetic shielding layer at the bottom of the package structure, which is made of silver / copper / nickel multilayer composite material and deposited with a thickness of 5-10 μm by magnetron sputtering; the shielding layer is connected to the circuit board through a grounding pin to form a Faraday cage structure with a shielding effectiveness ≥80dB; and a flexible thermal pad is embedded between the shielding layer and the chip, which is made of silicone / boron nitride composite material with a thermal conductivity ≥5W / m·K to ensure the synergistic optimization of electromagnetic shielding and heat dissipation functions.

[0016] Compared with the prior art, the beneficial effects of the present invention are: The chip packaging heat dissipation structure preparation method proposed in this invention uses a nanocrystalline ceramic substrate as the outer frame body, and embeds silver palladium alloy electrodes into the ceramic frame body through a low-temperature co-fired ceramic process to form an electrode structure with a gradient thermal expansion coefficient. Furthermore, a nanoscale glass paste is coated on the bonding surface between the heat dissipation carrier and the ceramic frame body, and a gapless connection is achieved through laser-assisted co-firing technology, thereby improving the heat conduction efficiency to over 20 W / m·K.

[0017] A bottom filler layer is set between the chip and the heat sink, and a self-healing polymer material is used to replace the traditional die bond. Low-stress connection is achieved through thermo-press bonding process. The coefficient of thermal expansion of the self-healing polymer material is adjusted by molecular design to match the chip and heat sink with a degree of ≤3ppm / ℃. When the package structure develops microcracks due to thermal stress, the microencapsulated repair agent ruptures at the crack and releases repair monomers. The crack self-heals through free radical polymerization reaction, and the thermal resistance recovery rate after repair is ≥95%.

[0018] A redistribution layer is fabricated on the surface of a ceramic frame, and photosensitive polyimide is used as the dielectric layer. A 12-layer stacked structure is achieved through a series of processes. The bonding accuracy is ≤0.5μm, the signal transmission loss is ≤0.3dB / cm, and it is suitable for high-frequency signal transmission above 40GHz.

[0019] The C4 bump flip-mount process is used to fabricate a solder ball array on the functional side of the chip. The interconnection between the chip and the redistribution layer is achieved through thermo-press bonding. The bonding pressure is precisely adjusted by a force feedback control system to ensure a bonding strength of ≥30MPa. An elastic sealant is applied around the SoC. The sealant is a silicone rubber / nano silica composite material and is cured rapidly by ultraviolet light. The chip warpage is controlled to ≤8μm to ensure the reliability of the package structure under mechanical vibration.

[0020] The co-packaged optical module is integrated into the packaging structure, and the optical engine, GPU, and HBM are co-packaged through a two-dimensional planar glass waveguide scheme. A single-mode waveguide is embedded in the molten glass panel using a thermal ion exchange process. The refractive index of the waveguide core layer is precisely controlled by doping with germanium, and the refractive index difference Δn ≥ 0.5%. 2048 optical connections are achieved, which is compatible with a 204.8Tb / s optical switching chip architecture. An anti-reflection coating is prepared on the waveguide surface, and an alumina thin film is deposited using atomic layer deposition technology.

[0021] An electromagnetic shielding layer is set at the bottom of the package structure. It is made of silver / copper / nickel multilayer composite material and deposited with a thickness of 5-10μm by magnetron sputtering. The shielding layer is connected to the circuit board through a grounding pin to form a Faraday cage structure with a shielding effectiveness of ≥80dB. A flexible thermal pad is embedded between the shielding layer and the chip. The thermal pad is made of silicone / boron nitride composite material with a thermal conductivity of ≥5W / m·K to ensure the synergistic optimization of electromagnetic shielding and heat dissipation functions. Attached Figure Description

[0022] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the present invention clear and complete, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some, not all, embodiments of the present invention, and are merely illustrative of the embodiments of the present invention. They are not intended to limit the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Example 1: Heat dissipation structure for high-performance computing chip packaging Scenario requirements: High-performance computing chips generate a lot of heat during operation, requiring an efficient heat dissipation structure to maintain stable operation of the chip, while ensuring high-frequency performance of signal transmission and structural reliability.

[0025] Outer frame and electrode fabrication: A nanocrystalline ceramic substrate is used as the outer frame. Silver-palladium alloy electrodes are embedded inside the ceramic frame using a low-temperature co-fired ceramic process, forming an electrode structure with a gradient coefficient of thermal expansion. The electrode consists of a first part located inside the ceramic frame and a second part exposed on the outside. The surface of the second part is coated with an anti-oxidation solder joint using a chemical nickel-palladium-gold plating process.

[0026] Fabrication of the heat sink carrier: A microfin heat sink is fabricated using a 5nm silicon process. A boron nitride film is deposited on the fin surface using atomic layer deposition (ALD) technology to create a superhydrophobic surface. Vertical liquid cooling channels are constructed using TSV (Through-Vacuum Transistor) technology, filled with nanofluids. This, combined with the microfin array, achieves composite heat dissipation with a cooling capacity of 350W / cm². A shape memory alloy spring is embedded at the bottom of the heat sink carrier. Electrical stimulation controls the spring's deformation, dynamically adjusting the contact pressure between the heat sink carrier and the chip, ensuring that the contact thermal resistance fluctuation range is ≤0.05℃·cm. 2 / W.

[0027] Connection and Filling: A nano-scale glass paste is coated on the bonding surface between the heat sink carrier and the ceramic frame. Laser-assisted co-firing technology achieves a gapless connection between the heat sink carrier and the ceramic frame, increasing thermal conductivity to over 20 W / m·K. A bottom filler layer is placed between the chip and the heat sink carrier, using a self-healing polymer material instead of traditional die-attach adhesive. A low-stress connection between the chip and the heat sink carrier is achieved through thermo-press bonding. The coefficient of thermal expansion of the self-healing polymer material is adjusted through molecular design to match the chip and heat sink carrier to ≤3 ppm / ℃. When microcracks appear in the encapsulation structure due to thermal stress, the microencapsulated repair agent ruptures at the crack and releases repair monomers. Self-healing of the crack is achieved through free radical polymerization, resulting in a thermal resistance recovery rate ≥95% after repair.

[0028] Redundancy Layer Fabrication: A redundancy layer is fabricated on the surface of the ceramic frame. Photosensitive polyimide is used as the dielectric layer. A 12-layer stacked structure is achieved through negative photoresist patterning, Ti / Cu / Ni multilayer barrier layer deposition, electrochemical copper deposition, and chemical mechanical polishing. Bonding accuracy is ≤0.5μm, signal transmission loss is ≤0.3dB / cm, and it is suitable for high-frequency signal transmission above 40GHz. Simultaneously, a temperature sensor array is embedded in the RDL layer, and the chip temperature is monitored in real time using an embedded resistance temperature detector with a monitoring accuracy of ±0.1.

[0029] Guiding and Vibration Suppression: Guide posts fixed to the circuit board and guide sleeves fixed to the heat dissipation unit are installed. The guide posts are made of carbon fiber reinforced composite material, and the inner wall of the guide sleeve is coated with a magnetic coating. The fit clearance between the guide posts and the guide sleeve is optimized through finite element thermal simulation to ensure that the chip tilt angle is ≤0.05° within a temperature range of -55℃ to 150℃. A piezoelectric ceramic sheet is embedded between the guide posts and the guide sleeve. The deformation of the piezoelectric ceramic sheet is controlled by electrical stimulation to achieve active vibration suppression of the packaging structure, with a vibration attenuation rate ≥80%.

[0030] Heat dissipation unit fabrication: A vapor chamber is fabricated on the surface of the heat dissipation fins using a sintered copper powder capillary structure. The capillary pore size distribution is precisely controlled using 3D printing technology, with a pore size range of 5-20 μm. A fluorinated liquid working fluid is used to achieve planar temperature uniformity. A phase change material array is placed at the contact surface between the vapor chamber and the chip. The PCM uses a paraffin / graphene composite material with a latent heat of phase change ≥250 J / g. Micro-heating wires are embedded in the PCM array, and the phase change temperature of the PCM is dynamically adjusted using a PID control algorithm to adapt to the heat dissipation requirements under different operating conditions.

[0031] Encapsulation Colloid and Heat Dissipation Pillars: A heat dissipation pillar array is embedded in the encapsulation colloid. The heat dissipation pillars are made of carbon nanotube-reinforced copper-based composite material, forming heat dissipation channels surrounding the chip through an electrochemical deposition process. The ratio of heat dissipation pillar height to encapsulation colloid thickness is 1:1.5, and the area of ​​the heat dissipation pillars exposed on the surface of the encapsulation colloid is ≥40%. Simultaneously, a superhydrophobic coating is prepared on the surface of the heat dissipation pillars by depositing a fluorinated silane film using a sol-gel method, with a contact angle ≥150° to prevent the increase in thermal resistance caused by water vapor condensation.

[0032] Chip mounting and sealing: A C4 bump flip-mount process is used to fabricate an array of solder balls with a diameter of 15-40μm on the functional surface of the chip. A uniform solder layer is formed on the surface of the solder balls through a chemical tin plating process. The interconnection between the chip and the redistribution layer is achieved through thermocompression bonding. The bonding pressure is precisely adjusted through a force feedback control system to ensure a bonding strength ≥30MPa. An elastic sealant is applied around the SoC. The sealant is a silicone rubber / nano silica composite material and is rapidly cured using a UV curing process to control chip warpage ≤8μm, ensuring the reliability of the package structure under mechanical vibration.

[0033] Example 2: Heat dissipation structure for optical communication chip packaging Scenario requirements: Optical communication chips need to achieve co-packaging of optical engine, GPU, and HBM, while ensuring high-quality transmission of optical signals and efficient heat dissipation performance.

[0034] Outer frame and electrode fabrication: Similar to Example 1, a nanocrystalline ceramic substrate is used as the outer frame. A silver-palladium alloy electrode is embedded inside the ceramic frame using a low-temperature co-fired ceramic process, forming an electrode structure with a gradient coefficient of thermal expansion. Anti-oxidation welding points are formed on the surface of the second part of the electrode using a chemical nickel-palladium-gold plating process.

[0035] Fabrication of the heat dissipation carrier: A heat dissipation carrier structure suitable for the heat dissipation requirements of optical communication chips is adopted, such as a conventional heat dissipation carrier combined with high-efficiency heat dissipation materials. A nano-scale glass paste is coated on the interface between the heat dissipation carrier and the ceramic frame, and a gapless connection is achieved through laser-assisted co-firing technology, improving the thermal conductivity to over 20 W / m·K.

[0036] Connection and Filling: A bottom filler layer is set between the chip and the heat sink carrier. A self-healing polymer material is used to achieve low-stress connection through hot-press bonding process. The thermal expansion coefficient matching degree is adjusted to ≤3ppm / ℃ to achieve self-healing of cracks. The thermal resistance recovery rate after repair is ≥95%.

[0037] Redistribution layer fabrication: A redistribution layer is fabricated on the surface of the ceramic frame to achieve a multi-layer stacked structure, ensuring signal transmission performance meets the requirements of optical communication. A temperature sensor array is embedded in the RDL layer to monitor the chip temperature in real time.

[0038] Co-packaged optical module integration: A co-packaged optical module is integrated into the packaging structure, achieving co-packaging of the optical engine with the GPU and HBM through a two-dimensional planar glass waveguide scheme. A single-mode waveguide is embedded in the molten glass panel using a thermionic exchange process. The refractive index of the waveguide core layer is precisely controlled by germanium doping, with a refractive index difference Δn ≥ 0.5%, enabling 2048 optical connections and adapting to a 204.8Tb / s optical switching chip architecture. An anti-reflective coating is prepared on the waveguide surface, and an alumina thin film is deposited using atomic layer deposition (ALD).

[0039] Heat dissipation unit and encapsulating colloid: Based on the heat dissipation requirements of the optical communication chip, the structure of the heat dissipation unit is optimized, such as by fabricating a vapor chamber and setting up a phase change material array. A heat dissipation pillar array is embedded in the encapsulating colloid. The heat dissipation pillars are fabricated using appropriate materials and processes, and a superhydrophobic coating is prepared on their surface.

[0040] Chip mounting and sealing: A C4 bump flip-mount process is used to prepare a solder ball array and form a uniform solder layer. Interconnection between the chip and the redistribution layer is achieved through thermocompression bonding, with bonding pressure adjusted to ensure bond strength. An elastic sealant is applied around the SoC for rapid curing and to control chip warpage.

[0041] Example 3: Chip Packaging Heat Dissipation Structure in Electromagnetically Sensitive Environments Scenario requirements: In electromagnetically sensitive environments, chip packaging structures need to have good electromagnetic shielding performance, while ensuring efficient heat dissipation and structural stability.

[0042] Outer frame body and electrode preparation: Nanocrystalline ceramic substrate is used as the outer frame body, and silver-palladium alloy electrodes are embedded through low-temperature co-fired ceramic process. Anti-oxidation welding points are formed on the surface of the second part of the electrode.

[0043] Fabrication of the heat dissipation carrier: A heat dissipation carrier with high-efficiency heat dissipation capabilities is fabricated, such as by using microfin heat sinks and suitable heat dissipation materials. A gapless connection is achieved at the interface between the heat dissipation carrier and the ceramic frame to improve heat conduction efficiency.

[0044] Connection and filling: A self-healing polymer material bottom filling layer is set between the chip and the heat sink carrier, and low-stress connection is achieved through thermo-press bonding to realize self-healing of cracks.

[0045] Redundancy layer fabrication: A redundancy layer is fabricated on the surface of the ceramic frame to ensure signal transmission performance, and a temperature sensor array is embedded to monitor the chip temperature.

[0046] Guiding and Vibration Suppression: Guide posts and guide sleeves are installed, and the fitting clearance is optimized to ensure the required tilt angle of the chip within different temperature ranges. Active vibration suppression is achieved by embedding a piezoelectric ceramic sheet.

[0047] Electromagnetic shielding layer configuration: An electromagnetic shielding layer is installed at the bottom of the package structure. This layer is made of a multilayer silver / copper / nickel composite material and deposited using magnetron sputtering to achieve a thickness of 5-10 μm. The shielding layer is connected to the circuit board via a grounding pin, forming a Faraday cage structure with a shielding effectiveness ≥80 dB.

[0048] Thermal pad embedding: A flexible thermal pad is embedded between the shielding layer and the chip. The thermal pad is made of silicone / boron nitride composite material with a thermal conductivity of ≥5W / m·K, ensuring the synergistic optimization of electromagnetic shielding and heat dissipation functions.

[0049] Heat dissipation unit and encapsulating colloid: Heat dissipation units, such as heat spreaders and phase change material arrays, are fabricated according to heat dissipation requirements. A heat dissipation column array is embedded in the encapsulating colloid, and a superhydrophobic coating is prepared on the surface.

[0050] Chip mounting and sealing: A C4 bump flip-mount process is used to interconnect the chip with the redistribution layer and adjust the bonding pressure. An elastic sealant is applied around the SoC for rapid curing and to control chip warpage.

[0051] Example 4: High-Reliability Chip Packaging Heat Dissipation Structure for Harsh Environments Scenario requirements: In harsh environments, chip packaging structures need to have high reliability, be able to withstand the effects of mechanical vibration and temperature changes, and at the same time ensure efficient heat dissipation performance.

Claims

1. A method for fabricating a chip package heat dissipation structure, characterized in that: Includes the following steps: A nanocrystalline ceramic substrate is used as the outer frame, and a silver-palladium alloy electrode is embedded inside the ceramic frame through a low-temperature co-fired ceramic process to form an electrode structure with a gradient thermal expansion coefficient. The electrode is divided into a first part located inside the ceramic frame and a second part exposed outside. The surface of the second part is formed with anti-oxidation welding points through chemical nickel-palladium-gold plating process. At the same time, nano-scale glass paste is coated on the bonding surface between the heat dissipation carrier and the ceramic frame. The seamless connection between the heat dissipation carrier and the ceramic frame is achieved through laser-assisted co-firing technology, and the heat conduction efficiency is improved to more than 20W / m·K.

2. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: The fabrication of the heat dissipation carrier includes: fabricating a microfin heat sink using a 5nm silicon process; covering the fin surface with a boron nitride thin film using atomic layer deposition technology to form a superhydrophobic surface; constructing vertical liquid cooling channels using TSV (Through-Vacuum Transistor) technology, filling the channels with nanofluids, and combining this with the microfin array to achieve composite heat dissipation, with a cooling capacity of 350W / cm². 2 A shape memory alloy spring is embedded in the bottom of the heat sink carrier. The spring deformation is controlled by electrical stimulation to dynamically adjust the contact pressure between the heat sink carrier and the chip. The contact thermal resistance fluctuation range is ≤0.05℃·cm. 2 / W.

3. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: Also includes: A bottom filler layer is set between the chip and the heat sink, and a self-healing polymer material is used to replace the traditional die bond adhesive. The chip and the heat sink are connected with low stress through a thermo-press bonding process. The coefficient of thermal expansion of the self-healing polymer material is adjusted by molecular design to match the chip and the heat sink with a degree of ≤3ppm / ℃. When the package structure develops microcracks due to thermal stress, the microencapsulated repair agent ruptures at the crack and releases repair monomers. The crack self-heals through a free radical polymerization reaction, and the thermal resistance recovery rate after repair is ≥95%.

4. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: The packaging structure also includes: a redistribution layer is prepared on the surface of the ceramic frame, using photosensitive polyimide as the dielectric layer, and a 12-layer stacked structure is achieved through negative photoresist patterning, Ti / Cu / Ni multilayer barrier layer deposition, electrochemical deposition of copper filling, and chemical mechanical polishing; the bonding accuracy is ≤0.5μm, the signal transmission loss is ≤0.3dB / cm, and it is suitable for high-frequency signal transmission above 40GHz; at the same time, a temperature sensor array is embedded in the RDL layer to monitor the chip temperature in real time through an embedded resistance temperature detector with a monitoring accuracy of ±0.

1.

5. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: It includes guide posts fixed to the circuit board and guide sleeves fixed to the heat dissipation unit; the guide posts are made of carbon fiber reinforced composite material, and the inner wall of the guide sleeve is coated with a magnetic coating; the fit clearance between the guide posts and the guide sleeve is optimized by finite element thermal simulation to ensure that the chip tilt angle is ≤0.05° within the temperature range of -55℃ to 150℃; a piezoelectric ceramic sheet is embedded between the guide posts and the guide sleeve, and the deformation of the piezoelectric ceramic sheet is controlled by electrical stimulation to achieve active vibration suppression of the packaging structure, with a vibration attenuation rate ≥80%.

6. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: The fabrication of the heat dissipation unit includes: fabricating a vapor chamber on the surface of the heat dissipation fins, using a sintered copper powder capillary structure, with the capillary pore size distribution precisely controlled by 3D printing technology, ranging from 5 to 20 μm; using a fluorinated liquid working fluid to achieve planar temperature uniformity; setting a phase change material array on the contact surface between the vapor chamber and the chip, with the PCM using a paraffin / graphene composite material and a phase change latent heat ≥250 J / g; embedding micro heating wires in the PCM array, and dynamically adjusting the phase change temperature of the PCM through a PID control algorithm to adapt to the heat dissipation requirements under different operating conditions.

7. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: Also includes: A heat dissipation column array is embedded in the encapsulating colloid. The heat dissipation columns are made of carbon nanotube-reinforced copper-based composite material, and a heat dissipation channel surrounding the chip is formed by electrochemical deposition process. The ratio of heat dissipation column height to encapsulation colloid thickness is 1:1.5, and the area of ​​heat dissipation column exposed on the surface of encapsulation colloid accounts for ≥40%. At the same time, a superhydrophobic coating is prepared on the surface of the heat dissipation column by depositing a fluorinated silane film through the sol-gel method, with a contact angle ≥150° to prevent the increase in thermal resistance caused by water vapor condensation.

8. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: The fabrication of the packaging structure also includes: using the C4 bump flip-mount process to prepare an array of solder balls with a diameter of 15-40μm on the functional surface of the chip, and forming a uniform tin layer on the surface of the solder balls through a chemical tin plating process; achieving interconnection between the chip and the redistribution layer through thermo-press bonding, with the bonding pressure precisely adjusted through a force feedback control system to ensure a bonding strength ≥30MPa; and applying an elastic sealant around the SoC, using a silicone rubber / nano silica composite material, which is rapidly cured through an ultraviolet light curing process to control the chip warpage ≤8μm, ensuring the reliability of the packaging structure under mechanical vibration.

9. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: Also includes: A co-packaged optical module is integrated into the packaging structure, and the co-packaging of the optical engine with the GPU and HBM is achieved through a two-dimensional planar glass waveguide scheme; A single-mode waveguide is embedded in a molten glass panel using a thermal ion exchange process. The refractive index of the waveguide core layer is precisely controlled by doping with germanium, with a refractive index difference Δn ≥ 0.5%. It enables 2048 optical connections and is compatible with a 204.8Tb / s optical switching chip architecture; An anti-reflection coating is prepared on the waveguide surface, and an alumina thin film is deposited using atomic layer deposition technology.

10. The method for preparing the chip package heat dissipation structure according to claim 1, characterized in that: Also includes: An electromagnetic shielding layer is set at the bottom of the packaging structure. It is made of silver / copper / nickel multilayer composite material and the shielding layer with a thickness of 5-10μm is deposited by magnetron sputtering process. The shielding layer is connected to the circuit board via a grounding pin to form a Faraday cage structure with a shielding effectiveness of ≥80dB. A flexible thermal pad is embedded between the shielding layer and the chip. The thermal pad is made of silicone / boron nitride composite material with a thermal conductivity of ≥5W / m·K, ensuring the synergistic optimization of electromagnetic shielding and heat dissipation functions.

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