Bit serial input scheme for crossover circuit

Abstract

According to some aspects of the present disclosure, a crossover circuit may include a plurality of bit lines crossing a plurality of word lines, a plurality of crossover devices, and a plurality of switches connected to the plurality of word lines. Each cross point device is connected to at least one of the word lines and at least one of the bit lines, and may include one resistive random access memory (RRAM) device. Each switch may be selectively connected to ground or a reference voltage. A digital input may be provided to a cross-point device of the cross-point circuit by selectively grounding a word line connected to the cross-point device or connecting to a reference voltage.

Description

[0001] Cross-referencing This application claims priority to U.S. Patent Application No. 18 / 456,452, filed August 25, 2023, entitled “Bit Serial Input Scheme for Crossover Circuits,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of this disclosure primarily relate to crossover circuits including resistive random access memory devices, and more specifically, to bit-serial input schemes for crossover circuits. Background Technology

[0003] A crossover circuit is a circuit structure consisting of interconnected electrical wires that connect at their intersections to a storage element, such as a resistive switching material. Examples of resistive switching materials include memristors (also known as resistive random access memory (RRAM or ReRAM)). Crossover circuits can be used in applications such as in-memory computing, non-volatile solid-state memory, image processing, and neural networks. Summary of the Invention

[0004] The following is a simplified summary of this disclosure, intended to provide a basic understanding of certain aspects of this disclosure. This summary is not a comprehensive overview of this disclosure, nor is it intended to identify key or essential elements of this disclosure, nor to define the scope of any particular embodiment or claim. Its sole purpose is to present some concepts of this disclosure in a simplified form as a prelude to a more detailed description thereafter.

[0005] According to one or more aspects, an apparatus including crossover circuitry is provided. The apparatus may include: a plurality of bit lines crossing a plurality of word lines; a plurality of crossover point devices; and a plurality of switches connected to the plurality of word lines. Each of the switches may be selectively connected to ground or a reference voltage. Each of the crossover point devices is connected to at least one word line and at least one bit line. Each of the crossover point devices includes a resistive random access memory (RRAM) device.

[0006] In some embodiments, a first switch among the plurality of switches is connected to a first word line among the plurality of word lines, and when the first bit of the digital input is provided to the first crosspoint device, the first switch is connected to ground, and the first crosspoint device is connected to the first word line.

[0007] In some embodiments, when a second bit of the digital input is provided to the first crosspoint device, the first switch is connected to the reference voltage.

[0008] In some embodiments, the first digit of the numeric input is "1" and the second digit is "0".

[0009] In some embodiments, a first end of the first RRAM device is connected to the first word line, and a second end is connected to the source or drain of a transistor.

[0010] In some embodiments, the reference voltage corresponds to the read voltage provided to the bit line connected to the first crossover point device.

[0011] In some embodiments, the device further includes a buffer that generates the reference voltage, the output of which is selectively connected to the plurality of switches.

[0012] In some embodiments, the buffer is a unity-gain amplifier.

[0013] In some embodiments, the plurality of switches include a plurality of multiplexers.

[0014] According to one or more aspects of this disclosure, a method for performing in-memory computation using a crossover circuit is provided. The method includes: providing a "0" bit of a digital input to a first crossover device by providing the reference voltage to a first word line; and providing a "1" bit of the digital input to the first crossover device by grounding the first word line.

[0015] In some embodiments, the reference voltage is generated using the unity-gain amplifier. The crossover circuit includes multiple word lines crossing multiple bit lines. The first crossover point device is connected to the first word line and the first bit line. The reference voltage corresponds to the read voltage provided to the first bit line.

[0016] In some embodiments, providing the reference voltage to the first word line connected to the first crossover device includes connecting the input of the switch to the reference voltage and the output of the switch to the first word line.

[0017] In some embodiments, grounding the first word line includes connecting the input of the switch to ground.

[0018] According to one or more aspects of this disclosure, an apparatus including crossover circuitry is provided. The apparatus includes: a first set of bit lines and a second set of bit lines crossing a plurality of word lines; a first switch for selectively connecting a first segment of one of the plurality of word lines to ground; and a second switch for selectively connecting a second segment of the first word line to ground; a plurality of crossover point devices connected to the first segment of the first word line and the first set of bit lines; and a plurality of crossover point devices connected to the second segment of the first word line and the second set of bit lines.

[0019] In some embodiments, each of the first and second group of intersection devices includes an RRAM device.

[0020] In some embodiments, when the first switch is closed, the first segment of the first word line is left suspended.

[0021] In some embodiments, when the second switch is closed, the second segment of the first word line is left suspended.

[0022] According to one or more aspects of this disclosure, a method for performing in-memory computation using a crossover circuit is provided. The method includes: providing a first bit to a first crossover point device in the crossover circuit by connecting a first segment of a first word line to ground; and providing a second bit to the first crossover point device by setting the first segment of the first word line to floating, wherein the crossover circuit includes a plurality of word lines crossing a plurality of bit lines, wherein the first crossover point device is connected to the first word line and the first bit line among the plurality of bit lines.

[0023] In some embodiments, the method further includes providing a third bit to a second crosspoint device by grounding a second segment of the first word line, wherein the second crosspoint device is connected to the first word line and the second bit line among a plurality of bit lines.

[0024] In some embodiments, the method further includes providing a fourth bit to the second intersection device by setting a second segment of the first word line to be suspended. Attached Figure Description

[0025] The detailed description of this disclosure and the following accompanying drawings will aid in a more comprehensive understanding of the various embodiments thereof. However, these drawings are not intended to limit this disclosure to the specific embodiments, but are for purposes of explanation and understanding.

[0026] Figure 1A This is a schematic diagram illustrating an example crossover circuit according to some embodiments of the present disclosure.

[0027] Figure 1B and Figure 1C This is a schematic diagram illustrating an example cross-point device according to some embodiments of this disclosure.

[0028] Figure 2A and Figure 2B This is a schematic diagram showing an example crossover circuit according to some embodiments of the present disclosure.

[0029] Figure 3 This is a flowchart illustrating an example method of performing in-memory computation using a cross circuit according to an embodiment of the present disclosure.

[0030] Figure 4 This is a flowchart illustrating an example method of performing in-memory computation using cross circuitry according to another embodiment of this disclosure. Detailed Implementation

[0031] This disclosure provides a bit-serialized input scheme for crossover circuits and a method for performing in-memory computations using crossover circuits. A crossover circuit may include intersecting conductive lines (e.g., word lines, bit lines, etc.) and an array of crossover point devices (also referred to as a "crossover array") disposed at the intersections of these conductive lines. Each crossover point device may be connected to one word line and one bit line.

[0032] Traditional crossover circuits typically convert digital inputs to analog inputs and then provide the analog inputs to the crossover point device array. In such crossover circuits, a digital-to-analog converter (DAC) and driver are used to generate the input analog voltage capable of driving the bit line current, resulting in additional power and space consumption. Some existing crossover circuits provide digital inputs to the crossover array by applying the digital input to the gate of a transistor that controls access to the crossover point devices. This can lead to unnecessary power consumption and introduce read interference associated with unused RRAM devices connected to the same select line, since the select lines share the input. Furthermore, applying the input voltage to the transistor gate can cause voltage variations on the programmed RRAM devices, resulting in variations in RRAM resistance and read interference.

[0033] According to this disclosure, digital inputs can be provided to the crossover circuit via a bit-serial input scheme. In one embodiment, a digital input signal (e.g., a series of bits) can be provided to the crossover device by selectively connecting the word line connected to the crossover device to a reference voltage or to ground. For example, a "0" bit can be provided to the crossover device by connecting the word line to a reference voltage corresponding to the read voltage applied to the bit line connected to the crossover device. As another example, a "1" bit can be provided to the crossover device by grounding the word line.

[0034] In another embodiment, each word line in the crossover circuit may consist of multiple segments. Digital input signals can be provided to the crossover device by selectively grounding or floating word line segments connected to the crossover device. For example, a "1" bit can be provided to the crossover device by grounding a word line segment. As another example, a "0" bit can be provided to the crossover device by floating a word line segment.

[0035] The bit serial input scheme provided in this application can reduce the power consumption of the cross circuit and avoid read interference caused by applying a small switching voltage to the selected cross point device.

[0036] Figure 1A is a schematic diagram illustrating an example of a cross circuit 100 according to some embodiments of the present disclosure.

[0037] As shown in the figure, the cross circuit 100 may include multiple intersecting conductive lines, such as one or more rows of conductors (111a, 111b, ..., 111i, ..., 111n) and one or more columns of conductors (113a, 113b, ..., 113j, ..., 113m) for an nn row mmm column cross array. The cross circuit 100 may also include cross-point devices (120a, 120b, ..., 120ij, ..., 120z). Each cross-point device may connect one row of conductors and one column of conductors. For example, cross-point device 120ij may connect row conductor 111i and column conductor 113j. In some embodiments, the cross circuit 100 may also include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and any other suitable circuit components for implementing the cross circuit-based device. The number of column conductors 113a-m and the number of row conductors 111a-n may be the same or different.

[0038] The row conductors 111a-n may include a first row conductor 111a, a second row conductor 111b, ..., an iii row conductor 111i, ..., and an nn row conductor 111n. Each row conductor 111a-n may be made of any suitable conductive material. In some embodiments, each row conductor 111a-n may be a metallic conductor.

[0039] The column conductors 113a-m may include a first column conductor 113a, a second column conductor 113b, ..., and a m-th column conductor 113m. Each column conductor 113a-m may be made of any suitable conductive material. In some embodiments, each column conductor 113a-m may be a metallic conductor.

[0040] Each crosspoint device 120a-z can be any suitable device with adjustable resistance, such as a phase-change memory (PCM) device, a floating-gate device, a spintronic device, a resistive random access memory (RRAM) device, a static random access memory (SRAM) device, a ferroelectric device, etc. In some embodiments, one or more crosspoint devices 120a-z may include the crosspoint devices associated with Figures 1B-1C. In some embodiments, one or more crosspoint devices 120a-z may be connected to a transistor to achieve a 1TmR configuration.

[0041] Each column wire 113a-m may be connected to one or more column switches 133 (e.g., switches 133a, ..., 133j, ..., 133m). Each column switch 133a-m may include any suitable circuit structure for controlling the current through the bit wire 113a-m. In some embodiments, one or more switches 133a-m may also provide fault protection, electrostatic discharge (ESD) protection, noise reduction, and any other suitable functionality for one or more portions of the cross circuit 100.

[0042] The output sensor 140 may include any suitable components for converting the current flowing through the column conductors 113a-m into a digital output, such as one or more transimpedance amplifiers (not shown), analog-to-digital converters (not shown), etc. In some embodiments, the output sensor 140 may also include one or more multiplexers (not shown).

[0043] Crossover circuit 100 can perform parallel weighted voltage multiplication and current summation operations. For example, an input voltage signal can be applied to one or more selected rows of crossover circuit 100. The input signal can flow through the row crossover point devices of crossover circuit 100. The conductance of the crossover point device can be programmed to a specific value (also called a “weight”). According to Ohm’s law, the input voltage is multiplied by the conductance of the crossover point device to generate a current through that device. According to Kirchhoff’s law, the summation of the currents through each column device generates an output signal current, which can be read through the column (e.g., the output of an ADC). According to Ohm’s law and Kirchhoff’s current law, the input-output relationship of the crossover array can be expressed as I=VG, where I represents the output signal matrix (current), VVV represents the input signal matrix (voltage), and G represents the conductance matrix of the crossover point device. Therefore, the input signal is weighted by the conductance of each crossover point device according to Ohm’s law. The weighted current is output through each column wire and accumulates according to Kirchhoff’s current law. In some embodiments, one or more bit-serial input schemes associated with FIG2A-5 may be used to provide input signals to cross circuit 100.

[0044] The crossover circuit 100 can be configured to perform vector-matrix multiplication (VMM). A VMM operation can be represented as Y = XA, where Y, X, and A represent the corresponding matrices. For example, the input vector X can be mapped to the input voltage V of the crossover circuit 100. Matrix A can be mapped to the conductance value G. The output current I can be read and mapped back to the output result Y. In some embodiments, the crossover circuit 100 can implement part of the functionality of a neural network by performing VMM.

[0045] Figure 1B and Figure 1C This is a schematic diagram illustrating example crosspoint devices 1220a and 1220b according to some embodiments of this disclosure. Crosspoint devices 1220a and 1220b can be referred to as a 1 transistor 1 resistor (1T1R) configuration.

[0046] like Figure 1B and Figure 1C As shown, cross-point devices 1220a-b may include an RRAM device 1201 and a transistor 1203 connected in series. The transistor may include three terminals, labeled as gate (G), source (S), and drain (D). Reference Figure 1B The first terminal of RRAM device 1201 can be connected to the drain of transistor 1203. The second terminal of RRAM device 1201 can be connected to bit line 1211. The source of transistor 1203 can be connected to word line 1215. The gate of transistor 1203 can be connected to select line 1213.

[0047] like Figure 1C As shown, in some embodiments, the second terminal of the RRAM device 1201 can be connected to word line 1215, while the source of transistor 1203 can be connected to bit line 1211. Word line 1215 can correspond to... Figure 1A The row conductors 111a-n in the figure. The bit line 1211 can correspond to Figure 1A The column conductor 113a-m.

[0048] Transistor 1203 can function as a selector and current controller, setting the current limit to RRAM device 1201 during programming. The gate voltage applied to the gate of transistor 1203 can set the current limit of crosspoint devices 1220a-b during programming, thereby controlling the conductivity and analog behavior of crosspoint devices 1220a-b. For example, when crosspoint devices 1220a-b are set from a high-resistance state to a low-resistance state, a setting signal (e.g., a voltage signal, a current signal) can be provided via bit line (BL) 1211 (or word line (WL) 1215). Another voltage (also called the select voltage or gate voltage) can be applied to the transistor gate via select line (SEL) 1213 to turn on the gate and set the current limit, while word line (WL) 1215 (or bit line (BL)) can be grounded. When crosspoint devices 1220a-b are reset from a low-resistance state to a high-resistance state, the gate voltage can be applied to the gate of transistor 1203 via select line 1213 to turn on the transistor gate. Meanwhile, the reset signal can be sent to the RRAM device 1201 via word line 1215 (or bit line 1211), while bit line 1211 (or word line 1215) can be grounded.

[0049] Figure 2A and Figure 2BThis is a schematic diagram illustrating cross circuits 200a and 200b according to some embodiments of this disclosure. Cross circuits 200a and 200b are... Figure 1A A more detailed example of the crossover circuit 100.

[0050] refer to Figure 2A The cross circuit 200a may include word lines (WL) 211a, ..., 211n, bit lines (BL) 213a, ..., 213k, ..., 213j, ..., 213nk, and select lines (SEL) 215a, ..., 215k, ..., 215j, ..., 215nk, which are intersecting conductive lines. The cross circuit 200a may also include cross point devices 220(a, a), ..., 220(a, k), ..., 220(a, j), ..., 220(a, nk), ..., 220(n, a), ..., 220(n, k), ..., 220(n, j), ..., 220(n, nk) (collectively referred to as cross point devices 220). As shown in the figure, each crossover device 220 can be connected to a word line 211a-n, a bit line 213a-nk, and a select line 215a-nk. In some embodiments, the word lines 211a-n and bit lines 213a-m can respectively correspond to Figure 1A The row lines 111a-n and column lines 113a-m are used. In other embodiments, the word lines 211a-n and bit lines 213a-m may correspond to... Figure 1A The column conductors 113a-m and the row conductors 111a-n are shown in the figure.

[0051] In some embodiments, each crosspoint device 220 may include a transistor and an RRAM device connected in series (e.g., with...). Figure 1B and Figure 1C (Related 1T1R configuration).

[0052] The cross circuit 200a may also include multiple switches 231a, ..., 231n. Each switch 231a-n can selectively connect one of the multiple input lines to a single common output line. For example... Figure 2AAs shown, one input line of switches 231a-n can be connected to the output 243 of buffer 240, and the other input line can be connected to ground. The output lines of switches 231a-n can be connected to corresponding word lines and can be selectively connected to one input line of the switch. Therefore, each switch 231a, ..., 231n can be connected to corresponding word lines 211a, ..., 211n, and the corresponding word lines can be selectively connected to one of a plurality of inputs (e.g., ground, reference voltage, etc.). Switches 231a-n can be implemented by any circuit suitable for performing the switching functions described above. In some embodiments, one or more switches 231a-n can be multiplexers.

[0053] Performing memory computation using the crossover circuit 200a may involve selecting one or more crossover devices 220 by applying an appropriate selection voltage to one or more selection lines 215a-n connected to the target crossover device. The conductivity of the RRAM device in the selected crossover device can then be programmed to an appropriate value (e.g., a conductivity value corresponding to the weight matrix W).

[0054] Digital input signals (e.g., binary input signals) can be applied to the selected crosspoint device via word lines connected to the selected RRAM device and the crosspoint device. The binary input signal may include one or more bits (e.g., a series of bits). Each bit can be either "0" or "1". These bits can be applied to the selected RRAM device serially (e.g., one bit at a time). For example, a "1" bit can be provided as an input to the selected crosspoint device by grounding a word line (e.g., word line 211a) connected to the selected crosspoint device (e.g., crosspoint device 220(a, a)) (e.g., via switch 231a). As another example, a "0" bit can be provided as an input to the selected crosspoint device by connecting a word line (e.g., word line 211a) connected to a reference voltage. Thus, a "1" bit is provided to the selected crosspoint device via current flowing through the cell, while a "0" bit is provided to the selected crosspoint device via current not flowing through the crosspoint device. The reference voltage may correspond to a read voltage (e.g., bit line 213a) applied to the bit line connected to the selected crosspoint device. In other words, the reference voltage can be the same as or substantially the same as the read voltage. Therefore, in response to the input binary signal and the application of the read voltage, there may be little or no current flowing through the RRAM device in the selected crossover device. The read voltage is typically much lower than the select voltage applied to the transistor gate. For example, the read voltage is typically in the range of 0.1V to 0.3V, while the select voltage is typically 0.6V or higher because the transistor gate needs to be turned on. The power consumption during RRAM device switching can be expressed as CV²f, where C is the capacitance, V is the switching voltage, and f is the switching frequency. Therefore, by using a lower switching voltage, the bit serial input scheme can reduce power consumption.

[0055] The crossover circuit 200a may also include a buffer 240 for generating a reference voltage. In some embodiments, the buffer 240 may be a unity-gain amplifier. The output of the buffer 240 may be selectively connected to one or more word lines 211a-n via switches 231a-n. The input 241 of the buffer 240 may be connected to a word line reference voltage WL_REF. WL_REF may be the same as or substantially the same as the read voltage applied to the bit line connecting the selected crossover point device. In some embodiments, the word line reference voltage WL_REF may be generated by a DAC (not shown), a bandgap circuit (not shown), and / or any other circuitry suitable for generating the reference voltage. Because WL_REF is below a voltage that could cause read interference, the bit serial input scheme does not cause read interference in the crossover circuit 200a.

[0056] refer to Figure 2BCross-point devices in a cross circuit can be divided into multiple logic groups (also called "blocks"). Each logic group or block may include an array of cross-point devices connected to one or more bit lines. For example, the first block 201 of cross circuit 200b may include cross-point devices connected to bit lines 213a, ..., 213k and word lines 211a, ..., 211n, such as cross-point devices 220(a, a), ..., 220(a, k), ..., 220(n, a), ..., 220(n, k). The second block 203 may include cross-point devices connected to bit lines 213j, ..., 213nk and word lines 211a-n, such as cross-point devices 220(a, j), ..., 220(a, nk), ..., 220(n, j), ..., 220(n, nk). Each block may include an appropriate number of cross-point device arrays and connected bit lines (e.g., 8 bit lines, 16 bit lines, 32 bit lines, etc.).

[0057] Figure 2B Only two blocks are shown in a simplified illustration, but this is merely an example. The crossover circuit can be divided into any suitable number of blocks as needed to achieve the desired processing granularity, speed, and / or chip density.

[0058] As shown in the figure, each word line 211a-n can be composed of multiple segments (e.g., segments 2111a, ..., 2111b of word line 211a, segments 2113a, ..., 2113b of word line 211n, etc.). Each segment can be located in a corresponding block. For example, the first segment 2111a and the second segment 2111b of word line 211a are located in the first block 201 and the second block 203, respectively. The first segment 2111a of word line 211a is connected to the cross-point device 220(a, a), ..., 220(a, k). The second segment 2111b of word line 211a is connected to the cross-point device 220(a, j), ..., 220(a, nk).

[0059] Each word line 211a-n can be connected to the cross-point device of the first block 201 via switches 233a, ..., 233n (also referred to as the "first set of switches") to provide an input signal to it. The second segment of word line 211a-n can be connected to the cross-point device of the second block 203 via switches 235a, ..., 235n (also referred to as the "second set of switches") to provide an input signal to it. Each switch 233a, ..., 233n, 235a, ..., 235n can be selectively connected to ground. Therefore, a segment of word line 211a-n can be grounded or left floating via the corresponding switch 233a, ..., 233n, 235a, ..., 235n. For example, the first segment 2111a of word line 211a can be connected to switch 233 and grounded via switch 233a. When switch 233a is open, the first segment 2111a of word line 211a is left floating. As another example, the second segment 2111b of word line 211a can be connected to switch 235a and grounded through switch 235a. When switch 235a is closed, word line 2111b is left floating.

[0060] As described above, one or more crosspoint devices in cross circuit 200b can be selected for programming and / or memory computation. Digital input signals (e.g., binary input) can be applied to the selected crosspoint device by connecting word segments to the selected crosspoint device. The digital input signals may include one or more bits (e.g., a series of bits), which can be applied to the selected crosspoint device serially (e.g., one bit at a time). For example, a "1" bit can be provided as an input to the first crosspoint device 220 (a, a) by grounding the first segment 2111a of word line 211a via switch 233a. In some embodiments, a "1" bit can be provided to the first segment 2111a of word line 211a when switch 235a is open and switch 233a is closed. Similarly, a "1" bit can be provided to the second crosspoint device 220 (a, j) by grounding the second segment 2111b of word line 211a. As another example, a "0" bit can be provided to the first crosspoint device 220 (a, a) by leaving the first segment 2111a of word line 211a floating. For example, switch 233a is closed and not connected to ground. Similarly, by leaving the second segment 2111b of word line 211a floating (e.g., by disconnecting switch 235a from ground), the "0" bit can be provided to the second crosspoint device 220(a, j).

[0061] Figure 2BThe crossover circuit architecture shown does not accumulate word line current during memory computation operations, thus significantly reducing IR drop and supporting routing with minimal metal width. This reduces parasitic capacitive loads on word lines and minimizes vector-matrix multiplication (VMM) operation errors caused by IR drop. Furthermore, the independent block control scheme effectively decouples bit lines, minimizing leakage current between bit lines. This improves the accuracy of VMM operations performed by the crossover circuit 200b. Figure 2B The scheme described simplifies system configuration and eliminates the need for a buffer to generate the reference voltage.

[0062] Figure 3 This is a flowchart illustrating an example method of performing in-memory computation using a crossover circuit according to some embodiments of this disclosure. The crossover circuit may be, for example... Figure 2A The cross circuit 200a in the middle.

[0063] In step 310, the current bit of the digital input can be decoded. The current bit can be a "0" bit or a "1" bit. The digital input may include a series of bits. In some embodiments, the digital input may represent the input vector X used to perform the vector-matrix multiplication (VMM) operation Y=XA.

[0064] In some embodiments, when the current bit of the digital input is "0", process 300 can proceed to step 315 by sending a word line (e.g., to the crosspoint device) connected to the word line. Figure 2A The word line 211a) applies a reference voltage to provide the current bit to the cross-point device (e.g., Figure 2A The cross-point device 220(a, a) in the middle. The reference voltage can correspond to the bit line applied to the connection of the cross-point device (e.g., Figure 2A The read voltage of bit line 213a in the code. For example, the reference voltage can be the same as or approximately the same as the read voltage applied to the bit line. The reference voltage can be provided by a buffer (e.g., Figure 2A The buffer 240 in the buffer is generated. In some embodiments, it can be generated by a switch (e.g., Figure 2A Switch 231a) in the middle connects the word line to the reference voltage to apply the reference voltage.

[0065] In some embodiments, when the current bit of the digital input is "1", process 300 can proceed to step 320, providing the current bit to the crosspoint device by grounding the word line connected to the crosspoint device. For example, this can be achieved by turning on the switch connected to the word line (e.g., ...). Figure 2A The input of switch 231a) is switched to ground to achieve grounding.

[0066] In step 330, one or more outputs of the cross circuit are generated. For example, an output sensor connected to a bit line can be turned on (e.g., Figure 1A The output sensor 140 generates one or more digital outputs representing the current flowing through the bit line.

[0067] In step 340, it is determined whether the current bit is the last bit of the numeric input. If the current bit is the last bit of the numeric input, process 300 can end. Otherwise, process 300 can return to step 310 and decode the next bit of the numeric input.

[0068] Figure 4 This is a flowchart illustrating an example method of performing in-memory computation using a crossover circuit according to some embodiments of this disclosure. The crossover circuit includes intersections of multiple word lines and multiple bit lines, as well as an array of crossover point devices. The crossover circuit can be, for example... Figure 2B The cross circuit 200b in the middle.

[0069] In step 410, the current bit of the digital input can be decoded. The current bit can be "0" or "1". The digital input can include a series of bits. In some embodiments, the digital input can represent the input vector X used to perform the vector-matrix multiplication (VMM) operation Y=XA.

[0070] In some embodiments, when the current bit of the digital signal is "1", process 400 can proceed to step 415, providing the current bit to the crosspoint device by grounding the word line segment connected to the crosspoint device. For example, to provide "1" (i.e., the "first bit") to... Figure 2B The first cross-point device 220(a, a) in the middle can be connected to the first switch of the first segment of the word line (e.g., Figure 2B Switch 233a) grounds the first segment 2111a of word line 211a. Similarly, in order to provide "1" (i.e., the "third bit") to... Figure 2B The second cross-point device 220(a, j) in the middle can be connected to a second switch (e.g., the second switch of the second segment of the word line) via a connection to the second switch of the second segment of the word line. Figure 2B Switch 235a) grounds the second segment 2111b of the word line.

[0071] In some embodiments, when the current bit of the digital signal is "0", process 400 can proceed to step 420, providing the current bit to the crosspoint device by setting the word segment to floating. For example, to provide "0" (i.e., the "second bit") to... Figure 2B The first crossover device 220(a, a) in the middle can set the first segment 2111a of word line 211a to floating by disconnecting the first switch 233a from ground (e.g., turning off the switch). As another example, in order to provide "0" (i.e., "fourth bit") to Figure 2BThe second cross point device 220(a, j) in the middle can set the second segment 2111b of word line 211a to be floating by disconnecting the connection of the second switch 235a to ground (e.g., turning off the switch).

[0072] In step 430, one or more outputs of the cross circuit are generated. For example, an output sensor connected to a bit line can be turned on (e.g., Figure 1A The output sensor 140 in the middle generates one or more digital outputs, which represent the current flowing through the bit line.

[0073] In step 440, it is determined whether the current bit is the last bit of the numeric input. If the current bit is the last bit of the numeric input, process 400 can end. Otherwise, process 400 can return to step 410 to decode the next bit of the numeric input.

[0074] For simplicity, the methods of this disclosure are shown and described as a series of operations. However, these operations may occur in different orders and / or simultaneously, and may include other operations not shown. Furthermore, it is not necessary to perform all the operations to implement the methods of this disclosure. Those skilled in the art will also understand that these methods can be represented by state diagrams or related states in events.

[0075] As used herein, the terms “approximately,” “about,” and “substantially” can mean within normal tolerances in the art, for example, within two standard deviations of the mean in some embodiments, within ±20% of the target size in some embodiments, within ±10% of the target size in some embodiments, within ±5% of the target size in some embodiments, within ±2% of the target size in some embodiments, within ±1% of the target size in some embodiments, and within ±0.1% of the target size in some embodiments. The terms “approximately” and “about” can include the target size. Unless specifically stated or obvious from the context, all numerical values ​​described herein are modified by the term “about.”

[0076] The ranges used in this article include all values ​​within the range. For example, the range 1 to 10 can include any number, combination of numbers, subranges such as 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10 and their fractions.

[0077] Numerous details have been provided in the foregoing description. However, it will be apparent that this disclosure can be practiced without these specific details. In some cases, to avoid complicating this disclosure, well-known structures and apparatuses have been shown in block diagram form rather than in detailed description.

[0078] The terms “first,” “second,” “third,” “fourth,” etc., used in this article are intended as labels to distinguish different elements and do not necessarily have a meaning based on numerical order.

[0079] As used herein, the terms “example” or “instance” are meant as examples, instances, or illustrations. Any aspect or design described as an “example” or “instance” is not necessarily superior to other aspects or designs. Rather, the purpose of using these terms is to present concepts in a concrete form. In this document, the word “or” is intended to mean “inclusive or” rather than “exclusive or”. That is, unless otherwise stated or clearly understood from the context, “X includes A or B” is intended to mean any naturally inclusive permutation, i.e., “X includes A or B” holds true if X includes A, X includes B, or X includes both A and B. Furthermore, the articles “a” and “an” used herein and in the appended claims should generally be interpreted as “one or more” unless otherwise stated or clearly understood from the context to be in the singular form.

[0080] In this document, when a component or layer is described as being "on" another component or layer, that component or layer may be directly on the other component or layer, or there may be intermediate components or layers. Conversely, when a component or layer is described as being "directly on" another component or layer, there are no intermediate components or layers.

[0081] While those skilled in the art will undoubtedly discover many alterations and modifications to this disclosure after reading the foregoing description, it should be understood that any particular embodiment shown and described by way of example is in no way intended to limit this disclosure. Therefore, references to details of various embodiments are not intended to limit the scope of the claims, which themselves merely set forth features believed to be part of this disclosure.

Claims

1. An apparatus comprising: Multiple bit lines, which intersect with multiple word lines; Multiple cross-point devices, wherein each cross-point device is connected to at least one word line of the multiple word lines and at least one bit line of the multiple bit lines, and each cross-point device includes a resistive random access memory (RRAM) device. as well as Multiple switches are connected to the multiple word lines, wherein each of the switches can be selectively connected to ground or a reference voltage.

2. The apparatus of claim 1, wherein, The first switch of the plurality of switches is connected to the first word line of the plurality of word lines; when the first bit of the digital input is applied to the first crossover device, the first switch is connected to ground, and the first crossover device is connected to the first word line.

3. The apparatus of claim 2, wherein, When the second bit of the digital input is applied to the first cross-point device, the first switch is connected to the reference voltage.

4. The apparatus of claim 3, wherein the first bit of the digital input is "1" and the second bit of the digital input is "0".

5. The apparatus of claim 2, wherein, The first terminal of the first RRAM device is connected to the first word line, and the second terminal of the first RRAM device is connected to the source or drain of the transistor.

6. The apparatus of claim 2, wherein, The reference voltage corresponds to the read voltage applied to the bit line connected to the first crossover point device.

7. The apparatus of claim 1, further comprising a buffer for generating a reference voltage, wherein the output of the buffer is selectively connected to the plurality of switches.

8. The apparatus of claim 7, wherein, The buffer is a unity-gain amplifier.

9. The apparatus of claim 1, wherein, The multiple switches include multiple multiplexers.

10. A method for performing in-memory computation using a crossover circuit, comprising: A reference voltage is applied to a first word line to provide a "0" bit of a digital input to a first crossover device; wherein the crossover circuit includes multiple word lines that intersect with multiple bit lines; wherein the first crossover device is connected to the first word line and the first bit line; the reference voltage corresponds to a read voltage applied to the first bit line; and By grounding the first word line, the "1" bit of the digital input is provided to the first cross-point device.

11. The method of claim 10, further comprising generating the reference voltage via a unity-gain amplifier.

12. The method of claim 10, wherein, Applying a reference voltage to the first word line connected to the first crossover device includes connecting the input of a switch to the reference voltage, wherein the output of the switch is connected to the first word line.

13. The method of claim 12, wherein, Grounding the first word line includes connecting the input of the switch to ground.

14. An apparatus comprising: A first group of bit lines and a second group of bit lines, wherein the first group of bit lines and the second group of bit lines intersect with multiple word lines; A first switch is used to selectively connect the first segment of one of the plurality of word lines to ground; A second switch is used to selectively ground the second segment of the first word line; The first set of cross-point devices is connected to the first segment of the first word line and the first set of bit lines; as well as The second set of cross-point devices is connected to the second segment of the first word line and the second set of bit lines.

15. The apparatus of claim 14, wherein, Each of the first group of cross-point devices and the second group of cross-point devices includes an RRAM device.

16. The apparatus of claim 14, wherein, When the first switch is closed, the first segment of the first word line is suspended.

17. The apparatus of claim 16, wherein, When the second switch is closed, the second segment of the first character line is suspended.

18. A method for performing in-memory computation using a crossover circuit, comprising: By grounding the first segment of the first word line, the first bit is provided to the first cross point device in the cross circuit; as well as By setting the first segment of the first word line to be floating, the second bit is provided to the first crossover device, wherein the crossover circuit includes multiple word lines that intersect with multiple bit lines, wherein the first crossover device is connected to the first word line and the first bit line among the multiple bit lines.

19. The method of claim 18, further comprising providing a third bit to the second crosspoint device by grounding a second segment of the first word line, wherein, The second crossover device is connected to the first word line and the second bit line among the plurality of bit lines.

20. The method of claim 19, further comprising providing a fourth bit to the second crossover device by setting a second segment of the first word line to be floating.

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