Multi-channel synchronous sampling system for weak current detection and control method thereof

Abstract

The invention provides a multi-channel synchronous sampling system for weak current detection and a control method thereof. According to the method, a low-noise trans-impedance amplifier array is used for converting multiple paths of weak current signals into multiple paths of analog voltage signals; at least one reference channel for outputting reference noise data; the synchronous analog-to-digital conversion array is used for synchronously sampling the multi-path analog voltage signals and the reference noise data after receiving the global conversion starting signal sent by the field programmable gate array, and converting the multi-path analog voltage signals and the reference noise data into multi-path synchronous first digital data to be output; the field programmable gate array is used for receiving the first digital data and carrying out delay compensation and amplitude correction on the first digital data to obtain multiple paths of time-aligned and amplitude-normalized second digital data; and a filter for referencing the first digital data converted from the reference noise data and eliminating the common-mode noise component in the second digital data to output purified third digital data.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data detection, in particular to a multi-channel synchronous sampling system for weak current detection and a control method thereof. BACKGROUND

[0002] In the field of cutting-edge scientific research and high-end industrial detection, such as the readout of silicon photomultiplier array in high-energy physics experiments, single-molecule fluorescence detection, next-generation DNA sequencing, and precise detection of semiconductor wafer defects, etc., it is often necessary to collect and analyze the weak current of nano-ampere to pico-ampere level generated by dozens or even hundreds of channels simultaneously with high fidelity and high synchronization. These current signals have the characteristics of extremely small amplitude, extremely high source impedance, and are easily affected by environmental electromagnetic interference, and the accurate timing relationship between the signals of each channel often carries key physical or process information. Therefore, developing a current detection system that can simultaneously realize ultra-low noise, multi-channel expansion, high-precision synchronization, and long-term stable and reliable operation is the key to promoting the technological progress in related fields.

[0003] Currently, in response to the demand for multi-channel synchronous acquisition, some technical solutions have been proposed. For example, one solution uses a mechanism based on trigger signal loopback and feedback to calibrate the transmission delay between multiple modules, and achieves synchronization alignment by introducing an internal calibration signal source and a feedback measurement loop in the system. Another common solution relies on an external high-precision signal source to generate a standard calibration signal, and an FPGA to compensate for the amplitude and phase of the data collected by the ADC, thereby achieving consistency and synchronization between channels. However, these existing technical solutions still have obvious limitations and cannot meet the use requirements.

[0004] Therefore, the present application provides a multi-channel synchronous sampling system for weak current detection and a control method thereof to solve one of the above technical problems. SUMMARY

[0005] The present application aims to provide a multi-channel synchronous sampling system for weak current detection and a control method thereof, which can solve at least one of the above technical problems. The specific scheme is as follows: According to the specific embodiments of the present application, in a first aspect, the present application provides a control method of a multi-channel synchronous sampling system for weak current detection, comprising: The low-noise trans-impedance amplifier array is used for converting multiple weak current signals into multiple analog voltage signals; at least one reference channel is used for outputting reference noise data; a synchronous analog-digital conversion array is used for synchronously sampling the multiple analog voltage signals and the reference noise data and converting them into multiple synchronous first digital data outputs after receiving a global conversion start signal sent by a field programmable gate array; the field programmable gate array is used for receiving the first digital data, performing delay compensation and amplitude correction on the first digital data, and obtaining multiple second digital data which are time-aligned and amplitude-normalized; and the common-mode noise components in the second digital data are eliminated by taking the first digital data converted from the reference noise data as a reference to output third digital data which is purified; wherein the synchronous analog-digital conversion array comprises multiple analog-digital converter chips driven by the same clock source, and the conversion start pins of each analog-digital converter chip are connected in parallel for uniformly receiving the global conversion start signal.

[0006] In an embodiment, the low-noise trans-impedance amplifier array, the reference channel and the synchronous analog-digital conversion array are connected in the following manner: each output end of the low-noise trans-impedance amplifier array is connected to a first analog input channel of the synchronous analog-digital conversion array, and the first analog input channels connected by different output ends are different; the input end of each reference channel is short-circuited, and the output end is connected to a second analog input channel of the synchronous analog-digital conversion array; wherein the first analog input channels and the second analog input channels are different, and the second analog input channels connected by different reference channels are different.

[0007] In an embodiment, the field programmable gate array and the synchronous analog-digital conversion array are connected based on the following lines, including: a first line for transmitting a control command, the control command at least including the global conversion start signal; and a second line for transmitting the first digital data.

[0008] In an embodiment, the first line includes: a global conversion start signal line for distributing a single pulse signal generated by the field programmable gate array to the conversion start pins of each analog-digital converter chip; and a group of serial peripheral interface buses for the field programmable gate array to configure parameters and read states of each analog-digital converter chip in the synchronous analog-digital conversion array. Wherein, after each analog-digital converter chip is connected in parallel through the conversion start pins, the global conversion start signal line and the control pin of the field programmable gate array are connected.

[0009] In one embodiment, the second circuit comprises: a group of main signal links, wherein each main signal link is configured to transmit a first digital data converted from the analog voltage signal; and at least one reference link, wherein each reference link is configured to transmit a first digital data converted from the reference noise data; and wherein each digital data output of the synchronous analog-digital conversion array is connected to a data receiving end of the FPGA via a main signal link or a reference link, and the data receiving ends connected by different links are different.

[0010] In one embodiment, the delay compensation and amplitude correction of the first digital data to obtain a plurality of time-aligned and amplitude-normalized second digital data comprises: performing delay compensation on the first digital data of each channel based on a pre-stored fixed transmission delay parameter corresponding to each link to align the first digital data on the time axis; and performing a linear operation on the time-aligned first digital data using a pre-stored gain coefficient and offset corresponding to the channel to obtain a plurality of time-aligned and amplitude-normalized second digital data.

[0011] In one embodiment, each channel for converting a weak current signal in the low-noise trans-impedance amplifier array is arranged in a separate area in the circuit layout, and a ground protection ring is arranged around each area.

[0012] In one embodiment, the elimination of the common-mode noise component in the second digital data comprises: using the first digital data corresponding to the reference channel as a noise reference to eliminate the common-mode noise component from the second digital data through adaptive filtering.

[0013] In one embodiment, the FPGA is further configured to: form an input vector from the data of a plurality of channels in the second digital data; perform a product operation on the input vector and a pre-set crosstalk suppression matrix, and update the second digital data based on the operation result before eliminating the common-mode noise component in the second digital data.

[0014] According to the specific embodiments of the present application, in a second aspect, the present application provides a multi-channel synchronous sampling system for weak current detection, which is applied to the system of any one of the first aspect and comprises: inputting the plurality of weak current signals into the low-noise trans-impedance amplifier array to convert the plurality of weak current signals into the plurality of analog voltage signals; inputting the plurality of analog voltage signals and the reference noise data output by at least one reference channel into the synchronous analog-digital conversion array; sending a global conversion start signal from the field programmable gate array to the synchronous analog-to-digital conversion array, so that the synchronous analog-to-digital conversion array synchronously samples and converts the plurality of analog voltage signals and the reference noise data to obtain a plurality of first digital data in response to the global conversion start signal; The synchronous analog-to-digital conversion array comprises a plurality of analog-to-digital converter chips driven by the same clock source, and conversion start pins of each of the analog-to-digital converter chips are connected in parallel to uniformly receive the global conversion start signal. The field programmable gate array is configured to input the first digital data obtained by the synchronous analog-to-digital conversion array, to delay compensate and amplitude correct the first digital data to obtain a plurality of second digital data which are time-aligned and amplitude-normalized, and to eliminate common-mode noise components in the second digital data by referring to first digital data converted from the reference noise data, and output third digital data after purification.

[0015] Compared with the prior art, the above scheme of the embodiment of the present application has at least the following beneficial effects: The present application provides a multi-channel synchronous sampling system for weak current detection. On the one hand, a single global conversion start signal is generated by a field programmable gate array, and all analog-to-digital converter chips are directly driven to start synchronously in parallel, so that hardware-level nanosecond synchronization is realized without interrupting the acquisition process, thereby meeting the requirement of continuous monitoring for uninterrupted data. On the other hand, a special reference channel with an internal input end short-circuit is used to collect common-mode noise in real time, which is used as an internal reference. The field programmable gate array dynamically eliminates environmental noise in the main signal through adaptive filtering, so that the system is completely free from dependence on unstable external calibration signal sources, establishes self-sustaining real-time calibration capability, and ensures high reliability and stability of long-term measurement. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A flowchart of a control method of a multi-channel synchronous sampling system for weak current detection is shown; Figure 2 A specific system overall architecture block diagram is exemplarily shown; Figure 3 A single-channel protection ring layout schematic diagram is exemplarily shown; Figure 4 An internal block diagram of AD4858 is exemplarily shown; Figure 5 An FPGA core algorithm processing pipeline block diagram is shown; Figure 6 A unit block diagram of a multi-channel synchronous sampling system for weak current detection according to the embodiment of the present application is shown. DETAILED DESCRIPTION

[0017] To make the objectives, technical solutions and advantages of the present application clearer, the following further describes the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, any other embodiments obtained by a person of ordinary skill in the art without creative effort should fall into the scope of the present application.

[0018] The terms used in the embodiments of the present application are only for the purpose of describing particular embodiments and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. "Plural" generally contains at least two.

[0019] It should be understood that the term "and / or" used herein only describes an association relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0020] It should be understood that although the terms first, second, third, etc. can be used in the embodiments of the present application, these descriptions should not be limited to these terms. These terms are only used to distinguish the description. For example, without departing from the scope of the embodiments of the present application, the first can also be called the second, and similarly, the second can also be called the first.

[0021] Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined" or "if (a stated condition or event) is detected" can be interpreted as "when it is determined" or "in response to determining" or "when (a stated condition or event) is detected" or "in response to detecting (a stated condition or event)".

[0022] It should also be noted that the terms "comprise", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the product or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such product or system. Without more limitations, the element defined by the sentence "comprises a" does not exclude the existence of other identical elements in the product or system including the element.

[0023] It is particularly important to note that the symbols and / or numbers present in the description, if not marked in the description, are not figure marks.

[0024] In the field of multi-channel high-speed data acquisition, especially in the application of weak signal detection, it is a key challenge to achieve high-precision synchronous acquisition and long-term stable measurement among multiple channels. There are various solutions in the prior art to try to solve this problem. One common solution is to use a trigger synchronization automatic calibration architecture. This solution usually includes a trigger feedback circuit and an internal calibration signal generation circuit, which measures the transmission delay of the trigger link and aligns the delay among channels using the internally generated calibration signal (such as a clock of a specific frequency). The advantage is that the synchronization accuracy is high, and the system scalability is good. However, the calibration process of this solution needs to switch the system to a dedicated internal calibration mode, and the normal signal acquisition task must be interrupted during this process. This mode interruption makes it impossible for the system to perform real-time or background calibration in a continuous acquisition state, so it is difficult to apply to long-term monitoring or real-time closed-loop control scenarios that require uninterrupted data.

[0025] Another widely used approach is to rely on an external high-precision signal source for system calibration. In such a system, a separate external signal source generates a standard calibration signal, which is collected by an analog-to-digital converter, and the amplitude and phase compensation of each channel data is performed in a field programmable gate array, thereby achieving synchronization. Although this method has high calibration efficiency, the calibration reference of the entire system is completely based on the absolute accuracy and stability of the external signal source. In actual complex industrial measurement environments, the external signal source may cause the output signal quality to decline due to its own performance drift, aging, or connection line faults. Since the system itself does not have the ability to verify and correct the calibration reference, the reliability and accuracy of long-term measurement cannot be guaranteed, and the requirement for system self-sufficiency in high-reliability applications cannot be met.

[0026] In view of this, a multi-channel synchronous sampling system for weak current detection is applied, which synchronously solves the above technical problems from two aspects of hardware architecture and processing algorithm. On the one hand, a single global conversion start signal is generated by a field programmable gate array, and all analog-to-digital conversion chips are directly driven in parallel to start synchronously, realizing hardware-level nanosecond synchronization without interrupting the acquisition process, thereby meeting the requirement of uninterrupted data for continuous monitoring. On the other hand, a special reference channel with an internal input terminal short circuit is used to collect common-mode noise in real time, which is used as an internal reference. The field programmable gate array dynamically eliminates environmental noise in the main signal through adaptive filtering, so that the system completely eliminates the dependence on unstable external calibration signal sources, establishes self-contained real-time calibration capability, and ensures high reliability and stability of long-term measurement.

[0027] The optional embodiments of the application will be described in detail below with reference to the accompanying drawings.

[0028] The embodiment of the application provides a multi-channel synchronous sampling system control method for weak current detection.

[0029] The embodiment of the application will be described below. Figure 1 The embodiment of the application will be described below.

[0030] Figure 1 A block diagram of a multi-channel synchronous sampling system control system for weak current detection is shown, as shown in Figure 1 As shown in the figure, the system 100 comprises a low-noise transimpedance amplifier array 101, a reference channel 102, a synchronous analog-to-digital conversion array 103, a field programmable gate array 104 and a clock source 105.

[0031] The low-noise transimpedance amplifier array 101 is used to convert multiple weak current signals into multiple analog voltage signals.

[0032] The reference channel 102 is used to output reference noise data.

[0033] For example, the application is provided with at least one reference channel 102, which is used to output common-mode noise such as power supply ripple, ground noise and environmental electromagnetic radiation as reference noise data.

[0034] The synchronous analog-to-digital conversion array 103 is used to synchronously sample the multiple analog voltage signals and the reference noise data and convert them into multiple synchronous first digital data outputs after receiving a global conversion start signal sent by the field programmable gate array 104.

[0035] The field programmable gate array 104 is used to receive the first digital data and perform delay compensation and amplitude correction on the first digital data to obtain multiple second digital data which are time-aligned and amplitude-normalized.

[0036] For example, the field programmable gate array 104 is also used to reference the first digital data converted from the reference noise data, eliminate the common-mode noise components in the second digital data, and output third digital data which is purified.

[0037] The synchronous analog-to-digital conversion array 103 comprises multiple analog-to-digital converter chips driven by the same clock source 105, and the conversion start pins of the analog-to-digital converter chips are connected in parallel and used to uniformly receive the global conversion start signal.

[0038] In the application, the low-noise transimpedance amplifier array 101 and the reference channel 102 are connected with the synchronous analog-to-digital conversion array 103, and the synchronous analog-to-digital conversion array 103 is connected with the field programmable gate array 104. In order to solve the related technical problems caused by the layout of the line in the related art, the connection between the modules is optimized in the following manner in the application.

[0039] For example, the low-noise transimpedance amplifier array 101 and the reference channel 102 are connected as follows: each output of the low-noise transimpedance amplifier array 101 is connected to a first analog input channel of the synchronous analog-to-digital converter array 103, and the first analog input channels connected to different outputs are different; the input of each reference channel 102 is shorted, and the output is connected to a second analog input channel of the synchronous analog-to-digital converter array 103.

[0040] The first analog input channel is different from the second analog input channel, and the second analog input channel connected to the different reference channels 102 is different.

[0041] In this embodiment of the application, the specific connection relationships between the low-noise transimpedance amplifier array 101 and the synchronous analog-to-digital converter array 103, and between the reference channel 102 and the synchronous analog-to-digital converter array 103 are given.

[0042] Specifically, for the low-noise transimpedance amplifier array 101 and the synchronous analog-to-digital converter array 103, it is specified that each output of the low-noise transimpedance amplifier array 101 exclusively occupies one analog input channel of the synchronous analog-to-digital converter array 103. In this way, the independence of each weak current signal on the transmission path is ensured through a point-to-point connection, and the mixing and crosstalk between analog signals are avoided from the physical connection.

[0043] For the reference channel 102 and the synchronous analog-to-digital converter array 103, when the reference channel 102 is not unique, different reference channels 102 are routed separately, providing a high-quality and pollution-free benchmark for the subsequent field-programmable gate array 104 to perform accurate adaptive noise cancellation, and further improving the overall suppression effect.

[0044] Furthermore, the reference channel 102 itself is required to have its input terminal shorted and connected to an independent and dedicated analog input channel in the analog-to-digital converter array. This method allows the channel to not receive any valid sensor signals, but only sense the common electromagnetic environment noise in which the system is located, thereby enabling it to output a pure noise reference signal that is highly correlated with the common-mode interference experienced by the main signal channel.

[0045] Furthermore, the wiring connections between the field-programmable gate array 104 and the synchronous analog-to-digital converter array 103 are shown below.

[0046] For example, the field-programmable gate array 104 and the synchronous analog-to-digital converter array 103 are connected based on the following lines, including a first line and a second line.

[0047] The first line is used to transmit control commands, and the second line is used to transmit the first digital data.

[0048] In some embodiments, the control commands include at least a global conversion start signal.

[0049] In some specific embodiments, the first line includes a global switching start signal line and a set of serial peripheral interface buses.

[0050] Among them, the global conversion start signal line is used to distribute the single pulse signal generated by the field programmable gate array 104 to the conversion start pin of each analog-to-digital converter chip, and the serial peripheral interface bus is used by the field programmable gate array 104 to configure parameters and read status of each analog-to-digital converter chip in the synchronous analog-to-digital converter array 103.

[0051] Each analog-to-digital converter chip is connected in parallel via a conversion start pin and then connected to the control pin of the field-programmable gate array 104 based on a global conversion start signal line.

[0052] In some specific embodiments, the second line includes a set of main signal links and at least one reference link.

[0053] Each main signal link is used to transmit one channel of first digital data based on analog voltage signal conversion, and each reference link is used to transmit one channel of first digital data based on reference noise data conversion.

[0054] Each digital data output of the synchronous analog-to-digital converter array 103 is connected to a data receiver of the field programmable gate array 104 through a main signal link or a reference link. The data receivers connected by different links are different.

[0055] In this embodiment, the physical connection lines between the field-programmable gate array 104 and the synchronous analog-to-digital converter array 103 are functionally divided. Specifically, this application divides the connection lines into a first line for transmitting control commands and a second line for transmitting high-speed digital data.

[0056] On the one hand, the first line is isolated from the high-speed, frequently switching data link, effectively preventing the switching noise during data transmission from interfering with the precision synchronization trigger signal, and ensuring the absolute accuracy and stability of the synchronization time.

[0057] The global conversion start signal line uses a single signal line connected in parallel to drive the start pins of all analog-to-digital converter (ADC) chips, achieving system-wide synchronous triggering with the simplest hardware routing. This configuration provides direct hardware assurance for achieving nanosecond-level synchronization accuracy. Simultaneously, a shared serial peripheral interface bus is used for parameter configuration and status management of all ADC chips. This bus is shared rather than exclusive, greatly simplifying the control interface complexity between the Field-Programmable Gate Array (FPGA) 104 and multiple ADC chips, reducing the number of required pins, and lowering the difficulty of printed circuit board routing and system cost.

[0058] On the other hand, the second line ensures that massive sampling data can be transmitted in parallel with high bandwidth and low latency, meeting the stringent requirements of high sampling rate and multi-channel systems for data throughput, while avoiding conflicts or delays caused by control commands and data streams competing for bandwidth.

[0059] The second line requires that each digital output of the synchronous analog-to-digital converter array 103 be connected to an independent data receiver of the field-programmable gate array 104 via a dedicated link. This dedicated line architecture ensures that each channel's sampled data has its own physical channel throughout the entire transmission process from the analog-to-digital converter output to the field-programmable gate array 104. Furthermore, this approach eliminates time-division multiplexing delays, bandwidth contention, and inter-channel crosstalk that may occur when multiple data streams share a bus or multiplexed link, guaranteeing that all channel data can be delivered to the processing core completely, in real-time, and without distortion in parallel.

[0060] In some embodiments, delay compensation can be performed using pre-stored fixed transmission delay parameters for each data link.

[0061] In some specific embodiments, delay compensation can be performed on the first digital data of the corresponding channel based on pre-stored fixed transmission delay parameters that correspond one-to-one with each link, so that the first digital data are aligned on the time axis.

[0062] In some embodiments, for the time-aligned first digital data, delay compensation can be performed on the time-aligned first digital data using the gain and offset parameters of each channel.

[0063] In some specific embodiments, pre-stored gain coefficients and offsets uniquely corresponding to the corresponding channels can be invoked to perform a linear operation on the time-aligned first digital data to obtain multiple time-aligned and amplitude-normalized second digital data.

[0064] As a specific embodiment, delay compensation and amplitude correction are performed on the first digital data to obtain multiple time-aligned and amplitude-normalized second digital data, including: performing delay compensation on the first digital data of the corresponding channel based on pre-stored fixed transmission delay parameters that correspond one-to-one with each link, so that each first digital data is aligned on the time axis; calling the pre-stored gain coefficient and offset that uniquely correspond to the corresponding channel to perform a linear operation on the time-aligned first digital data to obtain multiple time-aligned and amplitude-normalized second digital data.

[0065] In some embodiments, in the low-noise transimpedance amplifier array 101, each channel for converting weak current signals is arranged in an independent region in the circuit layout, and each region is surrounded by a grounded protective ring.

[0066] In this application, an adaptive filtering algorithm can be used to eliminate common-mode noise components.

[0067] In some embodiments, eliminating common-mode noise components in the second digital data includes: using the first digital data corresponding to the reference channel 102 as a noise reference, and eliminating common-mode noise components from the second digital data through adaptive filtering.

[0068] In some embodiments, before eliminating the common-mode noise component in the second digital data, the field-programmable gate array 104 is further configured to: construct an input vector from the data of multiple channels in the second digital data; perform a product operation on the input vector with a preset crosstalk suppression matrix; and update the second digital data based on the operation result.

[0069] For ease of understanding, the technical solution of the present invention will be described in detail below with reference to specific embodiments and accompanying drawings.

[0070] Figure 2 An example of a specific system architecture block diagram is shown.

[0071] Figure 3 An exemplary schematic diagram of a single-channel protection ring layout is shown.

[0072] This application provides a specific implementation of a multi-channel synchronous sampling system for weak current detection. For example... Figure 2 As shown, an exemplary system architecture block diagram is illustrated. The multi-channel synchronous sampling system is configured as a 32-channel nA-level current sensing system. This system includes a low-noise transimpedance amplifier array 101, at least one reference channel 102, a synchronous analog-to-digital converter array 103, and a field-programmable gate array 104.

[0073] As a specific embodiment, the low-noise transimpedance amplifier array 101 consists of 32 physically isolated transimpedance amplifier units. Each transimpedance amplifier unit uses an ADA4620 operational amplifier as its core. This operational amplifier has an input bias current of less than 1 pA and a voltage noise density of less than 3 nV / √Hz to meet the low-noise requirements of weak current detection. The feedback network of each unit consists of a 20 MΩ low-temperature coefficient precision metal film resistor connected in parallel with a 1 pF low-loss polypropylene film capacitor, used to accurately set the conversion gain and bandwidth. In the printed circuit board layout, each transimpedance amplifier unit is arranged in an independent area, and each area is surrounded by a grounded copper protective ring to achieve physical isolation and suppress surface leakage current and electromagnetic crosstalk. Figure 3 As shown, this illustrates the arrangement of the protective surround amplifier unit.

[0074] Figure 4 An example internal block diagram of the AD4858 is shown.

[0075] In this application, the synchronous analog-to-digital converter array 103 is used for synchronous sampling and digitization of analog voltage signals. In this embodiment, the array consists of four AD4858 8-channel successive approximation analog-to-digital converter chips, providing a total of 32 main signal analog input channels. Figure 4 As shown, these four analog-to-digital converter (ADC) chips are driven by the same clock. The conversion start pins of all ADC chips are connected in parallel via a strictly equal-length printed circuit board (PCB) trace. The other end of the trace is connected to an input / output pin of the field-programmable gate array (FPGA) 104 to receive a unified global conversion start signal. The digital data output of each ADC chip is connected to the FPGA 104 via an independent low-voltage differential signal link. These low-voltage differential signal links are routed on the PCB with a differential impedance of 100 ohms. A 100-ohm precision terminating resistor is connected in parallel between the receiving lines of each low-voltage differential signal link at one end of the FPGA 104 to eliminate signal reflections and ensure data transmission integrity. Additionally, the system includes a reference channel 102. The input of reference channel 102 is shorted to analog ground, and its output is connected to a reserved analog input channel of an AD4858 chip in the synchronous ADC array 103.

[0076] For example, the Field Programmable Gate Array (FPGA) 104 uses Xilinx Artix-7 series chips. The FPGA 104 is responsible for generating the global conversion start signal and serial peripheral interface bus timing, and configuring the operating parameters of the four AD4858 analog-to-digital converter chips through a shared serial peripheral interface bus and independent chip select signals. Simultaneously, the FPGA 104 receives digital data from the synchronous analog-to-digital converter array 103 through multiple independent low-voltage differential signal links and performs subsequent digital signal processing.

[0077] In this application, the system's workflow mainly includes three stages: initialization, delay calibration, and main acquisition loop. During initialization, the field-programmable gate array (FPGA) 104 configures the sampling rate, range, and other parameters of all analog-to-digital converter (ADC) chips via the serial peripheral interface bus. During delay calibration, the system applies a known step test signal to the input of all channels. The FPGA 104 sends a global conversion start signal to trigger synchronous sampling, then measures and records the time difference between the issuance of the start signal and complete reception of digital data from each low-voltage differential signal link. These time differences are stored in the internal memory as fixed transmission delay parameters for each link, used for subsequent configuration of the first-in-first-out (FIFO) memory compensation depth.

[0078] After initialization and calibration, the system enters the main acquisition loop. In the main acquisition loop, the field-programmable gate array (FPGA) 104 first generates a global conversion start signal pulse. This pulse simultaneously reaches the conversion start pins of all analog-to-digital converter (ADC) chips via equal-length traces, forcing the 32 main signal channels of the four chips to synchronously begin analog-to-digital conversion with one reference channel 102. After conversion, the digital data from each channel is transmitted to the FPGA 104 via their respective independent low-voltage differential signal links. The FPGA 104 performs delay compensation on the data from each channel according to pre-stored fixed transmission delay parameters, ensuring that all data points representing the same sampling moment are strictly aligned on the system's internal time axis.

[0079] After time alignment, the data enters the real-time digital signal processing flow. This flow is executed sequentially within the field-programmable gate array 104. The first step is programmable signal conditioning, i.e., amplitude correction. The field-programmable gate array 104 calls the pre-stored gain coefficient and offset uniquely corresponding to each channel and performs a linear operation on the time-aligned data of each channel: Data_corrected = Gain * Data_aligned + Offset. Here, Data_aligned represents the first digital data after time alignment, and Data_corrected represents the second digital data. This operation corrects the amplitude and DC deviation between channels caused by differences in front-end analog devices, achieving amplitude normalization. The second step is inter-channel crosstalk suppression. The system obtains a 32*32 crosstalk matrix H through offline calibration, describing the fixed coupling relationship between the 32 main channels in this embodiment.

[0080] In real-time processing, the field-programmable gate array 104 constructs the input vector X from the amplitude-corrected data of 32 channels, and calculates the output vector Y by solving Y = H_inv * X, where H_inv is the inverse matrix or compensation matrix of the crosstalk matrix H. The resulting output vector Y is the data after crosstalk cancellation. The third step is adaptive noise cancellation. The field-programmable gate array 104 uses the digital data acquired and converted in real time by the reference channel 102 as the noise reference signal, and the data of a certain main channel after crosstalk suppression as the desired response. The normalized least mean square adaptive filtering algorithm is used for processing. Each iteration of this algorithm is as follows: using the reference noise data vector as input, using the main channel data as the desired response, updating the filter weight vector according to the adaptive filtering formula, and after calculating the noise estimate at the current time, obtaining and outputting the purified signal by reducing the noise estimate.

[0081] After passing through the aforementioned processing pipeline, the final purified multi-channel digital signal is uploaded to the host computer via a high-speed interface interconnected with the high-speed peripheral components integrated in the FPGA 104, completing one full acquisition and processing cycle. The system operates in this cycle to achieve continuous, synchronous, and high-precision detection of multi-channel weak current signals.

[0082] The system provided in this application can achieve high-precision, high-synchronization, and low-noise acquisition of multi-channel nanoampere current signals without relying on external calibration sources during continuous operation.

[0083] In this application embodiment, the functions of each module of the system can be represented hierarchically. For example, this application achieves high performance through a hierarchical collaborative architecture, which comprises three progressively layered and interdependent functional levels from the signal source to the final data processing. Specifically, it can be represented as follows: Figure 2The modules are divided into first, second and third levels as shown.

[0084] As a feasible embodiment, the first stage of the system is a signal sensing and source purification stage, the core component of which is a low-noise transimpedance amplifier array 101. This array contains multiple transimpedance amplifier units used to convert multiple nA-level weak current signals into multiple analog voltage signals. The core of each transimpedance amplifier unit adopts a precision operational amplifier with an input bias current of less than 1 pA and a voltage noise density of less than 3 nV / √Hz, such as a JFET input type or self-stabilizing zero-type operational amplifier with low input bias current characteristics.

[0085] Each unit's feedback network consists of a low-temperature-coefficient precision metal film resistor with a resistance selectable from 1 MΩ to 10 GΩ, connected in parallel with a low-loss, low-dielectric-absorption thin-film capacitor. The thin-film capacitor can be, for example, a polypropylene or polystyrene capacitor. The feedback network is used to precisely set the conversion gain and bandwidth of each channel. To achieve high physical isolation, each transimpedance amplifier unit is arranged in an independent region on the printed circuit board, and each independent region is surrounded by a grounded guard ring. The guard ring effectively absorbs any potential surface leakage current. For applications with higher interference immunity requirements, the critical front-end circuitry containing the transimpedance amplifier unit can be placed in a separate metal-shielded cavity.

[0086] In addition, the input of the transimpedance amplifier unit is directly connected to the sensor via a coaxial connector or shielded twisted pair cable to ensure that the weak current signal is as free from external electromagnetic interference as possible before entering the high-impedance input node.

[0087] As a feasible embodiment, the second stage of the system is a synchronous sampling and hardware anti-interference stage, the core of which is a synchronous analog-to-digital converter array 103 and related synchronization and interface circuits. The input of this array is connected to the output of a low-noise transimpedance amplifier array 101 to convert multiple analog voltage signals into digital signals. The synchronous analog-to-digital converter array 103 uses one or more multi-channel, high-resolution successive approximation analog-to-digital converter chips as the core sampling unit. At the front end of each analog input pin of each analog-to-digital converter chip, an RC low-pass filter network composed of precision thin-film resistors and NPO ceramic capacitors is provided for differential-mode anti-aliasing filtering. The -3dB cutoff frequency of this RC network is calculated and determined based on the highest frequency component of the target signal and the sampling rate of the analog-to-digital converter. All analog-to-digital converter chips in the synchronous analog-to-digital converter array 103 are driven by the same ultra-low jitter clock source 105 to ensure that their timing references are from the same source.

[0088] For example, to achieve strict synchronous sampling across all channels, the field-programmable gate array 104 generates a common global conversion start signal. This signal is distributed in parallel to the conversion start pins of all analog-to-digital converter (ADC) chips via equal-length traces, thereby forcing all channels to latch the input signal and start the conversion process simultaneously in hardware. After conversion, the conversion data from each ADC chip is transmitted to the ADC 104 via its high-speed digital interface in the form of low-voltage differential signals through an independent data link.

[0089] In one specific implementation, the independent data link is a low-voltage differential signal link, and a 120-ohm terminating resistor is connected in parallel between each receiving line of the link at the field-programmable gate array 104 to ensure signal transmission integrity and anti-interference capability. Simultaneously, the field-programmable gate array 104 configures the parameters of all analog-to-digital converter chips in the array through a shared serial peripheral interface bus and addresses devices through independent chip select signals.

[0090] As a feasible embodiment, the third level of the system is an intelligent processing and data integration level, the core of which is a field-programmable gate array 104 and at least one reference channel 102. The input of the reference channel 102 is shorted, and its output is connected to a designated input channel of the synchronous analog-to-digital converter array 103 to provide reference noise data characterizing the environmental common-mode noise. The field-programmable gate array 104 is connected to multiple independent data links to receive multiple channels of raw digital data output from the synchronous analog-to-digital converter array 103, including data converted based on the main analog voltage signal and data converted based on the reference noise data. The field-programmable gate array 104 is configured to perform a series of processes, first generating the aforementioned global conversion start signal, and then performing delay compensation on the received multiple channels of raw digital data based on pre-stored fixed transmission delay parameters for each data link.

[0091] The fixed transmission delay parameter reflects the fixed time deviation introduced by the difference in physical length of each data link. It can be obtained by inputting a test signal to the system and measuring the transmission delay of each link by the field-programmable gate array 104. Through this compensation, data points representing the same physical sampling moment in all channels are strictly aligned on the internal time axis. Subsequently, the field-programmable gate array 104 uses pre-stored gain and offset parameters uniquely corresponding to each channel to perform amplitude correction on the time-aligned data, thereby eliminating inconsistencies in response caused by differences in front-end devices.

[0092] Based on this, the field-programmable gate array 104 uses the reference noise data obtained from the reference channel 102 to dynamically estimate and subtract the common-mode noise component from the amplitude-corrected main channel data through an adaptive filtering algorithm.

[0093] As a specific embodiment, the adaptive filtering algorithm can be implemented in the field-programmable gate array 104 using the normalized least mean square algorithm, thereby outputting a purified digital signal.

[0094] Figure 5 A block diagram of an FPGA core algorithm processing pipeline is shown.

[0095] For example, such as Figure 5 As shown, this application employs a real-time data processing and compensation pipeline to process the time-aligned raw data. This pipeline constructs an efficient digital signal processing flow within the FPGA, sequentially executing three core steps: configurable digital filtering and gain correction, digital suppression of inter-channel crosstalk, and adaptive noise cancellation based on reference channel 102.

[0096] In some embodiments, the system, based on the signal processing requirements of the application scenario, invokes a digital filter pre-stored within the FPGA to perform frequency domain conditioning on the time-aligned raw data. Then, a pre-configured programmable gain coefficient is applied to perform range normalization on the filtered and conditioned data. The digital filter can be a finite impulse response (FIR) filter or other digital filtering model with frequency domain conditioning capabilities. Its filtering parameters need to be pre-set according to the frequency characteristics of the target signal and stored in the FPGA's configuration memory. The programmable gain coefficient is configured through the FPGA's programmable logic resources. This coefficient is used to adjust the amplitude range of the filtered data to the range required by subsequent processing stages of the system, ensuring the accuracy and consistency of signal processing.

[0097] As a specific embodiment, the system pre-extracts crosstalk model parameters between channels. These parameters characterize the transmission characteristics of fixed coupling interference between channels and can be obtained and stored in the parameter storage area of ​​the FPGA through offline testing, system calibration, and other means.

[0098] In actual data processing, the aforementioned crosstalk model parameters are invoked, and digital algorithms are used to suppress fixed coupling interference in the data that has undergone frequency domain conditioning and gain correction. The acquisition of crosstalk model parameters requires offline testing based on factors such as the physical connection characteristics and circuit impedance matching of the multi-channel system. During testing, the interference coupling patterns between channels are recorded and fitted into a parameter form suitable for digital calculation. The digital algorithm can employ matrix operation-based interference cancellation algorithms or adaptive interference suppression algorithms. Its function is to accurately identify and cancel the fixed inter-channel interference components mixed into the original data using the crosstalk model parameters, thereby improving the purity of the effective signal.

[0099] In other embodiments, the system is specifically configured with 1-2 input terminals, which are electrically connected to the analog common ground to form a dummy reference channel 102. During actual operation, the dummy reference channel 102 outputs a reference signal containing common-mode noise in real time, while the main signal channel transmits the raw data to be processed. Then, an adaptive filtering algorithm is used to dynamically analyze the reference signal and the main signal channel data, estimating the shared environmental noise component, and subtracting this environmental noise component from the main signal channel data to improve the overall signal-to-noise ratio of the system. The hardware implementation of the dummy reference channel 102 must ensure that its input terminal is reliably connected to the analog common ground to acquire stable common-mode noise as the reference signal.

[0100] In some specific embodiments, the adaptive filtering algorithm can adopt a filtering model with adaptive characteristics, such as the least mean square (LMS) algorithm or the recursive least squares (RLS) algorithm. The input of the algorithm is the common-mode noise signal output by the reference channel 102 and the original data of the main signal channel. The output is the estimated environmental noise compensation signal. During the execution process, the algorithm will dynamically adjust its own parameters according to the changes in the signal to ensure the real-time tracking and elimination effect of environmental noise.

[0101] In the above embodiments, the real-time data processing and compensation pipeline can efficiently complete operations such as frequency domain conditioning, interference suppression and environmental noise elimination of the original data within the FPGA, which not only ensures the real-time performance of signal processing, but also improves the signal-to-noise ratio and purity of the effective signal, meeting the processing needs of multi-channel data in complex application scenarios.

[0102] This application also provides method embodiments that follow the above embodiments for controlling the system of the above embodiments. The interpretation of the same name meaning is the same as that of the above embodiments, and the same technical effects are achieved as those of the above embodiments. Therefore, they will not be repeated here.

[0103] like Figure 6 As shown, this application provides a multi-channel synchronous sampling method for weak current detection, such as... Figure 6 This includes the following steps: S601 inputs multiple weak current signals to a low-noise transimpedance amplifier array and converts them into multiple analog voltage signals.

[0104] S602: Input multiple analog voltage signals and reference noise data output from at least one reference channel to the synchronous analog-to-digital converter array.

[0105] S603: The field-programmable gate array sends a global conversion start signal to the synchronous analog-to-digital converter array, so that the synchronous analog-to-digital converter array responds to the global conversion start signal to synchronously sample and convert multiple analog voltage signals and reference noise data to obtain the first digital data of multiple synchronous signals.

[0106] The synchronous analog-to-digital converter array contains multiple analog-to-digital converter chips driven by the same clock source, and the conversion start pins of each analog-to-digital converter chip are connected in parallel to receive the global conversion start signal in a unified manner.

[0107] S604. Input the first digital data obtained from the synchronous analog-to-digital converter array to the field programmable gate array, so that the field programmable gate array performs delay compensation and amplitude correction on the first digital data to obtain multiple time-aligned and amplitude-normalized second digital data.

[0108] S605. Referencing the first digital data converted from the reference noise data, eliminate the common-mode noise component in the second digital data and output the purified third digital data.

[0109] Regarding the methods in the above embodiments, the specific details of the modules controlling each step have been described in detail in the embodiments of the relevant system, and will not be elaborated here.

[0110] Although the operations are described in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order or serial order shown, or requiring all of the operations shown to obtain the desired result. In certain environments, multitasking and parallel processing may be advantageous.

[0111] The system and control method of this application can be implemented using standard programming techniques, and various method steps can be implemented using rule-based logic or other logic. It should also be noted that the terms "system" and "module" as used herein and in the claims are intended to include implementations using one or more lines of software code and / or hardware implementations and / or devices for receiving input.

[0112] Any step, operation, or procedure described herein may be performed or implemented using one or more hardware or software modules, either alone or in combination with other devices. In one embodiment, the software module is implemented using a computer program product comprising a computer-readable medium containing computer program code, which is executable by a computer processor to perform any or all of the described steps, operations, or procedures.

[0113] The foregoing description of implementations of this application has been provided for illustrative and descriptive purposes. The foregoing description is not exhaustive and is not intended to limit this application to the exact forms disclosed. Various modifications and variations may exist in accordance with the foregoing teachings, or may arise from practice of this application. These embodiments were chosen and described to illustrate the principles of this application and its practical application, enabling those skilled in the art to utilize this application in various implementations and modifications to suit the specific purpose of the concept.

[0114] Regarding the system in the above embodiments, the specific ways in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0115] It can be further understood that, unless otherwise specified, "connection" includes both direct connections where no other components exist between the two parties and indirect connections where other components exist between them.

[0116] It is further understood that although the operations are described in a specific order in the accompanying drawings in the embodiments of this application, this should not be construed as requiring these operations to be performed in the specific order or serial order shown, or requiring all the operations shown to be performed to obtain the desired result. In certain environments, multitasking and parallel processing may be advantageous.

[0117] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the field of this application that are not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0118] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0119] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A multi-channel synchronous sampling system for weak current detection, characterized in that, include: Low-noise transimpedance amplifier arrays are used to convert multiple weak current signals into multiple analog voltage signals; At least one reference channel is provided for outputting reference noise data; A synchronous analog-to-digital converter array is used to synchronously sample the multiple analog voltage signals and the reference noise data after receiving a global conversion start signal sent by a field-programmable gate array, and convert them into multiple synchronous first digital data outputs. The field-programmable gate array is used to receive the first digital data and perform delay compensation and amplitude correction on the first digital data to obtain multiple time-aligned and amplitude-normalized second digital data. And to use first digital data converted from the reference noise data to eliminate common-mode noise components in the second digital data in order to output purified third digital data; The synchronous analog-to-digital converter array includes multiple analog-to-digital converter chips driven by the same clock source. The conversion start pins of each analog-to-digital converter chip are connected in parallel to receive the global conversion start signal.

2. The system according to claim 1, characterized in that, The low-noise transimpedance amplifier array, the reference channel, and the synchronous analog-to-digital converter array are connected in the following manner: Each output of the low-noise transimpedance amplifier array is connected to a first analog input channel of the synchronous analog-to-digital converter array, and the first analog input channels connected to different outputs are different. The input terminal of each of the reference channels is shorted, and the output terminal is connected to a second analog input channel of the synchronous analog-to-digital converter array; wherein the first analog input channel is different from the second analog input channel, and the second analog input channel connected to different reference channels is different.

3. The system according to claim 1, characterized in that, The field-programmable gate array and the synchronous analog-to-digital converter array are connected via the following lines: The first line is used to transmit control commands, which include at least the global conversion start signal; The second line is used to transmit the first digital data.

4. The system according to claim 3, characterized in that, The first line includes: A global conversion start signal line is used to distribute the single pulse signal generated by the field programmable gate array to the conversion start pin of each of the analog-to-digital converter chips; A set of serial peripheral interface buses is used by the field-programmable gate array to configure parameters and read status of each analog-to-digital converter chip in the synchronous analog-to-digital converter array. Each of the analog-to-digital converter chips is connected in parallel through the conversion start pin, and then connected to the control pin of the field-programmable gate array based on the global conversion start signal line.

5. The system according to claim 3, characterized in that, The second line includes: A set of main signal links; Each of the main signal links is used to transmit one channel of first digital data based on the analog voltage signal conversion; At least one reference link; Each of the reference links is used to transmit one channel of first digital data based on the reference noise data conversion; Each digital data output terminal of the synchronous analog-to-digital converter array is connected to a data receiver of the field-programmable gate array through a main signal link or a reference link, and the data receivers connected by different links are different.

6. The system according to claim 5, characterized in that, The step of performing delay compensation and amplitude correction on the first digital data to obtain multi-channel time-aligned and amplitude-normalized second digital data includes: Based on the pre-stored fixed transmission delay parameters that correspond one-to-one with each of the links, the first digital data of the corresponding channel is delayed to compensate for the delay so that each of the first digital data is aligned on the time axis. The pre-stored gain coefficient and offset, which are uniquely corresponding to the corresponding channel, are called to perform a linear operation on the time-aligned first digital data to obtain multiple time-aligned and amplitude-normalized second digital data.

7. The system according to claim 1, characterized in that, In the low-noise transimpedance amplifier array, each channel for converting weak current signals is set in an independent area in the circuit layout, and each area is surrounded by a grounded protective ring.

8. The system according to claim 1, characterized in that, The elimination of common-mode noise components in the second digital data includes: Using the first digital data corresponding to the reference channel as a noise reference, common-mode noise components are eliminated from the second digital data through adaptive filtering.

9. The system according to claim 8, characterized in that, Before eliminating the common-mode noise component in the second digital data, the field-programmable gate array is also used to: The data from multiple channels in the second digital data are used to form an input vector; The input vector is multiplied by a preset crosstalk suppression matrix, and the second digital data is updated based on the result.

10. A control method for a multi-channel synchronous sampling system for weak current detection, characterized in that, The method, applied to the system of any one of claims 1 to 9, comprises: The multiple weak current signals are respectively input to the low-noise transimpedance amplifier array and converted into the multiple analog voltage signals; The multi-channel analog voltage signals and the reference noise data output from at least one of the reference channels are input to the synchronous analog-to-digital converter array; The field-programmable gate array sends a global conversion start signal to the synchronous analog-to-digital converter array, so that the synchronous analog-to-digital converter array responds to the global conversion start signal to synchronously sample and convert the multiple analog voltage signals and the reference noise data to obtain the first digital data of multiple synchronous signals. The synchronous analog-to-digital converter array includes multiple analog-to-digital converter chips driven by the same clock source, and the conversion start pins of each analog-to-digital converter chip are connected in parallel to receive the global conversion start signal in a unified manner. The first digital data obtained by the synchronous analog-to-digital converter array is input to the field-programmable gate array (FPGA) so that the FPGA performs delay compensation and amplitude correction on the first digital data to obtain multiple time-aligned and amplitude-normalized second digital data. The common-mode noise component in the second digital data is eliminated by referring to the first digital data converted from the reference noise data, and the purified third digital data is output.

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