Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, the array substrate comprises a plurality of scanning lines and a plurality of data lines, and the scanning lines and the data lines are staggered to define a plurality of sub-pixels. Each sub-pixel comprises a first grid electrode, a second grid electrode, an active layer, a source electrode and a drain electrode. The first gate and the second gate are electrically connected with the scanning line. The active layer comprises a first channel part overlapped with the first grid electrode, a second channel part overlapped with the second grid electrode and an extension part overlapped with the scanning line, the first channel part is connected with the second channel part, and the extension part is connected with the first channel part. The source is electrically connected with the first channel part and the data line, and the drain is electrically connected with the second channel part. The first grid electrode, the first channel part, the source electrode and the drain electrode form a first thin film transistor, the second grid electrode, the second channel part, the source electrode and the drain electrode form a second thin film transistor, and the extension part and the scanning line form a capacitor.

Description

Technical Field

[0001] The present invention relates to an array substrate and a display panel, and particularly to an array substrate and a display panel comprising an extension of an active layer and a capacitor formed by scan lines. Background Technology

[0002] Variable refresh rate (VRR) panels adjust the screen refresh rate according to the actual content being displayed, rather than being fixed at 90 or 120 Hz. This is because with a fixed refresh rate, even when displaying static content (such as images), the screen refreshes at a fixed frequency, increasing power consumption. Using variable refresh rate panel technology, such as a 1 Hz low refresh rate (LRR) panel, can significantly reduce power consumption. However, with low refresh rate display panels, the extended off-time of the thin-film transistors (TFTs) in the sub-pixels of the array substrate causes leakage, resulting in screen flicker and affecting display quality. Furthermore, the TFTs in the array substrate sub-pixels can also experience leakage due to exposure to the backlight module or external light, affecting their electrical performance. Summary of the Invention

[0003] At least one embodiment of the present invention provides an array substrate and a display panel that can reduce leakage current in thin-film transistors in sub-pixels, thereby improving electrical performance and display quality.

[0004] At least one embodiment of the present invention provides an array substrate comprising a substrate, a plurality of scan lines, and a plurality of data lines. The scan lines are located on the substrate and extend along a first direction, while the data lines are located on the substrate and extend along a second direction, the first and second directions being different. The scan lines and data lines interleave to define a plurality of sub-pixels. Each sub-pixel includes a first gate, a second gate, an active layer, a source, and a drain. The first gate and the second gate are located on the substrate and electrically connected to one of the scan lines. The active layer is located on the substrate and includes a first channel portion, a second channel portion, and a first extension portion. Along the normal to the substrate, the first channel portion overlaps with the first gate, the second channel portion overlaps with the second gate, and the first extension portion overlaps with one of the scan lines. The first channel portion connects to the second channel portion, and the first extension portion connects to the first channel portion. The source is located on the active layer and electrically connected to one of the first channel portion and the data lines, and the drain is located on the active layer and electrically connected to the second channel portion. A first gate, a first channel portion, a source, and a drain form a first thin-film transistor; a second gate, a second channel portion, a source, and a drain form a second thin-film transistor; and a first extension portion and one of the aforementioned scan lines form a first capacitor.

[0005] In at least one embodiment of the present invention, on the normal line of the substrate, the area of ​​the first extension overlapping with one of the plurality of scan lines is 2 to 20 times the sum of the area of ​​the first channel portion overlapping with the first gate and the area of ​​the second channel portion overlapping with the second gate.

[0006] In at least one embodiment of the present invention, each of the sub-pixels further includes a masking metal layer located between the substrate and the active layer. The orthographic projections of the first channel portion and the second channel portion onto the substrate are both located within the orthographic projection of the masking metal layer onto the substrate. The orthographic projection of the portion of the first extension portion that overlaps with one of the plurality of scan lines on the normal of the substrate onto the substrate is located outside the orthographic projection of the masking metal layer onto the substrate.

[0007] In at least one embodiment of the present invention, each of the sub-pixels further includes a masking metal layer located between the substrate and the active layer, wherein the orthographic projections of the first channel portion, the second channel portion, and the first extension portion onto the substrate are all located within the orthographic projection of the masking metal layer onto the substrate.

[0008] In at least one embodiment of the present invention, the first gate extends along the first direction, the second gate extends along the second direction, the first channel portion extends along the second direction, the second channel portion extends along the first direction, and the first extension portion extends along the first direction.

[0009] In at least one embodiment of the present invention, the first gate and the second gate and one of the plurality of scan lines are formed by the same conductive layer, and the width of the first gate and the width of the second gate are both smaller than the width of one of the plurality of scan lines.

[0010] In at least one embodiment of the present invention, the ratio of the width of one of the plurality of scan lines to the width of the first gate and the ratio of the width of one of the plurality of scan lines to the width of the second gate are both 1.5 to 2.5.

[0011] In at least one embodiment of the present invention, the first extension includes a first main body and a first neck connecting the first channel and the first main body, the first main body overlaps with one of the plurality of scan lines, the first neck overlaps with the first gate, and the width of the first neck is not greater than the width of the first main body.

[0012] In at least one embodiment of the present invention, the ratio of the width of the first neck to the width of the first channel portion is 0.75 to 1.

[0013] In at least one embodiment of the present invention, the active layer further includes a second extension portion, which overlaps with one of the plurality of scan lines on the normal line of the substrate and connects to the second channel portion, wherein the second extension portion and one of the plurality of scan lines form a second capacitor.

[0014] In at least one embodiment of the present invention, on the normal line of the substrate, the area of ​​the first extension overlapping with one of the plurality of scan lines is greater than the area of ​​the second extension overlapping with one of the plurality of scan lines.

[0015] In at least one embodiment of the present invention, on the normal line of the substrate, the sum of the area where the first extension overlaps with one of the plurality of scan lines and the area where the second extension overlaps with one of the plurality of scan lines is 2 to 20 times the sum of the area where the first channel overlaps with the first gate and the area where the second channel overlaps with the second gate.

[0016] In at least one embodiment of the present invention, each of the sub-pixels further includes a masking metal layer located between the substrate and the active layer. The orthographic projections of the first channel portion and the second channel portion onto the substrate are both located within the orthographic projection of the masking metal layer onto the substrate. The orthographic projection of the portion of the first extension portion overlapping one of the plurality of scan lines on the normal of the substrate onto the substrate is located outside the orthographic projection of the masking metal layer onto the substrate. The orthographic projection of the portion of the second extension portion overlapping one of the plurality of scan lines on the normal of the substrate onto the substrate is located outside the orthographic projection of the masking metal layer onto the substrate.

[0017] In at least one embodiment of the present invention, each of the sub-pixels further includes a masking metal layer located between the substrate and the active layer. The orthographic projections of the first channel portion, the second channel portion, and the first extension portion onto the substrate are all located within the orthographic projection of the masking metal layer onto the substrate. The orthographic projection of the portion of the second extension portion that overlaps with one of the plurality of scan lines on the normal of the substrate onto the substrate is located outside the orthographic projection of the masking metal layer onto the substrate.

[0018] In at least one embodiment of the present invention, each of the sub-pixels further includes a masking metal layer located between the substrate and the active layer. The orthographic projections of the first channel portion, the second channel portion, and the second extension portion onto the substrate are all located within the orthographic projection of the masking metal layer onto the substrate. The orthographic projection of the portion of the first extension portion that overlaps with one of the plurality of scan lines on the normal of the substrate onto the substrate is located outside the orthographic projection of the masking metal layer onto the substrate.

[0019] In at least one embodiment of the present invention, each of the sub-pixels further includes a masking metal layer located between the substrate and the active layer, wherein the orthographic projections of the first channel portion, the second channel portion, the first extension portion, and the second extension portion onto the substrate are all located within the orthographic projection of the masking metal layer onto the substrate.

[0020] In at least one embodiment of the present invention, the second extension includes a second main body and a second neck connecting the second channel and the second main body. The second main body overlaps with one of the plurality of scan lines, the second neck overlaps with the second gate, and the width of the second neck is not greater than the width of the second main body.

[0021] In at least one embodiment of the present invention, the second main body extends along the first direction, and the second neck extends along the second direction.

[0022] In at least one embodiment of the present invention, the ratio of the width of the second neck to the width of the second channel portion is 0.75 to 1.

[0023] At least another embodiment of the present invention provides a display panel comprising the array substrate, the opposing substrate, and a display medium. The opposing substrate is disposed opposite to the array substrate, and the display medium is disposed between the array substrate and the opposing substrate. Attached Figure Description

[0024] Figure 1 This is a top view schematic diagram of an array substrate according to at least one embodiment of the present invention.

[0025] Figure 2 yes Figure 1 A magnified view of region A in the middle.

[0026] Figure 3A yes Figure 2 A magnified view of region B in the middle.

[0027] Figure 3B yes Figure 3A A schematic diagram of the cross section drawn along line a-a'.

[0028] Figure 3C yes Figure 3A A schematic diagram of the cross section drawn along the b-b' section.

[0029] Figure 3D This is a circuit diagram of a sub-pixel of an array substrate according to at least one embodiment of the present invention.

[0030] Figure 4A This is an enlarged schematic diagram of a partial area of ​​the array substrate according to at least another embodiment of the present invention.

[0031] Figure 4B yes Figure 4A A schematic diagram of the cross section drawn along the line c-c'.

[0032] Figure 4C This is a circuit diagram of a sub-pixel of an array substrate according to at least another embodiment of the present invention.

[0033] Figure 5A This is an enlarged schematic diagram of a partial area of ​​the array substrate according to at least another embodiment of the present invention.

[0034] Figure 5B yes Figure 5A A schematic diagram of the cross section drawn along the d-d' section.

[0035] Figure 6A This is an enlarged schematic diagram of a partial area of ​​the array substrate according to at least another embodiment of the present invention.

[0036] Figure 6B yes Figure 6A A schematic diagram of the cross section drawn along line e-e'.

[0037] Figure 7 This is a cross-sectional schematic diagram of a display panel according to at least one embodiment of the present invention.

[0038] Explanation of reference numerals in the attached figures: 10: Display panel 100: Array substrate 102: Substrate 104: Scan line 106: Data cable 108, 108A, 108B: Active Layer 110, 110A, 110B: Shielding metal layer 112: Pixel Electrode 114: First insulating layer 116: Second insulating layer 118: Third Insulation Layer 120: Fourth Insulation Layer 200: Opposing substrate 300: Display medium BP1: First Branch BP2: Second Branch C1: First capacitor C2: Second capacitor CH1: First Passage Section CH2: Second channel section CS: Pixel storage capacitor D1: First Direction D2: Second Direction D3: Third direction DE: Drain EP1: First Extension EP2: Second Extension GE1: First gate GE2: Second gate MP1: First Main Body MP2: Second Main Body NP1: First neck NP2: Second neck PX: Subpixel SE: Source T1: First thin-film transistor T2: Second thin-film transistor V1: First perforation V2: Second perforation W1~W9, W8': Width Detailed Implementation

[0039] In the following text, to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally, and the number of some elements may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings or the dimensions and shapes presented by the elements, but should cover dimensions, shapes, and deviations from both due to actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings of the present invention are primarily for illustration and are not intended to precisely depict the actual shape of the elements, nor are they intended to limit the claims of the present invention.

[0040] Secondly, the terms "approximately," "about," or "substantially" used in this invention not only cover explicitly stated numerical values ​​and ranges, but also the permissible deviation range understood by those skilled in the art to which this invention pertains. This deviation range can be determined by errors generated during measurement, which may arise from limitations of the measurement system or process conditions, for example. For instance, two objects (e.g., planes or traces of a substrate) are "substantially parallel" or "substantially perpendicular," where "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects can include non-parallelism and non-perpendicularity caused by permissible deviation ranges.

[0041] Furthermore, "approximately" can indicate that the value is within one or more standard deviations, such as ±30%, ±20%, ±10%, or ±5%. The terms "approximately," "approximately," or "substantially" used in this invention can be selected based on the optical, etching, mechanical, or other properties to determine an acceptable range of deviations or standard deviations, and are not applied to all optical, etching, mechanical, and other properties using a single standard deviation.

[0042] The spatial relative terms used in this invention, such as "below," "under," "above," and "above," are for the convenience of describing the relative relationship between one element or feature and another, as shown in the figures. The true meaning of these spatial relative terms includes other orientations. For example, when the illustration is rotated 180 degrees vertically, the relationship between one element and another may change from "below" or "under" to "above" or "above." Furthermore, the spatial relative descriptions used in this invention should be interpreted in the same way.

[0043] It should be understood that although the present invention may use terms such as "first," "second," and "third" to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are primarily used to distinguish one element from another, or one signal from another. Furthermore, the term "or" as used in this invention may, depending on the specific circumstances, include any combination of one or more of the associated listed items.

[0044] Furthermore, the present invention can be implemented or applied through other different specific embodiments, and the details of the present invention can also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.

[0045] Figure 1 This is a top view of an array substrate 100 according to at least one embodiment of the present invention. Figure 2 yes Figure 1 A magnified view of region A in the middle. Please refer to [link / reference]. Figure 1 and Figure 2 The array substrate 100 includes a substrate 102, a plurality of scan lines 104, and a plurality of data lines 106. The scan lines 104 are located on the substrate 102 and extend substantially along a first direction D1, and the data lines 106 are located on the substrate 102 and extend substantially along a second direction D2. The first direction D1 is different from the second direction D2, and the scan lines 104 and the data lines 106 intersect to define a plurality of sub-pixels PX.

[0046] Figure 3A yes Figure 2 A magnified view of region B in the middle. Please refer to [link / reference]. Figure 2 and Figure 3AEach sub-pixel PX includes a first gate GE1, a second gate GE2, an active layer 108, a source SE, a drain DE, a pixel electrode 112, and a common electrode (not shown). The first gate GE1 and the second gate GE2 are located on the substrate 102 and are electrically connected to one of the scan lines 104. The active layer 108 is located on the substrate 102 and includes a first channel portion CH1, a second channel portion CH2, and a first extension portion EP1. It is worth noting that, for the sake of simplicity in the accompanying drawings... Figure 3A The layers and components located on the active layer 108 are not shown, such as data line 106, source SE, drain DE and pixel electrode 112.

[0047] Figure 3B yes Figure 3A A schematic diagram of the cross section drawn along line a-a'. Figure 3C yes Figure 3A A schematic cross-sectional view drawn along line b-b'. Please refer to [link / reference]. Figures 3A to 3C On the normal (i.e., third direction D3) of the substrate 102, the first channel portion CH1 overlaps with the first gate GE1, the second channel portion CH2 overlaps with the second gate GE2, and the first extension portion EP1 overlaps with one of the scan lines 104. The first channel portion CH1 is connected to the second channel portion CH2, and the first extension portion EP1 is connected to the first channel portion CH1. The source SE is located on the active layer 108 and electrically connected to the first channel portion CH1 and one of the data lines 106, and the drain DE is located on the active layer 108 and electrically connected to the second channel portion CH2.

[0048] Figure 3D This is a circuit diagram of a sub-pixel PX of an array substrate 100 according to at least one embodiment of the present invention. The first gate GE1, the first channel portion CH1, the source SE, and the drain DE are formed as follows: Figure 3D The first thin-film transistor T1 shown has a second gate GE2, a second channel CH2, a source SE, and a drain DE formed as follows: Figure 3D The second thin-film transistor T2 shown, the first extension EP1, and one of the scan lines 104 are formed as described above. Figure 3D The first capacitor C1, pixel electrode 112, and common electrode shown are formed as follows: Figure 3D The pixel storage capacitor CS is shown in the diagram. (As shown in the diagram...) Figure 3D As shown, the first capacitor C1, which is electrically connected to the first thin-film transistor T1, is formed by the first extension EP1 in the active layer 108 that connects to the first channel CH1 and the scan line 104 that overlaps with it. This helps the first thin-film transistor T1 maintain a stable potential, thereby reducing leakage and improving electrical performance and display quality.

[0049] In some embodiments, on the normal (i.e., third direction D3) of the substrate 102, the area overlapping the first extension EP1 with one of the scan lines 104 is 2 to 20 times the sum of the areas overlapping the first channel CH1 and the first gate GE1 and the second channel CH2 and the second gate GE2. This proportional design ensures that a sufficiently large first capacitor C1 helps the first thin-film transistor T1 maintain a stable potential, thus reducing leakage current and improving electrical performance and display quality.

[0050] Please continue reading. Figures 3A to 3D The sub-pixel PX also includes a shielding metal layer 110, which is located between the substrate 102 and the active layer 108. The orthographic projections of the first channel portion CH1 and the second channel portion CH2 onto the substrate 102 are both within the orthographic projection of the shielding metal layer 110 onto the substrate 102. That is, the contours formed by the orthographic projections of the first channel portion CH1 and the second channel portion CH2 onto the substrate 102 do not exceed the contours formed by the orthographic projection of the shielding metal layer 110 onto the substrate 102. Through the aforementioned design, leakage current caused by the backlight module irradiation of the first channel portion CH1 and the second channel portion CH2 can be avoided, which would affect the electrical performance of the first thin-film transistor T1 and the second thin-film transistor T2.

[0051] Since the first extension EP1 of the active layer 108 is used to form the first capacitor C1 with the scan line 104, the electrical performance of the first capacitor C1 is not affected even when illuminated by the backlight module. Therefore, the orthographic projection of the portion of the first extension EP1 on the normal (i.e., the third direction D3) of the substrate 102 that overlaps with one of the scan lines 104 on the substrate 102 can be located outside the orthographic projection of the shielding metal layer 110 on the substrate 102. That is, the outline formed by the orthographic projection of the first extension EP1 on the substrate 102 can exceed the outline formed by the orthographic projection of the shielding metal layer 110 on the substrate 102.

[0052] In addition, the sub-pixel PX also includes a first insulating layer 114, a second insulating layer 116, a third insulating layer 118, and a fourth insulating layer 120. The first insulating layer 114 is disposed between the shielding metal layer 110 and the active layer 108. The second insulating layer 116 is disposed between the active layer 108 and the scan line 104, the first gate GE1, and the second gate GE2. The third insulating layer 118 is disposed between the scan line 104, the first gate GE1, and the second gate GE2 and the data line 106, the source electrode SE, and the drain electrode DE. The fourth insulating layer 120 is disposed between the data line 106, the source electrode SE, the drain electrode DE, and the pixel electrode 112. The source electrode SE is electrically connected to the active layer 108 via a first through-hole V1 extending through the second insulating layer 116 and the third insulating layer 118. The drain electrode DE is electrically connected to the active layer 108 via a second through-hole V2 extending through the second insulating layer 116 and the third insulating layer 118. The pixel electrode 112 is electrically connected to the drain electrode DE through the fourth insulating layer 120.

[0053] like Figure 3A As shown, the first gate GE1 extends substantially along the first direction D1, the second gate GE2 extends substantially along the second direction D2, the first channel portion CH1 extends substantially along the second direction D2, the second channel portion CH2 extends substantially along the first direction D1, and the first extension portion EP1 extends substantially along the first direction D1. In some embodiments, the first direction D1 is substantially perpendicular to the second direction D2, that is, the first channel portion CH1 and the second channel portion CH2 are arranged in an L-shape.

[0054] The width W1 of the first gate GE1 and the width W2 of the second gate GE2 are both smaller than the width W3 of one of the scan lines 104. The ratio of the width W3 of one of the scan lines 104 to the width W1 of the first gate GE1 and the ratio of the width W3 of one of the scan lines 104 to the width W2 of the second gate GE2 can be approximately 1.5 to 2.5.

[0055] The first extension EP1 includes a first main body MP1 and a first neck NP1 connecting the first channel CH1 and the first main body MP1. The first main body MP1 overlaps with one of the scan lines 104, and the first neck NP1 overlaps with the first gate GE1. The width W4 of the first neck NP1 is not greater than the width W5 of the first main body MP1, and the ratio of the width W4 of the first neck NP1 to the width W6 of the first channel CH1 is approximately 0.75 to 1. Through the aforementioned ratio design, the orthographic projection of the first neck NP1 onto the substrate 102 can be located within one of the scan lines 104 and the orthographic projection of the first gate GE1 onto the substrate 102. That is, the contour formed by the orthographic projection of the first neck NP1 onto the substrate 102 does not exceed one of the scan lines 104 and the contour formed by the orthographic projection of the first gate GE1 onto the substrate 102, and ensures that the channel width-to-length ratio of the first thin-film transistor T1 remains unchanged to maintain its electrical performance. By designing the width W5 of the first main body MP1 to be greater than the width W4 of the first neck NP1, the overlap area between the first main body MP1 and the scan line 104 can be increased to increase the first capacitance C1, which can help the first thin film transistor T1 maintain a stable potential, thereby reducing leakage current and improving electrical performance and display quality.

[0056] In some embodiments, the substrate 102 may be a transparent substrate, and the material of the substrate 102 may be quartz, glass, polymer, or other suitable materials. The scan line 104, the first gate GE1, and the second gate GE2 may be formed from the same conductive layer, and the data line 106, the source SE, and the drain DE may be formed from the same conductive layer. The aforementioned conductive layer may be a single-layer or multi-layer structure, and the material may include opaque conductive materials, transparent conductive materials, or other suitable materials. If it is a multi-layer structure, it may contain the same or different materials. The active layer 108 may be a single-layer or multi-layer structure, and the material may include polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, amorphous silicon, or silicon-rich semiconductors.

[0057] The shielding metal layer 110 can be a single layer or multiple layers. If it is a single layer, its material is a conductive metal material. If it is multiple layers, it can contain the same material or different materials, but at least one layer is a conductive metal material, and the other layers can contain transparent conductive materials or other suitable materials. The pixel electrode 112 can be a single layer or multiple layers, and its material includes transparent conductive materials or other suitable materials. If it is multiple layers, it can contain the same material or different materials. The first insulating layer 114, the second insulating layer 116, the third insulating layer 118, and the fourth insulating layer 120 can be a single layer or multiple layers, and their materials can include organic insulating materials or inorganic insulating materials. If they are multiple layers, they can contain the same material or different materials.

[0058] Figure 4A This is an enlarged schematic diagram of a partial area of ​​the array substrate 100 according to at least another embodiment of the present invention. Figure 4B yes Figure 4A A schematic diagram of the cross section drawn along the line c-c'. Figure 4C This is a circuit diagram of a sub-pixel PX of an array substrate 100 according to at least another embodiment of the present invention. Please refer to... Figures 4A to 4C , Figures 4A to 4C Implementation examples and Figures 3A to 3D Most of the components in the embodiments are the same in terms of structure, relative position, and materials. Figure 4A The top view of the array substrate 100 is essentially the same as... Figure 3A A top view of the array substrate 100, and Figure 4A Chinese correspondence Figure 3A The cross-sectional diagram of the position of the midline a-a' is essentially the same as... Figure 3B Therefore, the same technical features will not be repeated here. Figures 4A to 4C Implementation examples and Figures 3A to 3D The main differences in the embodiments are Figures 4A to 4C The active layer 108A of the embodiment also includes a second extension EP2.

[0059] In detail, the second extension EP2 overlaps with one of the scan lines 104 on the normal (i.e., third direction D3) of the substrate 102 and connects to the second channel portion CH2. The second extension EP2 and one of the scan lines 104 are formed as follows: Figure 4C The second capacitor C2 is shown in the diagram. Figure 4C As shown, in addition to the first capacitor C1 which helps the first thin-film transistor T1 maintain a stable potential, the sub-pixel PX also includes a second capacitor C2 which helps the second thin-film transistor T2 maintain a stable potential. Therefore, leakage current can be reduced, thereby improving electrical performance and display quality.

[0060] On the normal (i.e., third direction D3) of the substrate 102, the sum of the areas where the first extension EP1 overlaps with one of the scan lines 104 and the sum of the areas where the second extension EP2 overlaps with one of the scan lines 104 is 2 to 20 times the sum of the areas where the first channel CH1 overlaps with the first gate GE1 and the sum of the areas where the second channel CH2 overlaps with the second gate GE2. Through the aforementioned proportional design, it can be ensured that the first capacitor C1 and the second capacitor C2 are sufficiently large to help the first thin-film transistor T1 and the second thin-film transistor T2 maintain a stable potential, thus reducing leakage current and improving electrical performance and display quality.

[0061] like Figure 4CAs shown, since the leakage path is from the pixel electrode 112 to the data line 106, the first capacitor C1 can help reduce leakage more significantly than the second capacitor C2. Therefore, on the normal (i.e., the third direction D3) of the substrate 102, the area where the first extension EP1 overlaps with one of the scan lines 104 is greater than the area where the second extension EP2 overlaps with one of the scan lines 104. This makes the first capacitor C1 larger than the second capacitor C2, which can significantly reduce leakage and thus improve electrical performance and display quality.

[0062] Please continue reading. Figure 4A and Figure 4B Since the second extension EP2 of the active layer 108A is used to form the second capacitor C2 with the scan line 104, the electrical performance of the second capacitor C2 is not affected even when illuminated by the backlight module. Therefore, the orthographic projection of the portion of the second extension EP2 on the normal (i.e., the third direction D3) of the substrate 102 that overlaps with one of the scan lines 104 on the substrate 102 can be located outside the orthographic projection of the shielding metal layer 110 on the substrate 102. That is, the outline formed by the orthographic projection of the second extension EP2 on the substrate 102 can exceed the outline formed by the orthographic projection of the shielding metal layer 110 on the substrate 102.

[0063] like Figure 4A As shown, the second extension EP2 includes a second main body MP2 and a second neck NP2 connecting the second channel CH2 and the second main body MP2. The second main body MP2 extends substantially along a first direction D1, and the second neck NP2 extends substantially along a second direction D2, i.e., the second main body MP2 and the second neck NP2 are arranged in an L-shape. The second main body MP2 overlaps with one of the scan lines 104, and the second neck NP2 overlaps with the second gate GE2. The width W7 of the second neck NP2 is not greater than the width W8 of the second main body MP2, and the ratio of the width W7 of the second neck NP2 to the width W8 of the second channel CH2 is approximately 0.75 to 1. Through the aforementioned ratio design, the orthographic projection of the second neck NP2 onto the substrate 102 can be located within one of the scan lines 104 and the orthographic projection of the second gate GE2 onto the substrate 102. That is, the contour formed by the orthographic projection of the second neck NP2 onto the substrate 102 does not exceed one of the scan lines 104 and the contour formed by the orthographic projection of the second gate GE2 onto the substrate 102, and ensures that the channel width-to-length ratio of the second thin film transistor T2 remains unchanged to maintain its electrical performance.

[0064] Figure 5A This is an enlarged schematic diagram of a partial area of ​​the array substrate 100 according to at least another embodiment of the present invention. Figure 5B yes Figure 5A A schematic cross-sectional view drawn along line d-d'. Please refer to [link / reference]. Figure 5A and Figure 5B , Figure 5A and Figure 5B Implementation examples and Figures 4A to 4C Most of the components in the embodiments are the same in terms of structure, relative position, and materials. Figure 5A The top view of the array substrate 100 is essentially the same as... Figure 3A A top view of the array substrate 100, and Figure 5A Chinese correspondence Figure 3A The cross-sectional diagram of the position of the midline a-a' is essentially the same as... Figure 3B , Figure 5A The circuit diagram of the sub-pixel PX of the array substrate 100 is essentially the same as that of... Figure 4C The circuit diagram of the sub-pixel PX of the array substrate 100 is shown below, so the same technical features will not be described again here. Figure 5A and Figure 5B Implementation examples and Figures 4A to 4C The main differences in the embodiments are Figure 5A and Figure 5B The shielding metal layer 110A in the embodiment further includes a first branch BP1.

[0065] In detail, on the normal (i.e., third direction D3) of the substrate 102, the first branch BP1 of the shielding metal layer 110A overlaps with the first extension EP1, and the orthographic projection of the first extension EP1 onto the substrate 102 lies within the orthographic projection of the first branch BP1 onto the substrate 102, that is, the orthographic projection of the first extension EP1 onto the substrate 102 lies within the orthographic projection of the shielding metal layer 110A onto the substrate 102. Meanwhile, the portion of the second extension EP2 on the normal (i.e., third direction D3) of the substrate 102 that overlaps with one of the scan lines 104 has its orthographic projection onto the substrate 102 located outside the orthographic projection of the shielding metal layer 110 onto the substrate 102. In other words, the contour formed by the orthographic projection of the first extension EP1 onto the substrate 102 does not exceed the contour formed by the orthographic projection of the shielding metal layer 110A onto the substrate 102, while the contour formed by the orthographic projection of the second extension EP2 onto the substrate 102 exceeds the contour formed by the orthographic projection of the shielding metal layer 110A onto the substrate 102. By designing the first extension EP1 to be projected onto the substrate 102 within the projection of the shielding metal layer 110A onto the substrate 102, the first capacitor C1 can be increased to help the first thin film transistor T1 maintain a stable potential, thereby reducing leakage current and improving electrical performance and display quality.

[0066] Figure 6A This is an enlarged schematic diagram of a partial area of ​​the array substrate 100 according to at least another embodiment of the present invention. Figure 6B yes Figure 6A A schematic cross-sectional view drawn along line e-e'. Please refer to [link / reference]. Figure 6A and Figure 6B , Figure 6A and Figure 6B Implementation examples and Figure 5A and Figure 5B Most of the components in the embodiments are the same in terms of structure, relative position, and materials. Figure 6A The top view of the array substrate 100 is essentially the same as... Figure 3A A top view of the array substrate 100, and Figure 6A Chinese correspondence Figure 3A The cross-sectional diagram of the position of the midline a-a' is essentially the same as... Figure 3B , Figure 6A The circuit diagram of the sub-pixel PX of the array substrate 100 is essentially the same as that of... Figure 4C The circuit diagram of the sub-pixel PX of the array substrate 100 is shown below, so the same technical features will not be described again here. Figure 6A and Figure 6B Implementation examples and Figure 5A and Figure 5B The main differences in the embodiments are Figure 6A and Figure 6B The shielding metal layer 110B in the embodiment also includes a second branch BP2.

[0067] In detail, on the normal (i.e., the third direction D3) of the substrate 102, the second branch BP2 of the shielding metal layer 110B overlaps with the second extension EP2, and the orthographic projection of the second extension EP2 onto the substrate 102 lies within the orthographic projection of the second branch BP2, that is, the orthographic projection of the second extension EP2 onto the substrate 102 lies within the orthographic projection of the shielding metal layer 110B onto the substrate 102. In other words, the contour formed by the orthographic projection of the second extension EP2 onto the substrate 102 does not exceed the contour formed by the orthographic projection of the shielding metal layer 110B onto the substrate 102. By designing that the orthographic projection of the second extension EP2 onto the substrate 102 lies within the orthographic projection of the shielding metal layer 110B onto the substrate 102, the second capacitor C2 can be increased, helping the second thin-film transistor T2 maintain a stable potential, thus reducing leakage current and improving electrical performance and display quality.

[0068] In addition, such as Figure 6A As shown, the width W7 of the second neck NP2 of the active layer 108B is smaller than the width W8' of the second main body MP2. By designing that the width W8' of the second main body MP2 is larger than the width W7 of the second neck NP2, the overlap area between the second main body MP2 and the scan line 104 can be increased to increase the second capacitor C2, which can help the second thin film transistor T2 maintain a stable potential, thus reducing leakage current and improving electrical performance and display quality.

[0069] In other embodiments, the shielding metal layer 110B may include a second branch BP2 but not a first branch BP1. That is, the orthographic projection of the second extension EP2 onto the substrate 102 lies within the orthographic projection of the shielding metal layer 110B onto the substrate 102, while the orthographic projection of the portion of the first extension EP1 on the normal (i.e., third direction D3) of the substrate 102 that overlaps with one of the scan lines 104 lies outside the orthographic projection of the shielding metal layer 110B onto the substrate 102. In other words, the contour formed by the orthographic projection of the second extension EP2 onto the substrate 102 does not exceed the contour formed by the orthographic projection of the shielding metal layer 110B onto the substrate 102, while the contour formed by the orthographic projection of the first extension EP1 onto the substrate 102 exceeds the contour formed by the orthographic projection of the shielding metal layer 110B onto the substrate 102.

[0070] Figure 7 This is a cross-sectional schematic diagram of a display panel 10 according to at least one embodiment of the present invention. Please refer to... Figure 7 The display panel 10 includes the array substrate 100, the opposing substrate 200, and the display medium 300. The opposing substrate 200 is disposed opposite to the array substrate 100, and the display medium 300 is disposed between the array substrate 100 and the opposing substrate 200. In some embodiments, the opposing substrate 200 may be a color filter substrate, and the display medium 300 may be a liquid crystal. The display panel 10 can be applied in a display device, and the display device may further include a backlight module as a light source for the display panel 10, but the present invention is not limited thereto.

[0071] In summary, in the array substrate and display panel of at least one embodiment of the present invention, the capacitors that electrically connect the thin-film transistors are formed by the extension of the connecting channel portion in the active layer and the scan lines that overlap therewith, which can help the thin-film transistors maintain a stable potential, thereby reducing leakage current and improving electrical performance and display quality.

[0072] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art to which this invention pertains may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. An array substrate, comprising: One substrate; Multiple scan lines are located on the substrate and extend along a first direction; as well as Multiple data lines are located on the substrate and extend along a second direction, wherein the first direction is different from the second direction, and the scan lines and data lines intersect to define multiple sub-pixels, wherein each sub-pixel includes: A first gate and a second gate are located on the substrate and electrically connected to one of the scan lines; An active layer is located on the substrate and includes a first channel portion, a second channel portion and a first extension portion, wherein on a normal line of the substrate, the first channel portion overlaps with the first gate, the second channel portion overlaps with the second gate, and the first extension portion overlaps with one of the scan lines, wherein the first channel portion is connected to the second channel portion and the first extension portion is connected to the first channel portion. A source electrode is located on the active layer and is electrically connected to the first channel section and one of the data lines; as well as A drain is located on the active layer and electrically connected to the second channel portion, wherein the first gate, the first channel portion, the source and the drain form a first thin-film transistor, the second gate, the second channel portion, the source and the drain form a second thin-film transistor, and one of the first extension portion and the scan lines forms a first capacitor.

2. The array substrate of claim 1, wherein on the normal line of the substrate, the area of ​​the first extension overlapping with one of the scan lines is 2 to 20 times the sum of the area of ​​the first channel portion overlapping with the first gate and the area of ​​the second channel portion overlapping with the second gate.

3. The array substrate as claimed in claim 1, wherein each sub-pixel further comprises: A shielding metal layer is located between the substrate and the active layer, wherein the orthographic projections of the first channel portion and the second channel portion onto the substrate are both located within the orthographic projection of the shielding metal layer onto the substrate, and the orthographic projection of the first extension portion on the normal line of the substrate that overlaps with one of the scan lines onto the substrate is located outside the orthographic projection of the shielding metal layer onto the substrate.

4. The array substrate as claimed in claim 1, wherein each sub-pixel further comprises: A shielding metal layer is located between the substrate and the active layer, wherein the orthographic projections of the first channel portion, the second channel portion and the first extension portion onto the substrate are all located within the orthographic projection of the shielding metal layer onto the substrate.

5. The array substrate of claim 1, wherein the first gate extends along the first direction, the second gate extends along the second direction, the first channel portion extends along the second direction, the second channel portion extends along the first direction, and the first extension portion extends along the first direction.

6. The array substrate of claim 1, wherein the first gate and the second gate and one of the scan lines are formed of the same conductive layer, and the width of the first gate and the width of the second gate are both smaller than the width of one of the scan lines.

7. The array substrate of claim 6, wherein the ratio of the width of one of the scan lines to the width of the first gate and the ratio of the width of one of the scan lines to the width of the second gate are both 1.5 to 2.

5.

8. The array substrate of claim 6, wherein the first extension includes a first main body and a first neck connecting the first channel and the first main body, wherein the first main body overlaps with one of the scan lines, the first neck overlaps with the first gate, and the width of the first neck is not greater than the width of the first main body.

9. The array substrate of claim 8, wherein the ratio of the width of the first neck to the width of the first channel portion is 0.75 to 1.

10. The array substrate of claim 6, wherein the active layer further comprises: A second extension overlaps with one of the scan lines on the normal of the substrate and connects to the second channel portion, wherein the second extension and one of the scan lines form a second capacitor.

11. The array substrate of claim 10, wherein on the normal line of the substrate, the area of ​​the first extension overlapping with one of the scan lines is greater than the area of ​​the second extension overlapping with one of the scan lines.

12. The array substrate of claim 10, wherein on the normal line of the substrate, the sum of the area of ​​the first extension overlapping with one of the scan lines and the area of ​​the second extension overlapping with one of the scan lines is 2 to 20 times the sum of the area of ​​the first channel overlapping with the first gate and the area of ​​the second channel overlapping with the second gate.

13. The array substrate of claim 10, wherein each sub-pixel further comprises: A shielding metal layer is located between the substrate and the active layer, wherein the orthographic projections of the first channel portion and the second channel portion onto the substrate are both located within the orthographic projection of the shielding metal layer onto the substrate, and the orthographic projection of the portion of the first extension portion overlapping with one of the scan lines on the normal line of the substrate onto the substrate is located outside the orthographic projection of the shielding metal layer onto the substrate, and the orthographic projection of the second extension portion overlapping with one of the scan lines on the normal line of the substrate onto the substrate is located outside the orthographic projection of the shielding metal layer onto the substrate.

14. The array substrate of claim 10, wherein each sub-pixel further comprises: A shielding metal layer is located between the substrate and the active layer, wherein the orthographic projections of the first channel portion, the second channel portion, and the first extension portion onto the substrate are all located within the orthographic projection of the shielding metal layer onto the substrate, and the orthographic projection of the portion of the second extension portion that overlaps with one of the scan lines on the normal line of the substrate onto the substrate is located outside the orthographic projection of the shielding metal layer onto the substrate.

15. The array substrate of claim 10, wherein each sub-pixel further comprises: A shielding metal layer is located between the substrate and the active layer, wherein the orthographic projections of the first channel portion, the second channel portion, and the second extension portion onto the substrate are all located within the orthographic projection of the shielding metal layer onto the substrate, and the orthographic projection of the portion of the first extension portion that overlaps with one of the scan lines on the normal line of the substrate onto the substrate is located outside the orthographic projection of the shielding metal layer onto the substrate.

16. The array substrate of claim 10, wherein each sub-pixel further comprises: A shielding metal layer is located between the substrate and the active layer, wherein the orthographic projections of the first channel portion, the second channel portion, the first extension portion and the second extension portion onto the substrate are all located within the orthographic projection of the shielding metal layer onto the substrate.

17. The array substrate of claim 10, wherein the second extension includes a second body portion and a second neck portion connecting the second channel portion and the second body portion, wherein the second body portion overlaps with one of the scan lines, the second neck portion overlaps with the second gate, and the width of the second neck portion is not greater than the width of the second body portion.

18. The array substrate of claim 17, wherein the second body portion extends along the first direction and the second neck portion extends along the second direction.

19. The array substrate of claim 17, wherein the ratio of the width of the second neck to the width of the second channel portion is 0.75 to 1.

20. A display panel, comprising: The array substrate as claimed in any one of claims 1 to 19; A pair of opposing substrates is disposed opposite to the array substrate; as well as A display medium is disposed between the array substrate and the opposing substrate.

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