Display panel and display device
By setting multiple active control transistors spaced apart in the display panel, the problem of low reliability of control transistors is solved, achieving the effects of reducing operating temperature and improving reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-12
- Publication Date
- 2026-04-07
AI Technical Summary
The low reliability of control transistors in existing display devices leads to display malfunctions.
By placing a control transistor in the display panel, each data input line is electrically connected to at least two data lines, and the active pattern of the control transistor is designed as multiple active parts spaced apart, the number of data input lines is reduced, the parasitic capacitance of the control transistor is reduced, thereby improving its reliability.
It effectively reduced the operating temperature of the control transistor, improved its reliability, reduced the number of source driver chips, and improved display abnormality issues.
Smart Images
Figure CN121806340A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology
[0002] TFT-LCD (thin film transistor-liquid crystal display) is widely used due to its advantages such as long lifespan, mature technology, and low price. With the development of display devices, the resolution of display panels is getting higher and higher. Higher resolution leads to an increase in the number of source driver chips, increasing costs. To reduce the number of source driver chips, multiplexing line technology is used, where one source input line is connected to multiple data lines through one control transistor, thus reducing the number of source driver chips. However, during the operation of the display panel, it was found that the control transistors draw a large current for a long time, generate significant heat, and have low reliability, leading to display abnormalities.
[0003] Therefore, existing display devices suffer from a technical problem: the low reliability of control transistors leads to display abnormalities. Summary of the Invention
[0004] This application provides a display panel and a display device to improve the technical problem of display abnormalities caused by the low reliability of control transistors in existing display devices.
[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, the display panel including a plurality of data lines and a plurality of data input lines, each of the data input lines being electrically connected to at least two of the data lines, and at least one control transistor being provided between each of the data lines and its corresponding data input line, the display panel comprising:
[0006] Substrate; An active layer is disposed on one side of the substrate, and the active layer includes the active pattern of the control transistor; Each of the control transistors has an active pattern comprising a plurality of active portions spaced apart.
[0007] According to a second aspect of this application, a display device is provided, the display device including a display panel as described in any of the above embodiments.
[0008] This application provides a display panel and a display device. The display panel, by setting a control transistor, electrically connects each data input line to at least two data lines. The control transistor is connected between the data lines and the data input lines. The control transistor can control the signal writing of the data input lines, thereby reducing the number of data input lines and thus reducing the number of source driver chips. Furthermore, the active pattern of each control transistor includes multiple active portions spaced apart, resulting in a smaller parasitic capacitance of the control transistor, thereby reducing the operating temperature of the control transistor and improving its reliability.
[0009] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0011] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.
[0012] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application.
[0013] Figure 2 This is a cross-sectional schematic diagram of the display panel provided in an embodiment of this application.
[0014] Figure 3 This is a first stacking diagram of some film layers of a display panel provided in an embodiment of this application.
[0015] Figure 4 This is a second stacking diagram of some film layers of a display panel provided in an embodiment of this application.
[0016] Figure 5 A plan view of the light-shielding layer of the display panel provided in an embodiment of this application.
[0017] Figure 6 for Figure 5 The overlay diagram of the light-shielding layer and the active layer of the display panel.
[0018] Figure 7 for Figure 6 The stack-up diagram of the light-shielding layer, active layer and gate layer of the display panel.
[0019] Figure 8 for Figure 7 A stack-up diagram of the vias in the light-shielding layer, active layer, gate layer, and interlayer insulating layer of the display panel.
[0020] Figure 9 for Figure 8 The diagram shows the stack-up of the light-shielding layer, active layer, gate layer, interlayer insulating layer, and source / drain layers of the display panel.
[0021] Figure 10 A line graph showing the capacitance of the control transistor and the voltage at which the control transistor remains on, provided in an embodiment of this application.
[0022] Figure 11 A line graph showing the product of the capacitance of the control transistor and the channel length and channel width of the control transistor, as provided in the embodiments of this application.
[0023] Figure 12 A line graph showing the capacitance of the control transistor versus the temperature of the driving chip, provided in an embodiment of this application.
[0024] Figure 13 Timing diagram of the control lines provided in the embodiments of this application. Detailed Implementation
[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.
[0026] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connection" and "electrical connection" should be interpreted broadly. For example, it can refer to a direct connection or an indirect connection through an intermediate medium, or it can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0027] This application addresses the technical problem of low reliability of control transistors in existing display devices, which leads to display abnormalities. It provides a display panel and a display device to improve the above-mentioned technical problem.
[0028] Based on the current issue of low reliability of control transistors, the applicant of this application has discovered that the channel length, channel width, total channel width, device structure, distance between the light-shielding pattern and the gate, number of control lines, and timing of the control lines all affect the reliability of the control transistor. Specifically, it has been further discovered that a smaller channel length results in a smaller capacitance, thus improving reliability; a smaller channel width leads to a less pronounced self-heating effect, reducing stress and controlling the temperature of the driver chip; a smaller total channel width results in a smaller capacitance, further improving reliability; and a floating light-shielding pattern design can reduce the capacitance of the control transistor, improving reliability; a smaller distance between the light-shielding pattern and the channel also results in a smaller capacitance, improving reliability; additionally, a greater number of control lines results in a lower impedance per control line, reducing stress on the control transistor; and controlling the timing can also reduce stress and improve the reliability of the control transistor.
[0029] Based on the above analysis, the design of the display panel will be specifically described in the following embodiments of this application.
[0030] like Figure 1 As shown, this application embodiment provides a display panel 1, which includes a first sub-pixel 111, a second sub-pixel 112, and a third sub-pixel 113 of different emitting colors. A plurality of first sub-pixels 111 are arranged along a second direction Y to form a sub-pixel column, a plurality of second sub-pixels 112 are arranged along a second direction Y to form a sub-pixel column, a plurality of third sub-pixels 113 are arranged along a second direction Y to form a sub-pixel column, and the first sub-pixels 111, the second sub-pixels 112, and the third sub-pixels 113 are arranged along a first direction to form a sub-pixel row.
[0031] Specifically, for ease of explanation, the following embodiments use the first sub-pixel 111, the second sub-pixel 112, and the third sub-pixel 113 as examples, where the light emission colors are red, green, and blue, respectively. However, the embodiments of this application are not limited to this. The light emission colors of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be green, red, and blue, respectively, or the light emission colors of the first sub-pixel, the second sub-pixel, and the third sub-pixel can be other colors.
[0032] Specifically, such as Figure 1 As shown, this application embodiment uses the example of three data lines Data being electrically connected to the same data input line SL for illustration, but this application embodiment is not limited to this, for example, two data lines Data can be electrically connected to the same data input line SL.
[0033] Specifically, such as Figure 1 As shown, this application embodiment uses a display panel with six control lines (Mux) as an example for illustration, but this application embodiment is not limited to this, and three control lines or two control lines can be set.
[0034] Specifically, this application embodiment uses the example of the first, third, and fifth data lines being electrically connected to the same data input line SL, and the second, fourth, and sixth data lines being electrically connected to the same data input line SL among six adjacent data lines. However, this application embodiment is not limited to this. For example, the first, second, and third data lines can be electrically connected to the same data input line SL.
[0035] Specifically, such as Figure 2 As shown, the display panel 1 includes a substrate 11, a light-shielding layer 12, a buffer layer 131, an active layer 132, a gate insulating layer 133, a gate layer 134, an interlayer insulating layer 135, a source-drain layer 136, an organic layer 137, a common electrode layer 138, and a pixel electrode layer 141. However, the embodiments of this application are not limited to this. For example, the display panel 1 can be an organic light-emitting diode display panel. Accordingly, the common electrode layer 138 in the display panel 1 will be disposed on the side of the light-emitting material layer away from the pixel electrode layer.
[0036] like Figures 1 to 9 As shown, this application embodiment provides a display panel 1, which includes multiple data lines Data and multiple data input lines SL. Each data input line SL is electrically connected to at least two data lines Data. At least one control transistor (e.g., a first control transistor T1) is provided between each data line Data and the corresponding data input line SL. The display panel 1 includes a substrate 11 and an active layer 132. The active layer 132 is disposed on one side of the substrate and includes an active pattern of the control transistor (e.g., the active pattern T1A of the first control transistor T1). Each of the control transistors has an active pattern including a plurality of active portions 132a spaced apart.
[0037] This application provides a display panel 1. By setting a control transistor, each data input line SL is electrically connected to at least two data lines Data. The control transistor is connected between the data lines Data and the data input line SL. The signal writing of the data input line SL can be controlled by the control transistor, thereby reducing the number of data input lines SL and thus reducing the number of source driver chips. Furthermore, the active pattern of each control transistor includes a plurality of spaced active portions 132a, which makes the parasitic capacitance of the control transistor smaller, thereby reducing the operating temperature of the control transistor and improving the reliability of the control transistor.
[0038] Specifically, in current display devices, the active pattern of the control transistor is set as a single block, resulting in a large capacitance and high operating temperature of the control transistor, which leads to a decrease in the reliability of the control transistor. In the embodiments of this application, by making the active pattern of each control transistor include multiple active parts 132a arranged at intervals, the parasitic capacitance of the control transistor is reduced, thereby reducing the operating temperature of the control transistor and improving its reliability.
[0039] In some embodiments, such as Figures 2 to 5 As shown, the display panel 1 further includes a light-shielding layer 12, which is disposed between the substrate 11 and the active layer 132. The light-shielding layer 12 includes a plurality of light-shielding patterns 121, which are spaced apart along a first direction X. The active portion 132a is spaced apart along a second direction Y. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.
[0040] Specifically, such as Figures 3 to 5 As shown, the light-shielding pattern 121 is set to correspond with the active pattern. The light-shielding pattern 121 can block the active pattern to prevent external light from affecting the performance of the control transistor. Furthermore, by setting multiple light-shielding patterns 121 at intervals, the overlapping area between the light-shielding pattern 121 and the active pattern can be reduced, thereby reducing parasitic capacitance, lowering the operating temperature of the control transistor, and improving the reliability of the control transistor.
[0041] Specifically, the gate of the control transistor is connected to the control line Mux.
[0042] In some embodiments, the light-shielding pattern 121 is suspended; by suspending the light-shielding pattern 121, the light-shielding pattern 121 does not need to be connected to other film layers, reducing the overlap area between the light-shielding pattern 121 and the active pattern, thereby reducing parasitic capacitance, lowering the operating temperature of the control transistor, and improving the reliability of the control transistor.
[0043] Specifically, Figure 5 To illustrate the shape and position of the light-blocking pattern 121, a black background is used, with blank spaces representing the shape and position of the light-blocking pattern 121. However, gaps 122 exist between different structures. It is understood that gaps 122 are not the light-blocking pattern 121. The light-blocking pattern 121 refers to the graphic in multiple blank spaces within the black background.
[0044] In some embodiments, such as Figure 1 , Figure 3 , Figure 4 , Figure 6As shown, at least one of the control transistors includes a first control transistor T1, a second control transistor T2, a third control transistor T3, a fourth control transistor T4, a fifth control transistor T5, and a sixth control transistor T6. The active layer 132 includes an active pattern T1A of the first control transistor T1, an active pattern T2A of the second control transistor T2, an active pattern T3A of the third control transistor T3, an active pattern T4A of the fourth control transistor T4, an active pattern T5A of the fifth control transistor T5, and an active pattern T6A of the sixth control transistor T6. The active patterns T1A of the first control transistor T1, T2A of the second control transistor T2, and T3A of the third control transistor T3 are connected. The active patterns T4A of the fourth control transistor T4, T5A of the fifth control transistor T5, and T6A of the sixth control transistor T6 are connected. The active pattern T3A of the third control transistor T3 is disconnected from the active pattern T4A of the fourth control transistor T4. By connecting the active patterns of each transistor, the space occupied by the transistors can be reduced, and the bezel of the display panel can be reduced.
[0045] Specifically, such as Figure 3 , Figure 4 , Figure 6 As shown, the active pattern of each control transistor includes multiple active parts, thereby reducing parasitic capacitance, lowering the operating temperature of the control transistor, and improving the reliability of the control transistor.
[0046] In some embodiments, such as Figure 1 , Figure 3 , Figure 4 , Figure 7 As shown, the control line Mux includes a first control line Mux1, a second control line Mux2, a third control line Mux3, a fourth control line Mux4, a fifth control line Mux5, and a sixth control line Mux6. The first control line Mux1, the second control line Mux2, the third control line Mux3, the fourth control line Mux4, the fifth control line Mux5, and the sixth control line Mux6 are respectively connected to the gate T1G of the first control transistor T1, the gate T2G of the second control transistor T2, the gate T3G of the third control transistor T3, the gate T4G of the fourth control transistor T4, the gate T5G of the fifth control transistor T5, and the gate T6G of the sixth control transistor T6. The data input line SL includes a first data input line SL1 and a second data input line SL2. The display panel 1 further includes a gate layer 134, which is disposed on the side of the active layer 132 away from the substrate 11. The gate layer 134 includes a first portion Mux1a of a first control line Mux1, a first portion Mux2a of a second control line Mux2, a first portion Mux3a of a third control line Mux3, a first portion Mux4a of a fourth control line Mux4, a first portion Mux5a of a fifth control line Mux5, a first portion Mux6a of a sixth control line Mux6, a first data input line SL1, a second data input line SL2, a first gate connection line GL1, and a second gate connection line GL2. The first part of the first control line Mux1, Mux1a, the first data input line SL1, the first part of the second control line Mux2, Mux2a, the first part of the third control line Mux3, Mux4a, the first part of the fourth control line Mux4, the second data input line SL2, the first part of the fifth control line Mux5, Mux5a, and the first part of the sixth control line Mux6 are arranged sequentially along the second direction Y.
[0047] Specifically, such as Figure 7 As shown, the first gate connection line GL1 and the second gate connection line GL2 are located on the side of the gate of each control transistor away from each control line.
[0048] Specifically, such as Figure 7 As shown, the lengths of the first part Mux1a of the first control line Mux1, the first part Mux2a of the second control line Mux2, the first part Mux3a of the third control line Mux3, the first part Mux4a of the fourth control line Mux4, the first part Mux5a of the fifth control line Mux5, and the first part Mux6a of the sixth control line Mux6 increase sequentially.
[0049] Specifically, such as Figure 7 As shown, the active pattern of each control transistor includes multiple active parts, and each control transistor includes two gates connected together.
[0050] Specifically, such as Figure 8 As shown, Figure 8 The location of the via 135a in the interlayer insulating layer 135 is shown.
[0051] Specifically, the first control line Mux1 can be connected to the fourth control line Mux4, the second control line Mux2 can be connected to the fifth control line Mux5, and the third control line Mux3 can be connected to the sixth control line Mux6.
[0052] In some embodiments, such as Figure 1 , Figure 3 , Figure 4 , Figure 9 As shown, the display panel 1 further includes a source-drain layer 136, which includes a second portion of the first control line Mux1 (Mux1b), a second portion of the second control line Mux2 (Mux2b), a second portion of the third control line Mux3 (Mux3b), a second portion of the fourth control line Mux4 (Mux4b), a second portion of the fifth control line Mux5 (Mux5b), a second portion of the sixth control line Mux6 (Mux6b), a first electrode T1S of the first control transistor T1, a second electrode T1D of the first control transistor T1, a first electrode T2S of the second control transistor T2, a second electrode T2D of the second control transistor T2, a first electrode T3S of the third control transistor T3, a second electrode T3D of the third control transistor T3, a first electrode T4S of the fourth control transistor T4, a second electrode T4D of the fourth control transistor T4, a first electrode T5S of the fifth control transistor T5, a second electrode T5D of the fifth control transistor T5, a first electrode T6S of the sixth control transistor T6, and a second electrode T6D of the sixth control transistor T6. The second part of the first control line Mux1, the second part of the second control line Mux2, the second part of the third control line Mux3, the second part of the fourth control line Mux4, the second part of the fifth control line Mux5, and the second part of the sixth control line Mux6 are respectively connected to the first part of the first control line Mux1, the first part of the second control line Mux2, the first part of the third control line Mux3, the first part of the fourth control line Mux4, the first part of the fifth control line Mux5, and the first part of the sixth control line Mux6. The first electrode T1S of the first control transistor T1, the first electrode T2S of the second control transistor T2, and the first electrode T3S of the third control transistor T3 are connected to the first data input line SL1. The first electrode T4S of the fourth control transistor T4, the first electrode T5S of the fifth control transistor T5, and the first electrode T6S of the sixth control transistor T6 are connected to the second data input line SL2. The second electrode T2D of the second control transistor T2 is connected to the first gate connection line GL1, and the second electrode T4D of the fourth control transistor T4 is connected to the second gate connection line GL2.
[0053] Specifically, such as Figure 9As shown, the first electrode T1S of the first control transistor T1, the first electrode T2S of the second control transistor T2, and the first electrode T3S of the third control transistor T3 are connected together and pass through a via to connect to the first data input line SL1. The first electrode T4S of the fourth control transistor T4, the first electrode T5S of the fifth control transistor T5, and the first electrode T6S of the sixth control transistor T6 are connected together and pass through a via to connect to the second data input line SL2.
[0054] Specifically, such as Figure 9 As shown, due to the active pattern connection of multiple control transistors, the electrodes of some control transistors share the same structure. For example, the first electrode T1S of the first control transistor T1 includes two parts, one of which is located between the gate of the first control transistor T1 and the gate of the second control transistor T2. This part can serve as the first electrode T1S of the first control transistor T1 and also as the first electrode T2S of the second control transistor T2. Similarly, the meaning of other structures can be determined.
[0055] In some embodiments, the first electrode T1S of the first control transistor T1, the first electrode T2S of the second control transistor T2, the first electrode T3S of the third control transistor T3, the first electrode T4S of the fourth control transistor T4, the first electrode T5S of the fifth control transistor T5, and the first electrode T6S of the sixth control transistor T6 are spaced apart. By spaced apart the second electrodes of each transistor, each transistor is independently configured, thereby enhancing heat dissipation and improving the stability of the control transistors.
[0056] Specifically, such as Figure 4 As shown, the first electrode of each control transistor can be set independently, thereby enabling each control transistor to be set independently, enhancing the heat dissipation capacity of the control transistor, and improving the stability of the control transistor.
[0057] Specifically, such as Figure 3 , Figure 9 As shown, some transistors can also share the same structure for their first electrodes, thereby saving space and reducing the bezel size.
[0058] In some embodiments, the gate width L1 of the control transistor is less than or equal to 4 micrometers, thereby reducing the channel length, which in turn reduces the capacitance and improves the stability of the control transistor.
[0059] Specifically, the gates T1G of the first control transistor T1, T2G of the second control transistor T2, T3G of the third control transistor T3, T4G of the fourth control transistor T4, T5G of the fifth control transistor T5, and T6G of the sixth control transistor T6 are all less than or equal to 4 micrometers. This makes the gate width of each transistor less than or equal to 4 micrometers, which can reduce the channel length of each transistor, thereby reducing the capacitance and improving the stability of each control transistor.
[0060] In some embodiments, the distance between the edge of the gate of the control transistor and the edge of the light-shielding pattern 121 is less than or equal to 2 micrometers.
[0061] In some embodiments, the distance L2 between the edge of the gate of the control transistor and the edge of the light-shielding pattern 121 is less than or equal to 1.5 micrometers. By making the distance between the edge of the gate of the control transistor and the edge of the light-shielding pattern 121 less than or equal to 1.5 micrometers, the width of the light-shielding pattern can be reduced, thereby reducing the distance between the light-shielding pattern and the channel, resulting in a smaller capacitance, which in turn reduces the capacitance and improves the stability of each control transistor.
[0062] Specifically, the distance between the edge of the gate of the first control transistor T1 and the edge of the corresponding light-shielding pattern 121 is less than or equal to 1.5 micrometers; the distance between the edge of the gate of the second control transistor T2 and the edge of the corresponding light-shielding pattern 121 is less than or equal to 1.5 micrometers; the distance between the edge of the gate of the third control transistor T3 and the edge of the corresponding light-shielding pattern 121 is less than or equal to 1.5 micrometers; the distance between the edge of the gate of the fourth control transistor T4 and the edge of the corresponding light-shielding pattern 121 is less than or equal to 1.5 micrometers; the distance between the edge of the gate of the fifth control transistor T5 and the edge of the corresponding light-shielding pattern 121 is less than or equal to 1.5 micrometers; and the distance between the edge of the gate of the sixth control transistor T6 and the edge of the light-shielding pattern 121 is less than or equal to 1.5 micrometers.
[0063] In some embodiments, such as Figure 4 As shown, the active patterns of multiple control transistors are spaced apart. By setting the active patterns of multiple control transistors apart, each control transistor can be set independently, thereby improving heat dissipation and stability.
[0064] Specifically, the control transistors include a first control transistor T1, a second control transistor T2, a third control transistor T3, a fourth control transistor T4, a fifth control transistor T5, and a sixth control transistor T6, and the active layer 132 includes an active pattern T1A of the first control transistor T1, an active pattern T2A of the second control transistor T2, an active pattern T3A of the third control transistor T3, an active pattern T4A of the fourth control transistor T4, an active pattern T5A of the fifth control transistor T5, and an active pattern T6A of the sixth control transistor T6. The active patterns T1A of the first control transistor T1, T2A of the second control transistor T2, T3A of the third control transistor T3, T4A of the fourth control transistor T4, T5A of the fifth control transistor T5, and T6A of the sixth control transistor T6 are spaced apart.
[0065] In some embodiments, such as Figure 3 As shown, the width L3 of the active part 132a is less than or equal to 10 micrometers, which makes each sub-transistor in each control transistor smaller, the self-heating effect of each sub-transistor is less, the pressure is reduced, the parasitic capacitance is reduced, and the reliability of the control transistor is improved.
[0066] Specifically, the active pattern of the control transistor includes multiple active portions, with corresponding gate, source, and drain terminals. This results in the control transistor comprising multiple sub-transistors, making the width of the active portions smaller, which is equivalent to reducing the size of the sub-transistors. Consequently, the self-heating effect of each control transistor is less pronounced, reducing stress, lowering parasitic capacitance, and improving the reliability of the control transistor.
[0067] In some embodiments, the sum of the widths of the plurality of active portions in the active pattern is less than or equal to 330 micrometers, which makes the width of the active pattern of the control transistor smaller, thereby reducing capacitance and improving the reliability of the control transistor.
[0068] Specifically, for example, if an active pattern of a control transistor includes 10 active portions, each with a width of 10 micrometers, then the sum of the widths of the multiple active portions of the active pattern is 10. 10 micrometers, which is 100 micrometers.
[0069] In some embodiments, such as Figure 2 , Figure 4As shown, the display panel 1 further includes an organic layer 137, which is disposed on the side of the active layer 132 away from the substrate 11. The organic layer 137 has a slot 137a in the area corresponding to the control transistor. By making the organic layer 137 have a slot in the area corresponding to the control transistor, the heat dissipation effect of the control transistor can be improved, and the reliability of the control transistor can be improved.
[0070] In some embodiments, the display panel 1 further includes multiple rows of sub-pixels 114, wherein the activation order of adjacent rows of sub-pixels 114 is reversed. By reversing the activation order of adjacent rows of sub-pixels, power consumption can be reduced.
[0071] Specifically, such as Figure 13 As shown, the timing of the first control line Mux1, the second control line Mux2, and the third control line Mux3 is used for explanation. The fourth control line Mux4, the fifth control line Mux5, and the sixth control line Mux6 are connected to the first control line Mux1, the second control line Mux2, and the third control line Mux3, respectively. Therefore, the timing of the fourth control line Mux4, the fifth control line Mux5, and the sixth control line Mux6 can be referred to the first control line Mux1, the second control line Mux2, and the third control line Mux3.
[0072] Specifically, such as Figure 13 As shown, taking a high potential as the effective level and a low potential as the ineffective level, with a pulse width of 1H for an effective level, from... Figure 13 As can be seen, the first control line Mux1, the second control line Mux2, and the third control line Mux3 are sequentially input with valid levels to activate the first row of subpixels. After this activation, the third control line Mux3, the second control line Mux2, and the first control line Mux1 are sequentially input with valid levels to activate the second row of subpixels. Then, the other rows of subpixels are activated sequentially according to the same timing sequence. It can be seen that the subpixels in the first and second rows activate in the following order: the subpixels in the first row are activated first by the one electrically connected to the first control line Mux1, then by the one electrically connected to the second control line Mux2, and finally by the one electrically connected to the third control line Mux3. Similarly, the subpixels in the second row activate in the following order: the subpixels in the first row are activated first by the one electrically connected to the third control line Mux3, then by the one electrically connected to the second control line Mux2, and finally by the one electrically connected to the first control line Mux1. The activation order of the first and second row of subpixels is reversed.
[0073] Meanwhile, since the two valid input levels on the third control line Mux3 are adjacent in time, the two valid input levels on the third control line Mux3 can be combined into a single valid input level. However, extending the input time will result in... Figure 13As can be seen, the duration of each valid input level on the second control line Mux2 is 1 hour, while the duration of each valid input level on the third control line Mux2 is 2 hours. This reduces the amount of data that needs to be stored and processed, reduces power consumption, and allows the display panel to function normally. Similarly, the duration of each valid input level on the first control line Mux1 can be 2 hours, except for the first and last valid input levels which are 1 hours; or the duration of each valid input level on the first control line Mux1 can be 2 hours, except for the first and last valid input levels which are 1 hours.
[0074] In some embodiments, the capacitance of the control transistor is 1000pF. By making the capacitance of the control transistor 1000pF, the active level of the control line input to the gate of the control transistor is smaller, the temperature of the driving chip is lower, thereby improving the stability of the control transistor.
[0075] In some embodiments, the effective voltage of the control line input to the gate of the control transistor is 16 volts, which can improve the reliability of the control transistor.
[0076] Specifically, such as Figure 10 As shown, Figure 10 A line graph showing the relationship between the capacitance of the control transistor and the voltage required to keep the transistor on. Figure 10 The horizontal axis represents Mux C, the capacitance controlling the transistor, measured in pF (picofarads), and the vertical axis represents Vgh, the voltage that keeps the transistor on, measured in volts. Figure 10 As can be seen, when the Vgh voltage is 16 volts, the Mux C is 1000pF. Reducing the capacitance of the control transistor can reduce the Vgh voltage, thereby reducing the voltage on the control transistor and improving its stability.
[0077] In some embodiments, the product of the channel width and channel length of the control transistor is 1300, which results in a smaller capacitance of the control transistor and improves the reliability of the control transistor.
[0078] Specifically, such as Figure 11 As shown, Figure 11 A line graph showing the capacitance of a control transistor as a function of the product of its channel length and channel width. Figure 11 The horizontal axis of Mux TFT W L represents the product of the channel width and channel length of the control transistor, with the vertical axis representing Mux. C represents the capacitance of the control transistor, measured in pF (picofarads). Figure 11As can be seen, when the product of the channel width and channel length of the control transistor is 1300, the Mux C is 1000pF. Reducing the product of the channel width and channel length of the control transistor can reduce the capacitance of the control transistor, thereby improving the stability of the control transistor.
[0079] Specifically, such as Figure 12 As shown, Figure 12 A line graph showing the relationship between the capacitance of the transistor and the temperature of the driver chip. Figure 12 The horizontal axis represents the Mux TFT C, the capacitance of the control transistor, measured in pF (picofarads), and the vertical axis represents the IC temperature, the temperature of the driver chip, measured in degrees Celsius. Figure 12 As can be seen, when VMux C is 1000pf, the temperature of the driver chip is 50 degrees Celsius. Reducing the capacitance of the control transistor can reduce the temperature of the driver chip, thereby improving the stability of the control transistor.
[0080] Specifically, the above embodiments have provided a detailed description of the display panel from aspects such as pixel design, film layer structure, and transistor design. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the width of the active part is less than or equal to 10 micrometers, and the sum of the widths of the multiple active parts in the active pattern is less than or equal to 330 micrometers.
[0081] Meanwhile, this application provides a display device, which includes a display panel as described in any of the above embodiments.
[0082] Specifically, the display device may also include a driver chip, which is connected to the display panel.
[0083] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0084] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0085] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.
[0086] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A display panel, characterized in that, The display panel includes multiple data lines and multiple data input lines, each data input line being electrically connected to at least two of the data lines, and at least one control transistor being provided between each data line and its corresponding data input line. Substrate; An active layer is disposed on one side of the substrate, and the active layer includes the active pattern of the control transistor; Each of the control transistors has an active pattern comprising a plurality of active portions spaced apart.
2. The display panel according to claim 1, characterized in that, The display panel further includes a light-shielding layer disposed between the substrate and the active layer. The light-shielding layer includes a plurality of light-shielding patterns, which are spaced apart along a first direction. The active layer is spaced apart along a second direction. The light-shielding patterns are suspended. The angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.
3. The display panel according to claim 2, characterized in that, The at least one control transistor includes a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, and a sixth control transistor, and the active layer includes an active pattern of the first control transistor, an active pattern of the second control transistor, an active pattern of the third control transistor, an active pattern of the fourth control transistor, an active pattern of the fifth control transistor, and an active pattern of the sixth control transistor. The active patterns of the first control transistor, the second control transistor, and the third control transistor are connected; the active patterns of the fourth control transistor, the fifth control transistor, and the sixth control transistor are connected; and the active pattern of the third control transistor is disconnected from the active pattern of the fourth control transistor.
4. The display panel according to claim 3, characterized in that, The display panel further includes a first control line, a second control line, a third control line, a fourth control line, a fifth control line, and a sixth control line. The first control line, the second control line, the third control line, the fourth control line, the fifth control line, and the sixth control line are respectively connected to the gate of the first control transistor, the gate of the second control transistor, the gate of the third control transistor, the gate of the fourth control transistor, the gate of the fifth control transistor, and the gate of the sixth control transistor. The data input line includes a first data input line and a second data input line. The display panel further includes a gate layer, which is disposed on the side of the active layer away from the substrate. The gate layer includes a first portion of a first control line, a first portion of a second control line, a first portion of a third control line, a first portion of a fourth control line, a first portion of a fifth control line, a first portion of a sixth control line, a first data input line, a second data input line, a first gate connection line, and a second gate connection line. The first portion of the first control line, the first data input line, the first portion of the second control line, the first portion of the third control line, the first portion of the fourth control line, the second data input line, the first portion of the fifth control line, and the first portion of the sixth control line are arranged sequentially along the second direction.
5. The display panel according to claim 4, characterized in that, The display panel further includes a source-drain layer, which includes a second portion of a first control line, a second portion of a second control line, a second portion of a third control line, a second portion of a fourth control line, a second portion of a fifth control line, a second portion of a sixth control line, a first electrode of a first control transistor, a second electrode of a first control transistor, a first electrode of a second control transistor, a second electrode of a second control transistor, a first electrode of a third control transistor, a second electrode of a third control transistor, a first electrode of a fourth control transistor, a second electrode of a fourth control transistor, a first electrode of a fifth control transistor, a second electrode of a fifth control transistor, a first electrode of a sixth control transistor, and a second electrode of a sixth control transistor. Wherein, the second part of the first control line, the second part of the second control line, the second part of the third control line, the second part of the fourth control line, the second part of the fifth control line, and the second part of the sixth control line are respectively connected to the first part of the first control line, the first part of the second control line, the first part of the third control line, the first part of the fourth control line, the first part of the fifth control line, and the first part of the sixth control line; The first electrode of the first control transistor, the first electrode of the second control transistor, and the first electrode of the third control transistor are connected to the first data input line; the first electrode of the fourth control transistor, the first electrode of the fifth control transistor, and the first electrode of the sixth control transistor are connected to the second data input line; the second electrode of the second control transistor is connected to the first gate connection line; and the second electrode of the fourth control transistor is connected to the second gate connection line.
6. The display panel according to claim 5, characterized in that, The first electrode of the first control transistor, the first electrode of the second control transistor, the first electrode of the third control transistor, the first electrode of the fourth control transistor, the first electrode of the fifth control transistor, and the first electrode of the sixth control transistor are spaced apart.
7. The display panel according to claim 4, characterized in that, The width of the gates of the first control transistor, the second control transistor, the third control transistor, the fourth control transistor, the fifth control transistor, and the sixth control transistor is less than or equal to 4 micrometers.
8. The display panel according to claim 4, characterized in that, The distance between the edge of the gate of the first control transistor, the edge of the gate of the second control transistor, the edge of the gate of the third control transistor, the edge of the gate of the fourth control transistor, the edge of the gate of the fifth control transistor, and the edge of the gate of the sixth control transistor and the edge of the corresponding light-shielding pattern is less than or equal to 1.5 micrometers.
9. The display panel according to claim 2, characterized in that, The control transistor includes a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, and a sixth control transistor. The active layer includes active patterns of the first control transistor, the second control transistor, the third control transistor, the fourth control transistor, the fifth control transistor, and the sixth control transistor. The active patterns of the first control transistor, the second control transistor, the third control transistor, the fourth control transistor, the fifth control transistor, and the sixth control transistor are spaced apart.
10. The display panel according to any one of claims 1 to 9, characterized in that, The width of the active part is less than or equal to 10 micrometers, and the sum of the widths of the multiple active parts in the active pattern is less than or equal to 330 micrometers.
11. The display panel according to any one of claims 1 to 9, characterized in that, The display panel further includes an organic layer disposed on the side of the active layer away from the substrate, and the organic layer has a slot in the region corresponding to the control transistor.
12. The display panel according to any one of claims 1 to 9, characterized in that, The display panel also includes multiple rows of sub-pixels, with adjacent rows of sub-pixels being activated in opposite order.
13. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 12.