Segmented zero compensation FVF-LDO circuit
By using a segmented zero-point compensation FVF-LDO circuit and adaptively switching the compensation network topology, the problem of phase margin imbalance in the FVF-LDO circuit over a wide load range is solved, thereby improving stability and robustness across the entire load current domain, reducing power consumption, and decreasing capacitor size.
Patent Information
- Application Number
- CN202610025801.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-09
- Publication Date
- 2026-04-07
AI Technical Summary
Existing FVF-LDO circuits suffer from unbalanced phase margins over a wide load range, insufficient process robustness, and the inability of fixed compensation zero points to adapt to changes in load current, resulting in poor system stability.
A segmented zero-compensation FVF-LDO circuit is adopted. By adaptively switching the compensation network topology, current sensing and a high-precision comparator are used to control the connection and disconnection of the compensation capacitor, thereby optimizing the phase margin.
It significantly improves phase margin across the full load current domain, exhibits strong robustness, low power consumption, and moderate capacitor size, reducing the impact of process angle variations. It is suitable for various low dropout linear regulator circuits.
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Figure CN121807091A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog integrated circuit technology, and specifically to a segmented zero-point compensation FVF-LDO circuit. Background Technology
[0002] With the increasing demands on power management systems in portable electronic devices, high-stability, fast transient response LDOs have become critical modules. At advanced process nodes, the FVF (Flexible Voltage Filter) structure is widely used in LDO design due to its high gain and low impedance characteristics. However, this structure introduces pole drift and zero-point mismatch over a wide load range, especially during transitions between light and heavy loads, leading to a sharp deterioration in phase margin. One compensation scheme uses a fixed RC zero-point network, providing a left-half-plane zero in the loop to improve the phase margin of the FVF loop across the entire load range. However, this fixed compensation capacitor scheme cannot dynamically adapt to load changes ranging from 1uA to 100mA, making it prone to bandwidth reduction due to overcompensation under light loads and oscillations due to undercompensation under heavy loads. It is difficult to unify the compensation schemes under these two conditions, which severely restricts system stability.
[0003] In existing technologies, single zero-point compensation networks face multiple bottlenecks. First, there is a lack of load adaptability. Fixed compensation zero points cannot track the drift of poles with load current. When the load current changes, the loop gain and bandwidth will change. However, the severity of load current changes in the system cannot be fully predicted. Therefore, fixed zero-point compensation will cause the phase margin to fluctuate by more than 40° under typical process conditions, which is extremely unstable. Second, the RC constant is significantly affected by process angle deviations and may lose its compensation effect under some process angles. In addition, over-designing compensation capacitors to cover the entire load range is also an important problem.
[0004] In recent years, with the rapid iteration and booming development of various electronic products, the performance requirements for power management chips have become increasingly stringent. As a key component of power management systems, the circuit design and performance optimization of low-dropout linear regulators (LDOs) also affect the overall performance of the circuit system. Among them, FVF-LDOs, with their fast transient response, fully integrated capacitor-free structure, and high process compatibility, have become an ideal choice for wearable devices, sensor nodes, and SoC power supply modules, laying the technological foundation for the next generation of high-efficiency power management ICs. FVF-LDOs possess wide load adaptability, and their compensation schemes are diverse across the entire load range. Miller compensation, as the most conventional compensation method, often introduces a right-half-plane zero and is frequently used in conjunction with a zero-adjustment resistor to modulate the generated right-half-plane zero to the left-half-plane. However, this comes at the cost of sacrificing a significant amount of bandwidth; the larger the compensation capacitor, the lower the dominant pole frequency and the smaller the bandwidth, especially when the loop gain is very low under light loads. As one of many compensation schemes, zero-point compensation is widely used because it can provide sufficient phase margin under heavy loads. However, as the load current decreases, i.e. under light load conditions, the impedance at the external secondary pole increases, causing the external secondary pole to move to a lower frequency, while the zero position remains almost unchanged, resulting in the separation of the zero and the secondary pole. The existing zero compensation capacitor is insufficient to compensate and stabilize the phase margin under light load conditions. Summary of the Invention
[0005] The purpose of this invention is to address the problems of unbalanced phase margin and insufficient process robustness in existing folded voltage follower type low dropout linear regulators over a wide load range. This invention provides a segmented zero-compensation FVF-LDO circuit, which optimizes the phase margin by adaptively switching the compensation network topology, resulting in a significant improvement in the full load current domain of the zero-compensation folded voltage follower type low dropout linear regulator.
[0006] The technical solution adopted in this invention is as follows: A segmented zero-point compensation FVF-LDO circuit, the circuit comprising an FVF-LDO circuit and a compensation control circuit; The FVF-LDO circuit includes an LDO circuit composed of an operational amplifier and a transistor, a loop clamp, a bias circuit, and a current mirror. The loop clamp is used to transmit the reference voltage, the bias circuit is used to stabilize the branch current, and the current mirror is used to receive the reference voltage modulated by the bias circuit and output an output voltage equal to the reference voltage. The FVF loop is connected to the LDO circuit for zero-point compensation of the LDO circuit. The compensation control circuit is used to collect the current of the LDO circuit, convert the detected low-multiplier current to voltage through a resistor voltage divider, compare the converted voltage with a set reference voltage through a high-precision comparator, and use the comparator output as a control signal for the compensation circuit switch to control the opening and closing of the compensation circuit, thereby realizing zero-point compensation for light loads.
[0007] Furthermore, the FVF-LDO circuit specifically includes: operational amplifier OP1, PMOS transistors MP1, MP2, MP3, MP4, MP5, NMOS transistors MN1, MN2, MN3, MN4, capacitors C1, C2, C3, resistor R1, and transmission gate switch SW1; Specifically, reference VREF is connected to the negative input terminal of OP1; the gate terminal of MP1 is connected to the output terminal of OP1, the source terminal of MP1 is connected to the power supply VDD, and the drain terminal of MP1 is connected to the positive input terminal of OP1, the source terminal of MP3, and the gate terminal of MN2; the two ends of C1 are connected to the gate terminal and the drain terminal of MP1, respectively; the gate terminal of MP3 is connected to the drain terminal of MP3, the drain terminal of MN1, and one end of R1; the other end of R1 is connected to the gate terminal of MP5 and the gate terminal of MN4; the source terminal and the drain terminal of MN4 are both connected to ground VSS; the gate terminal of MN1 is connected to the external bias voltage VBN, and the source terminal of MN1 is connected to ground VSS; the gate terminal of MP2 is connected to the external bias voltage V The source terminals of BP and MP2 are connected to the power supply VDD. The drain terminal of MP2 is connected to the drain terminal of MN2, the gate terminal of MP4, and the gate terminal of MP6. The source terminal of MN2 is connected to the drain terminal of MN3, the drain terminal of MP5, the lower-level board of C2, and the lower-level board of C3. The gate terminal of MN3 is connected to the bias voltage VBN, and the source terminal of MN3 is connected to ground VSS. The source terminal of MP4 is connected to the power supply VDD. The drain terminal of MP4 is the output terminal of the LDO circuit and is connected to the source terminal of MP5, the upper-level board of C2, and the upper terminal of SW1. The lower terminal of SW1 is connected to the upper-level board of C3. The clock input terminal of SW1 is connected to the voltages VSW and VSWN output by the compensation control circuit, respectively.
[0008] Furthermore, the reference voltage VREF is input to the LDO circuit, and the loop clamping of OP1 and MP1 makes the voltage at the positive input terminal of OP1 equal to the voltage at the negative input terminal, completing one transfer of VREF; MN1, MN3, and MP2 are all biased MOS current sources used to stabilize the branch current; by setting the transistor size ratio of MN1, MN3, and MP2, the current in the branch where MP3 is located is equal to the current in the branch where MP5 is located; then, based on the current mirror relationship between MP3 and MP5, VREF is transferred to VOUT, making VREF equal to VOUT.
[0009] Furthermore, the zero-point compensation of the FVF loop is specifically as follows: the major pole of the LDO circuit is located at the gate of MP4, the minor pole is located at the output terminal VOUT, and capacitor C2 is the zero-point compensation capacitor. Zero-point compensation is performed by adjusting the capacitance value of capacitor C2.
[0010] Furthermore, the compensation control circuit specifically includes operational amplifiers OP2 and OP3, PMOS transistors MP6 and MP7, NMOS transistors MN5, MN6, MN7, and MN8, resistors R2 to R9, and inverters INV1 and INV2. In this circuit, the output of the LDO is connected to the positive output of OP2; the drain of MP6 is connected to the negative input of OP2 and the source of MP7, and the source of MP6 is connected to the power supply VDD; the gate of MP7 is connected to the output of OP2, and the drain of MP7 is connected to the drain of MN5, the gate of MN6, and the gate of MN7; the gate of MN5 is connected to the gate of MN8, and the source of MN5 is connected to the drain of MN6; the source of MN6 is connected to ground VSS; the source of MN7 is connected to ground VSS, and the drain of MN7 is connected to the source of MN8; the drain of MN8 is connected to the lower end of R4; and the upper end of R4 is connected to the lower end of R3. The positive input terminal of OP3 is connected to the positive input terminal of OP3; the upper end of R3 is connected to the lower end of R2, and the upper end of R2 is connected to the power supply VDD; the upper end of R5 is connected to the power supply VDD, and the lower end of R5 is connected to the upper end of R6; the upper end of R7 is connected to the lower end of R6, and the lower end of R7 is connected to the upper end of R8 and the negative input terminal of OP3; the upper end of R9 is connected to the lower end of R8, and the lower end of R9 is connected to ground VSS; the input terminal of INV1 is connected to the output terminal of OP3, and the output terminal VSW of INV1 is connected to the input terminal of INV2; the output terminal of INV2 is VSWN; VSW and VSWN are used as clock signals for the transmission gate switch and are connected to SW1.
[0011] Furthermore, in the compensation control circuit, MP6 and MP7, and operational amplifier OP2 collect the current flowing through the LDO circuit. The current is passed through a common-source cascode current mirror composed of MN5, MN6, MN7, and MN8, and copied to the R2, R3, and R4 branches. A voltage is input to the comparator composed of operational amplifier OP3 through a resistor voltage divider. A specified reference voltage is input to the comparator composed of operational amplifier OP3 through a resistor voltage divider network composed of R5, R6, R7, R8, and R9. The two input voltages are compared, and the output results are high and low levels VSWN and VSW, which serve as the clock signal for SW1 and control the compensation capacitor C3 to be connected to the LDO circuit.
[0012] Furthermore, under heavy load, the voltage at the positive input terminal of op-amp OP3 is higher than the fixed reference voltage generated by the resistor divider network. The clock signal VSW generated by the comparator is low and VSWN is high, so switch SW1 is closed, that is, compensation capacitor C3 does not work.
[0013] Furthermore, under light load, the voltage at the positive input terminal of op-amp OP3 is lower than the fixed reference voltage generated by the resistor divider network. The clock signal VSW generated by the comparator is high and VSWN is low, so switch SW1 is turned on, that is, compensation capacitor C3 is working.
[0014] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: This invention discloses a segmented zero-point compensation FVF-LDO circuit with strong robustness: This segmented zero-point compensation circuit is applicable to almost all types of low-dropout linear regulator circuits requiring zero-point compensation; Segmented zero-point compensation technology: Utilizing the characteristic of different secondary pole positions under light and heavy loads, an additional capacitor is connected to the circuit through current sensing to compensate the zero point to the corresponding pole position, thereby improving stability; Low power consumption: Utilizing a high current replication ratio, it does not cause significant power loss to the low-dropout linear regulator; Small capacitor value: Compared with ordinary zero-point compensation or Miller compensation, the capacitor size can be effectively reduced under heavy load conditions; and under light load conditions, the compensation capacitor size of this scheme is also smaller than that of commonly used compensation capacitors; Less affected by process angle changes: Under different process angles, after selecting an appropriate compensation capacitor, the low-dropout linear regulator can achieve stable and good performance. Attached Figure Description
[0015] Figure 1 This is a block diagram of a segmented zero-point compensation FVF-LDO circuit according to the present invention; Figure 2 The circuit diagram for an existing folded voltage follower low-dropout linear regulator; Figure 3 This is a circuit diagram of a segmented zero-point compensation FVF-LDO according to the present invention. Detailed Implementation
[0016] The present invention will now be described in detail with reference to the accompanying drawings.
[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0018] This invention proposes an adaptive adjustment compensation capacitor circuit based on a zero-point compensation FVF-LDO. It monitors the load current by detecting the power transistor current using a high-ratio current mirror. The detected low-multiplier current is converted to voltage via a resistor divider. This voltage is input to a high-precision comparator and compared with a preset fixed voltage, which is a manually selected voltage value generated by a resistor corresponding to a specific low load current. The comparator output (high or low level) is used as a control signal to control the switching on and off of the capacitor array. That is, when the load current is high... During operation, a normally open compensation capacitor is used. When a predetermined low load current is reached, the switch opens, and another compensation capacitor is connected to the circuit to achieve zero-point compensation for light loads. This ensures that the phase margin of the FVF loop remains stable across the entire load range. Traditional Miller compensation, however, cannot simultaneously optimize phase margins under both light and heavy loads, and its bandwidth becomes very low as the load current decreases. Furthermore, the zero-adjustment resistor requires precise control, potentially necessitating calibration circuits or high-precision metal resistors, increasing design complexity. Additionally, the large capacitance requirement of Miller capacitors contradicts the trend towards miniaturization. Therefore, this invention employs a segmented zero-point compensation scheme, eliminating the need for complex zero-adjustment resistor designs, optimizing bandwidth frequency, and improving phase margin across the entire load range.
[0019] like Figure 2 As shown, the basic zero-point compensation scheme also has the problem of not being able to simultaneously optimize the phase margin under light and heavy loads. A fixed left half-plane zero point cannot be fully compatible with the optimization under light and heavy loads. This means that a compensation scheme that meets the phase margin requirements under heavy loads may fail to meet the phase margin requirements when switching to light loads, resulting in a deterioration in the system's transient response. Therefore, this invention, based on this, adopts a segmented compensation scheme specifically to improve the situation of using the zero-point compensation scheme to compensate for FVF-LDOs. Under heavy load conditions, only a fixed small capacitor is used for compensation. When switching to light loads, after system operation through detection and comparison, an additional capacitor is connected to the circuit to perform zero-point compensation under light load conditions together with the original compensation capacitor. The specific implementation is shown in the following example: Example like Figure 1 As shown, a current signal is acquired in a folded voltage follower type LDO and transmitted to the compensation control module, which then generates a pair of inverted clock signals, which are fed back to the LDO to control whether the compensation capacitor is connected or not. This allows for different compensation schemes to be used under different load conditions, thereby achieving system stability across the entire load range. Based on this, this embodiment proposes a segmented zero-point compensation folded voltage follower type FVF low-dropout linear regulator LDO. Addressing the stability issues of zero-point compensation LDOs under different load conditions, different compensation schemes are adopted under different load conditions to achieve segmented compensation, such as... Figure 3 As shown: The overall circuit is divided into two parts: the FVF-LDO main body and the compensation control circuit. In the FVF-LDO main body, the external input VREF is connected to the negative input terminal of operational amplifier OP1. The gate of PMOS transistor MP1 is connected to the output terminal of operational amplifier OP1, its source is connected to the power supply VDD, and its drain is connected to the positive input terminal of operational amplifier OP1, the source of PMOS transistor MP3, and the gate of NMOS transistor MN2. Additionally, the two ends of capacitor C1 are connected to the gate and drain of PMOS transistor MP1, respectively. The gate and drain of PMOS transistor MP3, the drain of NMOS transistor MN1, and one end of resistor R1 are connected. The other end of resistor R1 is connected to the gate of PMOS transistor MP5 and the gate of NMOS transistor MN4. The source and drain of transistor MN4 are both connected to ground VSS. The gate of NMOS transistor MN1, used as a current source, is connected to the external bias voltage VBN, and its source is connected to ground VSS. The gate of PMOS transistor MP2, used as a current source, is connected to the external bias voltage VBP. Its source is connected to the power supply VDD, and its drain is connected to the drain of NMOS transistor MN2, the gate of PMOS transistor MP4, and the gate of PMOS transistor MP6. The source of NMOS transistor MN2 is connected to the drain of NMOS transistor MN3, the drain of PMOS transistor MP5, the lower stage of capacitor C2, and the lower stage of capacitor C3. The gate of NMOS transistor MN3, used as a current source, is connected to the bias voltage VBN, and its source is connected to ground VSS. The source of PMOS transistor MP4 is connected to the power supply VDD, and its drain is the output of the LDO, connected to the source of PMOS transistor MP5, the upper stage of capacitor C2, and the upper end of transmission gate switch SW1. The lower end of transmission gate switch SW1 is connected to the upper stage of capacitor C3, and its clock input is connected to the VSW and VSWN voltages from the compensation control section.
[0020] In the compensation control circuit section, the VOUT output of the pre-amplifier LDO is connected to the positive output of operational amplifier OP2. The drain of PMOS transistor MP6 is connected to the negative input of operational amplifier OP2 and the source of PMOS transistor MP7, whose source is connected to power supply VDD. The gate of PMOS transistor MP7 is connected to the output of operational amplifier OP2, and its drain is connected to the drain of NMOS transistors MN5, MN6, and MN7. The gate of NMOS transistor MN5 is connected to the gate of NMOS transistor MN8, and its source is connected to the drain of NMOS transistor MN6. The source of NMOS transistor MN6 is connected to ground VSS. The source of NMOS transistor MN7 is connected to ground VSS, and its drain is connected to the source of NMOS transistor MN8. The drain of NMOS transistor MN8 is connected to the lower end of resistor R4. The upper end of resistor R4 is connected to the lower end of resistor R3 and the positive input of operational amplifier OP3. The upper end of resistor R3 is connected to the lower end of resistor R2, and the upper end of resistor R2 is connected to power supply VDD. The upper end of resistor R5 is connected to the power supply VDD, and the lower end is connected to the upper end of resistor R6. The upper end of resistor R7 is connected to the lower end of resistor R6, and its lower end is connected to the upper end of resistor R8 and the negative input terminal of operational amplifier OP3. The upper end of resistor R9 is connected to the lower end of resistor R8, and its lower end is connected to ground VSS. The input terminal of inverter INV1 is connected to the output terminal of operational amplifier OP3, and its output terminal VSW is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is VSWN. VSW and VSWN serve as the clock signals for the transmission gate switch and are connected together to switch SW1 in the LDO body.
[0021] The circuit principle of this embodiment is as follows: The working principle of a folded voltage follower type low dropout linear regulator: The reference voltage VREF is input to the LDO. Through the loop clamping of operational amplifier OP1 and PMOS transistor MP1, based on the principle of virtual short and virtual open, the voltage at the positive input terminal of operational amplifier OP1 is made equal to the voltage at the negative input terminal, thus completing one transfer of VREF. MN1, MN3, and MP2 are all biased MOS current sources, providing stable branch current. By setting the transistor size ratio of the above three current sources, the current in the branch where MP3 is located is made equal to the current in the branch where MP5 is located. Based on the current mirror relationship between MP3 and MP5, VREF is transferred to VOUT, making VREF equal to VOUT. MP4, MP5, and MN2 constitute the folded voltage follower structure FVF. The task of handling changes in load weight all occurs within this FVF loop, while the preceding operational amplifier loop only serves to transfer voltage. In other words, the transient response of the LDO is largely independent of the preceding op-amp loop and is primarily affected by the FVF loop performance. The dominant pole of this LDO is located at the gate of the PMOS transistor MP4 and remains fixed. The secondary pole, however, is located at the output VOUT and varies with the load current. To improve system stability, zero-point compensation is used to enhance the phase margin, with capacitor C2 serving as the zero-point compensation capacitor. Under heavy load conditions, the secondary pole frequency of this capacitor is relatively high. By setting an appropriate capacitance value, a left-half-plane zero can be generated at the secondary pole location, thereby improving the phase margin. However, while the position of this left-half-plane zero remains essentially constant, the position of the secondary pole changes under both light and heavy load conditions. Therefore, a fixed zero can only compensate for a limited range of secondary pole frequencies.
[0022] Therefore, the following compensation capacitor control module was adopted: The current flowing through the LDO power transistors is acquired using PMOS transistors MP6 and MP7 and operational amplifier OP2, thus capturing the load current. This is achieved by clamping the gate-drain voltage of MP6 to be the same as that of power transistor MP4; adjusting the size ratio allows for precise replication of the downscaled current. This current is then passed through a common-source, common-gate current mirror composed of MN5, MN6, MN7, and MN8, replicated to the R2, R3, and R4 branches, and input to a comparator composed of operational amplifier OP3 via a resistor divider. A resistor divider network composed of R5, R6, R7, R8, and R9 inputs a specified reference voltage to the comparator composed of operational amplifier OP3. This voltage value is primarily determined by a specified light-load / heavy-load switching threshold, i.e., at what current level a compensation capacitor is connected to the circuit to compensate for light-load conditions. The two inputs are compared, and the outputs are high and low levels VSWN and VSW. These two signals serve as the clock signal for switch SW1, controlling whether the compensation capacitor C3 is connected to the LDO circuit. The functionality is as follows: Under heavy load (i.e., when the load current is large), the voltage at the positive input terminal of op-amp OP3 is higher than the fixed reference voltage generated by the resistor divider network. The clock signal VSW generated by comparator OP3 is low and VSWN is high, so switch SW1 is closed, meaning the compensation capacitor module does not work. Under light load (i.e., when the load current is small), the voltage at the positive input terminal of op-amp OP3 is lower than the fixed reference voltage generated by the resistor divider network. The clock signal VSW generated by comparator OP3 is high and VSWN is low, so switch SW1 is open, meaning the compensation capacitor module works.
[0023] This article uses specific embodiments to illustrate the principles and implementation methods of the present invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
Claims
1. A segmented zero-point compensation FVF-LDO circuit, characterized in that, The circuit includes an FVF-LDO circuit and a compensation control circuit; The FVF-LDO circuit includes an LDO circuit composed of an operational amplifier and a transistor, a loop clamp, a bias circuit, and a current mirror. The loop clamp is used to transmit the reference voltage, the bias circuit is used to stabilize the branch current, and the current mirror is used to receive the reference voltage modulated by the bias circuit and output an output voltage equal to the reference voltage. The FVF loop is connected to the LDO circuit for zero-point compensation of the LDO circuit. The compensation control circuit is used to collect the current of the LDO circuit, convert the detected low-multiplier current to voltage through a resistor voltage divider, compare the converted voltage with a set reference voltage through a high-precision comparator, and use the comparator output as a control signal for the compensation circuit switch to control the opening and closing of the compensation circuit, thereby realizing zero-point compensation for light loads.
2. The segmented zero-point compensation FVF-LDO circuit according to claim 1, characterized in that, The FVF-LDO circuit specifically includes: operational amplifier OP1, PMOS transistors MP1, MP2, MP3, MP4, MP5, NMOS transistors MN1, MN2, MN3, MN4, capacitors C1, C2, C3, resistor R1, and transmission gate switch SW1; Specifically, reference VREF is connected to the negative input terminal of OP1; the gate terminal of MP1 is connected to the output terminal of OP1, the source terminal of MP1 is connected to the power supply VDD, and the drain terminal of MP1 is connected to the positive input terminal of OP1, the source terminal of MP3, and the gate terminal of MN2; the two ends of C1 are connected to the gate terminal and the drain terminal of MP1, respectively; the gate terminal of MP3 is connected to the drain terminal of MP3, the drain terminal of MN1, and one end of R1; the other end of R1 is connected to the gate terminal of MP5 and the gate terminal of MN4; the source terminal and the drain terminal of MN4 are both connected to ground VSS; the gate terminal of MN1 is connected to the external bias voltage VBN, and the source terminal of MN1 is connected to ground VSS; the gate terminal of MP2 is connected to the external bias voltage V The source terminals of BP and MP2 are connected to the power supply VDD. The drain terminal of MP2 is connected to the drain terminal of MN2, the gate terminal of MP4, and the gate terminal of MP6. The source terminal of MN2 is connected to the drain terminal of MN3, the drain terminal of MP5, the lower-level board of C2, and the lower-level board of C3. The gate terminal of MN3 is connected to the bias voltage VBN, and the source terminal of MN3 is connected to ground VSS. The source terminal of MP4 is connected to the power supply VDD. The drain terminal of MP4 is the output terminal of the LDO circuit and is connected to the source terminal of MP5, the upper-level board of C2, and the upper terminal of SW1. The lower terminal of SW1 is connected to the upper-level board of C3. The clock input terminal of SW1 is connected to the voltages VSW and VSWN output by the compensation control circuit, respectively.
3. The segmented zero-point compensation FVF-LDO circuit according to claim 2, characterized in that, The reference voltage VREF is input to the LDO circuit. The loop clamping of OP1 and MP1 makes the voltage at the positive input terminal of OP1 equal to the voltage at the negative input terminal, completing one transfer of VREF. MN1, MN3, and MP2 are all biased MOS current sources used to stabilize the branch current. By setting the transistor size ratio of MN1, MN3, and MP2, the current in the branch where MP3 is located is equal to the current in the branch where MP5 is located. Then, based on the current mirror relationship between MP3 and MP5, VREF is transferred to VOUT, making VREF equal to VOUT.
4. A segmented zero-point compensation FVF-LDO circuit according to claim 2, characterized in that, The zero-point compensation of the FVF loop is as follows: the main pole of the LDO circuit is located at the gate of MP4, the secondary pole is located at the output terminal VOUT, and capacitor C2 is the zero-point compensation capacitor. Zero-point compensation is performed by adjusting the capacitance value of capacitor C2.
5. A segmented zero-point compensation FVF-LDO circuit according to claim 2, characterized in that, The compensation control circuit specifically includes operational amplifiers OP2 and OP3, PMOS transistors MP6 and MP7, NMOS transistors MN5, MN6, MN7, and MN8, resistors R2 to R9, and inverters INV1 and INV2. In this circuit, the output of the LDO is connected to the positive output of OP2; the drain of MP6 is connected to the negative input of OP2 and the source of MP7, and the source of MP6 is connected to the power supply VDD; the gate of MP7 is connected to the output of OP2, and the drain of MP7 is connected to the drain of MN5, the gate of MN6, and the gate of MN7; the gate of MN5 is connected to the gate of MN8, and the source of MN5 is connected to the drain of MN6; the source of MN6 is connected to ground VSS; the source of MN7 is connected to ground VSS, and the drain of MN7 is connected to the source of MN8; the drain of MN8 is connected to the lower end of R4; and the upper end of R4 is connected to the lower end of R3. The positive input terminal of OP3 is connected to the positive input terminal of OP3; the upper end of R3 is connected to the lower end of R2, and the upper end of R2 is connected to the power supply VDD; the upper end of R5 is connected to the power supply VDD, and the lower end of R5 is connected to the upper end of R6; the upper end of R7 is connected to the lower end of R6, and the lower end of R7 is connected to the upper end of R8 and the negative input terminal of OP3; the upper end of R9 is connected to the lower end of R8, and the lower end of R9 is connected to ground VSS; the input terminal of INV1 is connected to the output terminal of OP3, and the output terminal VSW of INV1 is connected to the input terminal of INV2; the output terminal of INV2 is VSWN; VSW and VSWN are used as clock signals for the transmission gate switch and are connected to SW1.
6. A segmented zero-point compensation FVF-LDO circuit according to claim 5, characterized in that, In the compensation control circuit, MP6 and MP7, and operational amplifier OP2 collect the current flowing through the LDO circuit. The current is passed through a common-source cascode current mirror composed of MN5, MN6, MN7, and MN8, and copied to the R2, R3, and R4 branches. A voltage is then input to the comparator composed of operational amplifier OP3 through a resistor divider. A specified reference voltage is input to the comparator composed of operational amplifier OP3 through a resistor divider network composed of R5, R6, R7, R8, and R9. The two input voltages are compared, and the output results are high and low levels VSWN and VSW, which serve as the clock signal for SW1 and control the compensation capacitor C3 to be connected to the LDO circuit.
7. A segmented zero-point compensation FVF-LDO circuit according to claim 6, characterized in that, When under heavy load, the voltage at the positive input terminal of op-amp OP3 is higher than the fixed reference voltage generated by the resistor divider network. The clock signal VSW generated by the comparator is low and VSWN is high, so switch SW1 is closed, that is, compensation capacitor C3 does not work.
8. A segmented zero-point compensation FVF-LDO circuit according to claim 6, characterized in that, When lightly loaded, the voltage at the positive input terminal of op-amp OP3 is lower than the fixed reference voltage generated by the resistor divider network. The clock signal VSW generated by the comparator is high and VSWN is low, so switch SW1 is turned on, that is, compensation capacitor C3 is working.