A memory allocation method, system, medium and product

Abstract

This invention discloses a memory allocation method, system, medium, and product, applied in the field of storage technology. The method includes: monitoring the memory access status of running tasks to obtain memory space release information of the running tasks; determining the physical address of the memory space to be addressed based on the memory space release information; addressing the physical address of the memory space to be addressed to obtain consecutive addressable addresses; and allocating memory space for a memory space request instruction based on the consecutive addressable addresses and the unaddressed physical addresses of the memory space. This improves memory utilization, thereby enhancing the real-time processing performance of tasks.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a memory allocation method, system, medium, and product. Background Technology

[0002] Currently, RISC-V (Reduced Instruction Set Computing-V) RTOS (Real-Time Operating System) applications typically use physical address mapping. When allocating memory resources, they pre-allocate multiple contiguous memory blocks of the same size. If multiple smaller memory spaces exist, they may not be able to be allocated to the task requesting the memory space due to their non-contiguous nature, thus causing a decrease in the real-time processing performance of RISC-V RTOS applications.

[0003] Therefore, how to improve memory utilization and thus enhance the real-time processing performance of tasks is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a memory allocation method, system, medium, and product that can improve memory utilization and thus enhance the real-time processing performance of tasks.

[0005] In a first aspect, the present invention provides a memory allocation method, comprising: monitoring the memory access status of a running task to obtain memory space release information of the running task; determining the physical address of the memory space to be addressed based on the memory space release information; addressing the physical address of the memory space to be addressed to obtain consecutive addressable addresses; and allocating memory space for a memory space request instruction based on the consecutive addressable addresses and the unaddressed physical address of the memory space.

[0006] Optionally, determining the memory space address to be addressed based on the memory space release information includes: if any preset condition in the preset condition set is met, the physical address of the memory space carried in the memory space release information is not used as the physical address of the memory space to be addressed; otherwise, the physical address of the memory space carried in the memory space release information is determined as the physical address of the memory space to be addressed; wherein, the preset condition set includes a first preset condition, a second preset condition, and a third preset condition, the first preset condition is that the memory space requested by the running task is greater than a first preset space threshold, the second preset condition is that the average size of the memory space requested by the most recent preset number of memory space request instructions is greater than a second preset space threshold, and the third preset condition is that the memory space corresponding to the currently unallocated address is greater than the second preset space threshold.

[0007] Optionally, addressing the physical address of the memory space to be addressed to obtain a continuous address includes: addressing the physical address of the memory space to be addressed and setting an address identifier at the end of the address to obtain a continuous address.

[0008] Optionally, monitoring the memory access status of running tasks to obtain memory space release information of the running tasks includes: receiving a memory unit access end instruction, wherein the memory unit access end instruction indicates that the running task has completed the access of the corresponding memory unit, and the memory unit is any memory unit in the memory space of the running task; and determining the space address of the corresponding memory unit as memory space release information.

[0009] Optionally, allocating memory space for a memory space request instruction based on the continuous addressing addresses and the unaddressed physical addresses of memory space includes: if the available continuous physical addresses of unaddressed memory space satisfy the memory space requirement of the memory space request instruction, then allocating memory space for the memory space request instruction from the available continuous physical addresses of memory space.

[0010] Optionally, allocating memory space for a memory space request instruction based on the continuous addressing addresses and the unaddressed physical addresses of memory space further includes: if the available continuous physical addresses of memory space in the unaddressed physical addresses do not meet the memory space requirements of the memory space request instruction, then allocating the available continuous physical addresses of memory space to the memory space request instruction, and allocating the remaining required memory space for the memory space request instruction from the continuous addressing addresses.

[0011] Optionally, allocating memory space for memory space request instructions based on the continuous addressing addresses and unaddressed physical addresses includes: when memory space request instructions for parallel execution tasks corresponding to different processor cores are obtained, if the available continuous physical addresses in the unaddressed physical addresses do not meet the memory space requirements of all memory space request instructions for parallel execution tasks, and there are memory space request instructions with memory space requirements greater than or equal to a third preset space threshold, and memory space request instructions with memory space requirements less than the third preset space threshold, then the available continuous physical addresses are allocated to the memory space request instructions with memory space requirements greater than or equal to the third preset space threshold; if there are remaining continuous physical addresses, they are allocated to the memory space request instructions with memory space requirements less than the third preset space threshold.

[0012] Optionally, after allocating memory space for the memory space request instruction based on the continuous address and the physical address of the unaddressed memory space, the method further includes: caching the address range of the memory space allocated to the memory space request instruction.

[0013] Optionally, it also includes: receiving a memory access address sent by the processor core; if the memory access address is an addressable address, determining the physical address of the memory space corresponding to the memory access address based on the mapping relationship between the addressable address and the physical address of the memory space.

[0014] Optionally, after receiving the memory access address sent by the processor core, the method further includes: determining whether the memory access address is within the address range of the corresponding task; if the memory access address is not within the address range of the corresponding task, generating an alarm.

[0015] Optionally, it also includes: if the memory access address is not within the address range of the corresponding task, then access to the memory access address is prohibited.

[0016] Secondly, the present invention provides a memory allocation system, comprising:

[0017] The memory release monitoring module is used to monitor the memory access of running tasks in order to obtain memory space release information of the running tasks.

[0018] The physical address determination module is used to determine the physical address of the memory space to be addressed based on the memory space release information.

[0019] The physical address addressing module is used to address the physical address of the memory space to be addressed, so as to obtain a continuous address.

[0020] The address allocation module is used to allocate memory space for memory space request instructions based on the continuous addressed addresses and the physical addresses of unaddressed memory space.

[0021] Optionally, it also includes: an address resolution module, used to receive the memory access address issued by the processor core; if the memory access address is an addressable address, then the physical address of the memory space corresponding to the memory access address is determined based on the mapping relationship between the addressable address and the physical address of the memory space.

[0022] Thirdly, the present invention provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the aforementioned memory allocation method.

[0023] Fourthly, the present invention provides a computer program product, including a computer program / instruction that, when executed by a processor, implements the aforementioned memory allocation method.

[0024] As can be seen, the beneficial effects of the present invention are as follows: It monitors the memory access status of running tasks to obtain memory space release information of the running tasks, determines the physical address of the memory space to be addressed based on the memory space release information, and then addresses the physical address of the memory space to be addressed to obtain a continuous address. When allocating memory space, it allocates memory space for memory space request instructions based on the continuous address and the unaddressed physical address of the memory space. Thus, by monitoring and obtaining memory space release information, determining the physical address of the memory space to be addressed, and addressing it as a continuous address for allocating memory space, it can improve memory utilization and thereby improve the real-time processing performance of tasks. Attached Figure Description

[0025] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is an architecture diagram of memory management in a RISC-V CPU RTOS system application in the prior art;

[0027] Figure 2 This is a schematic diagram of physical memory allocation in a RISC-V CPU RTOS system application in the prior art;

[0028] Figure 3 A flowchart of a memory allocation method provided in an embodiment of the present invention;

[0029] Figure 4 This is an application architecture diagram of a memory allocation scheme provided in an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of a hybrid address reordering unit provided in an embodiment of the present invention;

[0031] Figure 6 A schematic diagram of an instruction decomposition unit provided in an embodiment of the present invention;

[0032] Figure 7 A schematic diagram of an address monitoring unit provided in an embodiment of the present invention;

[0033] Figure 8 This is a schematic diagram of a memory allocation system provided in an embodiment of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0035] The terms "comprising" and "having," and any variations thereof, in the specification and accompanying drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may include steps or units not listed.

[0036] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] An RTOS (Real-Time Operating System) is an operating system specifically designed for real-time computing needs. In an RTOS, deterministic response tasks must be completed within strict time constraints (hard real-time) or as quickly as possible (soft real-time). It is suitable for mission-critical applications such as medical devices (pacemakers, ventilators), autonomous driving, and flight control systems. A physical address is the actual address used by the computer's memory hardware, directly corresponding to the physical location on the memory chip. A virtual address is the logical address used by a program at runtime, mapped from a physical address by the operating system and the Memory Management Unit (MMU). This mapping from virtual to physical addresses enables memory protection, sharing, and efficient utilization.

[0038] The most significant characteristic of implementing RISC-V RTOS systems in traditional solutions is the high real-time processing of software tasks, requiring highly controllable / deterministic response times. To meet the requirements of RTOS systems, traditional solutions employ direct physical mapping of application memory, avoiding virtual address mapping (because virtual address mapping is susceptible to page faults, causing unpredictable memory access latency). Traditional RISC-V CPU (Central Processing Unit) RTOS system implementations suffer from two major drawbacks: Drawback 1: Because application software uses physical address mapping and pre-allocates multiple contiguous memory blocks of the same size, it cannot efficiently utilize already released physical memory. Drawback 2: Since application software executes directly using physical addresses within the RISC-V CPU, there is a risk of tasks accessing each other's physical memory addresses abnormally during multitasking, leading to memory data leaks. The first drawback is the inefficient use of physical memory space. Because traditional solutions use physical addresses, non-contiguous physical memory blocks cannot be allocated to the RTOS software. This results in idle physical memory space that the RISC-V RTOS software tasks cannot use, leading to reduced memory utilization. The second drawback is memory data leakage. The independence of memory addresses between multiple tasks cannot be guaranteed, allowing task A to illegally access, obtain, or even modify data in task B's memory space, causing data leaks and even abnormal execution between tasks (when task data is illegally / abnormally modified).

[0039] See Figure 1 As shown, Figure 1 This is an architecture diagram of memory management in a RISC-V CPU RTOS system application in the prior art. RISC-V cores refer to individual cores; see [link to relevant documentation]. Figure 2 As shown, Figure 2 This is a schematic diagram of physical memory allocation in a RISC-V CPU RTOS system application in the prior art.

[0040] like Figure 1The memory management process in traditional RISC-V CPU RTOS systems is as follows: Software programs (software tasks) running in the RTOS system request allowed memory space from the RTOS. The memory allocation unit is responsible for memory allocation in the RTOS system. First, the memory allocation unit divides the memory in the RISC-V CPU system into equal spaces, such as dividing 512MB of memory into 256 equal parts, each part being 2MB in size. The RTOS system then binds tasks to physical memory based on the memory allocation unit's allocation of physical memory and the software tasks' memory requirements (space requests). Figure 2 Task A requests 6MB of physical space. The RTOS then allocates 6MB of physical space to Task A. Thus, the memory access space in the instructions compiled from Task A's code is as follows: Figure 2 The space allocated to task A. Similarly, if task B requests 9MB of physical space, the RTOS will allocate 10MB of physical space to task B. Thus, the memory access space in the instructions compiled from task B's code will be as follows: Figure 2 The space allocated to task B is 6MB. (The reason for requesting 9MB but allocating 10MB is because each memory segment is 2MB in size). Task C requests 6MB of physical space, and the RTOS allocates 6MB of physical space to task C. Thus, the memory access space in the instructions compiled from task C's code is as follows... Figure 2 The space of C.

[0041] In the steps described above, the instructions compiled for tasks A / B / C all use real physical memory addresses, while the RTOS system, although... Figure 1 While illustrated separately, in actual operation, the RTOS system also runs on DDR (Double Data Rate Synchronous Dynamic Random-Access Memory). Task instructions are stored in the ICache (instruction cache) after RTOS compilation. The RISC-V Core (a RISC-V processor core consisting of an instruction fetch unit, decode unit, execution unit, memory access unit, and write-back unit) reads instructions from the ICache for execution. During instruction execution, if a memory access instruction is required—that is, an instruction that needs to load data into or read data from memory—the data is written to or read from memory based on the address information in the instruction (in traditional RTOS applications, this address information refers to the physical memory address). In traditional solutions... Figure 2In the process, after tasks A and C are completed, their corresponding 12MB of memory space has already been released. However, if task D requests 12MB of memory space from the RTOS at this time, there is no contiguous 12MB of memory space available (the memory address requested by the task must be contiguous, while the RTOS uses physical addresses, so there must be a contiguous 12MB of physical memory address). It can only wait until task B is completed and the corresponding memory is released, and then the memory management unit and the RTOS will reallocate a contiguous 12MB address to task D.

[0042] Therefore, when handling multiple tasks, there is a risk of tasks accessing each other's physical memory addresses abnormally, leading to memory data leaks. For example... Figure 2 In this RISC-V RTOS system, the physical addresses used by Task A and Task B are physically contiguous. This can lead to situations where Task A accidentally accesses Task B's physical memory. For example, if Task A enters debug mode, the user controls the operation, but is not fully aware of the allocated physical memory space. Therefore, there's a high probability of accessing a boundary memory region that originally belonged to Task B, causing data leaks or overwriting of Task B's data, resulting in abnormal execution. Furthermore, because of the physical address mapping method and the pre-allocation of multiple contiguous memory blocks of the same size, efficient utilization of released physical memory is limited. As illustrated above, this prevents efficient and reasonable use of numerous small, idle physical memory spaces, leading to a decline in the real-time processing performance of the RISC-V RTOS system.

[0043] To address this, the present invention provides a memory allocation scheme that improves memory utilization, thereby enhancing real-time processing performance of tasks. Furthermore, it improves data security.

[0044] Next, a memory allocation method provided by an embodiment of the present invention will be described in detail. Figure 3 This invention provides a flowchart of a memory allocation method, which includes:

[0045] Step S11: Monitor the memory access status of running tasks to obtain memory space release information of the running tasks.

[0046] The memory space release information may include the address of the released memory space. Tasks can release the memory space they have requested in succession. In this embodiment, monitoring the memory access status of running tasks to obtain the memory space release information of the running tasks includes: receiving a memory unit access end instruction, wherein the memory unit access end instruction indicates that the running task has completed the access of the corresponding memory unit, and the memory unit is any memory unit in the memory space of the running task; and determining the space address of the corresponding memory unit as the memory space release information.

[0047] In this embodiment, a memory unit can be the smallest unit of space allocation, such as 2M. This embodiment can utilize a memory release monitoring module to monitor the real-time access status of allocated memory by software tasks that have completed memory allocation. It can obtain memory space allocation information corresponding to the software task, monitor the memory access status of running tasks, and obtain memory space release information for the running tasks.

[0048] This embodiment modifies the compiler in the RTOS to generate a new instruction, ACCESS_END (i.e., a memory access completion instruction). After completing the access to any memory unit, an ACCESS_END instruction is issued. The memory release monitoring module receives this instruction and can then determine that the memory unit has completed its corresponding task in the current software task's memory access, allowing it to be released early without waiting for the entire current task to finish processing before releasing the entire memory space. This timely memory release information enables subsequent processing and ensures faster addressing when needed.

[0049] Step S12: Determine the physical address of the memory space to be addressed based on the memory space release information.

[0050] In an optional embodiment, determining the memory space address to be addressed based on the memory space release information includes: if any preset condition in the preset condition set is met, the physical address of the memory space carried in the memory space release information is not used as the physical address of the memory space to be addressed; otherwise, the physical address of the memory space carried in the memory space release information is determined as the physical address of the memory space to be addressed; wherein, the preset condition set includes a first preset condition, a second preset condition, and a third preset condition, the first preset condition is that the memory space requested by the running task is greater than a first preset space threshold, the second preset condition is that the average size of the memory space requested by the most recent preset number of memory space request instructions is greater than a second preset space threshold, and the third preset condition is that the memory space corresponding to the currently unallocated address is greater than the second preset space threshold.

[0051] The first preset condition avoids addressing large blocks of physical memory. This first preset threshold can be pre-set or adjusted; for example, it could be 200MB. A second preset threshold indicates that the average size of memory requested by a recent preset number of memory allocation instructions is greater than the average size of the requested memory. This avoids addressing large blocks of memory, ensuring that subsequent tasks have more physical memory available for allocation when requesting large blocks. The second preset threshold can also be pre-set or adjusted, such as to 100MB. The third preset condition indicates that there are currently enough addressable addresses, so there's no need to rush to address free physical addresses. Since tasks using physical addresses are more efficient than those using addressable addresses, this submodule creates a combined address for each task. This maintains flexibility between addressable and physical addresses, preserving as much contiguous physical memory space as possible without affecting normal memory allocation.

[0052] Since the released memory space may include memory space corresponding to an address, in other embodiments, the first preset condition can be adjusted to satisfy the condition if the memory space requested by the running task is greater than a first preset space threshold, and the space corresponding to the physical address in the memory space requested by the running task is greater than the preset threshold. That is, addressing can also be performed if it includes space corresponding to a smaller physical address.

[0053] Step S13: Address the physical address of the memory space to be addressed to obtain a continuous address.

[0054] In this embodiment, a target address can be selected, and addressing continues from the target address to obtain consecutive addressable addresses. That is, the address corresponding to the physical address of the memory space to be addressed is consecutive to the target address. In an optional implementation, the target address can be the last address of all current addressable addresses. In another optional implementation, the target address can be the last address of a certain addressable address segment. If there is no address to be addressed yet, addressing starts from a preset initial address.

[0055] It is understood that the memory space release information may contain addressable addresses and / or physical addresses. In an optional implementation, the address carried in the memory space release information may be determined as the address to be re-addressed if any preset condition in a preset condition set is met, and then the address to be re-addressed is re-addressed. In another optional implementation, the address carried in the memory space release information is directly determined as the address to be re-addressed, and then the address to be re-addressed is re-addressed, so that it is continuous with the current address.

[0056] Furthermore, the physical address of the memory space to be addressed is addressed to obtain a continuous addressable address. This includes: addressing the physical address of the memory space to be addressed and setting an addressing address identifier at the end of the address to obtain a continuous addressable address. Since bit 0 (i.e., the last bit of the address) is always 0, it can be set to 1 as an addressing address identifier to distinguish between physical addresses and addressable addresses. For example, 0x0000_0000---0x0000_1000, 0x0000_3000---0x0000_4000, and 0x0001_0000---0x0001_1000 belong to the idle space reported by the memory release monitoring module, and are uniformly addressed as 0x0000_0001---0x0000_3001. In this way, continuous addressing of non-contiguous physical memory space is achieved. If task E uses address space, after the memory space 0x0002_2001---0x0002_4001 is freed, this memory space needs to be re-addressed. If the space that has been re-addressed at the time of freeing is 0x0000_0001----0x0010_0001, then the freed space is encoded at the end of the address space, forming a new address space 0x0000_0001----0x0010_2001. After re-addressing, the mapping relationship between the address space and the physical address of the memory space is also obtained.

[0057] Step S14: Allocate memory space for the memory space request instruction based on the continuous addressing addresses and the physical addresses of the unaddressed memory space.

[0058] In an optional embodiment, if the available contiguous physical addresses in the unaddressed memory space can satisfy the memory space requirement of a memory request instruction, then memory space is allocated to the memory request instruction from the available contiguous physical addresses. If the available contiguous physical addresses in the unaddressed memory space cannot satisfy the memory space requirement of a memory request instruction, then the available contiguous physical addresses are allocated to the memory request instruction, and the remaining required memory space is allocated to the memory request instruction from the contiguous addressed addresses.

[0059] In other words, physical addresses of memory space are allocated first. If there are not enough physical addresses of memory space, then addressable addresses are allocated to ensure access efficiency.

[0060] In an optional embodiment, when memory space request instructions for parallel execution tasks corresponding to different processor cores are obtained, if the available contiguous physical addresses of unaddressed memory space do not meet the memory space requirements of all memory space request instructions for parallel execution tasks, and there are memory space request instructions with memory space requirements greater than or equal to a third preset space threshold, and memory space request instructions with memory space requirements less than the third preset space threshold, then the available contiguous physical addresses of memory space are allocated to the memory space request instructions with memory space requirements greater than or equal to the third preset space threshold; if there are remaining contiguous physical addresses of memory space, they are allocated to the memory space request instructions with memory space requirements less than the third preset space threshold.

[0061] In this context, parallel task execution can be understood as the difference between the start times being less than a threshold. In this embodiment of the invention, physical memory addresses can be preferentially allocated to instructions with larger memory space requirements. Furthermore, for memory request instructions whose memory space requirements are less than a third preset threshold and for which there are remaining contiguous physical memory addresses, the memory request instructions can be split into a first memory request instruction and a second memory request instruction. This allows the first memory request instruction to be allocated remaining contiguous physical memory addresses, and the second memory request instruction to be allocated address addresses, thus satisfying the memory space requirements before splitting.

[0062] Furthermore, after allocating memory space for the memory space request instruction based on the continuous address and the physical address of the unaddressed memory space, the method further includes: caching the address range of the memory space allocated to the memory space request instruction.

[0063] This embodiment can cache the mapping relationship between tasks and address ranges. A task is the task corresponding to a memory space allocation instruction. The address range can include the physical address range and / or the address range of the memory space allocated to the task.

[0064] In addition, this embodiment can also receive memory access addresses sent by the processor core; if the memory access address is an addressable address, the physical address of the memory space corresponding to the memory access address is determined based on the mapping relationship between the addressable address and the physical address of the memory space.

[0065] In this embodiment, the memory access address can be a physical address in memory space or an addressable address. For an addressable address, the corresponding physical address in memory space is determined.

[0066] Furthermore, after receiving the memory access address from the processor core, it can be determined whether the memory access address is within the address range of the corresponding task; if the memory access address is not within the address range of the corresponding task, an alarm is generated. If the memory access address is not within the address range of the corresponding task, access to the memory access address is prohibited.

[0067] In this embodiment, an alarm interrupt can be generated to stop reading and writing to spaces not currently in use by disabling access.

[0068] As can be seen, this embodiment of the invention monitors the memory access of running tasks to obtain memory space release information of the running tasks, determines the physical address of the memory space to be addressed based on the memory space release information, and then addresses the physical address of the memory space to be addressed to obtain a continuous set of addresses. When allocating memory space, memory space is allocated for memory space request instructions based on the continuous addressing addresses and the unaddressed physical addresses of the memory space. In this way, by monitoring and obtaining memory space release information, determining the physical address of the memory space to be addressed, and assigning it a continuous set of addresses for memory space allocation, memory utilization can be improved, thereby improving the real-time processing performance of tasks. Furthermore, data security is enhanced.

[0069] Further, see Figure 4 As shown, Figure 4 This invention provides an application architecture diagram for a memory allocation scheme, specifically, an architecture diagram for memory management in a RISC-V CPU RTOS system application. This invention adds an instruction decomposition unit, a hybrid address reordering unit, and an address monitoring unit. These features enable logical reordering and efficient allocation of idle physical memory, synchronous instruction decomposition of task memory request instructions based on real-time idle physical memory status, and dynamic security monitoring of multi-task memory access addresses. This significantly improves the memory utilization of the RISC-V CPU RTOS system, greatly enhances the real-time performance of task processing, and ensures the security of memory data between multiple tasks, guaranteeing the safe and reliable operation of multiple tasks.

[0070] See Figure 5 As shown, Figure 5 This diagram illustrates a hybrid address reordering unit provided in an embodiment of the present invention. The hybrid address reordering unit collects idle memory units in physical memory, performs combined address encoding (i.e., addressing), and allocates hybrid addresses (including combined addresses (i.e., addressable addresses) used by software tasks according to memory request instructions. It achieves logical reordering and efficient allocation of idle physical memory. It includes a memory release monitoring module, an addressable address generation module, and an addressable address and physical address allocation module.

[0071] Memory Release Monitoring Module: This submodule monitors the real-time access status of allocated memory by software tasks that have completed memory allocation. It receives detailed memory allocation information from each software task. In this invention, the compiler in the RTOS is modified to generate a new instruction, ACCESS_END. After a task instruction completes its memory access to the corresponding memory block (based on the smallest unit of memory allocation, such as 2MB in the previous example), it issues the ACCESS_END instruction. The memory release monitoring module receives this instruction and can then determine that the memory block has completed its corresponding task in the current software task's memory access, allowing it to be released early without waiting for the entire current task to finish processing before releasing the entire memory space. Figure 2 Task A in the example uses 6MB of memory. After using the first 2MB of space, a new ACCESS_END instruction is added to the execution instructions for Task A. The memory release monitoring module then uses the first 2MB of space as the release space and synchronizes its memory address information to the subsequent modules. Since the memory release monitoring module knows the memory space of the entire task, it knows that the entire memory space corresponding to the task can be released after receiving the corresponding number of ACCESS_END instructions. For example, if Task A occupies 6MB of memory, after receiving 6 / 2 = 3 ACCESS_END instructions, it means that the memory access of Task A has been completed, and all space can be released. In other words, this embodiment of the invention uses a memory release monitoring module to monitor the memory access of running tasks to obtain memory space release information for the running tasks.

[0072] Address Generation Module: This module combines the non-contiguous physical address spaces reported by the memory release monitoring module, re-addresses these physical spaces, and obtains the combined address. To distinguish it from the physical address, bit 0 of the combined address is set to 1. Since physical addresses change in steps of 4 (e.g., 0x4, 0x8), bit 0 of the physical address is always 0. For example, if the original addresses 0x0000_0000---0x0000_1000, 0x0000_3000---0x0000_4000, and 0x0001_0000---0x0001_1000 belong to the idle space reported by the memory release monitoring module, they are uniformly addressed as 0x0000_0001---0x0000_3001. Understandably, there are 0x1000 free address segments from 0x0000_0000 to 0x0000_1000, 0x1000 free address segments from 0x0000_3000 to 0x0000_4000, and 0x10001_1000, for a total of 0x3000 free address space. However, these address segments are not contiguous. This application addresses these 0x3000 segments to 0x0000_0001 to 0x0000_3001, keeping the total address space at 0x3000. This achieves contiguous addressing of non-contiguous physical memory space. Simultaneously, the memory release monitoring module must also monitor the operation of tasks using combined address spaces, release combined addresses in a timely manner, and then re-address the free memory addresses using combined addresses. For example, if task E uses combined addresses, after its space 0x0002_2001---0x0002_4001 is released, this memory space must continue to be programmed into a new combined address space. If, at the time of the space release, the space already addressed by the combined address generation module is 0x0000_0001----0x0010_0001, then the released space is encoded to the end of the address space, forming a new combined address 0x0000_0001----0x0010_2001. That is, based on the combined address range 0x0000_0001----0x0010_0001, a new freed combined address space (0x0002_2001---0x0002_4001, a total of 0x2000) is added, thus expanding the combined address range to 0x0000_0001----0x0010_2001. In other words, the address generation module includes a physical address addressing module, used to address the physical addresses of the memory space to be addressed, obtaining consecutive addressable addresses.

[0073] Addressing and Physical Address Allocation Module: The main function of this module is to respond to memory space request instructions (details of which will be discussed below). For example, if a memory space request instruction requests 100MB of memory, memory using physical addresses should be allocated first, followed by memory using combined addresses. If there is 60MB of contiguous physical memory, then 40MB of combined address space memory will be allocated. This module also needs to determine whether contiguous physical memory space should be addressed using combined addresses. The determination principle is as follows: Condition 1: If the memory space requested by the running software task (software program) is large (e.g., greater than the agreed default value SIZE0 = 200MB), i.e., the aforementioned first preset condition; Condition 2: Monitor the average size of memory space requested by previous memory request instructions (e.g., the average size of memory requested by 10 memory request instructions is greater than 100MB), i.e., the aforementioned second preset condition; Condition 3: The memory space corresponding to the currently unallocated combined address is sufficient to meet the average size of the memory space described in Condition 2, i.e., the aforementioned third preset condition. If any one of conditions 1, 2, or 3 is met, the memory space gradually released by the current software task (e.g., memory blocks in 2MB units) will not be included in the combined address space. Instead, it will wait for the current task to complete and release the entire physical memory space, continuing to be used as the memory space for physical address encoding. If none of conditions 1, 2, or 3 are met, the released physical addresses will be addressed. It can be understood that if the average size of the memory space is greater than the threshold SIZE_DEFAULT, it indicates that the predicted memory request space for processes during this period is large, and more contiguous physical addresses should be reserved for subsequent processes, rather than immediately addressing combined addresses as soon as any free physical address becomes available. If there is currently enough combined address space, there is no need to rush to address the free physical address space using combined address mode.

[0074] This approach maintains flexibility between combined and physical addresses, preserving as much contiguous physical memory space as possible without affecting the normal memory allocation of tasks (ensuring the real-time performance of RTOS multitasking). This ensures that subsequent tasks have more memory space available when requesting large blocks of memory. (This is because tasks using physical address memory space are more efficient in execution and memory access than those using combined address memory space, requiring no additional address processing and directly accessing the corresponding memory). Simultaneously, this module creates a combined address space for each task.

[0075] It is understood that the addressing and physical address allocation module includes an address allocation module and a physical address determination module. The address allocation module allocates memory space for memory space request instructions based on the consecutive addressable addresses and the physical addresses of unaddressed memory space. The physical address determination module is used to determine the physical address of the memory space to be addressed based on the memory space release information. In optional embodiments, the physical address determination module can also be included in the memory release monitoring module, or it can be a separate module.

[0076] Further, see Figure 6 As shown, Figure 6 This is a schematic diagram of an instruction decomposition unit provided in an embodiment of the present invention. The instruction decomposition unit's function is to decompose memory space allocation instructions based on feedback information from the hybrid address reordering unit and the space requirements of memory space allocation instructions. This ensures fast memory allocation for tasks, guaranteeing real-time task processing, and simultaneously ensuring the rapid execution of tasks corresponding to large memory allocation instructions. It may include an address space analysis module, a task instruction analysis module, and an instruction decomposition module.

[0077] The address space analysis module receives feedback information from the hybrid address reordering unit. This feedback information includes the allocatable physical address space and the combined address space. Another important function of this module is to parse memory allocation instructions and the size of the memory space to be allocated. The following pseudocode can be used to illustrate this:

[0078] `li a0, 1024` # Parameter `size` = 1024 bytes are stored in `a0`.

[0079] call pvPortMalloc # Call the allocation function

[0080] mv s0, a0 # Save the return value (ptr) to the reserved register s0

[0081] The pseudocode described above obtains a contiguous block of 1024 bytes of memory by calling an allocation function and places the starting address of that memory block into the s0 register. The crucial pseudocode call pvPortMalloc is compiled into a jump instruction jal. This module determines whether the jump instruction is a memory allocation instruction by checking if its destination address matches the memory address of the allocation function. It also obtains the size of the requested memory space, SIZE_APPLY.

[0082] Task instruction analysis module: This module is used to determine the memory space requested by the memory space allocation instructions in each task (the task to be executed in parallel corresponding to each RISC-V Core), and to determine whether the space is greater than the agreed size (e.g., SIZE1 > 100M). The instructions of multi-tasks are located in different ICaches and need to be retrieved and executed by different RISC-V Cores (e.g., there are 8 RISC-V Cores in an 8-core RISC-V CPU). Therefore, this module will retrieve and analyze the space requirements of the instructions in the ICaches of different RISC-V Cores in parallel.

[0083] Instruction splitting module: This module splits instructions based on the size (space requirement) of each memory request instruction to be executed in parallel, the available contiguous physical address memory space, and the available combined address memory space. Condition 4 is defined as: if there is space larger than the agreed size (e.g., SIZE1 > 100M) and there are instructions smaller than SIZE1; Condition 5: available contiguous physical address memory space > SIZE1. If both conditions 4 and 5 are true: then contiguous physical memory is prioritized for tasks requiring space larger than the agreed size. For instructions with smaller space requirements, if there is insufficient space in the remaining contiguous physical memory, the current memory request instruction is split. For example, if the original memory request space is 50M and the available contiguous physical memory is 20MB, then the current memory request instruction is split into two: Instruction 1 uses 20MB of contiguous physical memory, and Instruction 2 uses 30MB of combined address memory. If there is sufficient space in the remaining contiguous physical memory, then the corresponding contiguous physical memory is allocated according to the size of the memory request instruction. Instructions 1 and 2 are passed to the addressing and physical address allocation module. In other words, the instruction splitting module can determine whether, given memory space request instructions for parallel tasks corresponding to different processor cores, the available contiguous physical addresses in the unaddressed memory space can satisfy the memory space requirements of all memory space request instructions for the parallel tasks, and whether there are memory space request instructions with memory space requirements greater than or equal to a third preset threshold, and memory space request instructions with memory space requirements less than the third preset threshold. That is, if multi-core tasks are executed in parallel, meaning the start time difference is relatively small, and if there is a large memory space requirement, it is preferentially allocated to the contiguous physical addresses of that task. If there are no memory space request instructions with memory space requirements greater than or equal to the third preset threshold, and no memory space request instructions with memory space requirements less than the third preset threshold, then instruction splitting is not performed. Similarly, if the available contiguous physical addresses in the unaddressed memory space can satisfy the memory space requirements of all memory space request instructions for the parallel tasks, instruction splitting is also not performed; all corresponding physical addresses are allocated.

[0084] This enables fast memory allocation for tasks, ensuring real-time task processing and fast execution of large memory allocation instructions. In scenarios using combined addresses, the corresponding physical memory is always of sufficient size, so there are no access misses for the software program, thus guaranteeing access latency and consequently ensuring task real-time performance.

[0085] Further, see Figure 7 As shown, Figure 7 This is a schematic diagram of an address monitoring unit provided in an embodiment of the present invention. The address monitoring unit monitors the range of memory space accessed by different tasks, ensuring that, under the premise of using physical addresses + combined addresses, no abnormal access to memory data between different tasks occurs, improving memory data security and ensuring the normal execution of RISC-V CPU RTOS system applications. Simultaneously, this module performs combined address parsing, ensuring that even when task instructions use combined addresses, the correct corresponding physical memory address space can still be accessed. The address monitoring unit includes an address parsing module, a multi-task memory space judgment module, and an alarm module.

[0086] The address resolution module is a submodule that resolves the actual physical address of the current memory access based on the memory access address sent by the RISC-V Core and the address space allocated to each task by the hybrid address reordering unit. According to the previous description, if address information bit0=1, it means that a composite address is used. Then, based on the combination relationship between the composite address and the physical address set in the composite address generation module, the actual physical address is obtained.

[0087] The multi-task memory space judgment module receives and caches the address space allocated by the addressing address in the hybrid address reordering unit and the memory address space of each task allocated by the physical address allocation module (because the space range of the combined address changes in real time, the allocation space must be cached for each task), including the combined address and the physical address. At the same time, it monitors whether the range of memory access addresses issued by the current task is within the range of the combined address and physical address of the current task.

[0088] The alarm module generates an alarm interrupt and stops reading and writing to the space of non-current tasks if the memory access address issued by the RISC-V Core executing the current task is not within the range of the combined address and physical address of the current task.

[0089] This approach adds an instruction decomposition unit, a hybrid address reordering unit, and an address monitoring unit, enabling logical reordering and efficient dynamic allocation of idle physical memory. It also synchronously decomposes task memory request instructions based on real-time idle physical memory status, and dynamically monitors the memory access addresses of multiple tasks. Furthermore, it ensures the real-time performance of multi-task parallel execution. This solution significantly improves the memory utilization of the RISC-V CPU RTOS system, greatly enhances the real-time performance of task processing, and guarantees the security of memory data between multiple tasks, ensuring safe and reliable operation of multiple tasks.

[0090] This invention designs and implements the logical reordering and efficient allocation of idle small blocks of physical memory. It uses hybrid addressing (including combined and physical addresses) for memory space configuration of software tasks, significantly improving the memory utilization of RISC-V CPURTOS systems. It implements instruction decomposition for memory allocation instructions, prioritizing the use of contiguous physical memory space for tasks requesting large amounts of memory, while simultaneously enabling fast memory allocation for tasks. This ensures the real-time processing of the current task and the rapid execution of tasks corresponding to other memory allocation instructions. Furthermore, it synchronously implements a memory data security mechanism for multi-tasking RTOS, guaranteeing that each task can safely and independently access its own memory space, ensuring the safe and normal execution of multiple tasks.

[0091] This invention enables hardware design of the aforementioned modules, namely, proposing a hardware design scheme to optimize memory management in RISC-V CPU RTOS system applications, thereby improving the performance of RISC-V CPU RTOS system applications, ensuring data security between multiple tasks, improving memory utilization, improving the real-time performance of software tasks, improving the corresponding memory management efficiency, and improving the real-time performance of RTOS processes.

[0092] See Figure 8 As shown, this embodiment of the invention provides a memory allocation system, including:

[0093] The memory release monitoring module 11 is used to monitor the memory access of running tasks in order to obtain memory space release information of the running tasks.

[0094] The physical address determination module 12 is used to determine the physical address of the memory space to be addressed based on the memory space release information.

[0095] The physical address addressing module 13 is used to address the physical address of the memory space to be addressed, so as to obtain a continuous address.

[0096] Address allocation module 14 is used to allocate memory space for memory space request instructions based on the continuous addressing addresses and the physical addresses of unaddressed memory space.

[0097] Furthermore, the system may also include: an address resolution module, used to receive a memory access address issued by the processor core; if the memory access address is an addressable address, then the physical address of the memory space corresponding to the memory access address is determined based on the mapping relationship between the addressable address and the physical address of the memory space.

[0098] The physical address determination module 12 can be specifically used to: if any preset condition in the preset condition set is met, then the physical address of the memory space carried in the memory space release information is not used as the physical address of the memory space to be addressed; otherwise, the physical address of the memory space carried in the memory space release information is determined as the physical address of the memory space to be addressed; the preset condition set includes a first preset condition, a second preset condition, and a third preset condition, wherein the first preset condition is that the memory space requested by the running task is greater than a first preset space threshold, the second preset condition is that the average size of the memory space requested by the most recent preset number of memory space request instructions is greater than a second preset space threshold, and the third preset condition is that the memory space corresponding to the currently unallocated address is greater than the second preset space threshold.

[0099] The physical address addressing module 13 can be specifically used to: address the physical address of the memory space to be addressed, and set the addressing address identifier at the end of the address to obtain a continuous addressing address.

[0100] The memory release monitoring module 11 can be specifically used to: receive a memory unit access end instruction, wherein the memory unit access end instruction indicates that the running task has completed the access of the corresponding memory unit, and the memory unit is any memory unit in the memory space of the running task; and determine the space address of the corresponding memory unit as memory space release information.

[0101] In an optional implementation, the address allocation module 14 can be specifically configured to: if the available contiguous physical addresses in the unaddressed memory space satisfy the memory space requirement of a memory space request instruction, then allocate memory space for the memory space request instruction from the available contiguous physical addresses. If the available contiguous physical addresses in the unaddressed memory space do not satisfy the memory space requirement of the memory space request instruction, then allocate the available contiguous physical addresses to the memory space request instruction, and allocate the remaining required memory space for the memory space request instruction from the contiguous addressed addresses.

[0102] Furthermore, in an optional implementation, the address allocation module 14 can be specifically used to: when memory space request instructions for parallel execution tasks corresponding to different processor cores are obtained, if the available contiguous physical addresses of unaddressed memory space do not meet the memory space requirements of all memory space request instructions for parallel execution tasks, and there are memory space request instructions with memory space requirements greater than or equal to a third preset space threshold, and memory space request instructions with memory space requirements less than the third preset space threshold, then the available contiguous physical addresses of memory space are allocated to the memory space request instructions with memory space requirements greater than or equal to the third preset space threshold; if there are remaining contiguous physical addresses of memory space, they are allocated to the memory space request instructions with memory space requirements less than the third preset space threshold.

[0103] The system may also include a caching module for caching the address range of memory space allocated by the memory space request instruction.

[0104] The system may also include an address determination module for determining whether the memory access address is within the address range of the corresponding task.

[0105] The system may further include an alarm module, used to generate an alarm if the memory access address is not within the address range of the corresponding task. If the memory access address is not within the address range of the corresponding task, access to the memory access address is prohibited.

[0106] That is, the aforementioned multi-task memory space determination module may include a cache module and an address determination module.

[0107] As can be seen, this embodiment of the invention monitors the memory access of running tasks to obtain memory space release information of the running tasks, determines the physical address of the memory space to be addressed based on the memory space release information, and then addresses the physical address of the memory space to be addressed to obtain a continuous set of addresses. When allocating memory space, memory space is allocated for memory space request instructions based on the continuous addressing addresses and the unaddressed physical addresses of the memory space. In this way, by monitoring and obtaining memory space release information, determining the physical address of the memory space to be addressed, and assigning it a continuous set of addresses for memory space allocation, memory utilization can be improved, thereby improving the real-time processing performance of tasks. Furthermore, data security is enhanced.

[0108] Figure 8 For a description of the features in the corresponding embodiments, please refer to Figure 3 The relevant descriptions of the corresponding embodiments will not be repeated here.

[0109] It is understood that if the memory allocation method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.

[0110] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the memory allocation method described above. The computer program can be a program corresponding to a hardware description language.

[0111] Furthermore, the present invention provides a computer program product, including a computer program / instructions, which, when executed by a processor, implements the aforementioned memory allocation method. The computer program can be a program corresponding to a hardware description language.

[0112] The foregoing has provided a detailed description of a memory allocation method, system, medium, and product provided by embodiments of the present invention. The various embodiments are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0113] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0114] The present invention has provided a detailed description of a memory allocation method, system, medium, and product. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are merely illustrative of the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A memory allocation method, characterized in that, include: Monitor the memory access of running tasks to obtain memory space release information for the running tasks; The physical address of the memory space to be addressed is determined based on the memory space release information; The physical address of the memory space to be addressed is addressed to obtain a continuous address space; Memory space is allocated for memory space request instructions based on the continuous address and the physical address of the unaddressed memory space; The process of determining the memory space address to be addressed based on the memory space release information includes: If any of the preset conditions in the preset condition set is met, the physical address of the memory space carried in the memory space release information will not be used as the physical address of the memory space to be addressed; otherwise, the physical address of the memory space carried in the memory space release information will be determined as the physical address of the memory space to be addressed. The preset condition set includes a first preset condition, a second preset condition, and a third preset condition. The first preset condition is that the memory space requested by the running task is greater than a first preset space threshold. The second preset condition is that the average size of the memory space requested by the most recent preset number of memory space request instructions is greater than a second preset space threshold. The third preset condition is that the memory space corresponding to the currently unallocated address is greater than the second preset space threshold. The physical address of the memory space to be addressed is addressed to obtain a continuous set of addressable addresses, including: The physical address of the memory space to be addressed is addressed, and an addressing identifier is set at the end of the address to obtain a continuous address.

2. The memory allocation method according to claim 1, characterized in that, Monitor the memory access of running tasks to obtain memory space release information for the running tasks, including: Receive a memory unit access end instruction, wherein the memory unit access end instruction indicates that the running task has completed the access to the corresponding memory unit, and the memory unit is any memory unit in the memory space of the running task; The space address of the corresponding memory unit is determined as the memory space release information.

3. The memory allocation method according to claim 1, characterized in that, The memory space allocation for memory space request instructions based on the contiguous addressed addresses and the physical addresses of the unaddressed memory space includes: If the memory space requirement of a memory request instruction is satisfied by a contiguous block of unaddressed memory addresses, then memory space is allocated for the memory request instruction from the contiguous block of unaddressed memory addresses.

4. The memory allocation method according to claim 3, characterized in that, Allocating memory space for memory request instructions based on the continuous addressable addresses and the physical addresses of unaddressed memory spaces also includes: If the available contiguous physical addresses in the unaddressed memory space do not meet the memory space requirements of the memory space request instruction, then the available contiguous physical addresses are allocated to the memory space request instruction, and the remaining required memory space is allocated for the memory space request instruction from the contiguous addressed addresses.

5. The memory allocation method according to claim 1, characterized in that, The memory space allocation for memory space request instructions based on the contiguous addressed addresses and the physical addresses of the unaddressed memory space includes: If, when memory space request instructions for parallel execution tasks corresponding to different processor cores are obtained, the available contiguous physical addresses of unaddressed memory space do not meet the memory space requirements of all memory space request instructions for parallel execution tasks, and there are memory space request instructions with memory space requirements greater than or equal to the third preset space threshold, and memory space request instructions with memory space requirements less than the third preset space threshold, then the available contiguous physical addresses of memory space will be allocated to the memory space request instructions with memory space requirements greater than or equal to the third preset space threshold. If there are remaining contiguous physical addresses of memory space, then allocate memory space requests to instructions whose memory space requirements are less than the third preset space threshold.

6. The memory allocation method according to claim 1, characterized in that, After allocating memory space for the memory space request instruction based on the contiguous addressed addresses and the physical addresses of the unaddressed memory space, the process also includes: The memory space allocated by the memory space request instruction is cached within an address range.

7. The memory allocation method according to claim 1, characterized in that, Also includes: Receive the memory access address sent by the processor core; If the memory access address is an addressable address, then the physical address of the memory space corresponding to the memory access address is determined based on the mapping relationship between the addressable address and the physical address of the memory space.

8. The memory allocation method according to claim 7, characterized in that, After receiving the memory access address from the processor core, the process also includes: Determine whether the memory access address is within the address range of the corresponding task; If the memory access address is not within the address range of the corresponding task, an alarm is generated.

9. The memory allocation method according to claim 7, characterized in that, Also includes: If the memory access address is not within the address range of the corresponding task, access to the memory access address is prohibited.

10. A memory allocation system, characterized in that, include: The memory release monitoring module is used to monitor the memory access of running tasks in order to obtain memory space release information of the running tasks. The physical address determination module is used to determine the physical address of the memory space to be addressed based on the memory space release information. The physical address addressing module is used to address the physical address of the memory space to be addressed, so as to obtain a continuous address. The address allocation module is used to allocate memory space for memory space request instructions based on the continuous addressed addresses and the physical addresses of unaddressed memory space. The determination of the memory space address to be addressed based on the memory space release information includes: if any preset condition in the preset condition set is met, the physical address of the memory space carried in the memory space release information is not used as the physical address of the memory space to be addressed; otherwise, the physical address of the memory space carried in the memory space release information is determined as the physical address of the memory space to be addressed; the preset condition set includes a first preset condition, a second preset condition, and a third preset condition, wherein the first preset condition is that the memory space requested by the running task is greater than a first preset space threshold, the second preset condition is that the average size of the memory space requested by the most recent preset number of memory space request instructions is greater than a second preset space threshold, and the third preset condition is that the memory space corresponding to the currently unallocated address is greater than the second preset space threshold; Addressing the physical address of the memory space to be addressed to obtain a continuous addressable address includes: addressing the physical address of the memory space to be addressed and setting an addressing address identifier at the end of the address to obtain a continuous addressable address.

11. The memory allocation system according to claim 10, characterized in that, Also includes: The address resolution module is used to receive memory access addresses sent by the processor core; If the memory access address is an addressable address, then the physical address of the memory space corresponding to the memory access address is determined based on the mapping relationship between the addressable address and the physical address of the memory space.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the memory allocation method as described in any one of claims 1 to 9.

13. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the memory allocation method as described in any one of claims 1 to 9.

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