System and method for improving data configuration efficiency of test machine

Abstract

The invention discloses a system and method for improving data configuration efficiency of a test machine, and relates to the technical field of board card testing, the system comprises an FPGA PCIE module, a DMA address data analysis module and a data transmission module, a general data frame is divided into an independent 32b address field and an independent 32b data field through the arranged DMA address data analysis module, then bit [31] and 0 of an 32b address are analyzed to represent write operation, and the data transmission module is connected with the FPGA PCIE module. 1 represents read operation, an identifier is independently extracted and embedded into a subsequent instruction packet, then a bit [27: 0] of a 32b address is extracted, a target daughter card number is determined according to a preset address mapping table, and data is packaged after determination, so that data distribution of different address fields is realized, the data transmission module receives the data and then sends the data to each post-stage daughter card module in parallel, and data read-write is realized. Therefore, the read-write speed of the test machine is greatly increased, and the read-write efficiency is further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of board card testing, and in particular to a system and method for improving the efficiency of test machine configuration data. BACKGROUND

[0002] With the continuous improvement of the performance and integration of chips in the semiconductor industry, the design complexity of test machines has increased exponentially. On the one hand, to cover multiple types and parameters of testing requirements, the number of functional boards that need to be carried by the test machine has increased significantly. On the other hand, the degree of functional refinement of each board has been continuously improved, and the number of control registers on a single board has increased from hundreds to thousands, and the dimensionality of the parameters that need to be configured has become increasingly complex, which has directly led to a geometric increase in the amount of configuration data that needs to be issued by the test machine each time it starts or switches testing tasks. In the prior art, the test machine can only read and write one register data at a time through pcie, and each transmission through the link takes several us of time. If the registers of all the boards in the entire system are read, it will take a lot of time, which reduces the testing efficiency and causes many inconveniences to actual production work. SUMMARY

[0003] The present application aims to provide a system and method for improving the efficiency of test machine configuration data to solve the technical problem that the existing test machine can only read and write one register data at a time when testing sub-cards.

[0004] To achieve the above-mentioned purpose, the present application provides a system and method for improving the efficiency of test machine configuration data, characterized by comprising a FPGA PCIE module, a DMA address data analysis module and a data transmission module. The FPGA PCIE module is used to receive a general data frame containing register configuration information and perform integrity check on the data frame. The DMA address data analysis module splits the general data frame issued by the FPGA PCIE module into independent address segments and data segments and performs encoding and checking. The data transmission module receives the data issued by the DMA address data analysis module and sends it to each subsequent sub-card module in parallel to realize data reading and writing.

[0005] Preferably, the FPGA PCIE module further comprises a FIFO buffer unit, which is used to temporarily store the data frame issued by the DMA address data analysis module to prevent data overflow.

[0006] Preferably, the DMA address data analysis module further comprises a data input unit, which is used to receive the general data frame issued by the FPGA PCIE module.

[0007] Preferably, the DMA address data parsing module further includes a bit-width segmentation circuit unit, which splits the general data frame into address segments and data segments according to preset rules.

[0008] Preferably, the DMA address data parsing module further includes a synchronization control unit, which is used to control the data input, splitting and output of the DMA address data parsing module to be performed on the same clock.

[0009] Preferably, the DMA address data parsing module splits the general data frame in a fixed bit-width manner, with the middle bit in the general data frame as the split boundary.

[0010] Preferably, the DMA address data parsing module further includes a data output unit, which is used to synchronously send address segments and data segments.

[0011] Preferably, it also includes a host computer control module, which is used to generate a general data frame that matches the registers of the target sub-card.

[0012] Preferably, it also includes a PCIE DMA bus, which is used to receive general data frames issued by the host computer control module and send the general data frames to the FPGA PCIE module in batches.

[0013] In another aspect of the present invention, a method for improving the efficiency of test machine configuration data is proposed, comprising the following steps: A general data frame containing register configuration information is sent to the FPGA PCIE module. The FPGA PCIE module performs integrity verification on the data frame. After the verification is successful, the data frame is sent to the DMA address data parsing module. The DMA address data parsing module is used to split the general data frame issued by the FPGAPCIE module into independent address segments and data segments, and then encode and verify them. After verification, the data is sent to the data transmission module. The data transmission module receives data from the DMA address data parsing module and sends it in parallel to each subsequent sub-card module to achieve data reading and writing.

[0014] Compared with the prior art, the present invention has at least the following beneficial effects: This invention uses a DMA address data parsing module to split a general data frame into independent 32-bit address segments and 32-bit data segments. Then, it parses the bits of the 32-bit address

[31] , where 0 indicates a write operation and 1 indicates a read operation. The identifier is extracted separately and embedded into the subsequent instruction packet. Then, the bits of the 32-bit address [27:0] are extracted. According to the preset address mapping table, the target sub-card number is determined. After the number is determined, the data is packaged to achieve data distribution of different address segments. After receiving the data, the data transmission module sends it to each subsequent sub-card module in parallel to achieve data reading and writing, thereby greatly accelerating the reading and writing speed of the test machine and further improving the reading and writing efficiency. Attached Figure Description

[0015] The invention will now be further described with reference to the accompanying drawings.

[0016] Figure 1 This is a schematic diagram of a system for improving the efficiency of test machine configuration data in one embodiment of the present invention; Figure 2 This is a flowchart of a method for improving the efficiency of test machine configuration data in one embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] The preferred embodiments described below are merely examples, and other obvious variations will be apparent to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0019] Those skilled in the art should understand that, in the disclosure of this invention, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0020] Example 1 like Figure 1As shown, this invention proposes a system and method for improving the efficiency of test machine configuration data, characterized by including an FPGA PCIE module, a DMA address data parsing module, and a data transmission module.

[0021] In this embodiment, the FPGA PCIE module is used to receive 64b general data frames containing register configuration information and to perform integrity verification on the data frames. The FPGA PCIE module also includes a FIFO buffer unit, which is used to temporarily store data frames sent by the DMA address data parsing module to prevent data overflow.

[0022] In this embodiment, the FPGA PCIe module specifically interfaces with the physical layer and data link layer of the PCIe DMA bus, receiving batch data frames sent by the host computer control module through the PCIe DMA bus. In this embodiment, these are 64-bit general data frames, thereby completing physical layer adaptation operations such as signal level conversion and differential signal decoding to ensure accurate data reception.

[0023] Furthermore, when the FPGA PCIe module is operating, it only interfaces with the upstream PCIe DMA bus and does not directly receive sequential commands from the host computer control module. The data it receives is unsplit general data frames without explicit address and data separation. Subsequently, the FPGA PCIe module performs cyclic redundancy check and data frame format check on the received batch data frames, verifying whether the frame header, frame trailer, and data length conform to the PCIe protocol specification. If the check passes, the data frame is retained and proceeds to the next forwarding step. If the check fails, the erroneous data frame is discarded, and a data transmission error signal is fed back to the host computer control module via the PCIe DMA bus, requesting retransmission.

[0024] It is important to note that the FPGA PCIe module only verifies the integrity of data transmission and does not parse the data content, thereby avoiding resource consumption or extended data processing time due to content parsing.

[0025] Furthermore, in actual operation, since the transmission rate of the PCIe DMA bus may be higher than the processing rate of the DMA address data parsing module, a FIFO buffer unit is set up within the FPGA PCIe module. The FIFO buffer unit temporarily stores verified data frames to prevent data overflow. Based on the processing capacity of the DMA address data parsing module, the data forwarding rate is dynamically adjusted. Forwarding is paused when the DMA address data parsing module is busy and accelerated when it is idle, thus achieving upstream and downstream traffic matching. The data buffered in the FIFO buffer unit is a complete general data frame without any format modification. It is only forwarded downstream to the DMA address data parsing module and not directly forwarded to the daughter card or other modules. When the FIFO buffer unit receives the daughter card status data packet returned by the DMA address data parsing module, it packages it into a data frame according to the PCIe protocol format and returns it to the host computer control module via the PCIe DMA bus. It only encapsulates the daughter card data into PCIe data frames and does not participate in the parsing or encoding of the daughter card data.

[0026] In this embodiment, the DMA address data parsing module splits the 64-bit general data frame issued by the FPGA PCIe module into independent 32-bit address segments and 32-bit data segments, and performs encoding and verification. The DMA address data parsing module also includes a 64-bit data input unit, a bit-width segmentation circuit unit, a synchronization control unit, and a 32-bit data output unit. The 64-bit data input unit is used to receive data from the FPGA. The DMA address data parsing module also includes a bit-width segmentation circuit unit, which splits the 64-bit general data frame into a 32-bit address segment and a 32-bit data segment according to a preset rule. The high 32 bits are the address and the low 32 bits are the data, or vice versa. The DMA address data parsing module also includes a synchronization control unit, which controls the data input, splitting, and output of the DMA address data parsing module to be performed on the same clock. The DMA address data parsing module splits the 64-bit general data frame according to a fixed bit width, with the middle bit of the 64-bit general data frame as the splitting boundary. The DMA address data parsing module also includes a 32-bit data output unit, which is used to synchronously send the 32-bit address segment and the 32-bit data segment.

[0027] Furthermore, after receiving the 64-bit general data frame forwarded by the FPGA PCIE module, the DMA address data parsing module splits the 64-bit data bits into 32-bit address segments and 32-bit data segments according to preset rules. The splitting rules are fixed, that is, the high 32 bits are defined as address and the low 32 bits as data, or the high 32 bits are defined as data and the low 32 bits as address. In actual operation, the splitting rules can be defined according to actual needs. During the data splitting process, the DMA address data parsing module does not modify the data itself, but only performs format division to ensure the originality of the address and data.

[0028] Furthermore, in actual operation, the DMA address data parsing module only connects to the upstream FPGA PCIE module and does not directly receive PCIE DMA bus data. Therefore, the data received by the DMA address data parsing module is a complete general data frame verified by the FPGA, without errors or abnormal formats. Then, the split 32b address segment is encoded to convert the system-level general address issued by the host computer into a local physical address that the daughter card can recognize. The bits of the 32b address are parsed

[31] , where 0 indicates a write operation and 1 indicates a read operation. The identifier is extracted separately and embedded into the subsequent instruction packet. Then, the bits of the 32b address [27:0] are extracted, and the target daughter card number is determined according to the preset address mapping table. If the 32b address belongs to the group sending address segment, it is marked as a group sending instruction, which needs to be synchronously sent to all daughter cards in the future. The encoding rules of the DMA address data parsing module are strongly bound to the daughter card hardware address logic. It needs to be configured in advance according to the daughter card model. The encoded address is only suitable for the corresponding daughter card and cannot be directly used for other daughter cards. The split 32-bit data segment and the encoded address need to be double-checked. First, check whether the encoded local address of the child card is within the valid address range of the child card register to ensure data validity and avoid sending erroneous instructions to the child card. Then, perform CRC check (or parity check) on the 32-bit data segment. If the check fails, discard the data and send a data error signal to the FPGA PCIE module, which is indirectly transmitted to the host computer control module for retransmission.

[0029] In this embodiment, the data transmission module receives data sent by the DMA address data parsing module and sends it in parallel to each subsequent sub-card module to realize data reading and writing. At the same time, the data transmission module receives sub-card status data in reverse.

[0030] Specifically, the data transmission module receives the sub-card instruction packets forwarded by the DMA address data parsing module and parses the key identifiers in the instruction packets, such as the operation type identifier. After confirmation, it needs to send write configuration data or read status requests to the sub-card. The data transmission module only extracts the identifier information and does not modify the address and data content in the instruction packet. The data transmission module allocates an independent hardware transmission channel for each sub-card module and implements differentiated distribution according to the instruction packet type. When the instruction packet is a single-card instruction, the instruction packet is sent through the independent channel of the corresponding sub-card module, and the channels do not interfere with each other. When the instruction packet is a group instruction, the instruction packet is copied to the transmission channels of all sub-cards, and then the synchronization clock signal is used to control all channels to send data simultaneously to ensure that multiple sub-cards receive data synchronously. At this time, the group transmission time is the same as that of a single card.

[0031] Furthermore, the data transmission module can dynamically adjust the transmission parameters of the corresponding channels based on the hardware timing differences of different daughter card modules, avoiding data transmission errors caused by timing mismatch. The data transmission module can also be configured with an independent clock generator for each channel to generate the clock frequency supported by the daughter card as needed, thereby achieving precise matching. If multiple daughter card modules are physically different from the transmission module, resulting in signal delay differences, an independent clock generator can be used to add signal delay to the long-distance channels to ensure that the group transmission command arrives at all daughter cards synchronously, ensuring consistent delivery of the group transmission command.

[0032] In this embodiment, a host computer control module is also included. The host computer control module is used to generate a 64-bit general data frame that matches the registers of the target daughter card. The host computer control module is responsible for the overall scheduling of the daughter card module test tasks. It is the source of configuration data generation and the initiator of transmission instructions. The host computer generates original configuration information according to the test requirements. The original configuration information includes the target address, configuration value, and operation type of the registers in each daughter card module. It should be noted that the host computer control module does not perform 64-bit splitting, but only packages these original configuration information into a general data frame format.

[0033] In this embodiment, a PCIE DMA bus is also included. The PCIE DMA bus is used to receive 64-bit general data frames issued by the host computer control module and send the 64-bit general data frames to the FPGA PCIE module in batches. The PCIE DMA bus is a high-speed data transmission carrier between the host computer control module and the FPGA PCIE module. Its core function is to realize the batch data transmission of the host computer control module through the combination of PCIE protocol and DMA technology.

[0034] In this embodiment, the host computer control module, PCIE DMA bus, FPGA PCIE module, DMA address data parsing module, data transmission module and daughter card module are all equipped with a verification unit. The verification unit is used to verify the integrity of the received data and to feed back a verification signal.

[0035] Example 2 like Figure 2 As shown, this embodiment is a method for improving the efficiency of test machine configuration data based on Embodiment 1, including the following steps: A general data frame containing register configuration information is sent to the FPGA PCIE module. The FPGA PCIE module performs integrity verification on the data frame. After the verification is successful, the data frame is sent to the DMA address data parsing module. The DMA address data parsing module is used to split the general data frame issued by the FPGAPCIE module into independent address segments and data segments, and then encode and verify them. After verification, the data frame is sent to the data transmission module. The data transmission module receives data from the DMA address data parsing module and sends it in parallel to each subsequent daughter card module to achieve data reading and writing.

[0036] Example 3 This embodiment is based on Embodiment 1 and proposes a specific process when the host computer control module issues a write operation.

[0037] First, the host computer control module generates the configuration information of the registers in the target daughter card module according to the test requirements, including the daughter card number, register system-level address, configuration data, and operation type "write". Then, the configuration information is packaged according to the PCIE DMA general format to generate a batch write operation data packet, and then the data packet is transmitted.

[0038] Then, the PCIe DMA bus transmits data to the FPGA PCIe module at high bandwidth. During the transmission, the data content is not modified; it is only responsible for data transfer. The PCIe DMA bus supports batch continuous transmission, reducing the number of link transmissions.

[0039] Next, the FPGA PCIe module receives the 64-bit data frame transmitted via the PCIe DMA bus, performs differential decoding and level conversion, and then performs CRC (Cyclic Redundancy Check) and format checks on the data frame. If the checks pass, the data frame is sent to the built-in FIFO buffer unit; if the checks fail, the erroneous frame is discarded, and a retransmission request is sent to the host computer control module via the PCIe DMA bus to re-obtain the corresponding data. When the FIFO buffer unit is half full, the FPGA PCIe module sends a slowdown transmission signal to the host computer control module to prevent data overflow.

[0040] Subsequently, the DMA address data parsing module receives the 64b data frame forwarded by the FPGA PCIE module, splits it into a 32b system-level address and a 32b configuration data according to preset rules, and encodes the 32b address: parsing bit

[31] (0 = write operation, confirming the operation type), extracting bits[27:0], and determining the sub-card number by combining the address mapping table; calculating the sub-card local address. If the address belongs to the mass address segment, it is marked as a mass write instruction. Then, the split 32b configuration data is subjected to CRC verification to check whether the encoded local address is within the valid range of the register. If the verification passes, the local address, configuration data, write identifier and sub-card number are packaged into a sub-card write instruction packet. If the verification fails, the instruction packet is discarded and a data error signal is sent to the FPGA PCIE module, so as to obtain the corresponding data again for splitting. The DMA address data parsing module only filters invalid data and does not modify valid data. After the data is packaged, the DMA address data parsing module sends a command packet ready signal to the data transmission module to confirm that it can receive data. The daughter card write command packet is forwarded to the data transmission module in the original order of the write operation data packet. If it is a group write command packet, only one copy is forwarded, which is then copied and distributed by the data transmission module. The forwarding order is consistent with the order issued by the host computer control module to ensure that the daughter card configuration timing is correct.

[0041] Finally, the data transmission module receives the daughter card write command packet and parses the key identifiers within the packet: if it is a single card command, it extracts the daughter card number and determines the corresponding transmission channel for distribution. If it is a group transmission command, it identifies the group transmission flag, determines that all daughter card channels need to be used, and calls the timing parameters of the target daughter card from the internal timing configuration table to ensure smooth distribution, thereby realizing the "write operation" on the daughter card module.

[0042] Example 4 This embodiment is based on Embodiment 1 and proposes a specific process when the host computer control module issues a read operation.

[0043] First, the host computer control module generates read operation request information according to the test requirements, including the target sub-card number, the system-level address of the register to be read, and the operation type "read". Then, the request information is packaged according to the PCIe DMA bus general format to generate a batch read operation data packet and sent to the PCIe DMA bus.

[0044] Then, the PCIe DMA bus reads the read operation data packet from the host computer control module and transmits it at high speed to the FPGA PCIe module. The data content is not modified during the transmission process. After the transmission is completed, the bus control is maintained, and the system waits for the status data of the daughter card module to be returned.

[0045] Next, the FPGA PCIE module receives the read operation data packet, completes the CRC check and format check, and sends it to the FIFO buffer unit after the check passes. Then, according to the data request signal of the DMA address data parsing module, it forwards the 64b data frame to the parsing module, and then clears the forwarded read request data in the FIFO buffer unit, reserving space for receiving subsequent status data.

[0046] Subsequently, the DMA address data parsing module receives the 64b read request frame forwarded by the FPGA PCIE module, splits it into a 32b system-level address and read operation identifier, and encodes the address: parses bit

[31] (1=read operation, confirmation type); extracts bits[27:0] to determine the sub-card number; calculates the sub-card local address, and then packages the local address, read identifier and sub-card number into a sub-card read instruction packet and forwards it to the data transmission module.

[0047] Finally, the data transmission module receives the sub-card read instruction packet, parses the sub-card number, and calls the timing parameters of the corresponding channel to send a data packet to the sub-card module.

[0048] After detecting a read request signal, the daughter card module reads the status data of the target register according to the local address. Then, it packages the daughter card number, local address, and status data into a daughter card status data packet and sends it back to the data transmission module. After receiving the daughter card status data packet, the data transmission module checks the format integrity and repackages the status data packet into a read return data packet according to the format required by the DMA address data parsing module. The DMA address data parsing module receives the read return data packet, performs CRC check on the status data to ensure error-free transmission, and then sends a data return request to the FPGA PCIE module. After confirming that it can receive data, the DMA address data parsing module forwards the read return data packet to the FPGA PCIE module in sequence. The FPGA PCIE module packages the read return data packet according to the PCIE protocol format and sends it to the PCIE DMA bus. The read return data packet is then transmitted to the host computer control module via the PCIE DMA bus, and the host computer control module reads the read return data packet.

[0049] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

[0050] The above-disclosed embodiments are merely a few specific examples of the present invention. However, the embodiments of the present invention are not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A system for improving the efficiency of test machine configuration data, characterized in that, This includes an FPGA PCIe module, a DMA address and data parsing module, and a data transmission module; The FPGA PCIE module is used to receive general data frames containing register configuration information and to perform integrity verification on the data frames. The DMA address data parsing module splits the general data frame issued by the FPGAPCIE module into independent address segments and data segments and performs encoding and verification. The data transmission module receives the data sent by the DMA address data parsing module and sends it in parallel to each subsequent sub-card module to realize data reading and writing.

2. The system for improving the efficiency of test machine configuration data according to claim 1, characterized in that, The FPGAPCIE module also includes a FIFO cache unit, which is used to temporarily store the data frames sent by the DMA address data parsing module to prevent data overflow.

3. The system for improving the efficiency of test machine configuration data according to claim 1, characterized in that, The DMA address data parsing module also includes a data input unit, which is used to receive general data frames issued by the FPGA PCIE module.

4. The system for improving the efficiency of test machine configuration data according to claim 1, characterized in that, The DMA address data parsing module also includes a bit-width segmentation circuit unit, which splits the general data frame into address segments and data segments according to preset rules.

5. The system for improving the efficiency of test machine configuration data according to claim 1, characterized in that, The DMA address data parsing module also includes a synchronization control unit, which controls the data input, splitting, and output of the DMA address data parsing module to be performed on the same clock.

6. The system for improving the efficiency of test machine configuration data according to claim 1, characterized in that, The DMA address data parsing module splits the general data frame in a fixed bit-width manner, with the middle bit of the general data frame as the split boundary.

7. The system for improving the efficiency of test machine configuration data according to claim 4, characterized in that, The DMA address data parsing module also includes a data output unit, which is used to synchronously send address segments and data segments.

8. The system for improving the efficiency of test machine configuration data according to claim 1, characterized in that, It also includes a host computer control module, which is used to generate a general data frame that matches the registers of the target sub-card.

9. The system for improving the efficiency of test machine configuration data according to claim 8, characterized in that, It also includes a PCIE DMA bus, which is used to receive general data frames issued by the host computer control module and send the general data frames to the FPGA PCIE module in batches.

10. A method for improving the efficiency of test machine configuration data, characterized in that, The system for improving the efficiency of test machine configuration data as described in any one of claims 1-9 includes the following steps: A general data frame containing register configuration information is sent to the FPGA PCIE module. The FPGA PCIE module performs integrity verification on the data frame. After the verification is successful, the data frame is sent to the DMA address data parsing module. The DMA address data parsing module is used to split the general data frame issued by the FPGAPCIE module into independent address segments and data segments, and then encode and verify them. After verification, the data is sent to the data transmission module. The data transmission module receives data from the DMA address data parsing module and sends it in parallel to each subsequent sub-card module to achieve data reading and writing.

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