PCB defect detection method and system

Abstract

The invention relates to the technical field of PCB defect detection, and provides a PCB defect detection method and system. The method comprises the following steps: preprocessing based on an obtained PCB defect data set to obtain a preprocessed PCB defect data set; the method comprises the steps that a PCB defect detection model is constructed, the PCB defect detection model is designed based on a preset YOLOv11 architecture, an FFAP-SAM double-attention cooperation and cross-scale fusion module is introduced into the YOLOv11 architecture, and micro defect feature expression and multi-scale defect perception are carried out; training the PCB defect detection model by using the preprocessed PCB defect data set to obtain a trained PCB defect detection model; and performing defect detection on a to-be-detected PCB image by using the trained PCB defect detection model. According to the invention, based on the PCB defect detection model, feature expression and multi-scale defect perception of PCB micro defects can be realized, so that accurate detection of the micro defects is realized.

Description

Technical Field

[0001] This invention relates to the technical field of PCB defect detection, and more specifically, to a PCB defect detection method and system. Background Technology

[0002] Printed Circuit Boards (PCBs) are core components of electronic devices, and their quality and reliability directly affect the overall performance and lifespan of the device. While PCB manufacturing processes are becoming increasingly sophisticated, various minor defects such as open circuits, short circuits, and missing vias can still occur during production due to material defects, etching residues, and misalignment.

[0003] Traditional defect detection methods are mainly based on image processing techniques such as edge feature extraction, morphological transformation, and template matching. These methods are effective in detecting defects with simple structures. However, with the increasing complexity of industrial inspection scenarios, especially in key scenarios such as complex texture backgrounds, strong noise interference, and micro-defect detection, their detection accuracy and robustness are significantly insufficient, making it difficult to meet the stringent requirements of modern intelligent manufacturing for inspection quality and stability.

[0004] With continuous breakthroughs in deep learning technology, convolutional neural networks have demonstrated powerful potential in image classification and object detection, driving the rapid development of PCB defect detection technology towards intelligence. Currently, deep learning-based object detection methods mainly fall into two major technical routes: two-stage and single-stage. Two-stage detection frameworks, represented by the Regions with Convolutional Neural Networks (R-CNN) series, generate candidate regions through selective search algorithms, then extract features and classify each region, transforming the detection task into a region classification problem. However, in practical applications, issues such as unstable candidate region generation quality leading to missed detections and localization errors still exist. Single-stage detection algorithms, on the other hand, exhibit higher computational efficiency. The Single Shot MultiBox Detector (SSD) algorithm, for example, implements a multi-scale detection strategy on multi-layer feature maps, effectively capturing defect targets of different sizes using convolutional features at different levels. The YOLO series of algorithms innovatively reconstructs the detection task as a regression problem, employing a grid partitioning mechanism to simultaneously predict target location and category, achieving satisfactory accuracy while maintaining real-time detection speed.

[0005] However, the feature information of minute defects is constantly attenuated as they propagate in deep networks, resulting in insufficient detection sensitivity for key defects such as microcracks in weld joints and short circuits in thin wires; noise interference in complex industrial backgrounds is highly similar to defect features, causing a decrease in model discrimination; traditional detection heads lack spatial context understanding capabilities, and are prone to target merging and missed detection in dense defect scenarios. Summary of the Invention

[0006] To address the issue of low accuracy in detecting minute defects in PCBs using existing technologies, this invention proposes a PCB defect detection method and system to achieve rapid and accurate identification of PCB defects.

[0007] To achieve the above-mentioned technical effects, the technical solution of the present invention is as follows: Firstly, this application proposes a PCB defect detection method, comprising the following steps: S1: Preprocess the acquired PCB defect dataset to obtain the preprocessed PCB defect dataset; S2: Construct a PCB defect detection model. The PCB defect detection model is based on a preset YOLOv11 architecture design. A module based on FFAP-SAM dual attention collaboration and cross-scale fusion is introduced into the YOLOv11 architecture to express micro-defect features and perceive multi-scale defects. S3: Use the preprocessed PCB defect dataset to train the PCB defect detection model to obtain a trained PCB defect detection model; S4: Use the trained PCB defect detection model to perform defect detection on the PCB image to be detected.

[0008] Preferably, the PCB defect detection model includes a backbone network, a neck network, and a detection head. The modules introduced in the YOLOv11 architecture based on FFAP-SAM dual attention collaboration and cross-scale fusion include an FFAP feature enhancement module, a first Zoom_Cat module, a second Zoom_Cat module, a SAM module, an Add module, and a ScalSeq module. The backbone network of the PCB defect detection model uses the FFAP feature enhancement module as the first layer to achieve feature enhancement. The part of the backbone network other than the FFAP feature enhancement module is consistent with the backbone network of the preset YOLOv11 architecture. The PCB defect detection model adds a first Zoom_Cat module before the first C3k2 layer of the neck network of the preset YOLOv11 architecture, adds a second Zoom_Cat module before the second C3k2 layer of the neck network of the preset YOLOv11 architecture, replaces the second C3k2 layer with a SAM module, and connects an Add module after the SAM module. The Add module is then connected to the ScalSeq module to achieve multi-scale defect perception. The detection head of the PCB defect detection model uses the GIoU function.

[0009] Preferably, in S3, the PCB defect detection model is trained using the preprocessed PCB defect dataset to obtain a trained PCB defect detection model. The process is as follows: The preprocessed PCB defect dataset is divided into a training set, a validation set, and a test set. The PCB defect detection model is trained using a training set. During training, the loss is calculated using the GIoU function of the detection head. The detection performance of the trained PCB defect detection model is evaluated using a validation set to obtain a pre-trained PCB defect detection model. The performance of the pre-trained PCB defect detection model is then tested using a test set to obtain the final trained PCB defect detection model.

[0010] Preferably, the process of using the trained PCB defect detection model to detect defects in the PCB image to be detected, as described in S4, is as follows: In the backbone network, the FFAP feature enhancement module is used to enhance the features of the defective part of the PCB image to be detected, and the enhanced feature map is obtained. The remaining layers in the backbone network are used to process the enhanced feature map to obtain ultra-large scale feature map, large scale feature map, medium scale feature map, small scale feature map and ultra-small scale feature map respectively. In the neck network, small-scale and extra-large-scale feature maps are processed by other layers of the neck network to obtain processed small-scale and extra-large-scale feature maps. Based on the mesoscale feature map, the processed small-scale feature map, and the processed extra-large-scale feature map, scale fusion is performed using the first Zoom_Cat module to obtain a first fused feature map. The extra-small-scale feature map is then processed by other layers of the neck network, and the first fused feature map is dimensionality reduced to obtain processed extra-small-scale feature maps and dimensionality-reduced first fused feature maps. Based on the processed extra-small-scale feature map, the small-scale feature map, and the extra-large-scale feature map, scale fusion is performed using the first Zoom_Cat module to obtain a first fused feature map. The first fusion feature map after dimensionality reduction is scale-fused using the second Zoom_Cat module to obtain the second fusion feature map. The second fusion feature map is then augmented with spatial information using the SAM module to obtain an augmented small-scale spatial feature map. Based on the augmented small-scale spatial feature map, large-scale feature map, medium-scale feature map, and small-scale feature map, the Add module and ScalSeq module are used for processing to obtain the P3 cross-scale fusion feature. The remaining layers in the neck network are used to process the augmented small-scale spatial feature map and the first fusion feature map to obtain the P4 cross-scale fusion feature and the P5 cross-scale fusion feature, respectively. The P3 cross-scale fusion feature, the P4 cross-scale fusion feature, and the P5 cross-scale fusion feature are input into the detection head to obtain the PCB defect detection results.

[0011] Preferably, the FFAP feature enhancement module includes a shallow convolutional layer, a deep feature extraction network, a channel attention unit (CA), a pixel attention unit (PA), a weighted fusion layer, and a reconstruction unit; the deep feature extraction network consists of multiple cascaded feature groups, and each feature group contains several block modules. The FFAP feature enhancement module is used to enhance the features of the defective portion of the PCB image to be detected, resulting in an enhanced feature map. The process is as follows: The shallow convolutional layer is used to perform preliminary feature acquisition on the PCB image to be detected, resulting in a basic feature map; A deep feature extraction network is used to progressively extract higher semantic-level features from the basic feature map, resulting in multiple high-level feature maps. The multiple high-level feature maps are concatenated, and the channel attention unit (CA) is used to enhance the attention of the concatenated high-level feature maps to obtain a channel attention-enhanced feature map. Then, the pixel attention unit (PA) is used to enhance the attention of the concatenated high-level feature maps to obtain a pixel-level attention feature map. Based on the channel attention enhancement feature map and the pixel-level attention feature map, a weighted fusion layer is used for integration. The feature map after weighted fusion layer integration is then passed to the reconstruction unit for optimization processing using global residual connections to obtain the enhanced feature map.

[0012] Preferably, the process of obtaining the first fused feature map is as follows: The first Zoom_Cat module is used to upsample the processed small-scale feature map to the medium-scale resolution using nearest neighbor interpolation to obtain the upsampled small-scale feature map. The medium-scale feature map, the processed ultra-large-scale feature map and the downsampled small-scale feature map are then weighted, fused and stitched together to obtain the first fused feature map. The process of obtaining the second fused feature map is as follows: The second Zoom_Cat module is used to downsample the first fused feature map after dimensionality reduction to a medium-scale resolution using adaptive pooling. The processed ultra-small scale feature map, small scale feature map and the downsampled first fused feature map are then weighted, fused and concatenated to obtain the second fused feature map.

[0013] Preferably, the SAM module includes an average pooling layer, a first convolutional layer, a horizontally separable convolutional layer, a vertically separable convolutional layer, a connection layer, a second convolutional layer, and a sigmoid function; The SAM module uses the second fused feature map to perform adaptive spatial information enhancement, resulting in an enhanced small-scale spatial feature map. The process is as follows: Based on the second fused feature map, the global context is first obtained through an average pooling layer, and then pooling features are generated through a first convolutional layer. Based on the pooling features, horizontally separable convolutional layers and vertically separable convolutional layers are used to capture the horizontal and vertical spatial relationships, respectively, to obtain the horizontal convolutional features. and vertical convolution features ; Based on the horizontal convolution features and the vertical convolution feature The concatenation layer is used to stitch the data along the channel dimension. After stitching, the data is fused using a second convolutional layer. Finally, the Sigmoid function is used to generate an enhanced small-scale spatial feature map.

[0014] Preferably, based on pooling features, horizontally and vertically separable convolutional layers are used to capture the horizontal and vertical spatial relationships, respectively. The features in the two directions are connected along the channel dimension using a connection layer, and then fused using a second convolutional layer. After fusion, a spatial attention weight map is generated using the Sigmoid function. The process is as follows: Utilizing horizontally depth-separable convolutional layers to pool features Horizontal depthwise separable convolution is performed, followed by batch normalization (BN) and SiLU activation to obtain horizontal convolution features. Satisfies the expression:

[0015] in, This indicates a horizontally depth-separable convolutional layer; Using vertically depth-separable convolutional layers to pool features Vertical depth-separable convolution is performed, followed by batch normalization (BN) and SiLU activation to obtain vertical convolution features. Satisfies the expression:

[0016] in, This indicates a vertically separable convolutional layer.

[0017] Preferably, based on the enhanced small-scale spatial feature map, large-scale feature map, medium-scale feature map, and small-scale feature map, the P3 cross-scale fusion feature is obtained by processing with the ScalSeq module and the Add module. The process is as follows: Based on large-scale, medium-scale, and small-scale feature maps, the ScalSeq module is used to stack the large-scale, medium-scale, and small-scale feature maps along the scale dimension into a three-dimensional sequence. Then, a 3D convolutional layer is used to extract cross-layer spatial and channel correlations. After extraction, pooling is performed to obtain unified multi-scale features. Based on the unified multi-scale features, the enhanced small-scale spatial feature map is added element by element to the unified multi-scale features using the Add module to obtain the P3 cross-scale fusion feature.

[0018] Secondly, this application proposes a PCB defect detection system for implementing the method, comprising: The data processing module preprocesses the acquired PCB defect dataset to obtain a preprocessed PCB defect dataset. The model building module constructs a PCB defect detection model. The PCB defect detection model is based on a preset YOLOv11 architecture design. A module based on FFAP-SAM dual attention collaboration and cross-scale fusion is introduced into the YOLOv11 architecture to express micro-defect features and perceive multi-scale defects. The model training module uses the preprocessed PCB defect dataset to train the PCB defect detection model, thereby obtaining a trained PCB defect detection model. The PCB defect detection module uses a trained PCB defect detection model to detect defects in the PCB image to be inspected.

[0019] Compared with the prior art, the beneficial effects of the technical solution of the present invention are: This invention proposes a PCB defect detection method and system. The method involves preprocessing an acquired PCB defect dataset to obtain a preprocessed PCB defect dataset. A PCB defect detection model is constructed based on a pre-defined YOLOv11 architecture, incorporating FFAP-SAM dual attention collaboration and cross-scale fusion modules to achieve feature representation of minute defects and multi-scale defect perception. The preprocessed PCB defect dataset is used to train the PCB defect detection model to optimize its parameters, resulting in a trained PCB defect detection model. The PCB image to be detected is then input into the trained PCB defect detection model, yielding the corresponding defect detection results. This invention, based on a PCB defect detection model, enables feature representation of minute PCB defects and multi-scale defect perception, thereby achieving accurate detection of minute defects. Attached Figure Description

[0020] Figure 1 A flowchart illustrating the PCB defect detection method proposed in this embodiment of the invention; Figure 2 This diagram illustrates the structure of the PCB defect detection model proposed in this embodiment of the invention. Figure 3 This diagram illustrates the FFAP feature enhancement module and cascaded feature group structure proposed in this embodiment of the invention. Figure 4 This diagram illustrates the structure of the channel attention unit (CA) and pixel attention unit (PA) proposed in this embodiment of the invention. Figure 5 This diagram illustrates the SAM module structure proposed in this embodiment of the invention. Figure 6 This diagram illustrates the structure of the ScalSeq module proposed in this embodiment of the invention. Figure 7 This represents the PR curve before the improvement of the Yolov11 architecture proposed in this embodiment of the invention; Figure 8 This represents the PR curve of the PCB defect detection model proposed in this embodiment of the invention. Figure 9 This diagram illustrates the composition of the PCB defect detection system proposed in this embodiment of the invention. Detailed Implementation

[0021] The accompanying drawings are for illustrative purposes only and should not be construed as limiting the scope of this patent. To better illustrate this embodiment, some parts of the accompanying drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions; It is understandable to those skilled in the art that some well-known details may be omitted from the accompanying drawings.

[0022] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments; The positional relationships depicted in the accompanying drawings are for illustrative purposes only and should not be construed as limiting this patent.

[0023] Example 1 This embodiment provides a PCB defect detection method, the flowchart of which can be found here. Figure 1 This includes the following steps: S1: Preprocess the acquired PCB defect dataset to obtain the preprocessed PCB defect dataset; S2: Construct a PCB defect detection model. The PCB defect detection model is based on a preset YOLOv11 architecture design. The YOLOv11 architecture introduces FFAP-SAM dual attention collaboration and cross-scale fusion modules to express micro-defect features and perceive multi-scale defects. S3: Use the preprocessed PCB defect dataset to train the PCB defect detection model to obtain a trained PCB defect detection model; S4: Use the trained PCB defect detection model to perform defect detection on the PCB image to be detected.

[0024] This embodiment provides a PCB defect detection method. It preprocesses an acquired PCB defect dataset to obtain a preprocessed PCB defect dataset. A PCB defect detection model is constructed based on a pre-defined YOLOv11 architecture, incorporating FFAP-SAM dual attention collaboration and cross-scale fusion modules to achieve feature representation of minute defects and multi-scale defect perception. The preprocessed PCB defect dataset is used to train the PCB defect detection model to optimize its parameters, resulting in a trained PCB defect detection model. The PCB image to be detected is then input into the trained PCB defect detection model, yielding the corresponding defect detection results. This invention, based on a PCB defect detection model, enables feature representation of minute PCB defects and multi-scale defect perception, thereby achieving accurate detection of minute defects.

[0025] Example 2 In this embodiment, as Figure 2As shown, the PCB defect detection model includes a backbone network 1, a neck network 2, and a detection head 3. The modules introduced in the YOLOv11 architecture based on FFAP-SAM dual attention collaboration and cross-scale fusion include an FFAP feature enhancement module, a first Zoom_Cat module, a second Zoom_Cat module, a SAM module, an Add module, and a ScalSeq module. The backbone network 1 of the PCB defect detection model uses the FFAP feature enhancement module as the first layer to achieve feature enhancement. The part of the backbone network other than the FFAP feature enhancement module is consistent with the backbone network of the preset YOLOv11 architecture. The PCB defect detection model's neck network 2 adds a first Zoom_Cat module before the first C3k2 layer of the preset YOLOv11 architecture's neck network, adds a second Zoom_Cat module before the second C3k2 layer of the preset YOLOv11 architecture's neck network, replaces the second C3k2 layer with a SAM module, and connects an Add module after the SAM module. The Add module is then connected to the ScalSeq module to achieve multi-scale defect perception. The detection head 3 of the PCB defect detection model uses the GIoU function.

[0026] Specifically, the first C3k2 layer is defined as the C3k2 layer in the neck network of the preset YOLOv11 architecture that is not connected to the detection head, and the second C3k2 layer is defined as the C3k2 layer that is connected to the P3 detection head Detect. In the PCB defect detection model, the Add module is connected to the P3 detection head.

[0027] In S3, the PCB defect detection model is trained using the preprocessed PCB defect dataset to obtain a trained PCB defect detection model. The process is as follows: The preprocessed PCB defect dataset is divided into a training set, a validation set, and a test set. The PCB defect detection model is trained using a training set. During training, the loss is calculated using the GIoU function of the detection head (GIoU (Generalized Intersection over Union) is an improved evaluation metric for assessing the localization accuracy of bounding boxes in object detection tasks. It solves the evaluation defects of traditional IoU (Intersection over Union) when the targets do not overlap or have inclusion relationships, and can be directly used as a loss function to optimize model training). The detection performance of the trained PCB defect detection model is evaluated using a validation set to obtain a pre-trained PCB defect detection model. The performance of the pre-trained PCB defect detection model is then tested using a test set to obtain the final trained PCB defect detection model.

[0028] Specifically, the preprocessed PCB defect dataset was divided into training, validation, and test sets in an 8:1:1 ratio. During training, SGD was selected as the model optimizer, with batch size set to 32, iterations to 300, initial learning rate (lr0) to 0.01, batch size to 4, and workers set to 0 to disable multi-process data loading. Input images were scaled to 640×640, and automatic mixed precision (amp) was enabled to accelerate training. Resuming training from the most recent checkpoint was supported by setting resume=True, and the loss was calculated using the GIoU function in each iteration to update the parameters of the PCB defect detection model in real time.

[0029] After each training cycle, the model is tested using a test set. The metrics used in the test include precision, recall, and mean precision (mAP). The loss and accuracy changes during the testing phase are tracked to obtain the trained PCB defect detection model.

[0030] In the early stages of training, Mosaic data augmentation was enabled, and this strategy was disabled in the last 10 rounds to improve the model's stability and generalization performance. Simultaneously, multi-scale prediction paths were optimized, achieving end-to-end detection through joint bounding box regression and class prediction. In the decoding and post-processing stages, the PCB defect detection model employs a Top-K mechanism to select candidate boxes with high confidence, and combines this with Non-Maximum Suppression (NMS) to remove redundant detection boxes, ultimately obtaining the detection results for surface defects on the printed circuit board.

[0031] The process described in S4 for using the trained PCB defect detection model to detect defects in the PCB image to be detected is as follows: In the backbone network, the FFAP feature enhancement module is used to enhance the features of the defective part of the PCB image to be detected, and the enhanced feature map is obtained. The remaining layers in the backbone network are used to process the enhanced feature map to obtain ultra-large scale feature map, large scale feature map, medium scale feature map, small scale feature map and ultra-small scale feature map respectively. In the neck network, small-scale and extra-large-scale feature maps are processed by other layers of the neck network to obtain processed small-scale and extra-large-scale feature maps. Based on the mesoscale feature map, the processed small-scale feature map, and the processed extra-large-scale feature map, scale fusion is performed using the first Zoom_Cat module to obtain a first fused feature map. The extra-small-scale feature map is then processed by other layers of the neck network, and the first fused feature map is dimensionality reduced to obtain processed extra-small-scale feature maps and dimensionality-reduced first fused feature maps. Based on the processed extra-small-scale feature map, the small-scale feature map, and the extra-large-scale feature map, scale fusion is performed using the first Zoom_Cat module to obtain a first fused feature map. The first fusion feature map after dimensionality reduction is scale-fused using the second Zoom_Cat module to obtain the second fusion feature map. The second fusion feature map is then augmented with spatial information using the SAM module to obtain an augmented small-scale spatial feature map. Based on the augmented small-scale spatial feature map, large-scale feature map, medium-scale feature map, and small-scale feature map, the Add module and ScalSeq module are used for processing to obtain the P3 cross-scale fusion feature. The remaining layers in the neck network are used to process the augmented small-scale spatial feature map and the first fusion feature map to obtain the P4 cross-scale fusion feature and the P5 cross-scale fusion feature, respectively. The P3 cross-scale fusion feature, the P4 cross-scale fusion feature, and the P5 cross-scale fusion feature are input into the detection head to obtain the PCB defect detection results.

[0032] like Figure 2 As shown, the backbone network outputs very small-scale feature maps from layer 2, small-scale feature maps from layer 4, medium-scale feature maps from layer 6, large-scale feature maps from layer 8, and very large-scale feature maps from layer 11. The very large-scale feature maps are processed using layer 12 of the neck network to obtain the processed very large-scale feature maps, and the small-scale feature maps are processed using layer 13 to obtain the small-scale feature maps. Finally, the very small-scale feature maps are projected using layer 17 of the neck network to obtain the processed very small-scale feature maps.

[0033] Specifically, the remaining layers in the neck network are used to process the enhanced small-scale spatial feature map and the first fused feature map to obtain the P4 cross-scale fused feature and the P5 cross-scale fused feature, respectively. The process is as follows: the enhanced small-scale spatial feature map is upsampled and then concatenated with the mid-scale feature map of the FPN to obtain the P4 cross-scale fused feature; the P4 cross-scale fused feature is upsampled and then concatenated with the large-scale feature map to obtain the P5 cross-scale fused feature.

[0034] like Figure 3As shown, the FFAP feature enhancement module includes a shallow convolutional layer, a deep feature extraction network, a channel attention unit (CA), a pixel attention unit (PA), a weighted fusion layer, and a reconstruction unit; the deep feature extraction network consists of multiple cascaded feature groups, and each feature group contains several block modules. The FFAP feature enhancement module is used to enhance the features of the defective portion of the PCB image to be detected, resulting in an enhanced feature map. The process is as follows: The shallow convolutional layer is used to perform preliminary feature acquisition on the PCB image to be detected, resulting in a basic feature map; A deep feature extraction network is used to progressively extract higher semantic-level features from the basic feature map, resulting in multiple high-level feature maps. The multiple high-level feature maps are concatenated, and the channel attention unit (CA) is used to enhance the attention of the concatenated high-level feature maps to obtain a channel attention-enhanced feature map. Then, the pixel attention unit (PA) is used to enhance the attention of the concatenated high-level feature maps to obtain a pixel-level attention feature map. Based on the channel attention enhancement feature map and the pixel-level attention feature map, a weighted fusion layer is used for integration. The feature map after weighted fusion layer integration is then passed to the reconstruction unit for optimization processing using global residual connections to obtain the enhanced feature map.

[0035] See the structure diagrams of the channel attention unit (CA) and pixel attention unit (PA). Figure 4 The channel attention unit (CA) processing procedure is as follows: Based on the concatenated high-level feature maps, global average pooling is performed. The resulting feature maps then undergo a first convolution transformation. The convolutionally transformed feature maps are then activated using the ReLU function to introduce non-linear feature representation capabilities. A second convolution transformation is performed on the ReLU-activated feature maps. Finally, the Sigmoid function is used for normalization, satisfying the expression:

[0036] Among them, This represents the result of global average pooling for the c-th high-level feature map. This represents the convolution operation. Represents the ReLU activation function. Represents the Sigmoid function; The expression is:

[0037] in, The feature map representing the c-th channel; This indicates the position in the c-th channel. The pixel values ​​at that location, where H and W represent the height and width, respectively.

[0038] The pixel attention unit (PA) processing procedure is as follows: Based on the concatenated high-level feature maps, a first convolution transformation is performed. The convolutionally transformed feature maps are then activated using the ReLU function to introduce non-linear modeling capabilities. A second convolution transformation is then performed on the ReLU-activated feature maps. Finally, the Sigmoid function is used for normalization, satisfying the expression:

[0039] Among them, This represents multiple high-level feature maps after being stitched together. This represents the convolution operation. Represents the ReLU activation function. This represents the Sigmoid function.

[0040] The process of obtaining the first fused feature map is as follows: The first Zoom_Cat module is used to upsample the processed small-scale feature map to the medium-scale resolution using nearest neighbor interpolation to obtain the upsampled small-scale feature map. The medium-scale feature map, the processed ultra-large-scale feature map and the downsampled small-scale feature map are then weighted, fused and stitched together to obtain the first fused feature map. The process of obtaining the second fused feature map is as follows: The second Zoom_Cat module is used to downsample the first fused feature map after dimensionality reduction to a medium-scale resolution using adaptive pooling. The processed ultra-small scale feature map, small scale feature map and the downsampled first fused feature map are then weighted, fused and concatenated to obtain the second fused feature map.

[0041] like Figure 5 As shown, the SAM module includes an average pooling layer, a first convolutional layer, a horizontally separable convolutional layer, a vertically separable convolutional layer, a connection layer, a second convolutional layer, and a sigmoid function. The SAM module uses the second fused feature map to adaptively enhance spatial information, resulting in an enhanced small-scale spatial feature map. The process is as follows: Based on the second fused feature map, the global context is first obtained through an average pooling layer, and then pooling features are generated through a first convolutional layer. Based on the pooling features, horizontally separable convolutional layers and vertically separable convolutional layers are used to capture the horizontal and vertical spatial relationships, respectively, to obtain the horizontal convolutional features. and vertical convolution features ; Based on the horizontal convolution features and the vertical convolution feature The concatenation layer is used to stitch the data along the channel dimension. After stitching, the data is fused using a second convolutional layer. Finally, the Sigmoid function is used to generate an enhanced small-scale spatial feature map.

[0042] Specifically, based on the aforementioned horizontal convolutional features and the vertical convolution feature The concatenation layer is used to stitch the data along the channel dimension. The stitched data is then fused using a second convolutional layer. Finally, the fused data is generated using the Sigmoid function to produce an enhanced small-scale spatial feature map that satisfies the expression:

[0043] in, This represents the Sigmoid activation function. This indicates the second convolutional layer. This indicates a splicing operation.

[0044] Based on pooling features, horizontally and vertically separable convolutional layers are used to capture the horizontal and vertical spatial relationships, respectively. Features from both directions are then connected along the channel dimension using a concatenation layer. After concatenation, a second convolutional layer is used to fuse the features. Finally, a spatial attention weight map is generated using the sigmoid function. The process is as follows: Utilizing horizontally depth-separable convolutional layers to pool features Horizontal depthwise separable convolution is performed, followed by batch normalization (BN) and SiLU activation to obtain horizontal convolution features. Satisfies the expression:

[0045] in, This indicates a horizontally separable convolutional layer with a kernel size of 1xN; Using vertically depth-separable convolutional layers to pool features Vertical depth-separable convolution is performed, followed by batch normalization (BN) and SiLU activation to obtain vertical convolution features. Satisfies the expression:

[0046] in, This indicates a vertically separable convolutional layer with a kernel size of Nx1.

[0047] See the structural diagram of the ScalSeq module. Figure 6 Based on the enhanced small-scale spatial feature map, large-scale feature map, medium-scale feature map, and small-scale feature map, the P3 cross-scale fusion feature is obtained by processing with the ScalSeq module and the Add module. The process is as follows: Based on large-scale, medium-scale, and small-scale feature maps, the ScalSeq module is used to stack the large-scale, medium-scale, and small-scale feature maps along the scale dimension into a three-dimensional sequence. Then, a 3D convolutional layer is used to extract cross-layer spatial and channel correlations. After extraction, pooling is performed to obtain unified multi-scale features. Based on the unified multi-scale features, the enhanced small-scale spatial feature map is added element by element to the unified multi-scale features using the Add module to obtain the P3 cross-scale fusion feature.

[0048] Example 3 In this embodiment, to verify the performance of the PCB defect detection model proposed in this invention, several mainstream defect detection models were trained and tested using the same PCB defect dataset for performance comparison. The mainstream defect detection models compared included Faster-RCNN, Yolov5, Yolov7, Yolov8, Yolov9s, Yolov10, Toood, and Dino. During the experiment, all models used uniform parameter settings: the optimizer was SGD, the number of training epochs was 300, the initial learning rate lr0 was 0.01, the batch size was 8, the number of workers was 4, and other parameters remained at their default values. All PCB defect datasets were uniformly scaled to 640×640 resolution for training. Performance evaluation metrics included precision, recall, and mean average precision (mAP). Furthermore, to further comprehensively evaluate model efficiency, the number of model parameters and detection speed were also used as supplementary performance metrics. After training, the optimal weights obtained after training were used to evaluate the test set, and the corresponding PCB defect detection results were recorded to comprehensively evaluate the model performance. Table 1 shows a comparison of the performance of the PCB defect detection model proposed in this invention with mainstream defect detection models in PCB defect detection tasks.

[0049] Table 1

[0050] As shown in Table 1, the PCB defect detection model proposed in this invention achieves a good balance between the number of parameters and accuracy, surpassing many mainstream defect detection models.

[0051] like Figure 7 and Figure 8 As shown, Figure 7 and Figure 8 The horizontal axis represents confidence, and the vertical axis represents precision, which represents the proportion of predicted positive results that are actually positive. Figure 8The all-classes curve in the model achieves a precision of 1.0 with a corresponding confidence level of 0.870. Figure 7 When the all classes curve reaches an accuracy of 1.0, the corresponding confidence level is only 0.845, indicating that the PCB defect detection model proposed in this embodiment can maintain perfect accuracy at a higher confidence level and still ensure that all predictions are correct in a more confident manner, effectively improving the accuracy of PCB defect detection and demonstrating superior performance.

[0052] Example 4 This embodiment provides a PCB defect detection system, see [link / reference] Figure 9 This is used to implement a PCB defect detection method, including: The data processing module preprocesses the acquired PCB defect dataset to obtain a preprocessed PCB defect dataset. The model building module constructs a PCB defect detection model. The PCB defect detection model is based on a preset YOLOv11 architecture design. A module based on FFAP-SAM dual attention collaboration and cross-scale fusion is introduced into the YOLOv11 architecture to express micro-defect features and perceive multi-scale defects. The model training module uses the preprocessed PCB defect dataset to train the PCB defect detection model, thereby obtaining a trained PCB defect detection model. The PCB defect detection module uses a trained PCB defect detection model to detect defects in the PCB image to be inspected.

[0053] The same or similar labels correspond to the same or similar parts; The terms used to describe positional relationships in the accompanying drawings are for illustrative purposes only and should not be construed as limiting the invention. Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A PCB defect detection method, characterized in that, Includes the following steps: S1: Preprocess the acquired PCB defect dataset to obtain the preprocessed PCB defect dataset; S2: Construct a PCB defect detection model. The PCB defect detection model is based on a preset YOLOv11 architecture design. The YOLOv11 architecture introduces FFAP-SAM dual attention collaboration and cross-scale fusion modules to express micro-defect features and perceive multi-scale defects. S3: Use the preprocessed PCB defect dataset to train the PCB defect detection model to obtain a trained PCB defect detection model; S4: Use the trained PCB defect detection model to perform defect detection on the PCB image to be detected.

2. The PCB defect detection method according to claim 1, characterized in that, The PCB defect detection model includes a backbone network, a neck network, and a detection head. The modules introduced in the YOLOv11 architecture based on FFAP-SAM dual attention collaboration and cross-scale fusion include an FFAP feature enhancement module, a first Zoom_Cat module, a second Zoom_Cat module, a SAM module, an Add module, and a ScalSeq module. The backbone network of the PCB defect detection model uses the FFAP feature enhancement module as the first layer to achieve feature enhancement. The part of the backbone network other than the FFAP feature enhancement module is consistent with the backbone network of the preset YOLOv11 architecture. The PCB defect detection model adds a first Zoom_Cat module before the first C3k2 layer of the neck network of the preset YOLOv11 architecture, adds a second Zoom_Cat module before the second C3k2 layer of the neck network of the preset YOLOv11 architecture, replaces the second C3k2 layer with a SAM module, and connects an Add module after the SAM module. The Add module is then connected to the ScalSeq module to achieve multi-scale defect perception. The detection head of the PCB defect detection model uses the GIoU function.

3. The PCB defect detection method according to claim 2, characterized in that, In S3, the PCB defect detection model is trained using the preprocessed PCB defect dataset to obtain a trained PCB defect detection model. The process is as follows: The preprocessed PCB defect dataset is divided into a training set, a validation set, and a test set. The PCB defect detection model is trained using a training set. During training, the loss is calculated using the GIoU function of the detection head. The detection performance of the trained PCB defect detection model is evaluated using a validation set to obtain a pre-trained PCB defect detection model. The performance of the pre-trained PCB defect detection model is then tested using a test set to obtain the final trained PCB defect detection model.

4. The PCB defect detection method according to claim 2, characterized in that, The process described in S4 for using the trained PCB defect detection model to detect defects in the PCB image to be detected is as follows: In the backbone network, the FFAP feature enhancement module is used to enhance the features of the defective part of the PCB image to be detected, and the enhanced feature map is obtained. The enhanced feature maps are processed using the remaining layers in the backbone network to obtain ultra-large scale feature maps, large scale feature maps, medium scale feature maps, small scale feature maps, and ultra-small scale feature maps, respectively. In the neck network, the small-scale feature map and the ultra-large-scale feature map are processed separately to obtain the processed small-scale feature map and the processed ultra-large-scale feature map. Based on the medium-scale feature map, the processed small-scale feature map and the processed ultra-large-scale feature map, the first Zoom_Cat module is used to perform scale fusion to obtain the first fused feature map. The neck network is used to process the ultra-small scale feature map and reduce the dimensionality of the first fused feature map to obtain the processed ultra-small scale feature map and the dimensionality-reduced first fused feature map. Based on the processed ultra-small scale feature map, the small scale feature map and the dimensionality-reduced first fused feature map, the second Zoom_Cat module is used to perform scale fusion to obtain the second fused feature map. The SAM module is used to adaptively enhance the spatial information of the second fused feature map to obtain an enhanced small-scale spatial feature map. Based on the enhanced small-scale spatial feature map, large-scale feature map, medium-scale feature map, and small-scale feature map, the P3 cross-scale fusion feature is obtained by processing with the Add module and the ScalSeq module. The enhanced small-scale spatial feature map and the first fusion feature map are processed using the remaining layers in the neck network to obtain the P4 cross-scale fusion feature and the P5 cross-scale fusion feature, respectively. The P3 cross-scale fusion feature, the P4 cross-scale fusion feature, and the P5 cross-scale fusion feature are input into the detection head to obtain the PCB defect detection results.

5. The PCB defect detection method according to claim 4, characterized in that, The FFAP feature enhancement module includes shallow convolutional layers, a deep feature extraction network, channel attention units (CA), pixel attention units (PA), a weighted fusion layer, and a reconstruction unit; the deep feature extraction network consists of multiple cascaded feature groups, each of which contains several block modules. The FFAP feature enhancement module is used to enhance the features of the defective portion of the PCB image to be detected, resulting in an enhanced feature map. The process is as follows: The shallow convolutional layer is used to perform preliminary feature acquisition on the PCB image to be detected, resulting in a basic feature map; A deep feature extraction network is used to progressively extract higher semantic-level features from the basic feature map, resulting in multiple high-level feature maps. The multiple high-level feature maps are concatenated, and the channel attention unit (CA) is used to enhance the attention of the concatenated high-level feature maps to obtain a channel attention-enhanced feature map. Then, the pixel attention unit (PA) is used to enhance the attention of the concatenated high-level feature maps to obtain a pixel-level attention feature map. Based on the channel attention enhancement feature map and the pixel-level attention feature map, a weighted fusion layer is used for integration. The feature map after weighted fusion layer integration is then passed to the reconstruction unit for optimization processing using global residual connections to obtain the enhanced feature map.

6. The PCB defect detection method according to claim 4, characterized in that, The process of obtaining the first fused feature map is as follows: The first Zoom_Cat module is used to upsample the processed small-scale feature map to the medium-scale resolution using nearest neighbor interpolation to obtain the upsampled small-scale feature map. The medium-scale feature map, the processed ultra-large-scale feature map and the downsampled small-scale feature map are then weighted, fused and stitched together to obtain the first fused feature map. The process of obtaining the second fused feature map is as follows: The second Zoom_Cat module is used to downsample the first fused feature map after dimensionality reduction to a medium-scale resolution using adaptive pooling. The processed ultra-small scale feature map, small scale feature map and the downsampled first fused feature map are then weighted, fused and concatenated to obtain the second fused feature map.

7. The PCB defect detection method according to claim 4, characterized in that, The SAM module includes an average pooling layer, a first convolutional layer, a horizontally separable convolutional layer, a vertically separable convolutional layer, a connection layer, a second convolutional layer, and a sigmoid function. The SAM module uses the second fused feature map to perform adaptive spatial information enhancement, resulting in an enhanced small-scale spatial feature map. The process is as follows: Based on the second fused feature map, the global context is first obtained through an average pooling layer, and then pooling features are generated through a first convolutional layer. Based on the pooling features, horizontally separable convolutional layers and vertically separable convolutional layers are used to capture the horizontal and vertical spatial relationships, respectively, to obtain the horizontal convolutional features. and vertical convolution features ; Based on the horizontal convolution features and the vertical convolution feature The concatenation layer is used to stitch the data along the channel dimension. After stitching, the data is fused using a second convolutional layer. Finally, the Sigmoid function is used to generate an enhanced small-scale spatial feature map.

8. A PCB defect detection method according to claim 7, characterized in that, Based on pooling features, horizontally and vertically separable convolutional layers are used to capture the horizontal and vertical spatial relationships, respectively. Features from both directions are then connected along the channel dimension using a concatenation layer. After concatenation, a second convolutional layer is used to fuse the features. Finally, a spatial attention weight map is generated using the sigmoid function. The process is as follows: Utilizing horizontally depth-separable convolutional layers to pool features Horizontal depthwise separable convolution is performed, followed by batch normalization (BN) and SiLU activation to obtain horizontal convolution features. Satisfies the expression: in, This indicates a horizontally depth-separable convolutional layer; Using vertically depth-separable convolutional layers to pool features Vertical depth-separable convolution is performed, followed by batch normalization (BN) and SiLU activation to obtain vertical convolution features. Satisfies the expression: in, This indicates a vertically separable convolutional layer.

9. A PCB defect detection method according to claim 4, characterized in that, Based on the enhanced small-scale spatial feature map, large-scale feature map, medium-scale feature map, and small-scale feature map, the P3 cross-scale fusion feature is obtained by processing with the ScalSeq module and the Add module. The process is as follows: Based on large-scale, medium-scale, and small-scale feature maps, the ScalSeq module is used to stack the large-scale, medium-scale, and small-scale feature maps along the scale dimension into a three-dimensional sequence. Then, a 3D convolutional layer is used to extract cross-layer spatial and channel correlations. After extraction, pooling is performed to obtain unified multi-scale features. Based on the unified multi-scale features, the enhanced small-scale spatial feature map is added element by element to the unified multi-scale features using the Add module to obtain the P3 cross-scale fusion feature.

10. A PCB defect detection system, used to implement the PCB defect detection method according to any one of claims 1-9, characterized in that, include: The data processing module preprocesses the acquired PCB defect dataset to obtain a preprocessed PCB defect dataset. The model building module constructs a PCB defect detection model. The PCB defect detection model is based on a preset YOLOv11 architecture design. A module based on FFAP-SAM dual attention collaboration and cross-scale fusion is introduced into the YOLOv11 architecture to express micro-defect features and perceive multi-scale defects. The model training module uses the preprocessed PCB defect dataset to train the PCB defect detection model, thereby obtaining a trained PCB defect detection model. The PCB defect detection module uses a trained PCB defect detection model to detect defects in the PCB image to be inspected.

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