Wiring diagram identification method and device based on deep learning, and electronic equipment

Abstract

The invention discloses a wiring diagram recognition method and device based on deep learning and electronic equipment, and the method comprises the steps: carrying out the correction and mask processing of an initial wiring diagram, obtaining a first wiring diagram, and fusing mask parameters and mask skeleton parameters; extracting circuit elements in the first wiring diagram based on fusion mask parameters and mask skeleton parameters, and classifying the circuit elements to obtain a first element set of the first wiring diagram; performing port connection line pairing processing and topological optimization processing on the first element set, and determining a second element set and a corresponding second wiring diagram; according to the second element set, performing multi-dimensional verification and global topological structuring processing on the second wiring diagram to obtain a topological graph data model; and determining a JSON file, a visual topological graph, a VF2 check report and a Neo4j graph database of the wiring diagram according to the structured data in the topological graph data model. According to the invention, a more accurate wiring diagram can be identified.

Description

Technical Field

[0001] This application relates to the field of wiring diagram recognition technology, and in particular to a wiring diagram recognition method, apparatus and electronic device based on deep learning. Background Technology

[0002] The automated understanding of engineering wiring / electrical diagrams usually follows the general route of "symbol and text detection → connection extraction and skeletonization → port / node association → topology construction and verification / matching → structured expression". In recent years, deep learning has been widely used for symbol / primitive detection (such as YOLO series, one-stage detector), text detection / recognition (OCR), while connections are mostly adopted by a combination of segmentation (U-Net / DeepLab, etc.) and geometric detection (such as line / arc detection, thinning / skeletonization); finally, the component terminals and connection skeletons are geometrically / topologically associated, and topology verification and template alignment can be performed with the help of graph matching algorithms (such as VF2 / VF2++) to reduce misconnections / omissions and obtain structured data that can be stored in the database [1]–[3],

[10] ,

[11] .

[0003] The closest technical solution is as follows:

[0004] (A) Method Class: Typical Steps of Existing Methods

[0005] Existing end-to-end or pipeline-style wiring / electrical diagram analysis typically includes the following steps:

[0006] Preprocessing (denoising, deskewing, binarization / enhancement);

[0007] Primitive / symbol detection (commonly YOLO, GFL, Faster R-CNN, etc.) and text detection / recognition (OCR / text localization + recognition);

[0008] Connection extraction (pixel-level segmentation + refinement, or straight line / polyline geometry detection) and node / terminal recognition;

[0009] Topology reconstruction (assembling "terminal-wire-component" into a graphical structure, handling jumpers / patches and contacts);

[0010] Topology verification / matching (using improved VF2 / VF2++, etc. for graph matching or template comparison), and outputting structured results / standard formats (such as digital diagrams for engineering systems).

[0011] For example, for hand-drawn circuit diagrams, there are methods to perform component detection using YOLOv5 and combine Hough transform for node identification, and recover the simulable circuit connectivity from the scan diagram [4].

[0012] For end-to-end digitization of P&ID / electrical diagrams, some studies use deep learning to recognize symbols / text / lines, then perform topology reconstruction and digital diagram generation (compatible with DEXPI and other formats) to achieve structured output usable in engineering[3].

[0013] In high-density drawings, there are also works that focus on line object recognition and connection relationship extraction[5], as well as improving the robustness of single-line graph symbol detection by synthesizing / enhancing datasets (such as GAN-based enhancement + YOLOv5)[6].

[0014] For the verification of the primary wiring diagram of the plant, existing methods use Faster R-CNN+OCR to obtain the elements and labels, and then use the improved VF2 to perform topology matching verification to improve the accuracy[9],

[10] .

[0015] (B) Device category: The structural composition and module relationships of existing systems

[0016] Device / system solutions often adopt a "multi-module cascaded" architecture:

[0017] The primitive / symbol detection module outputs the symbol category and location;

[0018] The text extraction / OCR module outputs a text box and the recognition result;

[0019] The text association / pairing module attaches text to corresponding primitives based on geometric proximity and rules;

[0020] The wiring / network identification module extracts the wire network and infers electrical continuity;

[0021] The matching / generation module completes the matching of bus / component templates, or generates structured representations such as XML / graph databases for upper-layer applications to query and interact with.

[0022] Early published patents have clearly proposed a pipeline and data flow of “symbol recognizer + wirenet recognizer + named (text) recognizer + XML generator + interactive viewer”; each module is interconnected by detection boxes / hotspot coordinates, etc., and connectivity highlighting and interaction are achieved accordingly [7]. In recent years, Chinese patents have further combined the above modules with deep learning detectors (including YOLOv5) and proposed a system-level solution of “graphical primitive detection - text extraction - text and graphic primitive center matching - template matching” [8]. There are also implementations of convolutional network graphic primitive recognition and line information extraction for a single wiring diagram [9].

[0023] However, the above-mentioned existing technologies have the following drawbacks: inaccurate port-level connectivity relationships, easy loss, ambiguity of "intersection / crossing" at connection intersections, broken lines and misconnections caused by text pressing lines, omissions or drifts of nets under low-quality scanning / noise, confusion between small black dots and stains / dirt, lack of cross-page connectivity due to multi-page diagrams / bus labels, differences in symbol sets and inconsistent legend specifications, weak structured database storage capability, difficulty in being consumed by engineering systems, lack of calculable verification and error correction loop for topology correctness, insufficient detection performance of small targets (terminals / pins), scarce training samples, poor generalization, and latency and throughput in scenarios with limited computing resources. Summary of the Invention

[0024] Therefore, the purpose of this application is to provide a wiring diagram recognition method, apparatus and electronic device based on deep learning, so as to more accurately recognize wiring diagrams.

[0025] In a first aspect, embodiments of the present invention provide a wiring diagram recognition method based on deep learning. Further, the method includes: S102: modifying and masking an initial wiring diagram to obtain a first wiring diagram, fusion mask parameters, and mask skeleton parameters; S104: extracting and classifying circuit elements in the first wiring diagram based on the fusion mask parameters and mask skeleton parameters to obtain a first element set of the first wiring diagram; S106: performing port connection pairing and topology optimization processing on the first element set to determine a second element set and a corresponding second wiring diagram; S108: performing multi-dimensional verification and global topology structuring processing on the second wiring diagram based on the second element set to obtain a topology diagram data model; S110: determining the wiring diagram's JSON file, visualized topology diagram, VF2 verification report, and Neo4j graph database based on the structured data in the topology diagram data model.

[0026] Further, S102 includes: S102-2: determining the tilt angle of the initial wiring diagram; S102-4: correcting the initial wiring diagram according to the tilt angle to obtain a corrected wiring diagram; S102-6: calculating the foreground mask parameters of the corrected wiring diagram and determining a first wiring diagram according to the foreground mask parameters; S102-8: performing line fusion on the first wiring diagram to determine the fusion mask parameters; S102-10: performing skeletonization processing on the first wiring diagram to determine the mask skeleton parameters.

[0027] Further, S104 includes: S104-2: performing segmentation and fusion processing on the first wiring diagram; S104-6: extracting and classifying the circuit elements in the segmented and fused first wiring diagram according to the YOLO algorithm, fusion mask parameters, and mask skeleton parameters to obtain a first element set of the first wiring diagram; wherein, the first element set includes a device / symbol candidate set, a port candidate set, and a line segment / skeleton candidate set; the first element set includes: the center horizontal coordinate of the element, the center vertical coordinate of the element, the element frame width, the element frame height, the element level, and the element confidence level.

[0028] Further, S104-2 includes: S104-2-2: cutting the first wiring diagram into multiple overlapping blocks based on a preset cutting size and cutting step size; S104-2-4: determining the cross-union ratio between the target detection box in each overlapping block and the overlapping block; S104-2-6: performing cross-block fusion on all target detection boxes based on the cross-union ratio.

[0029] Furthermore, S104 also includes: performing pyramid layering enhancement processing on the overlapping small blocks.

[0030] Further, S106 includes: S106-2: calculating the minimum distance from each element in the port candidate set to each element in the line segment / skeleton candidate set in the first element set; S106-4: establishing port connection pairing relationships based on the minimum distances; S106-6: performing topology optimization processing on the elements in the line segment / skeleton candidate set according to the port connection pairing relationships to determine the second element set; S106-8: determining the second wiring diagram based on the second element set.

[0031] Further, S108 includes: S108-2: determining whether the topological connectivity, closed-loop connectivity, attribute consistency, and spatial constraints of the second wiring diagram are qualified; S108-4: if all are qualified, then extracting the topological diagram data model of the second wiring diagram based on the second element set.

[0032] Secondly, embodiments of the present invention provide a wiring diagram recognition device based on deep learning. The device includes: a first recognition module, used to correct and mask an initial wiring diagram to obtain a first wiring diagram, fused mask parameters, and mask skeleton parameters; a second recognition module, used to extract and classify circuit elements in the first wiring diagram based on the fused mask parameters and mask skeleton parameters to obtain a first element set of the first wiring diagram; a third recognition module, used to perform port connection pairing and topology optimization processing on the first element set to determine a second element set and a corresponding second wiring diagram; a fourth recognition module, used to perform multi-dimensional verification and global topology structuring processing on the second wiring diagram based on the second element set to obtain a topology diagram data model; and a fifth recognition module, used to determine the JSON file of the wiring diagram, the visualized topology diagram, the VF2 verification report, and the Neo4j graph database based on the structured data in the topology diagram data model.

[0033] Thirdly, embodiments of the present invention provide an electronic device, including a processor and a memory, wherein the memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the above-described deep learning-based wiring diagram recognition method.

[0034] Fourthly, embodiments of the present invention provide a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are invoked and executed by a processor, the machine-executable instructions cause the processor to implement the aforementioned deep learning-based wiring diagram recognition method.

[0035] The beneficial effects of the embodiments of the present invention are as follows:

[0036] This application discloses a wiring diagram recognition method, apparatus, and electronic device based on deep learning, comprising: modifying and masking an initial wiring diagram to obtain a first wiring diagram, fused mask parameters, and mask skeleton parameters; extracting and classifying circuit elements in the first wiring diagram based on the fused mask parameters and mask skeleton parameters to obtain a first element set of the first wiring diagram; performing port connection pairing and topology optimization processing on the first element set to determine a second element set and a corresponding second wiring diagram; performing multi-dimensional verification and global topology structuring processing on the second wiring diagram based on the second element set to obtain a topology diagram data model; and determining a JSON file of the wiring diagram, a visualized topology diagram, a VF2 verification report, and a Neo4j graph database based on the structured data in the topology diagram data model. This invention can identify more accurate wiring diagrams.

[0037] Other features and advantages of this application will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the above-described techniques of this application.

[0038] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 A flowchart of the first deep learning-based wiring diagram recognition method provided in this application;

[0041] Figure 2 A flowchart of the second deep learning-based wiring diagram recognition method provided in this application;

[0042] Figure 3 A schematic diagram of a connection fusion process provided in this application;

[0043] Figure 4 A schematic diagram of skeleton node classification provided in this application;

[0044] Figure 5 A schematic diagram of port projection matching provided in this application;

[0045] Figure 6 A schematic diagram of cross-semantic determination provided in this application;

[0046] Figure 7 A schematic diagram of a text association process provided for this application;

[0047] Figure 8 A schematic diagram of topology construction and verification closed loop provided in this application;

[0048] Figure 9 A schematic diagram of a data model provided for this application;

[0049] Figure 10 A schematic diagram of a wiring diagram recognition device based on deep learning provided in this application;

[0050] Figure 11 A schematic diagram of an electronic device provided in this application. Detailed Implementation

[0051] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0052] This application is used in electrical drawing recognition scenarios.

[0053] Example 1

[0054] Specifically, existing drawing recognition technology has the following 12 defects / problems:

[0055] Problem 1) Port-level connectivity is inaccurate and easily lost.

[0056] Problem: Existing methods mostly infer connectivity at the "component level" or "near the contact," making it difficult to pinpoint the specific terminal / pin, resulting in incomplete netlist reconstruction.

[0057] The technical means of this invention is to introduce port anchors / terminal classes in YOLO detection and bind the ports to the connection skeleton using the skeleton nearest neighbor projection.

[0058] Technical effect: It achieves Port→Net binding at the port level, significantly reducing false connections / missed connections.

[0059] Question 2) Ambiguity in "intersection / crossing" at the intersection of lines.

[0060] Problem: Inconsistent continuity assessments are caused by the lack of markings or differences in symbols (small black dots / crossovers) at intersections.

[0061] The technical means of this invention are as follows: "small black dots at the junction" and "cross-line bridges" are included in the detection categories; a symbol priority rule is introduced in the topology stage (black dots = conduction; bridges = disconnection), and a configurable default strategy and uncertainty mark are set for unmarked intersections.

[0062] Technical effect: Unifies the communication semantics at intersections, reducing topology errors caused by rule ambiguity.

[0063] Question 3) Broken lines and incorrect connections caused by text overlapping lines.

[0064] Problem: OCR text and lines sticking together causes segmentation breaks and geometric misjudgments.

[0065] The technical means of this invention is as follows: First, the text is detected and a text mask is generated. Then, the line segmentation / skeletonization is completed under the mask. Subsequently, the occluded segment is restored by filling in the lines based on the OCR results and the shortest path of the skeleton endpoints.

[0066] Technical benefits: Improves connection continuity and traceability, and significantly reduces "disconnection-false bridging".

[0067] Question 4) Netting omissions or drift under low-quality scanning / noise.

[0068] Problem: Single-path (segmentation only or geometry only) is sensitive to stains, scan tilt, and changes in line thickness.

[0069] The technical means of this invention are: to use dual-path fusion of segmented mask ∪ geometric line segments, and to perform morphological repair + skeleton refinement + automatic endpoint bridging (distance / direction threshold).

[0070] Technical benefits: Improves network recall and robustness, and reduces reliance on a single threshold.

[0071] Question 5) Small black dots are confused with stains / dirt.

[0072] Problem: Traditional thresholding tends to treat noise as contact points.

[0073] The technical means of this invention is to introduce detection and geometric consistency verification (diameter range, roundness / Hough circle, and intersection with the skeleton) for the "small black dots at the contact point".

[0074] Technical benefits: Reduces pseudo-connections and stabilizes topology node detection.

[0075] Question 6) Cross-page connectivity loss caused by multi-page diagrams / bus labels.

[0076] Problem: Websites with the same name cannot be correctly merged on different pages / areas.

[0077] The technical means of this invention: OCR-based parsing of network names / bus tags and merging of Net-IDs, supporting cross-page and cross-regional network splicing.

[0078] Technical effect: Generates globally consistent network identifiers, supporting connectivity queries across the entire drawing set.

[0079] Question 7) Differences in symbol sets and inconsistent legend specifications.

[0080] Problem: Different projects / manufacturers have different illustrations, and the hard-coded rules have poor portability.

[0081] The technical means of this invention is to create a configurable knowledge base by combining the semantics of the legend with the default cross rules; the detection model is only responsible for perception, and the semantics are interpreted by the configuration.

[0082] Technical benefits: Adapts to various legends / industry standards without modifying the code, reducing deployment costs (technically achieved through rule decoupling).

[0083] Question 8) The structured data has weak storage capabilities and is difficult for engineering systems to consume.

[0084] Problem: The results are mostly hash labels and line graphs, lacking a unified data model.

[0085] The technical means of this invention is to define a standard JSON / database schema for device-port-line segment-node-network and provide graph database (Neo4j) mapping and constraints.

[0086] Technical effect: Outputs engineering-grade data assets that can be directly retrieved, verified, and traced.

[0087] Question 9) The topological correctness lacks a computable verification and error correction loop.

[0088] Problem: Results are not verifiable or are only subject to manual sampling.

[0089] The technical means of this invention is to introduce graph matching / constraint verification (such as subgraph isomorphism, degree / direction / label consistency) and output minimum repair suggestions (break / connect / change label) for conflict points.

[0090] Technical effect: Forms an automatic verification and suggested repair loop, improving end-to-end accuracy.

[0091] Question 10) Insufficient detection performance for small targets (terminals / pins).

[0092] Problem: The terminals are small in size and high in density, and are often missed during inspection.

[0093] The technical means of this invention are: enabling a high-resolution feature layer / dense feature pyramid in the detection network, data augmentation for small targets, and difficult example mining.

[0094] Technical results: The recall rate and positioning accuracy of terminals and micro-symbols are significantly improved.

[0095] Problem 11) Training samples are scarce and generalization is poor.

[0096] Problem: Labeling actual wiring diagrams is costly and varies greatly depending on the scenario.

[0097] The technical means of this invention is to construct a symbol library-driven synthetic data engine (random layout, connection, label) to automatically generate truth topology and superimpose scan / compression / stain perturbations.

[0098] Technical effect: Obtain transferable models with low manual annotation and improve cross-domain generalization.

[0099] Question 12) Latency and throughput in scenarios with limited computing resources.

[0100] Problem: Edge / embedded deployments are latency-sensitive.

[0101] The technical means of this invention are: lightweight model (pruning, quantization, distillation), block parallel / pyramid reasoning and two-stage fast path (fast detection followed by fine-tuning).

[0102] Technical effect: Achieve second-level response and high-throughput processing while ensuring accuracy.

[0103] To address the aforementioned deficiencies / problems, embodiments of the present invention provide a wiring diagram identification method, the flowchart of which is shown below. Figure 1 , Figure 2 As shown, the method includes:

[0104] S102: Correct and mask the initial wiring diagram to obtain the first wiring diagram, fusion mask parameters, and mask skeleton parameters.

[0105] S102 includes:

[0106] S102-2: Determine the tilt angle of the initial wiring diagram.

[0107] S102-4: Correct the initial wiring diagram according to the tilt angle to obtain the corrected wiring diagram.

[0108] S102-6: Calculate the foreground mask parameters of the corrected wiring diagram, and determine the first wiring diagram based on the foreground mask parameters.

[0109] S102-8: Perform connection fusion on the first wiring diagram to determine the fusion mask parameters.

[0110] S102-10: Perform skeletonization processing on the first wiring diagram to determine the mask skeleton parameters.

[0111] Specifically, S102 is equivalent to S1: it includes rotating and correcting the initial wiring diagram (defined as P0) and performing masking processing to obtain the separation mask of the initial wiring diagram. Fusion Mask The mask skeleton S and the first wiring diagram (defined as P1) are defined as follows. The first wiring diagram is a binary image containing the foreground mask B(x,y).

[0112] S1-1: Inclination angle Estimation: Obtain the initial wiring diagram P0 to be identified, accumulate the straight lines in the initial wiring diagram in Hough space, and give the dominant tilt angle of the page in the direction of maximum response. This angle will be used for full-image rotation correction:

[0113] Formula 1;

[0114] in, This is the polar coordinate distance parameter for the line, representing the signed shortest distance from the line to the origin. For the normal vector of the line and The included angle of the axis (unit: radians or degrees). For the Hough accumulator, set the edge / line element pairs Voting until satisfied On the parameter grid points, the number of votes is counted, and the dominant straight line direction of the page corresponds to the maximum response.

[0115] For the image coordinates of the initial wiring diagram If the direction of the straight line is from the normal angle The description then has .

[0116] Notice and To indicate the direction of the same group of lines, usually... or Remove duplicates.

[0117] S1-2: Rotational Correction: Utilizing Construct a rotation matrix to uniformly map the original pixel coordinates (x, y) of the initial wiring diagram to the corrected coordinates. , This yields a calibration map, which serves as the common input for subsequent segmentation and geometric detection.

[0118] Formula 2;

[0119] Formula 3;

[0120] S1-3: Local adaptive threshold: in the correction map ( , On the ), calculate the local mean using a sliding window. and standard deviation This yields an adaptive threshold T(x,y) for each pixel. The threshold is not a constant but dynamically changes with local noise and brightness.

[0121] Formula 4;

[0122] in, For Centered on, window size is (e.g., 15×15 or 31×31) local mean (calculated on the calibration plot);

[0123] This represents the local standard deviation within the same window, characterizing the local contrast / noise level.

[0124] This is the adjustment coefficient, usually taken as 0.2-0.5 (empirical value around 0.34). The larger the value, the more "lenient" it is for high-contrast regions.

[0125] This is the upper bound of the dynamic range of the standard deviation. For 8-bit grayscale, R0 is usually set to 128 (or 255, depending on training / experience).

[0126] The connection between formulas 2, 3, and 4: Formula 4 , All of these are obtained by sliding a window on the rotated and corrected image, and the entire subsequent process is within... Complete the task within a coordinate system to avoid frequent coordinate mapping.

[0127] S1-4: Binarization: Binarize the original image (i.e., the corrected image after grayscale conversion) with the threshold value. The foreground mask B(x,y) is obtained through comparison, and the first wiring diagram (defined as P1) is obtained based on the foreground mask B(x,y). This mask can be directly used as a priori for geometric detection and semantic segmentation, and participates in wiring fusion (Equation 6) and skeleton refinement (Equation 7):

[0128] Formula 5;

[0129] in: This is the grayscale intensity (0-255) after rotation correction. If the original image is RGB, it can be converted using the brightness formula: If the scan is grayscale, you can directly use its pixel value.

[0130] S1-5: Line fusion: In order to obtain a network that is both coherent and accurately positioned, the "union of semantic segmentation mask M_seg and geometric line segment L_geo" is adopted, and denoising and fragmentation are performed through morphological opening / closing operations to obtain a fusion mask M_fuse for skeletonization.

[0131] Formula 6;

[0132] in, As the foreground mask obtained from semantic segmentation, the network can use or As input.

[0133] This is the set of line segments obtained from geometric detection.

[0134] This is the result of rasterizing the line segment set into a binary mask.

[0135] ∪ represents the set union operation.

[0136] Perform morphological opening operations to remove isolated noise points. The structuring element can be a disk with a radius of 1-2 or a 3×3 cross.

[0137] For morphological closing operations, it bridges narrow gaps / breaks, making the connections more complete.

[0138] S1-6: Skeleton Refinement: [The following text appears to be incomplete and requires further context:] The data is refined (e.g., Zhang–Suen / Guo–Hall) to obtain a one-pixel-wide skeleton S. Then, the pixel degree is counted on S according to the 8-neighborhood to distinguish between "endpoints (degree = 1)" and "intersections (degree ≥ 3)", providing anchors for port projection and topology mapping.

[0139] Formula 7;

[0140] Where S is composed of A one-pixel wide skeleton mask obtained through thinning / skeletonization. .

[0141] It represents the 8-neighborhood of pixel p.

[0142] for The number of adjacent skeleton pixels, often used in topology analysis: As the endpoint, For intersection / branching points, This is a regular point on the connection line.

[0143] The endpoints and intersections of the skeleton will serve as initial vertex candidates for graph G=(V,E), and together with the port anchors (Equation (8)), they will determine the final connection relationship.

[0144] At this point, S1 obtains the preprocessed image, which contains the foreground mask B(x,y), a binary black and white image, and also obtains the separation mask, fusion mask, and mask skeleton of the initial wiring diagram, which serve as common inputs for subsequent segmentation, geometric detection, and wiring reconstruction.

[0145] Summary of S1: P0 → Edge detection / noise reduction → Hough accumulation → (Formula 1);

[0146] → Rotation matrix →Coordinate Mapping / Interpolation→ (Formula 2-3);

[0147] →Local statistics (Sliding window) → (Formula 4)

[0148] → (Formula 5) → Line segment detection L_geo and segmentation mask M_seg;

[0149] → (Formula 6);

[0150] →Skeletonization S→deg(p) endpoint / intersection extraction (Formula 7)→Downstream geometric / semantic parsing.

[0151] For S1, specifically, Used for rotation correction, is The premise; Decision B, and thus influence and Connectivity; It directly serves connection fusion, skeleton refinement, and topological point recognition.

[0152] S104: Extract circuit elements from the first wiring diagram based on the fusion mask parameters and mask skeleton parameters, and classify them to obtain the first element set of the first wiring diagram.

[0153] S104 includes:

[0154] S104-2: Perform segmentation and fusion processing on the first wiring diagram.

[0155] S104-6: Based on the YOLO algorithm, fusion mask parameters, and mask skeleton parameters, extract and classify the circuit elements in the first wiring diagram after segmentation and fusion processing to obtain a first element set of the first wiring diagram. The first element set includes a device / symbol candidate set, a port candidate set, and a line segment / skeleton candidate set. The first element set includes: the element's center x-coordinate, the element's center y-coordinate, the element's bounding box width, the element's bounding box height, the element's level, and the element's confidence level.

[0156] Specifically, S104 is S2, which includes: Input: the correction map from S1, and the binary foreground. Fusion Mask Skeleton S. Output: Detection set. It includes three categories of candidates: device / symbol set, port set, and line segment / skeleton set. Each element contains geometric, category, and confidence information.

[0157] YOLO Overview: Basic Principles: YOLO (You Only Look Once) is a deep learning-based object detection algorithm. Its core idea is to transform the object detection task into a one-time regression problem, that is, to simultaneously predict the location (Bounding Box) and class (Class) of all objects in an image during a single forward propagation of the neural network. YOLO divides the input image into an S×S grid, and each grid predicts: - Object center point coordinates (x, y); - Object width and height (w, h); Confidence score (object presence probability × IOU); Class probability (Class Probabilities); Finally, the final detection result is obtained through non-maximum suppression (NMS). Network Structure (Taking YOLOv5 / YOLOv8 as an example): The YOLO model generally consists of three parts: 1. Backbone: Extracts multi-level features of the image. 2. Neck: Uses a feature pyramid structure to fuse features at different scales. 3. Head: Outputs the predicted bounding box coordinates, confidence score, and class probability.

[0158] S2 (S104): Extract symbols from the elements in the first wiring diagram P1, classify them, and obtain the detection set I0. The element classification includes: device / symbol candidate set, port candidate set, and line segment / skeleton candidate set.

[0159] S2 includes: Input: First wiring diagram P1 from S1, binary foreground Fusion Mask Skeleton S. Output: Detection set. It includes three types of candidates: device / symbol candidate set, port candidate set, and line segment / skeleton candidate set. Each element contains geometric, category, and confidence information.

[0160] S2 Three Types of Output:

[0161] Category 1: Symbol: Box detection head output .

[0162] Category 2: Port: box + keypoint detection head; predict 1 keypoint within each port box.

[0163] The third category: line segments / skeletons: YOLO-Seg can be used to output thin line regions in the form of masks, or to approximate line segment candidates with "thin boxes", and then fused and corrected with the skeleton S of S1.

[0164] S2 includes:

[0165] S2-1: Preliminary detection using YOLO technology yields three initial candidate sets: device / symbol candidate set, port candidate set, and line segment / skeleton candidate set, resulting in candidate set parameters. .

[0166] S2-2: Extract the center point coordinates (x_p, y_p) of each port in the "port candidate set" using YOLO technology, and introduce port keypoints (portanchors) / terminal classes in YOLO detection.

[0167] Based on the port frame center before correction given in S2-1 With width and height Network output relative offset The corrected element coordinates (x_p, y_p) are obtained, which are the keypoint offsets for network regression.

[0168] Formula 8;

[0169] Formula 9;

[0170] in, The row and column of the feature map; s is the step size; For keypoint offsets in network regression; These are the parameters for the port detection frame.

[0171] S2-3: Port Direction (Optional): Coordinates of the center point of the port Nearby (radius) Take the local neighborhood of the skeleton S and perform PCA, and take the direction of the first principal component as the port normal; or perform refinement and orientation gradient estimation on B to obtain the tangential / normal direction, and obtain the port anchors / terminal classes.

[0172] S104-2 includes:

[0173] S104-2-2: Based on the preset cutting size and cutting step, the first wiring diagram is cut into multiple overlapping small blocks.

[0174] S104-2-4: Determine the cross-union ratio between the target detection box within each overlapping block and the overlapping block.

[0175] S104-2-6: Based on the intersection-union ratio, perform cross-block fusion on all target detection boxes.

[0176] S104-2, or block parallel processing, divides the entire image into multiple overlapping small blocks, feeds them into YOLO inference separately, and finally merges them in the global coordinate system.

[0177] S104-2 includes:

[0178] 1) Let the size of the overlapping small blocks be... If the overlap is 0, then the cutting step size is... .

[0179] No. Top left corner coordinates of the block:

[0180] Formula 10, For block indexes;

[0181] 2) The detection frame within the overlapping small block Map back to global:

[0182] Formula 11;

[0183] 3) Subsequently, cross-block NMS fusion was performed on the detection results of all overlapping small blocks, and the intersection-union ratio was calculated as follows:

[0184] Formula 12;

[0185] Preset suppression threshold ;

[0186] NMS: Press Retain from high to low, discard. Overlapping boxes;

[0187] The category confidence score is obtained from S2-1.

[0188] 4) In primitive / terminal / symbol detection, multiple candidate boxes from the detector need to be deduplicated by NMS. The core criterion is the intersection-union ratio (IoU). It ensures that only the most representative detection boxes are retained and the results are passed to port matching and text association.

[0189] refer to Figure 3 For IOU, in primitive / terminal / symbol detection, multiple candidate boxes from the detector need to be deduplicated using NMS, with the core criterion being the intersection-union ratio (IU). It ensures that only the most representative detection boxes are retained and passes the results to the port matching ( ) and text association ( After being filtered by NMS, geometric entities such as "device frame, terminal frame, and text frame" will be spatially registered with the downstream wire mesh and skeleton.

[0190] In the process of determining elements, corresponding to question 7, different projects / manufacturers have different legends, and the hard-coded rules have poor portability. S104 also includes making the legend semantics and cross-default rules into a configurable knowledge base; the detection model is only responsible for perception, and the semantics are interpreted by the configuration. Technical effect: Adapt to multiple legends / industry standards without changing the code, reducing deployment costs (technically, this is rule decoupling).

[0191] S104 further includes: performing pyramid layering enhancement processing on the overlapping small blocks (corresponding to problems 10 and 12).

[0192] S104 specifically includes:

[0193] Pyramid processing involves generating a series of coarse-to-fine image layers from the same image at multiple scales (scale down or scale up), performing detection / matching / segmentation at each scale; small targets are clearer in the scaled-up layers, while large targets are more stable in the original image or scaled-down layers. Finally, the results from each scale are mapped back to the original image and fused to improve recall and robustness.

[0194] For the input, construct a scale set, infer at each scale separately, and then backfeed to the original scale before fusion:

[0195] ,like ;

[0196] scale superior: ;

[0197] Scale recasting: ;

[0198] S104 also includes: Weighted Box Fusion (WBF):

[0199] Given candidate boxes for the same target With fractions Weight Integration Center: ;Integrated width and height: ; This is the scaling factor; For scale The box below; Controlling the influence of high-resolution frames; WBF needs to be merged before... Clustering to the same goal.

[0200] S106: Perform port connection pairing and topology optimization on the first element set to determine the second element set and the corresponding second wiring diagram.

[0201] S106 includes:

[0202] S106-2: Calculate the minimum distance from each element in the port candidate set in the first element set to each element in the line segment / skeleton candidate set.

[0203] S106-4: Establish port connection pairing relationships based on the minimum distance (corresponding to question 1).

[0204] Specifically, S106-2 and S106-4 include: establishing the geometric constraint relationship between the port and the network.

[0205] For each port anchor point u, perform nearest neighbor projection on the skeleton point set Γ (e.g., Figure 5 (As shown); when the projection distance does not exceed the threshold d0, it is considered that the port has fallen on a certain skeleton line, thus establishing constraints with subsequent connected components:

[0206] Formula 13;

[0207] Calculate nearest neighbor: For each port center, calculate the distance to all skeleton points and select the minimum.

[0208] Formula 14;

[0209] This process couples the "frame-level detection results" with the "pixel-level skeleton" to ensure the geometric consistency between the port and the net; if the distance exceeds d0, the system will mark it as uncertain and hand it over to the error correction stage for processing (see reference). Figure 7 ).

[0210] Beneficial effects: By calculating the nearest neighbor distance from the port to the skeleton point (Formula 8), the skeleton segment corresponding to each port is determined, forming a "port-connection" binding relationship. The output is a structured set containing all "port-connection" pairs, identifying the initial topological connection relationship between each device symbol and the connecting line.

[0211] Beneficial effects: This process couples the "frame-level detection results" with the "pixel-level skeleton" to ensure the geometric consistency between the port and the net; if the distance exceeds d0, the system will mark it as uncertain and hand it over to the error correction stage for processing.

[0212] The execution process also includes: text association: direction-first matching cost and cross-page merging. For the identified text t (such as net name, terminal number) and candidate object o (device, port, line segment or skeleton fragment), a direction-first matching cost function C(t,o) is constructed to balance spatial proximity and layout direction consistency; then the minimum total cost matching is solved, and cross-page merging is performed on nets with the same name (corresponding to problem 3):

[0213] Formula 15;

[0214] d⊥ emphasizes the close proximity of the text and object in the normal direction, Δθ penalizes inconsistent directions, and γ is used to avoid mistakenly associating device-level tags with port-level objects.

[0215] S106-6: Perform topology optimization processing on the elements in the candidate set of line segments / skeletons according to the port connection pairing relationship to determine the second element set.

[0216] S106-8: Determine the second wiring diagram based on the second set of elements.

[0217] Specifically, establish a binding relationship: bind the port to the corresponding skeleton segment to form a "port-connection" pairing (matching) relationship.

[0218] Based on the established initial "port-connection" relationship, further connection merging and structural optimization are performed. This mainly includes: 1. Identifying and merging skeleton segments belonging to the same logical connection (such as continuous line segments at nodes or intersections); 2. Determining based on semantics ( Figure 6 (corresponding to automatic endpoint bridging in questions 2 and 4) and skeleton node classification ( Figure 4 1. Identify connection types such as T-shapes, intersections, and endpoints; 2. Generate a more coherent connection topology. The output is a fused set of connections.

[0219] S108: Perform multi-dimensional verification and global topology structuring on the second wiring diagram based on the second element set to obtain the topology diagram data model.

[0220] S108 includes:

[0221] S108-2: Determine whether the topological connectivity, closed-loop connectivity, attribute consistency, and spatial constraints of the second wiring diagram are qualified.

[0222] S108-4: If all are qualified, then extract the topology data model of the second wiring diagram based on the second element set.

[0223] S108 is responsible for global topology construction and verification loop (see...) Figure 8 This process associates the merged connections with semantic objects such as devices and ports to construct a complete electrical or logical topology diagram. This includes: 1. Topology connectivity verification and loop closure detection; 2. Attribute consistency and spatial constraint checks; 3. Generation of a structured data model (see...). Figure 9 ER diagram). Output: Topology data model (including devices, ports, connections and their relationships).

[0224] Topology and verification specifically include (corresponding to question 9):

[0225] Net-IDs are generated from connected components to form closed loops: A graph G=(V,E) is constructed by combining skeleton vertices, port projections, and intersection semantics (whether the nodes are connected / crossed at intersections). The graph is then partitioned according to connected components, assigning each vertex / port to a unique network ID Net(u).

[0226] Formula 16;

[0227] The obtained Net-ID will be combined with the text association results to generate a structured output (device—port—line—node—net). To ensure project consistency, the system will then compare the template using graph matching (such as VF2). If a conflict is found, the system will provide suggestions to "disconnect / reconnect / rename" and return to the previous steps for minimal repairs, forming a closed loop.

[0228] S106 completes geometric matching (port and skeleton binding), S108 performs connection fusion and semantic layer structure optimization, and S108 performs topology modeling and global verification. The three processes form a closed-loop process from detection results → local pairing → global topology model.

[0229] S110: Based on the structured data in the topology data model, determine the JSON file of the wiring diagram, the visual topology diagram, the VF2 verification report, and the Neo4j graph database (corresponding to question 8).

[0230] In process S110, corresponding to problem 6, cross-page connectivity issues may arise due to multi-page diagrams / bus labels. Networks with the same name cannot be correctly merged on different pages / regions. The technical means of this invention: OCR-based network name / bus label parsing and Net-ID merging, supporting cross-page and cross-region network stitching. Technical effect: Generates globally consistent network identifiers, supporting connectivity queries for the entire drawing set.

[0231] Overall, the variable succession relationships in this embodiment are summarized (from upstream to downstream):

[0232] (Formula 1) → (Equation 2) → (Equation 4) → (Equation 5) → and → (Equation 6) → S and (Equation 7) → Nearest Neighbor Projection (Equation 14) → Match (Equation 15) → Assignment (Equation 16). Among them, IoU runs through the detection phase to ensure the high quality of the "device / terminal / text" box and provide reliable geometric and semantic candidates for subsequent processing.

[0233] The beneficial effects of the embodiments of the present invention are as follows:

[0234] This embodiment introduces key technologies such as port anchor point projection binding, symbol priority rules, text mask line filling, topology verification closed loop, knowledge base configuration, Neo4j structured data storage, pyramid enhancement, small target detection, synthetic data engine and lightweight inference in the corresponding steps to achieve end-to-end high-precision recognition of electrical wiring diagrams.

[0235] Example 2

[0236] based on Figure 2 This embodiment provides another drawing recognition method, including:

[0237] I. Preprocessing: From page-level geometric correction to pixel-level binary mask:

[0238] 1) Tilt Angle Estimation: First, accumulate straight lines in Hough space, and the direction of maximum response gives the dominant tilt angle of the page. This angle will be used for full-image rotation correction:

[0239] Equation (1) ;

[0240] 2) Rotation correction: obtained using equation (1) Construct a rotation matrix to uniformly map the original pixel coordinates x to the corrected coordinates x'—this serves as the common input for subsequent segmentation and geometric detection:

[0241] Equation (2) ;

[0242] 3) Local adaptive threshold: On the calibration map x', the local mean is calculated using a sliding window. and standard deviation This yields an adaptive threshold T(x,y) for each pixel. The threshold is not a constant but dynamically changes with local noise and brightness.

[0243] Equation (3) ;

[0244] 4) Binarization: The foreground mask is obtained by comparing the original image (or the corrected image after grayscale conversion) with a threshold. This mask can be directly used as a prior for geometric detection and semantic segmentation, and participates in connection fusion (Equation (6)) and skeleton refinement (Equation (7)):

[0245] Equation (4) .

[0246] II. Detection and Text: Suppression and Preparation of Box-Level Results:

[0247] In primitive / terminal / symbol detection, multiple candidate boxes from the detector need to be deduplicated using NMS, with the core criterion being the Intersection over Union (IoU). This ensures that only the most representative detection boxes are retained, and the results are passed to port matching (Equation (8)) and text association (Equation (9)).

[0248] Equation (5) ;

[0249] After being filtered by NMS, geometric entities such as “device frame, terminal frame, and text frame” will be spatially registered with the downstream wire mesh and skeleton (Equations (6) to (7)).

[0250] III. Line Blending: Complementarity of Pixel-Level Segmentation and Geometric Line Segments

[0251] To obtain a network that is both coherent and accurately positioned, a semantic segmentation mask is used. With geometric line segments The union of the two sets is used to denoise and fill gaps through morphological opening / closing operations, resulting in a fusion mask for skeletonization. :

[0252] Equation (6) ;

[0253] The rasterize(·) function rasterizes the line segment set to a pixel grid. Remove small noise and fill in small gaps.

[0254] IV. Skeleton and Nodes: From Fusion Masks to Topologically Descending Mesh Skeletons

[0255] right The data is then refined (e.g., Zhang–Suen / Guo–Hall) to obtain a one-pixel-wide skeleton S. Subsequently, pixel degrees are calculated on S in 8-neighborhoods to distinguish between "endpoints (degree = 1)" and "intersections (degree ≥ 3)," providing anchor points for port projection and topology mapping.

[0256] Equation (7) ;

[0257] The endpoints and intersections of the skeleton will serve as initial vertex candidates for graph G=(V,E), and together with the port anchors (Equation (8)), they will determine the final connection relationship.

[0258] V. Ports and Skeleton: Establishing the geometric constraints between ports and the mesh:

[0259] For each port anchor point u, perform nearest neighbor projection on the skeleton point set Γ; when the projection distance does not exceed the threshold d0, it is considered that the port has fallen on a certain skeleton line, thus establishing constraints with the subsequent connected components (Equation (10)):

[0260] Equation (8) ;

[0261] This process couples the "frame-level detection results" with the "pixel-level skeleton" to ensure the geometric consistency between the port and the net; if the distance exceeds d0, the system will mark it as uncertain and hand it over to the error correction stage for processing.

[0262] VI. Text Association: The Cost of Direction-First Matching and Cross-Page Merging:

[0263] For the identified text t (such as net name, terminal number), a direction-priority matching cost function C(t,o) is constructed between it and the candidate object o (device, port, line segment, or skeleton fragment) to balance spatial proximity and layout direction consistency; then, the minimum total cost matching is solved, and cross-page merging is performed on nets with the same name:

[0264] Equation (9) ;

[0265] In equation (9) above, d⊥ emphasizes the close relationship between the text and the object's normal direction, Δθ penalizes the inconsistent direction, and the γ term is used to avoid mistakenly associating device-level labels with port-level objects.

[0266] VII. Topology and Verification: Generate Net-IDs from connected components and form closed loops:

[0267] By combining the skeleton vertices (Equation (7)), port projections (Equation (8)), and intersection semantic determination (whether there is connectivity / crossing at the intersection), a graph G=(V,E) is constructed. Then, the graph is partitioned according to its connected components, and each vertex / port is assigned a unique network number Net(u):

[0268] Equation (10) ;

[0269] The obtained Net-ID will be combined with the text association (Equation (9)) to generate a structured output (device-port-line-node-network). To ensure project consistency, the system will then compare the template using graph matching (such as VF2). If a conflict occurs, the system will provide a "disconnect / reconnect / rename" suggestion and return to the aforementioned steps for minimal repair, forming a closed loop.

[0270] VIII. Overview of Variable Relationships (from upstream to downstream):

[0271] (Formula 1) → (Equation 2) → (Equation 3) → (Equation 4) → and (Equation 6) → S and (Equation 7) → Nearest Neighbor Projection (Equation 8) → Match (Equation 9) → Allocation (Equation 10).

[0272] Among them, the IoU of Equation (5) runs through the detection stage, ensuring the high quality of the "device / terminal / text" box and providing reliable geometric and semantic candidates for Equations (8)(9)(10).

[0273] The key technologies in this embodiment are as follows:

[0274] 1) Port anchor point - skeleton nearest neighbor projection binding method

[0275] Key point: Establish "port-net" association based on the minimum distance / projection from the port anchor point to the skeleton point set.

[0276] Effect: Enables port-level connectivity determination, significantly reducing false connections / missed connections.

[0277] 2) Unified cross-semantic judgment mechanism (multi-category detection of small black dots / overpasses + rule priority)

[0278] Key points: Treat "small black dots at the contact point" and "cross-line bridge" as detection categories, and use the symbol priority rule to determine whether the connection or disconnection is successful.

[0279] Effect: Achieve consistent and configurable conduction semantics at complex intersections, eliminating ambiguity.

[0280] 3) Connecting "dual-path fusion" with skeletonized production lines

[0281] Key points: Semantic segmentation mask ∪ geometric line segment (Hough / line segment detection) → Morphological repair → Skeleton refinement.

[0282] Results: Balances recall and positioning accuracy, and is more robust to stains / breakage.

[0283] 4) Text mask-driven shortest path completion

[0284] Key points: First, generate a text mask, then automatically bridge the lines obscured by the text within the mask area using the shortest path / endpoint.

[0285] Effect: Resolves broken lines and incorrect bridging caused by "text overlapping lines".

[0286] 5) Direction-oriented text-object matching cost function and cross-page same-name network merging

[0287] Key points: Construct a cost function that includes normal distance / direction consistency / hierarchy constraints to match text to devices / ports / lines; use a join lookup set for matching networks with the same name.

[0288] Results: Stable and accurate text association, achieving consistent network identification (Net-ID) across pages.

[0289] 6) Topology Construction and Net-ID Generation Methods

[0290] Key points: Construct a graph using endpoints / junctions / port hit points as vertices and skeleton segments as edges, and assign Net-IDs according to connected components.

[0291] Result: A netlist-level topology that can be directly used in engineering systems is obtained.

[0292] 7) VF2-based topology verification and "minimum repair suggestion" closed loop

[0293] Key points: Perform isomorphic / constraint matching on the subgraph and output the minimum patch for disconnection / connection / renaming.

[0294] Results: It forms an automatic verification and error correction closed loop, significantly improving end-to-end accuracy.

[0295] 8) Secondary verification of the geometric consistency of the small black dots at the contact points

[0296] Key points: The detected small black dots should be re-evaluated based on their roundness, diameter range, and degree of intersection with the skeleton.

[0297] Effect: Suppresses false nodes and improves the reliability of node detection.

[0298] 9) Unified data model and database interface (device—port—line—node—network)

[0299] Key points: Define standard JSON / SQL / graph database mappings and constraints.

[0300] Effect: Structured results can be directly retrieved, verified, traced, and integrated into the system.

[0301] 10) Small Goal Enhancement Strategy

[0302] Key points: High-resolution feature layers / dense pyramids, hard example mining, and data augmentation for terminal micro-targets.

[0303] Results: Significantly improved recall and location of terminals / micro-symbols.

[0304] 11) Synthetic Data Engine and Automatic Truth Topology Generation

[0305] Key points: The symbol library automatically generates multi-style drawings and corresponding truth topologies, and overlays scan / stain disturbances.

[0306] Results: Achieves transferable models under low-label conditions, enhancing cross-domain generalization.

[0307] 12) Lightweight and hierarchical inference (pruning / quantization / distillation + block parallelism / fast and slow paths)

[0308] Key takeaway: Optimize latency and throughput in edge / embedded scenarios.

[0309] Results: Achieve second-level response and high throughput while maintaining accuracy.

[0310] The beneficial technical effects that the core concept of this invention can produce.

[0311] 1) Port anchor point - skeleton nearest neighbor projection binding

[0312] Unlike existing technologies, existing methods mostly infer connectivity at the component / segment level, lacking geometric constraints at the port granularity.

[0313] Mechanism of action: The nearest neighbor projection of the port anchor point is performed on the skeleton point set and a radius threshold d0 is set to realize port-level Port→Net binding.

[0314] Direct technical benefits: Significantly improved port-level connectivity accuracy / recall, enabling direct generation of engineering netlists.

[0315] 2) Unified judgment of cross-semantic meaning (multi-category detection of small black dots / overpasses + rules)

[0316] Unlike existing technologies, traditional morphological or geometric methods struggle to reliably distinguish between "intersections" and "crossings".

[0317] Mechanism of action: "Connection black dot / cross-line bridge" is detected as an independent category, and the connection semantics are unified by the symbol priority rule.

[0318] Direct technical effects: Significantly reduced cross-ambiguity and decreased topology error rate.

[0319] 3) Connecting "dual-path fusion" + skeletonization

[0320] Unlike existing technologies: using only segmentation makes it easy for particles to stick together, and using only geometry makes it easy to miss detections.

[0321] Mechanism of action: (Segmentation) and (Geometric line segments) Take the union of the segments, perform opening / closing operations, and then skeletonize them.

[0322] Direct technical effect: Maintains high recall and good positioning even under network contamination / fracture.

[0323] 4) Text mask-driven shortest path completion

[0324] Unlike existing technologies, text overlay often leads to broken lines and incorrect bridging.

[0325] Mechanism of action: First, a text mask is generated, and then the shortest path / automatic bridging is performed within the mask area to restore the connection.

[0326] Direct technical benefits: Improved connection continuity and significantly reduced bridging errors.

[0327] 5) Direction-priority text-object matching and cross-page name merging

[0328] Unlike existing technologies, pure distance matching is prone to mistakenly associating device-level tags with ports or line segments.

[0329] Mechanism of action: Introduces a cost function that includes normal distance, directional consistency, and hierarchical constraints, and uses a disjoint-set union and a network of names.

[0330] Direct technical benefits: More robust text associations and consistent cross-page network identifiers.

[0331] 6) Topology construction + VF2 verification + minimum repair loop closure

[0332] Unlike existing technologies, it lacks a computable topology consistency check, making it difficult to locate and correct errors.

[0333] Mechanism of action: Graph is constructed with skeleton nodes / ports as points and skeleton segments as edges; VF2 / constraints are used to check the template, and the minimum repair value for breaks / connections / renaming is output.

[0334] Direct technical benefits: Improved end-to-end accuracy, traceability, and repairability.

[0335] The following is the verification process for the effectiveness of this solution:

[0336] Data: It is recommended to have at least 1,000 engineering wiring diagrams (scanned / electronic hybrid), divided into training / validation / test = 7 / 1 / 2; the test set should be labeled with truth netlists, cross semantics, port-net associations and text-bound truth values.

[0337] Indicator definition (formula)

[0338] (1) Precision / Recall / F1 of port-level connectivity dual (port pair):

[0339] Precision

[0340] Recall

[0341] F1

[0342] TP / FP / FN uses "whether the port pair is in the same network" as the criterion for judgment.

[0343] (2) Cross-semantic accuracy: For all cross-points, determine whether “conducting / non-conducting” is consistent with the true value.

[0344]

[0345] (3) Line continuity index: number of breaks per unit length.

[0346]

[0347] (4) Text association accuracy: The proportion of text that is correctly associated with objects (devices / ports / networks).

[0348]

[0349] (5) Topology integrity (net-level Jaccard) and exact match rate of the whole map netlist:

[0350]

[0351]

[0352] (6) Efficiency: throughput (pages / minute) and latency (seconds / page).

[0353] A. Comparison with typical baselines of existing technologies (detection only + geometric line segments):

[0354]

[0355] B. Ablation experiment (stepwise feature addition) — average of test set:

[0356] C. Efficiency and Resources (Single machine 16-core CPU + T4 GPU, batch processing 4 pages):

[0357]

[0358] Example 3

[0359] Secondly, such as Figure 10 As shown, this embodiment of the invention provides a wiring diagram recognition device based on deep learning, the device comprising:

[0360] The first identification module is used to correct and mask the initial wiring diagram to obtain the first wiring diagram, fusion mask parameters and mask skeleton parameters;

[0361] The second identification module is used to extract and classify the circuit elements in the first wiring diagram based on the fusion mask parameters and mask skeleton parameters, so as to obtain the first element set of the first wiring diagram.

[0362] The third identification module is used to perform port connection pairing and topology optimization on the first element set to determine the second element set and the corresponding second wiring diagram.

[0363] The fourth identification module is used to perform multi-dimensional verification and global topology structuring on the second wiring diagram based on the second element set to obtain a topology diagram data model;

[0364] The fifth identification module is used to determine the JSON file of the wiring diagram, the visual topology diagram, the VF2 verification report, and the Neo4j graph database based on the structured data in the topology diagram data model.

[0365] The wiring diagram recognition device based on deep learning provided in this application has the same implementation principle and technical effect as the aforementioned wiring diagram recognition method based on deep learning. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0366] Example 4

[0367] This application also provides an electronic device, see [link to relevant documentation] Figure 11 As shown, it includes a processor 100 and a memory 200. The memory 200 stores machine-executable instructions that can be executed by the processor. The processor executes the machine-executable instructions to implement the above-mentioned deep learning-based wiring diagram recognition method.

[0368] Furthermore, Figure 11 The electronic device shown also includes a bus 300 and a communication interface 400, with the processor 100, communication interface 400 and memory 200 connected via the bus 300.

[0369] The memory 200 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 400 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 300 may be an ISA bus, PCI bus, or EISA bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 11 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0370] The processor 100 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 100 or by instructions in software form. The processor 100 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams of the application in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method applied in conjunction with the embodiments of this application can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a readily available storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 200, and processor 100 reads information from memory 200 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0371] This application also provides a machine-readable storage medium storing machine-executable instructions. When these machine-executable instructions are called and executed by a processor, they cause the processor to implement the aforementioned deep learning-based wiring diagram recognition method. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0372] The computer program product of the wiring diagram recognition method, apparatus and electronic device based on deep learning provided in the embodiments of this application includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0373] If this function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, electronic device, or network device, etc.) to execute all or part of the steps of the methods in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0374] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A wiring diagram recognition method based on deep learning, characterized in that, The method includes: S102: Correct and mask the initial wiring diagram to obtain the first wiring diagram, fusion mask parameters and mask skeleton parameters; S104: Extract circuit elements from the first wiring diagram based on the fusion mask parameters and mask skeleton parameters, and classify them to obtain the first element set of the first wiring diagram; S106: Perform port connection pairing and topology optimization on the first element set to determine the second element set and the corresponding second wiring diagram; S108: Perform multi-dimensional verification and global topology structuring on the second wiring diagram based on the second element set to obtain the topology diagram data model; S110: Determine the JSON file of the wiring diagram, the visual topology diagram, the VF2 verification report, and the Neo4j graph database based on the structured data in the topology diagram data model.

2. The wiring diagram recognition method based on deep learning according to claim 1, characterized in that, S102 includes: S102-2: Determine the tilt angle of the initial wiring diagram; S102-4: Correct the initial wiring diagram according to the tilt angle to obtain the corrected wiring diagram; S102-6: Calculate the foreground mask parameters of the corrected wiring diagram, and determine the first wiring diagram based on the foreground mask parameters; S102-8: Perform connection fusion on the first wiring diagram to determine the fusion mask parameters; S102-10: Perform skeletonization processing on the first wiring diagram to determine the mask skeleton parameters.

3. The wiring diagram recognition method based on deep learning according to claim 2, characterized in that, S104 includes: S104-2: Perform segmentation and fusion processing on the first wiring diagram; S104-6: Extract and classify the circuit elements in the first wiring diagram after segmentation and fusion processing according to the YOLO algorithm, fusion mask parameters and mask skeleton parameters to obtain the first element set of the first wiring diagram; The first element set includes a device / symbol candidate set, a port candidate set, and a line segment / skeleton candidate set; the first element set includes: the center x-coordinate of the element, the center y-coordinate of the element, the width of the element frame, the height of the element frame, the element level, and the element confidence level.

4. The wiring diagram recognition method based on deep learning according to claim 3, characterized in that, S104-2 includes: S104-2-2: Based on the preset cutting size and cutting step, the first wiring diagram is cut into multiple overlapping small blocks; S104-2-4: Determine the intersection-union ratio between the target detection box within each overlapping block and the overlapping block; S104-2-6: Based on the intersection-union ratio, perform cross-block fusion on all target detection boxes.

5. The wiring diagram recognition method based on deep learning according to claim 4, characterized in that, S104 further includes: performing pyramid layering enhancement processing on the overlapping small blocks.

6. The wiring diagram recognition method based on deep learning according to claim 5, characterized in that, S106 includes: S106-2: Calculate the minimum distance from each element in the port candidate set in the first element set to each element in the line segment / skeleton candidate set; S106-4: Establish port connection pairing relationships based on the minimum distance; S106-6: Perform topology optimization processing on the elements in the candidate set of line segments / skeletons according to the port connection pairing relationship to determine the second element set; S106-8: Determine the second wiring diagram based on the second set of elements.

7. The wiring diagram recognition method based on deep learning according to claim 6, characterized in that, S108 includes: S108-2: Determine whether the topological connectivity, closed-loop connectivity, attribute consistency, and spatial constraints of the second wiring diagram are qualified; S108-4: If all are qualified, then extract the topology data model of the second wiring diagram based on the second element set.

8. A wiring diagram recognition device based on deep learning, characterized in that, The device includes: The first identification module is used to correct and mask the initial wiring diagram to obtain the first wiring diagram, fusion mask parameters and mask skeleton parameters; The second identification module is used to extract and classify the circuit elements in the first wiring diagram based on the fusion mask parameters and mask skeleton parameters, so as to obtain the first element set of the first wiring diagram. The third identification module is used to perform port connection pairing and topology optimization on the first element set to determine the second element set and the corresponding second wiring diagram. The fourth identification module is used to perform multi-dimensional verification and global topology structuring on the second wiring diagram based on the second element set to obtain a topology diagram data model; The fifth identification module is used to determine the JSON file of the wiring diagram, the visual topology diagram, the VF2 verification report, and the Neo4j graph database based on the structured data in the topology diagram data model.

9. An electronic device, characterized in that, The method includes a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the deep learning-based wiring diagram recognition method according to any one of claims 1-7.

10. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores machine-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the deep learning-based wiring diagram recognition method according to any one of claims 1-7.

Images