Partial updating method for display driving circuit

Abstract

The invention discloses a method for a display driving circuit, comprising the following steps: receiving an input frame from a main processor, the input frame having a plurality of segments; detecting an earliest horizontal sync start packet in the plurality of segments, where the earliest horizontal sync start packet indicates a start of an earliest segment of a full-refresh display area on an output frame; and updating the full-refresh display area on the output frame when the earliest horizontal synchronization start packet of the earliest segment of the full-refresh display area is detected.

Description

Technical Field

[0001] The present invention relates to a method for a display driving circuit, and more particularly to a method that can be used in a display driving circuit to achieve partial updates of image frames. Background Technology

[0002] The Mobile Industry Processor Interface (MIPI) specification incorporates a Video Hybrid Mode (VHM), which combines the advantages of both Video Mode and Command Mode. When using Video Hybrid Mode in conjunction with an external horizontal synchronization signal transmitted from the main processor to the Display Driver Integrated Circuit (DDIC), the MIPI transmission interface between the main processor and the DDIC can return to a stopped state (LP11) during periods when no image data is being transmitted to the DDIC.

[0003] The mobile industry processor interface specification further developed "Multi-Frequency Display (MFD) technology," which allows the display driver IC to partially refresh image frames when certain areas of image data do not require refresh. In video mixing modes combined with MFD applications, the main processor can transmit only the image data for the areas that need to be refreshed and return to the LP11 stop state during periods of no image data transmission. This approach requires the main processor to transmit a 2Bh instruction to the display driver IC on each image frame; this 2Bh instruction indicates the location of the area on the corresponding image frame that needs to be refreshed.

[0004] However, in some cases, the display driver IC may require the entire image frame to be fully refreshed and send a full refresh request to the main processor. The main processor should then modify the 2Bh instruction content based on this request. Furthermore, the main processor should carefully control the output timing of the 2Bh instruction to ensure that the display driver IC receives the information about the area to be refreshed carried by the 2Bh instruction completely before decoding the Vertical Synchronization Start (VSS) packet. In other words, the display driver IC must complete the decoding of the 2Bh instruction and obtain the relevant information before receiving the VSS packet of the corresponding image frame to avoid the speed-race problem caused by processing the 2Bh instruction only after decoding the VSS packet. This design increases the burden on the main processor, especially when the 2Bh instruction is generated based on the display driver IC's full refresh request. Summary of the Invention

[0005] Therefore, the main objective of this invention is to propose a novel method for use in display driver circuits to obtain partially refreshed information without using the 2Bh instruction.

[0006] An embodiment of the present invention discloses a method for a display driving circuit, the method comprising the following steps: receiving an input frame from a main processor, the input frame having a plurality of slices; detecting an earliest horizontal synchronization start (HSS) packet in the plurality of slices, wherein the earliest horizontal synchronization start packet indicates the start of the earliest slice of a full-flash display area on an output frame; and updating the full-flash display area on the output frame when the earliest horizontal synchronization start packet of the earliest slice of the full-flash display area is detected.

[0007] Another embodiment of the present invention discloses a method for a display driving circuit, the method comprising the following steps: receiving an input frame from a main processor, the input frame having a plurality of segments; detecting a transmission start packet and a transmission end packet, wherein the transmission start packet indicates the start of a full-scroll display area on the input frame, and the transmission end packet indicates the end of the full-scroll display area on the input frame; and updating the full-scroll display area on an output frame based on the transmission start packet and the transmission end packet.

[0008] Another embodiment of the present invention discloses a method for a display driving circuit, the method comprising the steps of: receiving an input frame from a main processor, the input frame having a plurality of segments; detecting the earliest valid data packet located after a horizontal synchronization start packet in the plurality of segments; and updating a full refresh display area on an output frame when the earliest valid data packet is detected.

[0009] Another embodiment of the present invention discloses a method for a display driving circuit, the method comprising the steps of: receiving an input frame from a main processor, the input frame having a plurality of segments; detecting an output signal transmitted by the main processor when the input frame is received; and updating a full refresh display area on an output frame according to the level of the output signal. Attached Figure Description

[0010] Figure 1 This is a timing diagram for a display operation.

[0011] Figure 2 This is a timing diagram for a display operation under multiple frequency displays.

[0012] Figure 3 This is a flowchart of the image transmission process according to Embodiment 1 of the present invention.

[0013] Figure 4 This is a timing diagram showing the operation of Embodiment 1 of the present invention.

[0014] Figure 5 This is a flowchart of another image transmission process according to an embodiment of the present invention.

[0015] Figure 6 This is a timing diagram showing the operation of Embodiment 1 of the present invention.

[0016] Figure 7 This is a flowchart of another image transmission process according to an embodiment of the present invention.

[0017] Figure 8 This is a timing diagram showing the operation of Embodiment 1 of the present invention.

[0018] Figure 9 This is a timing diagram of another display operation according to an embodiment of the present invention.

[0019] Figure 10 This is a flowchart of another image transmission process according to an embodiment of the present invention.

[0020] Figure 11 This is a timing diagram of a display operation using a general purpose output port, according to an embodiment of the present invention.

[0021] Figure 12 This is a schematic diagram of the display system according to Embodiment 1 of the present invention.

[0022] The reference numerals in the attached figures are explained as follows:

[0023] EXT_HS External Horizontal Synchronization Signal

[0024] INT_VS Internal Vertical Synchronization Signal

[0025] INT_HS Internal Horizontal Synchronization Signal

[0026] VSS Vertical Synchronization Start Packet

[0027] HSS Horizontal Synchronization Start Packet

[0028] DAT data packets

[0029] LP11 Stopped state

[0030] Image transmission process for 30, 50, 70, and 100 pixels.

[0031] 302~306, 502~506, 702~706, Steps

[0032] 1002~1006

[0033] DL delay time

[0034] SOT Transmission Start Packet

[0035] EOT End Transmission Packet

[0036] BLLP low power gap

[0037] 120 display system

[0038] 1200 main processor

[0039] 1202 Display Driver Circuit

[0040] 1204 display screen Detailed Implementation

[0041] Figure 1 This is a timing diagram of a display operation, illustrating the operation of a main processor transmitting a frame of image data and corresponding control signals to a display driver circuit (e.g., a display driver integrated circuit (DDIC)) through a transmission interface conforming to the Mobile Industry Processor Interface (MIPI) standard, specifically, Figure 1The diagram illustrates the transmission status of the MIPI transmission interface located between the main processor and the display driver circuit, an external horizontal synchronization signal EXT_HS received by the display driver circuit, an internal vertical synchronization signal INT_VS and an internal horizontal synchronization signal INT_HS used by the display driver circuit to control the display timing, as well as the display operation and the corresponding gate control operation.

[0042] In detail, when transmitting image data, the main processor can follow the Display Stream Compression (DSC) guidelines established by the Video Electronics Standards Association (VESA). According to the DSC guidelines, a frame of image data can be divided into multiple slices for compression. Each slice represents a block or region of image data after compression; that is, a slice can be considered the smallest unit of image data compression or the smallest unit of image data transmission. For example, such as... Figure 1 As shown, a frame of image data is divided into N segments, and the first to (N-1)th segments are transmitted sequentially. Each segment may include one or more Horizontal Synchronization Start (HSS) packets, where each HSS packet indicates the start of a line of image data, followed by the data packet DAT for that line.

[0043] like Figure 1 As shown, at the beginning of an image frame, the main processor can transmit a Vertical Synchronization Start (VSS) packet and a Horizontal Synchronization Start (HSS) packet. Then, the MIPI transmission interface, controlled by the main processor, enters a stop state (LP11) during the Vertical Back Porch (VBP) interval. Subsequently, during the active period of image data transmission, the main processor transmits the first to (N-1)th segments, each including a Horizontal Synchronization Start (HSS) packet and a Data Amount (DAT) packet. After the entire frame of image data has been transmitted, the MIPI transmission interface re-enters the LP11 state during the Vertical Front Porch (VFP) interval, until the start of the next frame.

[0044] To more precisely control the timing of image data transmission and reception, the main processor (or external device) can transmit an external horizontal sync signal EXT_HS to the display driver circuit via a dedicated physical wire. In one or more embodiments, the main processor transmits the external horizontal sync signal EXT_HS to the display driver circuit simultaneously (via the physical wire) while transmitting image data packets (through the data channel of the MIPI transmission interface). In other embodiments, when the main processor does not need to transmit image data, it can enter sleep mode to save power. In this mode, the display driver circuit can still receive the external horizontal sync signal EXT_HS from the main processor (or external device), even if the display driver circuit no longer receives the horizontal sync start packet HSS and data packet DAT through the MIPI transmission interface. Based on the received vertical sync start packet VSS and the external horizontal sync signal EXT_HS, the display driver circuit can generate an internal vertical sync signal INT_VS and an internal horizontal sync signal INT_HS to control the timing of the display data voltage output to the display screen. Figure 1 As shown, the internal vertical sync signal INT_VS is generated after a delay (i.e., internal delay) following the receipt of the vertical sync start packet VSS. Then, the display data voltages for the 1st to (N-1th)th segments are output to the display screen according to the timing determined by the internal vertical sync signal INT_VS and the internal horizontal sync signal INT_HS. Furthermore, during the display data voltage output, the gate control signal is enabled to appropriately control the data voltage received by the pixels on the display screen.

[0045] Figure 2 This is a timing diagram for a display operation under Multi-Frequency Display (MFD). In MFD operation, the main processor can transmit only a portion of the image data within an image frame. More specifically, a partially refreshed image frame can be divided into one or more full refresh display areas and one or more partial refresh display areas. The full refresh display area refers to the region where image data needs to be refreshed, while the partial refresh display area refers to the region where image data does not need to be refreshed. In the Video Hybrid Mode (VHM) of the MIPI transmission interface, the main processor can transmit only the image data of the full refresh display area, without transmitting the entire image frame's image data, while the image data transmission can still proceed according to the predetermined timing as in video mode.

[0046] For example, such as Figure 2 As shown, the timing of the main processor outputting image data within a single image frame can be compared with... Figure 1The timing configuration of the full-flash image frames shown is the same. For the full-flash display area, the main processor can still transmit image data to the display driver circuit at predetermined times (such as the 3rd to (N-3)th segments). For the partial-flash display area, the main processor can stop transmitting image data to the display driver circuit at predetermined times (such as the 1st, 2nd, (N-2nd), and (N-1st)th segments). During these time intervals when no image data is transmitted, the main processor can control the MIPI transmission interface to enter LP11 state to save power.

[0047] Since the image frame is not fully refreshed, the main processor may provide information about the range of the full-refresh display area and the partial-refresh display area. According to the mobile industry processor interface specification, the main processor can transmit a 2Bh instruction before the vertical synchronization start packet. The 2Bh instruction includes information indicating the start and end positions of the full-refresh display area. Based on this information, the display driver circuit can determine when to start updating image data (i.e., data voltage) and when to stop updating image data (i.e., data voltage). In other words, the display driver circuit can obtain the boundary or range of the full-refresh display area and transmit data voltage accordingly to refresh the pixels of the full-refresh display area on the display screen, while stopping the transmission of data voltage to other areas (i.e., the partial-refresh display area). Furthermore, the display driver circuit can also correspondingly control the gate circuit to start during the time interval used to refresh the full-refresh display area and remain off during the time interval corresponding to the partial-refresh display area.

[0048] It is worth noting that, Figure 2 Only one exemplary implementation is shown. In another embodiment, an image frame may also include multiple full-scan display areas; therefore, the main processor may send multiple 2Bh instructions to the display driver circuitry, each 2Bh instruction carrying start and end position information of one of the full-scan display areas. These 2Bh instructions may be sent at the vertical leading edge before the vertical synchronization start packet (VSS).

[0049] As mentioned above, the main processor should carefully control the output timing of the 2Bh instruction to avoid speed-race issues caused by the display driver circuit decoding the 2Bh instruction only after decoding the vertical synchronization start packet (VSS). This speed-race issue increases the design burden on the main processor. To solve this problem, this invention proposes a novel method for display driver circuits, enabling them to obtain information about the full-screen display area without relying on the 2Bh instruction. In other words, the main processor does not need to send the 2Bh instruction to the display driver circuit, and the display driver circuit can independently determine the start and / or end positions of the full-screen display area.

[0050] In one or more embodiments, the display driving circuitry can determine the extent of the full-screen display area by detecting the horizontal synchronization start packet of a segment. Figure 3 This is a flowchart of image transmission process 30 according to an embodiment of the present invention. Image transmission process 30 can be implemented in a display driving circuit (e.g., a display driving integrated circuit).

[0051] like Figure 3 As shown, the image transmission process 30 includes the following steps:

[0052] Step 302: Receive an input frame from a main processor, the input frame having multiple segments.

[0053] Step 304: Detect the earliest horizontal synchronization start packet among the plurality of segments, wherein the earliest horizontal synchronization start packet indicates the start of the earliest segment of a full-scroll display area on an output frame.

[0054] Step 306: When the earliest horizontal synchronization start packet of the earliest segment of the full-screen display area is detected,

[0055] Update the full refresh display area on this output frame.

[0056] According to image transmission process 30, the display driver circuit can receive an input frame from the main processor (step 302), wherein the input frame may include multiple segments, and each segment represents a unit of image data transmission. Within these segments, the display driver circuit can detect the earliest horizontal synchronization start packet in a full-fledged display area to determine the starting position of the full-fledged display area on the output frame (step 304), wherein the output frame refers to a frame of image data that the display driver circuit intends to output to the display screen. Then, when the display driver circuit detects the earliest horizontal synchronization start packet, it can update the image data within the full-fledged display area (step 306).

[0057] As described above, the valid image data segment transmitted by the main processor should include one or more Horizontal Synchronization Start Packets (HSS), followed by corresponding Data Packets (DAT). For example, such as... Figure 4 As shown, if a segment is allocated to the full refresh display area, the main processor can transmit the data packet DAT for that segment (such as the 2nd or 3rd segment), and the transmission of that segment will begin with a Horizontal Synchronization Start Packet (HSS). On the other hand, if a segment is allocated to the partial refresh display area, the main processor will not transmit the image data for that segment (such as the 1st or 4th segment). Therefore, during the time interval of that segment, the main processor will not transmit any image data or Horizontal Synchronization Start Packet (HSS), and the MIPI transmission interface can enter LP11 state.

[0058] In this case, the display driver circuit can detect the horizontal synchronization start packet in the segment to determine whether the segment is located in the full refresh display area or the partial refresh display area. In one embodiment, the display driver circuit detects the earliest horizontal synchronization start packet of the segment in the input frame to determine the start position of the full refresh display area and updates / refreshes the data voltage of the full refresh display area accordingly. Figure 4 In one embodiment, the display driver circuit can detect that the earliest horizontal synchronization start packet (HSS) appears in the second segment, and therefore will perform an update / refresh operation starting from the second segment of the output frame.

[0059] Next, the display driver circuit continuously detects the horizontal sync start packet and stops updating the data voltage when no horizontal sync start packet is detected in another segment. In other words, the first segment where no horizontal sync start packet is detected can be considered the starting position of a full-flash display area (i.e., the ending position of the previous full-flash display area). Figure 4 In one embodiment, the display driver circuit detects that the Horizontal Synchronization Start Packet (HSS) has not been received in the fourth segment, and therefore stops the update / refresh operation in the fourth segment of the output frame.

[0060] Within the time interval corresponding to the partial refresh display area where image refresh has not been performed, the display driver circuit can further detect the earliest horizontal synchronization start packet in subsequent segments to determine the starting position of the next full refresh display area. Therefore, the display driver circuit can determine whether each segment of the image frame is located in the partial refresh display area or the full refresh display area, thereby deciding whether to refresh the data for each segment.

[0061] Since the display driver circuit determines the start and / or end position of the full-flash display area based on the detection result of the horizontal synchronization start packet, it does not need to consider the paging address setting instruction (i.e., the 2Bh instruction, whose hexadecimal format is 0x2B) to decide whether to perform data update / refresh operations within the full-flash display area. In other words, the main processor does not need to send the paging address setting instruction to the display driver circuit to provide information about the full-flash display area, meaning it does not need to send the 2Bh instruction. At the display driver circuit end, the range of the full-flash display area can be identified by detecting the horizontal synchronization start packet, and data update / refresh operations can be performed accordingly, regardless of whether it receives the 2Bh instruction.

[0062] In addition, the display driver circuit can continuously detect the horizontal synchronization start packet in each segment throughout the entire frame to determine the range or position of each full-brush display area on the image frame. In this case, if there are multiple full-brush display areas, the main processor does not need to provide multiple 2Bh instructions, and the display driver circuit can identify the range of all full-brush display areas included in the image frame.

[0063] To ensure the display driver circuit has sufficient time to detect the horizontal synchronization start packet and determine whether each segment is located within the full refresh display area, the internal vertical synchronization signal INT_VS should have a relative capability to the external vertical synchronization signal (such as...). Figure 4 The delay time is sufficiently long for the received Vertical Synchronization Start Packet (VSS). In an exemplary embodiment, the delay time should be greater than or equal to a preset time length for each segment; that is, the delay time should be greater than or equal to the segment size (e.g., segment height). For example, such as Figure 4 As shown, the length of the delay time DL is greater than the size of a segment. In this case, although the image data is received according to the timing defined by the external synchronization signal, the update or refresh of the data voltage is based on the timing defined by the internal vertical synchronization signal INT_VS, which has a sufficient delay time DL for the display driver circuit to determine whether each subsequent segment needs to be updated / refreshed.

[0064] It is worth noting that the above-described operation of detecting the horizontal synchronization start packet is only one of many embodiments of the present invention. In another embodiment, the display driving circuit can detect a transmission start packet (such as...) Figure 6 The SOT packet in the middle) and a transmission end packet (such as Figure 6 The range of the full refresh display area is determined by the EOT packet in the image. Figure 5 This is a flowchart of another image transmission process 50 according to an embodiment of the present invention. The image transmission process 50 can be implemented in a display driving circuit (e.g., a display driving integrated circuit).

[0065] like Figure 5 As shown, the image transmission process 50 includes the following steps:

[0066] Step 502: Receive an input frame from a main processor, the input frame having multiple segments.

[0067] Step 504: Detect a transmission start packet and a transmission end packet, wherein the transmission start packet indicates the start of a full-screen display area on the input frame, and the transmission end packet indicates the end of the full-screen display area on the input frame.

[0068] Step 506: Update the full-scroll display area on an output frame based on the start and end transmission packets.

[0069] According to image transmission process 50, the display driver circuit can receive an input frame from the main processor (step 502), wherein the input frame may include multiple segments, and each segment represents a unit of image data transmission. The display driver circuit can also detect a transmission start packet and a transmission end packet, wherein the transmission start packet indicates the start of a full-fledged display area, and the transmission end packet indicates the end of a full-fledged display area (step 504). Then, the display driver circuit can update the image data in the full-fledged display area according to the transmission start packet and the transmission end packet (step 506). In other words, the display driver circuit starts updating a full-fledged display area to display data (segments) and continues to update until it receives a transmission end packet (e.g., ...). Figure 6 The data (fragments) are up to the EOT packet in the transmission, and these data (fragments) are in the transmission start packet (such as... Figure 6 After receiving the SOT packet (in the middle), the receiver will receive it.

[0070] It is worth noting that image data on the MIPI transmission interface is transmitted in high-speed mode, which is initiated by the Start of Transmission (SOT) procedure. In the SOT procedure, the host processor sends a start-of-transmission packet to initiate high-speed transmission. Similarly, when the MIPI transmission interface wants to exit high-speed mode, the host processor sends an end-of-transmission (EOT) packet.

[0071] exist Figure 6 In this embodiment, the first segment is allocated to the partial refresh display area, followed by the second and third segments allocated to the full refresh display area. Therefore, the main processor sends a Transmission Start Packet (SOT) at the beginning of the second segment to initiate high-speed transmission of the data packet DAT. Subsequently, the image processing program enters the partial refresh display area in the fourth segment, so the main processor sends a Transmission End Packet (EOT) at the end of the third segment, after which the MIPI transmission interface enters the LP11 state.

[0072] In this scenario, the display driver circuit can determine the start time of the full-flash display area by detecting the start packet (SOT) and the end time of the full-flash display area by detecting the end packet (EOT). Based on the detection results of the start packet (SOT) and end packet (EOT), the display driver circuit updates / refreshes the image data within the full-flash display area.

[0073] Similarly, since the display driver circuit can determine the start and / or end position of the full-flash display area based on the transmission start packet and / or transmission end packet, the display driver circuit can decide whether to perform data update / refresh operations within the full-flash display area without considering the paging address setting instruction. That is, the display driver circuit does not need to receive the 2Bh instruction from the main processor.

[0074] Furthermore, to ensure the display driver circuit has sufficient time to detect the start and end packets of transmission and determine whether each segment is located in the full refresh display area or the partial refresh display area, the internal vertical synchronization signal INT_VS should have a sufficiently long delay time relative to the external vertical synchronization signal. For example... Figure 6 As shown, the delay time DL between the external vertical synchronization signal (e.g., the received vertical synchronization start packet VSS) and the internal vertical synchronization signal INT_VS is greater than or equal to a segment size.

[0075] Figure 7 This is a flowchart of another image transmission process 70 according to an embodiment of the present invention. The image transmission process 70 can be implemented in a display driving circuit (e.g., a display driving integrated circuit). Figure 7 As shown, the image transmission process 70 includes the following steps:

[0076] Step 702: Receive an input frame from a main processor, the input frame having multiple segments.

[0077] Step 704: Detect the earliest valid data packet that is located after a horizontal synchronization start packet in multiple segments.

[0078] Step 706: When the earliest valid data packet is detected, update a full refresh display area on an output frame.

[0079] According to image transmission process 70, the display driver circuit can receive an input frame from the main processor (step 702), wherein the input frame may include multiple segments, and each segment represents a unit of image data transmission. Within these segments, the display driver circuit can determine the starting position of the full-flash display area by detecting the earliest valid data packet following the horizontal synchronization start packet (step 704). Then, when the display driver circuit detects a valid data packet, it can update the image data within the full-flash display area (step 706).

[0080] For example, within the time interval corresponding to the full-flash display area, the main processor can continuously transmit horizontal synchronization start packets and valid data packets. Therefore, in addition to determining the start time of the full-flash display area by detecting the horizontal synchronization start packet, the display driver circuit can also determine the start time of the full-flash display area by detecting valid data packets. Figure 8For example, in one embodiment, the display driver circuit can detect that the earliest valid data packet DAT appears in the second segment, and therefore will perform an update / refresh operation starting from the second segment of the output frame.

[0081] exist Figure 8 In this embodiment, when no image data is transmitted, the MIPI transmission interface does not enter the LP11 state; instead, the main processor continuously transmits the Horizontal Synchronization Start Packet (HSS) according to a predetermined timing sequence. In segments allocated to the full refresh display area, the Horizontal Synchronization Start Packet (HSS) is followed by the valid data packet (DAT); while in segments allocated to the partial refresh display area, the Horizontal Synchronization Start Packet (HSS) is followed by a Blanking or Low-Power (BLLP) period during which no valid data packet (DAT) is transmitted.

[0082] In this situation, since the Horizontal Synchronization Start Packet (HSS) appears simultaneously in both the full refresh display area and the partial refresh display area, the display driver circuit cannot determine the starting position of the full refresh display area by detecting the HSS. Instead, the display driver circuit should detect the valid data packet (DAT) and perform data update / refresh based on the detection result of the valid data packet (DAT).

[0083] Similarly, the display driver circuit can determine the end position of the full-refresh display area (i.e., the start position of the next partial-refresh display area) by detecting low-power blank periods. In this case, when the display driver circuit detects a low-power blank period, it can stop updating the data voltage within the partial-refresh display area. Figure 8 In one embodiment, the display driver circuit can detect that the low power blank period (BLLP) occurs in the fourth segment, and therefore will stop the update / refresh operation in the fourth segment of the output frame.

[0084] Similarly, since the display driver circuit can determine the start and / or end position of the full-flash display area based on the detection results of valid data packets and / or low-power blank periods, the display driver circuit can decide whether to perform data update / refresh operations within the full-flash display area without considering paging address setting instructions. In other words, the display driver circuit does not need to receive 2Bh instructions from the main processor.

[0085] Furthermore, to ensure the display driver circuit has sufficient time to detect valid data packets and low-power blank periods and determine whether each segment is located in the full refresh display area or the partial refresh display area, the internal vertical synchronization signal INT_VS should have a sufficiently long delay time relative to the external synchronization signal. For example... Figure 8 As shown, the delay time DL between the external vertical synchronization signal (e.g., the received vertical synchronization start packet VSS) and the internal vertical synchronization signal INT_VS is greater than or equal to a segment size.

[0086] Figure 9 This is a timing diagram for another display operation according to an embodiment of the present invention. In this example, the main processor still transmits the Horizontal Synchronization Start Packet (HSS) within the time interval corresponding to the partial refresh display area. After the transmission of the HSS, the MIPI transmission interface enters the LP11 state to save power. Specifically, the main processor transmits a Transmission Start Packet (SOT) to initiate the transmission of the HSS and a Transmission End Packet (EOT) to terminate the transmission of the HSS. In this case, the display driver circuit can determine the starting position of the full refresh display area by detecting valid data packets (DAT), similar to... Figure 8 The operation is illustrated. Furthermore, the display driver circuit can also determine the end position of the full-flash display area by detecting the End of Transmission (EOT) packet or the state of the MIPI transmission interface. In other words, when the display driver circuit detects an EOT packet in a segment or that the MIPI transmission interface is in a stopped state (such as LP11) for a certain period, it can stop updating the data voltage on the output frame.

[0087] It is worth noting that in the above embodiments, the display driver circuit detects the behavior of the MIPI transmission interface to determine the start position, end position, and / or range of the full-flash display area, and performs an update / refresh operation accordingly. In another embodiment, the display driver circuit can also determine the range of the full-flash display area by detecting another interface. Figure 10 This is a flowchart of another image transmission process 100 according to an embodiment of the present invention. The image transmission process 100 can be implemented in a display driving circuit (e.g., a display driving integrated circuit).

[0088] like Figure 10 As shown, the image transmission process 100 includes the following steps:

[0089] Step 1002: Receive an input frame from a main processor, the input frame having multiple segments.

[0090] Step 1004: When the input frame is received, detect an output signal transmitted by the main processor.

[0091] Step 1006: Update a full refresh display area on an output frame according to the level of the output signal.

[0092] According to image transmission process 100, the display driver circuit can receive an input frame from the main processor (step 1002), wherein the input frame may include multiple segments, and each segment represents a unit of image data transmission. When the display driver circuit receives the input frame, it can determine the range of the full-screen display area by detecting the output signal transmitted by the main processor (step 1004). Then, the display driver circuit can update the image data within the full-screen display area according to the detection result of the output signal (step 1006).

[0093] For example, in one or more embodiments, the display driver circuitry can communicate with the main processor via a General Purpose Output (GPO) port. Generally, the main processor can transmit an output signal via the GPO port to notify the display driver circuitry that the currently transmitted segment is located in the full refresh display area or the partial refresh display area.

[0094] Figure 11 This is a timing diagram illustrating a display operation utilizing a general purpose output port according to an embodiment of the present invention. In this example, the main processor can transmit a frame of image data to the display driver circuit via the MIPI transmission interface. Simultaneously with the transmission of image data, the main processor can also transmit an output signal to the display driver circuit via the general purpose output port. For the display driver circuit, the signal on the general purpose output port can be considered a flag signal. When the flag signal is "high," it indicates that the currently transmitted segment is located in the full refresh display area; when the flag signal is "low," it indicates that the currently transmitted segment is located in the partial refresh display area.

[0095] In this scenario, the display driver circuit can determine whether to perform an update / refresh operation based on the signal level on the general purpose output port. In this example, when the display driver circuit detects a "high level" signal on the general purpose output port, it can update the data voltage; when the display driver circuit detects a "low level" signal on the general purpose output port, it can stop updating the data voltage. Therefore, the display driver circuit can determine, in an appropriate manner, whether each segment is located in the full refresh display area or the partial refresh display area based on the signal on the general purpose output port, thereby performing an update / refresh operation on the image data within the full refresh display area and stopping the update / refresh operation within the partial refresh display area.

[0096] Similarly, since the display driver circuit can determine the range of the full refresh display area based on the detection of the general purpose output port, the display driver circuit can decide whether to perform data update / refresh operations within the full refresh display area without considering the paging address setting instruction. That is, the display driver circuit does not need to receive the 2Bh instruction from the main processor.

[0097] Furthermore, to ensure the display driver circuit has sufficient time to detect the signal level on the general purpose output port and determine whether each segment is located in the full refresh display area or the partial refresh display area, the internal vertical sync signal INT_VS should have a sufficiently long delay time relative to the external vertical sync signal. For example... Figure 11 As shown, the delay time DL between the external vertical synchronization signal (e.g., the received vertical synchronization start packet VSS) and the internal vertical synchronization signal INT_VS is greater than or equal to a segment size.

[0098] Figure 12 This is a schematic diagram of a display system 120 according to an embodiment of the present invention. The display system 120 includes a main processor 1200, a display driver circuit 1202, and a display screen 1204. The main processor 1200 may be the core processor of the display system 120, such as a central processing unit (CPU), application processor (AP), microcontroller unit (MCU), microprocessor, etc. Taking a smartphone or wearable device as an example, the main processor 1200 may be an application processor used to control the operation of various applications on the device. The display driver circuit 1202 may be an integrated circuit (i.e., a display driver integrated circuit) used to control the display operation of the display screen 1204. In one or more embodiments, the display driver circuit 1202 may receive image data from the main processor 1200 through a MIPI transmission interface. The display screen 1204 can be any type of display device, which may include, but is not limited to, a liquid crystal display (LCD) panel, a light-emitting diode (LED) panel, and an organic light-emitting diode (OLED) panel.

[0099] It is worth noting that the purpose of this invention is to propose a novel method for display driver circuits that can obtain partial screen refresh information without using the 2Bh instruction. Those skilled in the art can make modifications or variations accordingly, and are not limited thereto. For example, in the above embodiments, the display system can operate in video mode or video hybrid mode of the MIPI transmission interface with multi-frequency display operation. In this case, the main processor can transmit partial image data within an image frame according to the timing defined by the synchronization signal. It should be noted that the application of this invention is not limited to this. For example, the image data received by the display driver circuit from the main processor can be directly transmitted to the display screen, or it can be written to memory first. Furthermore, the main processor can use a multi-frequency display scheme when transmitting image data, or it can choose not to. In fact, as long as the display driver circuit can determine the start and / or end position of the full refresh display area without considering the 2Bh instruction or other paging address setting instructions, it should fall within the scope of this invention.

[0100] In addition, according to embodiments of the present invention, since the display driver circuit can independently determine the range of the full-screen display area, the main processor is allowed not to transmit the 2Bh instruction. In one or more embodiments, the main processor may stop transmitting the 2Bh instruction or other similar paging address setting instructions. Alternatively, the main processor may still transmit the 2Bh instruction through the MIPI transmission interface or other interfaces, but the display driver circuit may choose to ignore or discard the instruction.

[0101] It is also important to note that in this specification, the term "full refresh display area" refers to a display area that is refreshed in both full refresh and partial refresh image frames, while "partial refresh display area" refers to a display area that is not refreshed in partial refresh image frames. Generally, image frames can be refreshed in different ways depending on the multi-frequency display operation. In a series of image frames, there may be some full refresh image frames where all areas are refreshed, and there may be some partial refresh image frames where only some areas are refreshed. Therefore, to distinguish these areas, "full refresh display area" refers to the area that is refreshed in all image frames, including both full refresh and partial refresh image frames; "partial refresh display area" refers to the area that is refreshed only in full refresh image frames but not in partial refresh image frames. In this case, for partial refresh image frames, "full refresh display area" is the area where data is refreshed, while "partial refresh display area" is the area where data is not refreshed. Those skilled in the art should understand that the “full refresh display area” can also be called the “active area” or “refresh area”, while the “partial refresh display area” can also be called the “non-active area” or “non-refresh area”.

[0102] In summary, this invention proposes a method for a display driving circuit that can obtain information about the range of a full-refresh display area on an image frame without considering or receiving 2Bh instructions provided by the main processor. According to multi-frequency display operations, a full-refresh display area refers to the area where data is refreshed, while a partial-refresh display area refers to the area where data is not refreshed. In one embodiment, the display driving circuit can determine the starting position of the full-refresh display area by detecting the earliest horizontal synchronization start packet. In another embodiment, the display driving circuit can determine the starting and ending positions of the full-refresh display area by detecting the transmission start packet and transmission end packet, respectively. In one embodiment, the display driving circuit can determine the starting position of the full-refresh display area by detecting the earliest valid data packet after the horizontal synchronization start packet, and determine the ending position of the full-refresh display area by detecting a low-power blank period, a transmission end packet, or an LP11 state. In one embodiment, the display driving circuit can determine the range of the full-refresh display area by detecting the signal level on the general purpose output port. In this way, the display driver circuit can decide to perform data update / refresh operations in the full refresh display area and stop data update / refresh operations in the partial refresh display area, without the main processor needing to provide 2Bh instructions to the display driver circuit.

[0103] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for a display driving circuit, characterized in that, include: Receive an input frame from a main processor, the input frame having multiple segments; Detect the earliest horizontal synchronization start packet among the multiple segments, wherein the earliest horizontal synchronization start packet indicates the start of the earliest segment of a full-flash display area on an output frame; and When the earliest horizontal sync start packet of the earliest segment of the full-scroll display area is detected, the full-scroll display area on the output frame is updated.

2. The method as described in claim 1, characterized in that, The steps to update the full refresh display area on the output frame include: Without considering whether a page address setting instruction has been received, determine when to update the full refresh display area on the output frame.

3. The method as described in claim 1, characterized in that, Also includes: Receive an external vertical synchronization signal; and An internal vertical synchronization signal is generated by delaying the external vertical synchronization signal by a delay time; wherein the full refresh display area on the output frame is updated according to the timing defined by the internal vertical synchronization signal; The delay time is greater than or equal to a preset time length for each of the multiple segments.

4. The method as described in claim 1, characterized in that, Also includes: When no horizontal sync start packet is detected in another segment of a refresh display area on the output frame, update of that refresh display area stops.

5. A method for a display driving circuit, characterized in that, include: Receive an input frame from a main processor, the input frame having multiple segments; Detect a start-of-transmission packet and a stop-of-transmission packet, wherein the start-of-transmission packet indicates the start of a full-screen display area on the input frame, and the stop-of-transmission packet indicates the end of the full-screen display area on the input frame; and The full refresh display area on an output frame is updated based on the start packet and the end packet of the transmission.

6. The method as described in claim 5, characterized in that, The steps to update the full refresh display area on the output frame include: Without considering whether a page address setting instruction has been received, determine when to update the full refresh display area on the output frame.

7. The method as described in claim 5, characterized in that, Also includes: Receive an external vertical synchronization signal; as well as An internal vertical synchronization signal is generated by delaying the external vertical synchronization signal by a delay time; wherein the full refresh display area on the output frame is updated according to the timing defined by the internal vertical synchronization signal; The delay time is greater than or equal to a preset time length for each of the multiple segments.

8. The method as described in claim 5, characterized in that, The start time of the full-screen display area is determined by the transmission start packet, and the end time of the full-screen display area is determined by the transmission end packet.

9. A method for a display driving circuit, characterized in that, include: Receive an input frame from a main processor, the input frame having multiple segments; Detect the earliest valid data packet that follows a horizontal synchronization start packet in these multiple segments; as well as When the earliest valid data packet is detected, update a full refresh display area on an output frame.

10. The method as described in claim 9, characterized in that, The steps to update the full refresh display area on the output frame include: Without considering whether a page address setting instruction has been received, determine when to update the full refresh display area on the output frame.

11. The method as described in claim 9, characterized in that, Also includes: Receive an external vertical synchronization signal; and An internal vertical synchronization signal is generated by delaying the external vertical synchronization signal by a delay time; wherein the full refresh display area on the output frame is updated according to the timing defined by the internal vertical synchronization signal; The delay time is greater than or equal to a preset time length for each of the multiple segments.

12. The method as described in claim 9, characterized in that, Also includes: When a segment with a low-power blank period is detected among the multiple segments, the update of a refresh display area on that output frame is stopped.

13. The method as described in claim 9, characterized in that, Also includes: When a segment with a transmission end packet or a stop state is detected among the multiple segments, the update of a refresh display area on that output frame is stopped.

14. A method for a display driving circuit, characterized in that, include: Receive an input frame from a main processor, the input frame having multiple segments; When the input frame is received, an output signal transmitted by the main processor is detected; as well as The full refresh display area on an output frame is updated based on the level of the output signal.

15. The method as described in claim 14, characterized in that, The steps to update the full refresh display area on the output frame include: Without considering whether a page address setting instruction has been received, determine when to update the full refresh display area on the output frame.

16. The method as described in claim 14, characterized in that, Also includes: Receive an external vertical synchronization signal; and An internal vertical synchronization signal is generated by delaying the external vertical synchronization signal by a delay time; wherein the full refresh display area on the output frame is updated according to the timing defined by the internal vertical synchronization signal; The delay time is greater than or equal to a preset time length for each of the multiple segments.

17. The method as described in claim 14, characterized in that, Also includes: When the output signal is at a second level that is different from the first level, the update of a refresh display area on the output frame stops.

18. The method as described in claim 14, characterized in that, The output signal is received through a general purpose output port of the display driver circuit.

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