28V power supply surge suppression and power switch control circuit

Abstract

The invention provides a 28V power supply surge suppression and power switch control circuit, which belongs to the technical field of power supply control, and comprises a current sampling unit, an overvoltage protection unit, a power supply configuration unit, a control chip unit, a filtering unit, a driving unit and a power switch, the current sampling unit, the overvoltage protection unit and the power supply configuration unit are connected in parallel and then enter the control chip unit, the control chip unit controls the driving unit through the filtering unit for fault timing, and the driving unit controls the power switch unit. The circuit has the advantages of high integration and light weight, intelligent driving, multiple protection, surge suppression and state monitoring are integrated in a single compact circuit, an external huge and heavy TVS module is not needed, the size and weight of the circuit are remarkably reduced, and the circuit is particularly suitable for applications sensitive to space and weight, such as unmanned aerial vehicles.

Description

Technical Field

[0001] This invention belongs to the field of power control technology, specifically relating to a 28V power surge suppression and power switch control circuit. Background Technology

[0002] In drones, automotive electronics, and industrial equipment, 28V power systems are required to power inductive loads such as motor controllers and servo systems. These loads are highly susceptible to severe voltage surges, current surges, and back electromotive forces when starting, stopping, experiencing sudden changes, or being subjected to external interference (such as lightning strikes), posing a significant threat to the reliability and lifespan of the power system.

[0003] In existing technologies, dedicated chips such as LT4356 and TPS2492 are often used to construct power switching and protection circuits, but the following significant technical bottlenecks still exist: Functional separation and low integration: Surge suppression (usually relying on external TVS diodes or MOVs) is separated from intelligent power management functions, resulting in complex circuit structures and large size and weight, making it difficult to meet the high-density integration requirements of aerospace and other fields; Fixed drive and poor adaptability: The gate drive current is fixed, making it difficult to optimize and adapt to N-channel MOSFETs with different on-resistances (Rds(on)), limiting the optimization of switching performance and the range of device selection; Severe temperature drift and insufficient reliability: Under wide operating temperature ranges (especially low-temperature start-up at -55℃ and high-temperature operation at 125℃), the protection thresholds (such as overvoltage and undervoltage) of traditional circuits can drift by more than 10%, leading to malfunctions or failures of protection functions, and reliability is difficult to meet high standards; Crude diagnosis and difficult maintenance: Fault diagnosis output is usually only a simple on / off signal, which cannot distinguish specific types such as overcurrent, overvoltage, power over-limit, or thermal faults, which is not conducive to the rapid location of problems and maintenance of the system. Summary of the Invention

[0004] The purpose of this invention is to address the problems existing in the prior art by providing a 28V power supply surge suppression and power switching control circuit based on the HKA2610 intelligent gate controller. This solution deeply integrates surge suppression, precise power control, multi-state monitoring, and wide temperature adaptability, aiming to provide a highly reliable, highly integrated, and highly adaptable power front-end solution.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a 28V power supply surge suppression and power switch control circuit, the circuit comprising: a current sampling unit, an overvoltage protection unit, a power supply configuration unit, a control chip unit, a filtering unit, a drive unit, and a power switch. The current sampling unit, overvoltage protection unit, and power supply configuration unit are connected in parallel and then enter the control chip unit. The control chip unit controls the drive unit through the filter unit used for fault timing, and the drive unit controls the power switching unit.

[0006] The 28V power surge suppression and power switch control circuit provided by the present invention also has the following technical feature: the current sampling unit includes resistors R1 and R2 connected in parallel.

[0007] The 28V power surge suppression and power switch control circuit provided by this invention also has the following technical feature: the equivalent resistance R_SENSE of the current sampling unit is: .

[0008] The 28V power surge suppression and power switch control circuit provided by this invention also has the following technical feature: the overvoltage protection unit includes a Zener diode. The Zener diode's voltage regulation value is the clamping voltage of the circuit and the Vgs of the diode in the power switch.

[0009] The 28V power surge suppression and power switch control circuit provided by this invention also has the following technical feature: the power supply configuration unit includes: resistors R4, R5, R6, R10, and R11. The upper ends of resistors R4 and R5 are connected, the lower end of resistor R5 is connected to ground, the upper ends of resistor R6 and R10 are connected, the lower end of resistor R10 is connected to the upper end of resistor R11, resistor R11 is grounded, resistor R6 is connected to the input power supply, resistor R4 is connected to the control chip unit, and the lower end of R10 and the upper end of R11 are simultaneously connected to the control chip unit.

[0010] The 28V power surge suppression and power switch control circuit provided by this invention also has the following technical feature: the resistors in the power supply configuration unit conform to the following formula:

[0011] V ov To control the overvoltage value of the chip unit, V ov_H This is the overvoltage protection threshold.

[0012] The 28V power surge suppression and power switch control circuit provided by this invention also has the following technical feature: the control chip unit is a control chip packaged in an SOP14 package. Pin 1 of the control chip is electrically connected to the 28V control power supply node. Pins 2 and 3 are respectively connected to the two ends of R4. Pin 4 is connected to the filter unit. Pin 5 is electrically connected to the common node of resistors R10 and R11. Pin 6 is connected to the filter unit. Pin 7 is grounded. Pins 8 and 9 are respectively connected to the power supply through double pull-up resistors to realize power supply configuration. Pin 10 is empty. Pin 11 is connected to the power switch control unit and the power output. Pin 12 is connected to the drive unit and the overvoltage protection unit. Pin 13 is connected to the current sampling unit and the power switch unit. Pin 14 is connected to the power supply, the current sampling unit, and the power supply configuration unit.

[0013] The 28V power surge suppression and power switch control circuit provided by this invention also has the following technical feature: the filtering unit includes: resistor R7, capacitor C1, capacitor C2, and capacitor C3. One end of resistor R7 is connected to the control chip unit, and the other end is connected to capacitor C1. The lower end of capacitor C1 is grounded. Capacitors C2 and C3 are connected in parallel, with one end connected to the control chip unit and the other end grounded respectively.

[0014] The 28V power surge suppression and power switch control circuit provided by the present invention also has the following technical features: the driving unit includes a limiting driving resistor R3 for limiting the gate charging and discharging current; one end of the driving resistor R3 is connected to the control chip unit and the overvoltage protection unit, and the other end is connected to the power switch.

[0015] The 28V power surge suppression and power switch control circuit provided by the present invention also has the following technical features: the power switch includes an N-channel power MOSFET Q1, the drain of Q1 is connected to the power output node and the control chip unit, the source of Q1 is connected to the common node of the control chip unit and the current sampling unit, and the gate of Q1 is connected to the driving unit.

[0016] Beneficial effects: Compared with the prior art, the circuit provided by the present invention has the following significant advantages: 1. High integration and lightweight: Intelligent drive, multiple protections, surge suppression and condition monitoring are integrated into a single compact circuit, eliminating the need for a bulky external TVS module. The circuit size and weight are significantly reduced, making it especially suitable for space- and weight-sensitive applications such as drones.

[0017] 2. Comprehensive Protection and Precise Diagnosis: Provides multiple protections including overcurrent, overvoltage, undervoltage, power limiting, and fault timeout. With three independent outputs—PG (Power Good), FLT (Fault), and IMON (Analog Current)—it can accurately distinguish system status and fault type (overcurrent, continuous overpower, undervoltage, etc.) in real time, greatly facilitating system monitoring and maintenance.

[0018] 3. Excellent environmental adaptability: The core controller HKA2610 has a wide junction temperature operating range of -55℃ to 125℃. Key configuration resistors use low-temperature drift (e.g., ≤50ppm / ℃) components to ensure that all protection thresholds drift very little at extreme temperatures (e.g., overvoltage threshold temperature drift <1%), meeting the stringent reliability requirements of industrial and aerospace grades.

[0019] 4. Powerful drive and flexible adaptation: The GATE pin provides up to 125mA of pull-down drive capability, which can quickly turn off high-current MOSFETs and reduce turn-off losses. Through the PROG, TIMER, UVEN pins and simple external resistors and capacitors, key parameters such as power limits, fault delay, undervoltage / overvoltage thresholds can be flexibly programmed, easily adapting to loads and application scenarios with different voltage and current specifications.

[0020] 5. Advanced surge handling capability: The basic solution provides fast voltage spike clamping through a drain Zener diode; the optional enhancement solution uses a gate Zener diode and a MOSFET in linear operating mode to achieve active and smooth suppression of surges of longer duration (such as 60V / 100ms), providing a cleaner power supply for subsequent circuits. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a circuit schematic diagram of the circuit mentioned in the embodiments of the present invention; Figure 2 This is an internal functional block diagram of the HKA2610 smart gate controller mentioned in the embodiments of the present invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. However, it should be noted that these embodiments are not intended to limit the present invention. Equivalent changes or substitutions in function, method, or structure made by those skilled in the art based on these embodiments are all within the protection scope of the present invention.

[0024] In the description of the embodiments of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the invention.

[0025] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0026] The terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art will understand the specific meaning of these terms in this invention based on the specific circumstances.

[0027] like Figure 1-2 As shown in the figure, this embodiment of the invention provides a 28V power supply surge suppression and power switch control circuit. The circuit includes: a current sampling unit, an overvoltage protection unit, a power supply configuration unit, a control chip unit, a filtering unit, a drive unit, and a power switch. The current sampling unit, overvoltage protection unit, and power supply configuration unit are connected in parallel and then enter the control chip unit. The control chip unit controls the drive unit through the filter unit used for fault timing, and the drive unit controls the power switching unit.

[0028] In some embodiments, the current sampling unit includes resistors R1 and R2 connected in parallel.

[0029] In some embodiments, the equivalent resistance R_SENSE of the current sampling unit is: .

[0030] In some embodiments, the overvoltage protection unit includes a Zener diode. The Zener diode's voltage regulation value is the clamping voltage of the circuit and the Vgs of the diode in the power switch.

[0031] In some embodiments, the power supply configuration unit includes: resistors R4, R5, R6, R10, and R11. The upper ends of resistors R4 and R5 are connected, the lower end of resistor R5 is connected to ground, the upper ends of resistor R6 and R10 are connected, the lower end of resistor R10 is connected to the upper end of resistor R11, resistor R11 is grounded, resistor R6 is connected to the input power supply, resistor R4 is connected to the control chip unit, and the lower end of R10 and the upper end of R11 are simultaneously connected to the control chip unit.

[0032] In some embodiments, the resistors in the power supply configuration unit conform to the following formula:

[0033] V ov To control the overvoltage value of the chip unit, V ov_H This is the overvoltage protection threshold.

[0034] In some embodiments, the control chip unit is a control chip packaged in an SOP14 package. Pin 1 of the control chip is electrically connected to the 28V control power supply node. Pins 2 and 3 are respectively connected to the two ends of R4. Pin 4 is connected to the filter unit. Pin 5 is electrically connected to the common node of resistors R10 and R11. Pin 6 is connected to the filter unit. Pin 7 is grounded. Pins 8 and 9 are respectively connected to the power supply through double pull-up resistors to realize power supply configuration. Pin 10 is empty. Pin 11 is connected to the power switch control unit and the power output. Pin 12 is connected to the drive unit and the overvoltage protection unit. Pin 13 is connected to the current sampling unit and the power switch unit. Pin 14 is connected to the power supply, the current sampling unit, and the power supply configuration unit.

[0035] In some embodiments, the filtering unit includes: resistor R7, capacitor C1, capacitor C2, and capacitor C3. One end of resistor R7 is connected to the control chip unit, and the other end is connected to capacitor C1. The lower end of capacitor C1 is grounded. Capacitors C2 and C3 are connected in parallel, with one end connected to the control chip unit and the other end grounded respectively.

[0036] In some embodiments, C2 (1μF / 50V) and C3 (330nF / 50V) are connected in parallel between the TIMER pin (pin 4) of U1 and PGND. Together, they form the timing capacitor of the fault timer, and their capacitance value determines the time from protection activation to fault lockout. They also stabilize the voltage of the TIMER pin. The formula for calculating the fault timing time T_TIMEOUT is as follows (where I_CHARGE is the internal charging current of the chip, typically 27μA; V_TH is the threshold voltage, typically 4V):

[0037] In some embodiments, the driving unit includes a limiting driving resistor R3 for limiting the gate charging and discharging current. One end of the driving resistor R3 is connected to the control chip unit and the overvoltage protection unit, and the other end is connected to the power switch.

[0038] In some embodiments, the power switch includes an N-channel power MOSFET Q1, the drain of Q1 is connected to the power output node and the control chip unit, the source of Q1 is connected to the common node of the control chip unit and the current sampling unit, and the gate of Q1 is connected to the driving unit.

[0039] The component selection for the circuit provided in any of the foregoing embodiments is as follows: U1: HKA2610-PSA or HKA2610-PSL (select according to the operating temperature range), SOP14 package.

[0040] Q1: XNM180N10T3, 100V / 180A N-MOSFET, or an equivalent model with a valid SOA.

[0041] Z1: XNBZT52B43SP, 43V, 1W Zener diode.

[0042] R1, R2: 5mΩ, 1% accuracy, low-temperature drift alloy sampling resistors.

[0043] R3: 10Ω, 0805 package, 1 / 8W.

[0044] R4: 47kΩ; R5: 150kΩ; R6: 0Ω; R10: 470kΩ; R11: 10kΩ. All are 1% precision, low temperature drift metal film resistors at 50ppm / ℃.

[0045] R8, R9: 10kΩ, pull-up resistors.

[0046] C1: 10nF, 100V, X7R ceramic capacitor.

[0047] C2: 1μF, 50V, X7R ceramic capacitor.

[0048] C3: 330nF, 50V, X7R ceramic capacitor.

[0049] Z1 (for enhanced surge suppression): XNBZT52B43SP, cathode connected to GATE pin, anode connected to PGND.

[0050] The operation of the circuit provided in any of the foregoing embodiments is as follows: Power-on and startup: The 28V control power supply (28V_DR) powers on, supplying power to the VCC pin of U1. U1 internally performs power-on reset (POR, approximately 6V) and undervoltage lockout (UVLO, approximately 8V) checks. After passing these checks, if the UVEN pin voltage is higher than its turn-on threshold (typically 1.35V), the chip starts up.

[0051] Power path turned on: The GATE pin of U1 starts to output drive voltage, which drives the gate of Q1 through R3. Q1 turns on, and the 28V main power supply can supply power to the load.

[0052] Real-time monitoring: During operation, U1 continuously monitors the voltage drop across sampling resistors R1 / R2 (VCC - V_SENSE) via the SENSE pin, thereby obtaining real-time load current. Simultaneously, it monitors the drain-source voltage Vds of Q1 via the OUT pin. Internally, the chip dynamically calculates the maximum allowable current based on Vds and a preset power limit (set via the PROG pin).

[0053] Protective actions: Overcurrent / Overpower: If the load current exceeds the 20A limit or the instantaneous power consumption exceeds the set power limit, U1 will immediately adjust the GATE pin voltage to bring Q1 into the linear region, limiting the current or power to a safe value. At the same time, the TIMER pin will start charging C2 / C3 at a current of 27μA.

[0054] Overvoltage: If the input voltage drops, causing the voltage on the OV pin to exceed its turn-off threshold, U1 will pull down the GATE pin to turn off Q1.

[0055] Voltage spike: When Q1 is turned off or encounters an external surge, the drain voltage rises. When it exceeds 43V, Zener diode Z1 breaks down and conducts, clamping the voltage and protecting Q1.

[0056] Fault Lockout: If the overcurrent or overpower condition persists, the voltage on C2 / C3 will reach 4V after approximately 197ms. U1 is determined to be in a persistent fault, triggering fault latch: the GATE output is forcibly shut down (pull-down Q1), and the FLT pin is pulled low. The system is locked in this protection state until reset by cycling the UVEN pin voltage or by power-on.

[0057] Status indication: When Q1 is fully turned on and its Vds is below approximately 1.25V for 9ms, the PG pin is internally pulled low, indicating "power is normal", which can be used to enable the downstream DC-DC converter.

[0058] When a fault latch occurs, the FLT pin is pulled low to indicate a "system fault".

[0059] The IMON pin continuously outputs a voltage signal (V_IMON) that is proportional to the load current, which can be sampled by the microcontroller's ADC to achieve digital monitoring of the current.

[0060] Enhanced surge suppression mode With the Zener diode Z1 soldered on, the circuit exhibits enhanced surge withstand capability. When faced with an input surge of 60V / 100ms: The voltage of the GATE pin of U1 is limited to approximately 43V by Z1.

[0061] As a source follower, Q1's source output voltage Vout is limited to approximately 41V (assuming Vgs(th) = 2V).

[0062] At this point, the voltage drop across Q1 is Vds = 60V - 41V = 19V. If the load current is 20A, then the instantaneous power consumption of Q1 is 380W.

[0063] This energy is dissipated as heat in Q1 within 100ms. During the design phase, it is essential to ensure that the allowable current in Q1's single-pulse safe operating area (SOA) at the coordinate point (Vds=19V, t=100ms) is greater than 20A, and to verify that its instantaneous temperature rise is within a safe range.

[0064] This mode transforms dangerous input high-voltage surges into a controlled, linearly regulated process with lower output voltage, providing extremely stable power supply for subsequent circuits.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention. The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the protection scope of the present invention.

Claims

1. A 28V power surge suppression and power switch control circuit, characterized in that, The circuit includes: a current sampling unit, an overvoltage protection unit, a power supply configuration unit, a control chip unit, a filtering unit, a drive unit, and a power switch. The current sampling unit, overvoltage protection unit, and power supply configuration unit are connected in parallel and then enter the control chip unit. The control chip unit controls the drive unit through the filter unit used for fault timing, and the drive unit controls the power switching unit.

2. The 28V power surge suppression and power switch control circuit according to claim 1, characterized in that, The current sampling unit includes resistors R1 and R2 connected in parallel.

3. The 28V power surge suppression and power switch control circuit according to claim 2, characterized in that, The equivalent resistance R_SENSE of the current sampling unit is: 。 4. The 28V power surge suppression and power switch control circuit according to claim 1, characterized in that, The overvoltage protection unit includes a Zener diode. The Zener diode's voltage regulation value is the clamping voltage of the circuit and the Vgs of the diode in the power switch.

5. The 28V power surge suppression and power switch control circuit according to claim 1, characterized in that, The power supply configuration unit includes: resistors R4, R5, R6, R10, and R11. The upper ends of resistors R4 and R5 are connected, the lower end of resistor R5 is connected to ground, the upper ends of resistor R6 and R10 are connected, the lower end of resistor R10 is connected to the upper end of resistor R11, resistor R11 is grounded, resistor R6 is connected to the input power supply, resistor R4 is connected to the control chip unit, and the lower end of R10 and the upper end of R11 are simultaneously connected to the control chip unit.

6. The 28V power surge suppression and power switch control circuit according to claim 5, characterized in that, The resistance in the power supply configuration unit conforms to the following formula: V ov To control the overvoltage value of the chip unit, V ov_H This is the overvoltage protection threshold.

7. The 28V power surge suppression and power switch control circuit according to claim 5, characterized in that, The control chip unit is a control chip packaged in SOP14. Pin 1 of the control chip is electrically connected to the 28V control power supply node. Pins 2 and 3 are respectively connected to the two ends of R4. Pin 4 is connected to the filter unit. Pin 5 is electrically connected to the common node of resistors R10 and R11. Pin 6 is connected to the filter unit. Pin 7 is grounded. Pins 8 and 9 are respectively connected to the power supply through double pull-up resistors to realize power supply configuration. Pin 10 is empty. Pin 11 is connected to the power switch control unit and the power output. Pin 12 is connected to the drive unit and the overvoltage protection unit. Pin 13 is connected to the current sampling unit and the power switch unit. Pin 14 is connected to the power supply, the current sampling unit, and the power supply configuration unit.

8. The 28V power surge suppression and power switch control circuit according to claim 1, characterized in that, The filtering unit includes: resistor R7, capacitor C1, capacitor C2, and capacitor C3. One end of resistor R7 is connected to the control chip unit, and the other end is connected to capacitor C1. The lower end of capacitor C1 is grounded. Capacitors C2 and C3 are connected in parallel, with one end connected to the control chip unit and the other end grounded respectively.

9. The 28V power surge suppression and power switch control circuit according to claim 1, characterized in that, The driving unit includes a limiting driving resistor R3 for limiting the gate charging and discharging current. One end of the driving resistor R3 is connected to the control chip unit and the overvoltage protection unit, and the other end is connected to the power switch.

10. The 28V power surge suppression and power switch control circuit according to claim 1, characterized in that, The power switch includes an N-channel power MOSFET Q1. The drain of Q1 is connected to the power output node and the control chip unit, the source of Q1 is connected to the common node of the control chip unit and the current sampling unit, and the gate of Q1 is connected to the driving unit.

Images