High-side on-time control circuits and methods for asymmetric half-bridge power converters

Abstract

Circuits and methods of the present disclosure control an effective off time (high side switch on time) to ensure that in each switching cycle, magnetization energy release and resonant capacitor energy release in an asymmetric half-bridge (AHB) converter are completed at the same time, and all stored energy is delivered to the output. Various parallel techniques to control high side switch on times are illustrated. One is to track volt-seconds applied during the storage cycle and allow the effective release off time to be limited to the same volt-seconds. The second option is to provide a high-side switch on-time proportional to the on-time of the low-side switch in the switching cycle. A third option is to provide a maximum high-side switching on-time that can be programmed to ensure that the high-side on-time is equal to or less than half of the resonance period.

Description

[0001] Cross Reference to Related Applications This application claims the benefit of U.S. Provisional Application No. 63 / 703,463, filed October 4, 2024, the entirety of which is incorporated by reference herein. TECHNICAL FIELD

[0002] The present disclosure relates generally to power converters, and more particularly, to control circuits and methods for controlling an asymmetrical half bridge power converter. BACKGROUND

[0003] Asymmetrical capacitively coupled resonant flyback converters (AHB) have significant advantages over more typical flyback converters at high output voltages and output power. AHB converters combine energy storage in the magnetization of the transformer and in a capacitor that is part of a resonant tank, which can be referred to as a storage cycle. When the storage cycle is ended, energy from the magnetization of the transformer and energy stored in the resonant capacitor are released to the power converter output. The energy in the resonant capacitor forms a resonant release cycle with the leakage inductance of the transformer.

[0004] Ideally, at maximum output voltage and power, the magnetization energy release and the resonant capacitor energy release are completed simultaneously, and all stored energy is delivered to the output. However, in real world operation at maximum output voltage, the magnetization will complete early and begin to cycle energy back to the primary side of the power converter. This is inefficient, and can cause the output to collapse at lighter loads.

[0005] Typical control methods for AHB power converters are complex, and include burst mode operation at lighter output loads, further increasing complexity and reducing performance. SUMMARY

[0006] Typical control methods for asymmetrical half bridge (AHB) power converters, such as burst mode operation, are complex, and result in recognized shortcomings in such designs. The present disclosure provides embodiments of control circuits and methods for controlling the on-time of the high side switch in an asymmetrical half bridge power converter that overcome the shortcomings of other control methods.

[0007] An AHB converter includes a high side switch coupled to the positive rail of the input voltage and a low side switch coupled to the input return of the AHB converter. Energy storage cycles in the AHB converter occur when the low side switch is on, and energy release occurs when the low side switch is off.

[0008] The circuit and method of the present disclosure controls the active off-time (time the high-side switch is on) to ensure the magnetization energy release and the resonant capacitor energy release in the AHB converter are completed at the same time in each switching cycle and all stored energy is delivered to the output.

[0009] For example, if the AHB converter is designed for an adjustable wide range output, at lower output voltage settings, the magnetization release will take longer than the resonant release period. In this case, the high-side switch on-time is set to be the same as the resonant period so that the magnetization release has enough time to deliver all stored energy to the output, instead of to the resonant capacitor.

[0010] The circuit and method of the present disclosure can provide multiple parallel techniques to control the high-side switch on-time. One option as described herein is to track the volt-seconds applied during the storage cycle and allow the active release off-time to be limited to the same volt-seconds. This is done by integrating the signal representing the primary side winding voltage to determine the high-side switch on-time.

[0011] A second option as described herein for controlling the high-side switch on-time is to provide a high-side switch on-time that is proportional to the on-time of the low-side switch in that switching cycle. A third option as described herein for controlling the high-side switch on-time is to provide a maximum high-side switch on-time that can be programmed to ensure the high-side on-time is equal to or less than half of the resonant period. The resonance is due to the transformer leakage inductance and the resonant capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0012] Non-limiting and non-exhaustive embodiments of controlling the secondary switches to achieve zero voltage switching are described with reference to the following drawings, wherein like reference numerals refer to like parts throughout the various views.

[0013] Figure 1 An example asymmetric half-bridge (AHB) power converter is illustrated that includes a primary controller implementing example high-side on-time control circuit and method in accordance with the teachings of the present disclosure.

[0014] Figure 2 Example waveforms associated with operation of the AHB power converter 100 of Figure 1

[0015] Figure 3 A functional block diagram of an example primary controller implementing an example high-side on-time control circuit in accordance with the teachings of the present disclosure is illustrated.

[0016] Figure 4 ​A simplified diagram of an example volt-sec on-time block of an example high-side control block according to the teachings of this disclosure is illustrated.

[0017] Figure 5 A simplified diagram of an example proportional on-time block of an example high-side on-time control circuit according to the teachings of this disclosure is illustrated.

[0018] Figure 6 A simplified diagram of an example maximum high-side on-time block of an example high-side on-time control circuit according to the teachings of this disclosure is illustrated.

[0019] Figure 7 A more detailed circuit diagram of an example volt-sec high-side on-time block of an example high-side on-time control circuit according to the teachings of this disclosure is illustrated.

[0020] Figure 8 A more detailed circuit diagram of an example proportional high-side on-time block of an example high-side on-time control circuit according to the teachings of this disclosure is illustrated.

[0021] Figure 9 A more detailed circuit diagram of an example maximum high-side on-time block of an example high-side on-time control circuit according to the teachings of this disclosure is illustrated.

[0022] Figure 10 A flow diagram illustrating an example method for controlling a high-side switch on-time using volt-sec calculations for use in an asymmetric half-bridge power converter according to the teachings of this disclosure is illustrated.

[0023] Figure 11 A flow diagram illustrating another example method for controlling a high-side switch on-time in an AHB power converter according to the teachings of this disclosure is illustrated.

[0024] Figure 12A A volt-sec on-time circuit according to an embodiment of the disclosure is illustrated.

[0025] Figure 12B A waveform according to an embodiment of the disclosure is illustrated. Figure 12A

[0026] Figure 12C A buffer circuit according to an embodiment of the disclosure is illustrated.

[0027] Figure 12D A trigger circuit according to an embodiment of the disclosure is illustrated.

[0028] Figure 13A A waveform according to an embodiment of the disclosure is illustrated.

[0029] ​Figure 13B A waveform is illustrated in accordance with another embodiment of the disclosure.

[0030] Figure 14 A trigger circuit is illustrated in accordance with another embodiment of the disclosure.

[0031] Figure 15 A waveform is illustrated in accordance with Figure 14 an embodiment of the disclosure.

[0032] Figure 16 A trigger circuit is illustrated in accordance with Figure 14 another embodiment of the disclosure.

[0033] Figure 17 A waveform is illustrated in accordance with Figure 16 an embodiment of the disclosure.

[0034] In all of the several views of the drawings, corresponding reference characters indicate corresponding parts throughout the several views. Skilled artisans will appreciate that the elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements to help improve the understanding of various embodiments of the teachings herein. Also, common but well-understood elements that are useful in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments controlling secondary switches to achieve zero voltage switching. DETAILED DESCRIPTION

[0035] Figure 1 An example AHB power converter 100 in accordance with the teachings of the disclosure is shown. The AHB power converter 100 includes an input voltage source V IN 101. The input voltage source V IN 101 can be from a rectified AC input or an input that is substantially DC. An input capacitor C IN 102 is coupled between the positive terminal of V IN 101 and a primary ground 107.

[0036] The AHB power converter 100 includes a power transformer T1 having a primary winding 104, a secondary winding 105, and an auxiliary winding 106. A resonant capacitor C R 103 is coupled between the input capacitor C IN 102 and the primary winding 104. Opposite ends of the primary winding 104 are coupled to a half-bridge node HB 120. During operation, a primary side current I P 110 flows through the primary winding 104 as will be discussed in greater detail below.

[0037] The AHB power converter 100 includes a primary controller 150. In one embodiment, the primary controller 150 can be implemented in circuitry packaged in a single integrated circuit package. In other embodiments, the primary controller 150 can be implemented in circuitry packaged in multiple packages. The primary controller 150 includes a high-side switch 151 and a low-side switch 153. In some embodiments, either or both of the switches 151 and 153 can be within the same integrated circuit package as the control circuitry, or can be packaged separately from the control circuitry.

[0038] The high-side switch 151 and the low-side switch 153 are high-voltage transistor switches, and in one embodiment can be transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), high-electron-mobility transistors (HEMTs), gallium-nitride (GaN)-based transistors, or silicon-carbide (SiC)-based transistors. In another embodiment, the high-side and / or low-side switches can be cascode switches, including a normally-on first switch and a normally-off second switch coupled together in a cascode configuration. The first switch can typically be a GaN- or SiC-based transistor, while the second switch can be a MOSFET, BJT, or IGBT.

[0039] The primary controller 150 includes a high-side driver 152 that generates appropriate output signals to drive the high-side switch 151 on and off. The primary controller 150 also includes a low-side driver 154 that generates appropriate output signals to drive the low-side switch 153 on and off. IN 101. The drain terminal D 162 of the high-side switch 151 is coupled to the drain terminal D 162, while the source terminal S 163 of the low-side switch 153 is coupled to the primary ground 107. The drain of the high-side switch 151 is coupled to the drain terminal D 162, while the source of the low-side switch 153 is coupled to the source terminal. The source of the high-side switch 151 and the drain of the low-side switch 153 are coupled together and to the half-bridge node HB 120, which is coupled as an input to the primary controller 150.

[0040] The primary controller 150 includes a high-side driver 152 that generates appropriate output signals to drive the high-side switch 151 on and off. The primary controller 150 also includes a low-side driver 154 that generates appropriate output signals to drive the low-side switch 153 on and off.

[0041] The primary controller 150 also includes a primary control block 155 that generates control signals to instruct the high-side driver 152 and the low-side driver 154 to turn on / off the high-side switch 151 and the low-side switch 153, respectively, as will be discussed in more detail below. The primary controller 150 includes a communication path 157 for communicating the control signals from the primary control block 155 to the high-side driver 152.

[0042] The AHB power converter 100 includes a capacitor C LBias172, for providing a bias power source to the primary control block 155 and the low side driver 154 of the primary controller 150. The AHB power converter 100 includes a capacitor C HBias 173, for providing a bias power source to the high side driver 152 of the primary controller 150. A diode 174 is coupled between the auxiliary winding 106 and the capacitor C HBIAS 173 to provide a current source to maintain the voltage on the capacitor C HBIAS 173.

[0043] The primary control block 155 includes an input AUX 130 for receiving a signal representative of the voltage on the auxiliary winding 106 through a resistor 175. The primary control block 155 also includes an input FL 160 for receiving a signal from the secondary side of the AHB power converter 100 and for controlling the low side switch 153, as will be discussed in more detail below.

[0044] The primary control block 155 also includes an input I SNS 156 for receiving a signal representative of the current flowing through the low side switch 153 and for controlling the low side switch 153, as will be discussed in more detail below. The primary control block 155 also includes an input HMX 161 for receiving the voltage on the resistor R HMX 171 for setting the maximum on-time of the high side switch 151, as will be discussed in more detail below.

[0045] The AHB power converter 100 also includes an output capacitor C O 181 coupled in parallel to the secondary winding 105. In operation, a secondary current I S 180 flows through the secondary winding 105 and creates an output voltage V O 182 on the output capacitor C O 181. An output current I O 183 is supplied to a load 185 coupled to the output capacitor C O 181 and a secondary ground 190.

[0046] The AHB power converter 100 includes a synchronous rectifier 186 that includes a transistor 188 and a diode 187. The diode 187 can be the intrinsic diode of the transistor 188 or a separate component. In other embodiments, the AHB power converter can include only a diode, rather than the synchronous rectifier 186.

[0047] The AHB power converter 100 includes a sensing circuit 191 configured to sense the output quantity U O 184 and generate an output sense signal U O 184. U OS 192. UO 184 can indicate the output voltage V O 182, the output current I O 183, or a combination of both. The AHB power converter 100 also includes a secondary controller 196. The secondary controller 196 includes a secondary control block 193 that is configured to receive an output sense signal U OS 192 and generate a synchronous rectifier control signal U SR 134 and a request signal U REQ 194.

[0048] The primary controller 150 and the secondary controller 196 can be collectively referred to as the control system of the AHB power converter 100.

[0049] The request signal U REQ 194 is a signal that represents the energy required by the load 185. In one embodiment, the request signal U REQ 194 can represent a signal that is communicated to the primary controller 150 to request that additional power be transferred from the input of the AHB power converter 100 to the output. In one embodiment, the request signal U REQ 194 can be transferred from the secondary control block 193 through a transfer mechanism that provides galvanic isolation between the input and the output of the AHB power converter 100. In one embodiment, the request signal U REQ 194 can be transferred through a FluxLink TM component, which is available from Power Integrations, Inc.

[0050] The secondary controller 196 includes a receiver 195 that is referenced to the primary ground 107 and is configured to receive the request signal U REQ 194 and generate a signal to couple to the FL input 160 of the primary controller 150 in response to the request signal U REQ 194. The output sense signal U OS 192, the request signal U REQ 194, and the signal at the FL input 160 can all be referred to as "feedback" signals because they all provide information about the output for use on the primary side of the AHB power converter.

[0051] In one embodiment, the secondary controller 196 can be implemented in a single integrated circuit package. In other embodiments, components of the secondary controller 196 can be implemented in multiple packages.

[0052] Figure 2 Waveforms of signals within the converter during a portion of one complete switching cycle and a subsequent cycle of the AHB power converter 100 are illustrated. AsFigure 2 As shown in the image, the waveform sharing represents the x-axis over time.

[0053] Waveform 210 represents the primary-side current IP 110 of the AHB power converter 100 over time. Waveform 220 represents the voltage at the half-bridge node HB 120 of the AHB power converter 100 over time. Waveform 230 represents the voltage of the auxiliary winding 106 sensed at the AUX input 130 of the primary controller 150 over time. Waveform 240 represents the magnetizing current in the transformer T1 of the AHB power converter 100 over time.

[0054] Waveforms 225 and 257 represent control signals generated by the primary control block 155 over time, which control the switching of the low-side switch 153 and the high-side switch 151 of the AHB power converter 100.

[0055] Tracing from left to right Figure 2 The waveform shows that at time 211, the low-side switch control signal 225 transitions from low to high, thereby indicating that the low-side switch 153 is turned on. Although in this embodiment the turn-on control signal 225 is indicated to transition from low to high, as those skilled in the art will understand, the control signal logic can also be reversed. At time 211, the turning on of the low-side switch 153 causes VHB 220 and VAUX 230 to go low, while the primary-side current IP 210 and the magnetizing current 240 in the primary winding 104 begin to rise. These currents will continue to increase during the duration during which the low-side switch 153 is on.

[0056] At time 212, the low-side switch control signal 225 transitions from high to low, thereby indicating that the low-side switch 153 is turned off. In response to the low-side switch 153 turning off, VAUX 230 and VHB 220 begin to rise at time 212. Also at time 212, the waveforms of the magnetizing current 240 and the primary-side current IP 210 begin to decline.

[0057] At time 213, the high-side switch control signal 257 transitions from low to high, thereby indicating that the high-side switch 151 is turned on. Although in this embodiment the turn-on control signal 257 is indicated to transition from low to high, as those skilled in the art will understand, the control signal logic can also be reversed.

[0058] A dead time is maintained between time 212 when the low-side switch 153 is turned off and time 213 when the high-side switch 151 is turned on. This dead time is maintained to ensure that the conduction of the low-side switch 153 and the high-side switch 151 does not overlap, thereby preventing potential cross-conduction. In one embodiment, the dead time between the turn-off of the low-side switch 153 and the turn-on of the high-side switch 151 may be a fixed time period. In other embodiments, the dead time may be adaptive and dependent on the operating conditions within the AHB power converter 100.

[0059] At time 213, the closing of the high-side switch 151 causes the voltages VHB 220 and VAUX 230 to be clamped to their maximum values. In one embodiment, the maximum value of VHB 220 can be in the range between 100 and 420 volts. In one embodiment, the maximum value of VAUX 230 can be in the range between 5 and 70 volts.

[0060] At time 214, the high-side switch control signal 257 transitions from high to low, thereby indicating that the high-side switch 151 is turned off. Figure 2 In the embodiment shown, at time 214, the waveforms of the magnetizing current 240 and the primary-side current 210 are close to or at zero, thereby indicating that energy delivery has been completed within the switching cycle.

[0061] The conduction time of the high-side switch 151 will be explained in more detail below (in Figure 2 In the embodiment, the time between time 213 and time 214 is controlled by the primary controller 150 in such a way that the high-side switch 151 is kept on for a sufficient time so that the magnetization release has enough time to deliver substantially all the stored energy to the output of the AHB power converter.

[0062] Between times 214 and 215, the voltage waveforms VHB 220 and VAUX 230 will drop and then resonate sinusoidally with a frequency and magnitude determined by the Coss of the low-side switch 153 and the high-side switch 151, as well as the magnetizing inductance of the primary winding 104 of transformer T1. Similarly, the magnetizing current waveform 240 and the primary current waveform 210 will also vary sinusoidally around zero. Due to relaxation ringing, a resonant current travels through the magnetizing inductance of the primary winding 104 of transformer T1.

[0063] At time 215, the low-side switch control signal 225 transitions from low to high again and begins the next switching cycle, which repeats in a similar manner to that previously discussed.

[0064] Figure 3 An example primary controller 350 is shown, which corresponds to Figure 1The primary controller 150 of the embodiment shown in FIG. 1. As Figure 3 As shown in FIG. 3, an example primary controller 350 is implemented in a single integrated circuit package with several terminals configured to be coupled to the rest of the components of the AHB power converter. In other embodiments, the components of the primary controller 350 can be implemented in multiple packages.

[0065] The primary controller 350 includes a high-side switch 351 and associated high-side driver 352 as well as a low-side switch 353 and associated low-side driver 354. In some embodiments, the high-side switch 351 and / or the low-side switch 353 can be packaged in the same integrated circuit package as the control circuitry, while in other embodiments they can be packaged separately. The primary controller 350 has a drain terminal D(HS) 362 for coupling the drain of the high-side switch 351 to the input voltage. The primary controller also has a source terminal S(LS) 363 for coupling the source of the low-side switch 353 to a ground reference. The primary controller 350 has a terminal HB 320 for coupling the source of the high-side switch 351 and the drain of the low-side switch 353 to the half-bridge node of the AHB power converter.

[0066] The primary controller 350 has a terminal FL 360 that is configured to receive a signal from the secondary side of the AHB power converter to control switching of the low-side switch 353. In one embodiment, the signal received at terminal FL can be a request signal that indicates a request to transfer additional power from the input of the AHB power converter 100 to the output.

[0067] The primary controller 350 has a terminal AUX 330 that is configured to receive a signal that represents the voltage on the auxiliary winding of the AHB power converter. The primary controller 350 also has a terminal HMX 361 that is configured to receive a signal for programming the maximum on-time of the high-side switch 351.

[0068] While not shown, the primary controller 350 will also have input terminals for receiving operating bias sources for the low-side components and input terminals for receiving operating bias sources for the high-side components, as will be appreciated by those skilled in the art. Other terminals for implementing other features and functions can also be implemented in various embodiments of the primary controller 350 consistent with the teachings of the present disclosure.

[0069] The primary controller 350 includes a primary control block 355 that corresponds to Figure 1 The primary control block 155 of the embodiment shown in FIG. 1. The primary control block 355 includes a DCM detection block 321, a low-side control block 322, and a high-side control block 365.

[0070] The DCM detection block 321 is configured to receive a signal (V HB ) representing the voltage at the half-bridge node HB 320 of the AHB power converter. The DCM detection block 321 is configured to detect discontinuous conduction mode operation in the AHB power converter. The DCM detection block 321 is further configured to implement a dead-time period between switching of the high-side and low-side switches to ensure that the two switches are never on at the same time in order to prevent potential cross-conduction in the AHB power converter.

[0071] The low-side control block 322 is configured to receive a signal from the secondary side of the AHB power converter through terminal FL 360. In one embodiment, the signal at terminal FL can comprise a series of pulses arriving at a variable frequency, where each received pulse indicates that a switching cycle should be initiated. In other embodiments, the signal can take other forms to represent the state of the output load of the power converter.

[0072] The low-side control block 322 receives the signal at terminal FL 360 and the output of the DCM detection block 321 and generates a low-side switch control signal 325a to control operation of the low-side switch 353. The low-side switch control signal 325a is input to the low-side driver 354, which responsively generates an appropriate drive signal at the gate of the low-side switch 353 to control turn-on and turn-off of the low-side switch 353.

[0073] In some embodiments, the low-side control block 322 is configured to receive an I SNS signal 356 representing the current through the low-side switch 353. In some embodiments, when the current through the low-side switch 353 reaches a current threshold, the low-side control block 322 will respond to the I SNS signal 356 to turn off the low-side switch 353. As will be appreciated by those skilled in the art, other methods for controlling the on-time of the low-side switch 353 consistent with the teachings of the present disclosure can be implemented.

[0074] The low-side control block 322 also outputs a copy 325b of the low-side switch control signal as an input to the high-side control block 365. As will be appreciated by those skilled in the art, the control signal 325b can be the same signal as 325a, routed to multiple destinations. In the disclosed embodiment, the low-side switch control signal 325b is a logic level voltage in a first state when the low-side switch 353 is on (conducting current), and in a second state when the low-side switch 353 is off (not conducting any substantial current). In other embodiments, the low-side switch control signal 325b can represent the operation of the low-side switch 353 in other analog, logic, or digital forms.

[0075] The example high-side control block 365 implements three functional blocks for controlling the on-time of the high-side switch 351. In other embodiments, not all three functional blocks need be implemented, but the functional blocks can be implemented individually or in various combinations consistent with the teachings of the present disclosure.

[0076] The volt-second on-time block 335 is configured to receive the low-side switch control signal 325b and a signal at terminal AUX 330 that is representative of the voltage on the auxiliary winding of the AHB power converter. As will be discussed in greater detail below, the volt-second on-time block 335 uses the signal from terminal AUX 330 to generate an output signal to control the high-side switch on-time to implement volt-second balancing operation in the AHB power converter.

[0077] The proportional on-time block 340 is configured to receive the low-side switch control signal 325b and generate an output signal to control the high-side switch on-time to be proportional to the on-time of the low-side switch 353 in each switching cycle, as will be explained in greater detail below.

[0078] The maximum on-time block 345 is configured to receive the low-side switch control signal 325b and a signal at terminal HMX 361 that is an input signal to allow programming of the maximum high-side switch on-time, as will be explained in greater detail below.

[0079] In the example high-side control block 365, the output of the volt-second on-time block 335 and the output of the proportional on-time block 340 are coupled to an OR gate 327. The output of the OR gate 327 is coupled with the output of the maximum on-time block 345 to an AND gate 328. In Figure 3 In the example high-side control block 365, the output of the volt-second on-time block 335 and the output of the proportional on-time block 340 are coupled to an OR gate 327. The output of the OR gate 327 is coupled with the output of the maximum on-time block 345 to an AND gate 328. In

[0080] As explained with respect to Figure 2 but not shown in the Figure 3 example high-side control block 365, circuitry to implement a dead-time between the turn-off of the low-side switch 353 and the turn-on of the high-side switch 351 can be included in the primary control block 355.

[0081] In the example high-side control block 365, the output of the volt-second on-time block 335 and the output of the proportional on-time block 340 are coupled to an OR gate 327. The output of the OR gate 327 is coupled with the output of the maximum on-time block 345 to an AND gate 328. In

[0082] Furthermore, if either of the maximum on-time block 345 or the OR gate 327 output transitions low, the output of the AND gate 328 will transition low, commanding the high-side switch 351 to turn off. In other words, if the output of the maximum on-time block 345 indicates that the maximum on-time has expired, the high-side switch 351 will be commanded to turn off regardless of the state of the output of either the volt- second on-time block 335 or the proportional on-time block 340.

[0083] Although the example high-side control block 365 implements particular logic for combining the outputs of its various sub-blocks, other example combinations consistent with the teachings of the present disclosure are possible as will be appreciated by those skilled in the art. In some embodiments, the maximum on-time, proportional on-time, and volt-second on-time combination implementations can provide more robust operation over a wide range of potential operating conditions of the AHB power converter.

[0084] The output of the AND gate 328 is input to a high-side link block 329. This block provides the necessary level shifting for communicating the high-side control signal over the communication path 357. The high-side control signal will control the turn-on and turn-off of the high-side switch 351. Because the high-side switch 351 will reference a different voltage domain than the low-side switch 353 (i.e., will be coupled between the high voltage input of the AHB power converter and the half-bridge node), the control signal from the primary controller to the high-side switch can be level shifted accordingly.

[0085] The high-side link block 329 also communicates with the DCM detection block 321 to ensure proper dead-time between the switching of the low-side switch 353 and the switching of the high-side switch 351. DCM detection begins after the volt-second balance is reached in each switching cycle. After DCM detection is complete, the low-side is allowed to turn on.

[0086] The primary controller 350 includes a HS (high-side) receiver and driver logic block 358 configured to receive the high-side control signal over the communication path 357. The HS receiver and driver logic block 358 receives the high-side control signal and responsively generates a signal to the high-side driver 352 for controlling the operation of the high-side switch 351. Although not shown, the HS receiver and driver logic block 358 can incorporate other inputs to implement additional features and functionality. For example, the HS receiver and driver logic block 358 can be configured to receive a signal to sense temperature and / or to sense the high-side bias voltage and implement a fault management mode in response thereto. As will be appreciated by those skilled in the art, the HS receiver and driver logic block 358 can implement other example features and functionality consistent with the teachings of the present disclosure.

[0087] Figure 4 A simplified circuit diagram of an example volt-second on-time block 435 is shown, which corresponds to Figure 3The example primary controller 350 includes a volt-second on-time block 335. The volt-second on-time block 435 includes features for providing charging current I. C The first current source 401, the first switch 403, and the capacitor 405 together constitute the first integrator 431.

[0088] The first current source 401 is configured to receive signal V. LSON 430a, this signal indicates the primary winding (such as, for example) Figure 1 The voltage on the auxiliary winding 106 shown. In one embodiment, V LSON From such Figure 1 The signal at AUX input 130 shown is obtained. V LSON 430a represents the voltage on the primary winding when the low-side switch is on. Charging current I C Will with V LSON 430a is proportional.

[0089] The volt-second on-time block 435 also includes a method for providing discharge current I. DIS The second current source 402 and the second switch 404, together with the capacitor 405, constitute the second integrator 432.

[0090] The second current source 402 is configured to receive signal V. HSON 430b, this signal indicates the primary winding (such as, for example) Figure 1 The voltage on the auxiliary winding 106 shown. In one embodiment, V HSON From such Figure 1 The signal at AUX input 130 shown is obtained. V HSON 430b indicates the voltage on the primary winding when the high-side switch is on. Discharge current I DIS Will with V HSON 430b is proportional.

[0091] The volt-second on-time block 435 also includes a comparator 406, which is configured to compare the voltage across capacitor 405 with a reference voltage V. REF1 411 is compared. Although Figure 4 The embodiment illustrates comparator 406 as a voltage comparator, but as those skilled in the art will understand, other embodiments of comparators, analog and / or digital, consistent with the teachings of this disclosure can be used. Capacitor 405 is coupled to the non-inverting input of comparator 406, while the reference voltage V... REF1 411 is coupled to the inverting input of comparator 406. Reference voltage V REF1411 is a small offset from ground, so when capacitor 405 is reset, the comparator 406 output will be a logic 0. V REF1 The offset of 411 helps provide stability in the operation of the comparator 405.

[0092] The volt-second on-time block 435 also includes a third switch 409 configured to reset the voltage on the capacitor 405 at each switching cycle. The volt-second on-time block 435 also includes an inverter 407 and a reset circuit 408 coupled between the output of the comparator 406 and the third switch 409. The reset circuit 408 is configured to implement a reset pulse between a change in the state of the output of the comparator 406 and the switching of the third switch 409, thereby implementing a reset of the capacitor 405.

[0093] The output of the comparator 406 is also coupled to one input of an AND gate 412. The volt-second on-time block 435 also includes an input for receiving a low-side (LS) switch control signal 425b, which represents the timing of the turn-on and turn-off of the low-side switch of the AHB power converter, such as, for example, the low-side switch 353 of the example primary controller 350. Figure 3 The LS switch control signal 425b is coupled to control the first switch 403 such that the first switch 403 is on when the low-side switch is on and the first switch 403 is off when the low-side switch is off. The LS switch control signal 425b is also coupled to an inverter 413. The output of the inverter 413 is coupled to a second input of the AND gate 412. The output of the AND gate 412 is the HS switch on-time signal and is coupled to control the second switch 404 and is also coupled as an output of the volt-second on-time block 435.

[0094] The waveform 420 illustrates the voltage on the capacitor 405 during an example switching cycle, as will be explained in more detail below.

[0095] In an example switching cycle of the AHB power converter, the volt-second on-time block 435 can operate as follows. At the beginning of the switching cycle, the LS switch control signal 425b changes state (e.g., from low to high as in the illustrated embodiment), indicating that the low-side switch has turned on. When the LS switch control signal 425b is at a high value, the output of the AND gate 412 is at a low value.

[0096] The first switch 403 is configured to turn on in response to the LS switch control signal 425b, and the capacitor 405 is configured to begin charging. The rate at which the capacitor 405 charges depends on the value of V LSON 430a. During the on-time of the low-side switch, the voltage on the capacitor 405 will rise as illustrated by the waveform 420. The voltage on the capacitor 405 will be greater than the reference voltage V REF1411, and the output of the comparator 406 is a high value.

[0097] At the end of the low-side switch on-time, the LS switch control signal 425b changes state (e.g., from high to low as in the illustrated embodiment), and the first switch 403 is configured to turn off in response, which stops the charging of the capacitor 405. After the LS switch control signal 425b transitions, indicating the end of the low-side switch on-time, the output of the AND gate 412 transitions high, indicating the start of the high-side switch on-time. The output of the AND gate 412 going high turns on the second switch 404. As explained previously in the discussion of Figure 2 The dead-time between the end of the low-side switch on-time and the start of the high-side switch on-time can be implemented as explained previously in the discussion of

[0098] When the second switch 404 is turned on, the second current source 402 discharges the capacitor 405. The rate at which the capacitor 405 discharges depends on the value of V HSON 430a. During the on-time of the high-side switch, the voltage on the capacitor 405 will drop as illustrated in the waveform 420. When the voltage on the capacitor 405 drops below the threshold set by V REF1 411, the output of the comparator 406 will change state (e.g., from high to low as in the illustrated embodiment), and thus the output of the AND gate 412 will also go low. The output of the AND gate 412 is output from the volt-second on-time block 435 to control the turn-off of the high-side switch.

[0099] When the output of the AND gate 412 changes state, the second switch 404 will be turned off. Also, when the output of the comparator 406 changes state (e.g., from high to low in the illustrated embodiment), the third switch 409 will be turned on after a reset implemented by the reset circuit 408, resetting the voltage on the capacitor 405 and preparing the volt-second on-time block 435 for the next switching cycle.

[0100] Although Figure 4 A specific embodiment for controlling the first integrator 431 and the second integrator 432 and for the logic of the input signal and the output signal is illustrated, but as will be appreciated by one of skill in the art, other configurations consistent with the teachings of the present disclosure are possible. And although Figure 4 A specific example circuit structure for integrating the value of the input signal over time is illustrated, but as will be appreciated by one of skill in the art, other structures— analog and / or digital— consistent with the teachings of the present disclosure are possible.

[0101] Figure 5 A simplified circuit diagram of an example proportional on-time block 540 is shown, which in one embodiment can correspond toFigure 3 Example primary controller 350, block 340. Example proportional on-time block 540 and... Figure 4 The volt-second on-time block 435 is essentially the same and operates in essentially the same way, but has at least the differences discussed below.

[0102] In the proportional conduction time block 540, the input to the first current source 501 is the first reference voltage V. REF2 530a, and the input to the second current source 502 is the second reference voltage K * V. REF2 530b. Therefore, the proportional on-time block 540 is configured to control the on-time of the high-side switch 151 to be proportional to the on-time of the low-side switch 153 based on the scaling factor K rather than in response to the sensed auxiliary winding voltage.

[0103] In the proportional on-time block 540, the first integrator 531 is configured to adjust V during the on-time of the low-side switch. REF2 The value of 530a is integrated. The second integrator 532 will integrate K * V during the on-time of the high-side switch 151. REF2 The value of 530b is integrated. When these integrated values ​​are substantially equal to each other, the output of comparator 506 will change state and indicate that the high-side switch should be turned off.

[0104] The detailed operation tracking of the proportional on-time block 540 is as described above. Figure 4 The operation of the volt-second on-time block 435 is explained. In one embodiment, the value of K can be equal to 1, thereby controlling the on-time of the high-side switch to be substantially the same as the on-time of the low-side switch. In other embodiments, other values ​​of K are possible.

[0105] Ideally, the value of K is equal to 1. Due to potential mismatches in the charging and discharging circuits, in some embodiments, the value of K can be 0.95, 1.05, or some other value close to 1 to compensate for noise or mismatches in the circuit implementation. In some embodiments, the value of K can be a fine-tunable or programmable parameter.

[0106] Figure 6 A simplified circuit diagram of an example maximum on-time block 645 is shown. In one embodiment, this maximum on-time block may correspond to... Figure 3 Example primary controller 350, block 345. Maximum on-time block 645 includes a reference current I. REF The reference current source 601, capacitor 605, and comparator 606 together constitute a timer. The maximum on-time block 645 also includes a reference voltage V input to the comparator 606. REF4 611. Reference voltage VREF4 611 is coupled to a non-inverting input of the comparator 606, while the capacitor 605 is coupled to an inverting input of the comparator 606.

[0107] The maximum on-time block 645 also includes a terminal HMX 661 configured to be coupled to an external resistor R HMX 671 for programming the duration of the maximum high-side switch on-time. The terminal HMX 661 can correspond to Figure 1 the terminal HMX 161 of the embodiment illustrated in FIG. 1 1, and the resistor R HMX 671 can correspond to Figure 1 the resistor R HMX 171.

[0108] The maximum on-time block 645 also includes a switch 609 for resetting the voltage on the capacitor 605 during each switching cycle. The maximum on-time block 645 also includes an input for receiving a LS switch control signal 625b, which is representative of the timing of the turn-on and turn-off of a low-side switch of the AHB power converter, such as, for example, the low-side switch 353 of the example primary controller 350 of Figure 3 FIG. 1 1. The LS switch control signal 625b is also one example of the LS switch control signal 325b discussed with respect to Figure 3 FIG. 1 1. The LS switch control signal 625b is coupled to control the switch 609 such that the switch 609 is on when the low-side switch 153 is on, and the switch 609 is off when the low-side switch 153 is off.

[0109] The inverter 613 is coupled to receive the LS switch control signal, and the output of the inverter 613 is coupled to one input of the AND gate 612. The output of the comparator 606 is coupled to a second input of the AND gate 612, and the output of the AND gate 612 is coupled to provide the high-side switch maximum on-time signal as an output of the maximum on-time block 645.

[0110] In an example switching cycle of the AHB power converter, the maximum on-time block 645 can operate as follows. At the beginning of the switching cycle, the LS switch control signal 625b will change state (e.g., from low to high as in the illustrated embodiment), indicating that the low-side switch 151 has turned on. The switch 609 is turned on in response to the LS switch control signal 625b, resetting the voltage on the capacitor 605 to a low state, and resetting the output of the comparator 606 to a high state. In the illustrated embodiment, the voltage on the capacitor 605 is reset to the primary ground. While the LS switch control signal 625b is in the high state, the output of the inverter 613 is in the low state, and the output of the AND gate 612 is also low.

[0111] At the end of the low-side switch on-time, the LS switch control signal 625b changes state (e.g., from high to low as in the illustrated embodiment), indicating that the low-side switch 153 has turned off. The switch 609 is turned off in response to the LS switch control signal 625b, allowing the current source 601 to charge the capacitor 605. While the LS switch control signal 625b is in the low state, the output of the inverter 613 is high. The output of the AND gate 612 transitions to the high state, indicating the start of the maximum high-side on-time.

[0112] The voltage on the capacitor 605 will rise as illustrated in the waveform 620. When the voltage on the capacitor 605 crosses V REF4 611, the output of the comparator 606 will go low, and the output of the AND gate 612 will therefore also go low, indicating the expiration of the maximum on-time for the high-side switch.

[0113] In the disclosed Figure 6 embodiments, I REF and V REF4 611 have fixed values, so the time it takes for the capacitor 605 to charge to the reference voltage V REF4 611 depends on the value of the external resistor R HMX 671 coupled to the terminal HMX 661. In this way, the maximum on-time of the high-side switch can be programmed by selecting the value of the resistor R HMX 671.

[0114] Although Figure 6 specific embodiments of circuit structures and logic for controlling a timer and for input and output signals are illustrated, other structures and configurations— analog and / or digital— consistent with the teachings of the present disclosure are possible as will be appreciated by those skilled in the art.

[0115] Figure 7 A circuit diagram of a volt-second on-time block 735 is shown, which in one embodiment can correspond to the volt-second on-time block 335 of the primary controller 350 and / or the volt-second on-time block 435 shown in Figure 3 . Figure 4

[0116] ​The volt-second on-time block 735 includes a first reference voltage 700, a first transistor 701a, a second transistor 701b, and a first resistor 741. The first transistor 701a, the second transistor 701b, and the first resistor 741 collectively form a first current source for charging the first capacitor 705. The volt-second on-time block 735 also includes a third transistor 702a, a fourth transistor 702b, a second resistor 742, and a ground reference 707. The third transistor 702a, the fourth transistor 702b, and the second resistor 742 collectively form a second current source for discharging the first capacitor 705. The volt-second on-time block 735 also includes a fifth transistor 703 for controlling the charging of the first capacitor 705 and a sixth transistor 704 for controlling the discharging of the first capacitor 705.

[0117] The first transistor 701a, the second transistor 701b, the first resistor 741, the fifth transistor 703, and the first capacitor 705 collectively form a first integrator 731. The third transistor 702a, the fourth transistor 702b, the second resistor 742, the sixth transistor 704, and the first capacitor 705 collectively form a second integrator 732. The fifth transistor 703 and the second resistor 742 are coupled to a terminal AUX 730, which is configured to receive a signal representative of a voltage on a primary winding of an AHB power converter, such as, for example, the auxiliary winding 106 shown in FIG. 1. Figure 1

[0118] The volt-second on-time block 735 also includes a comparator 706 configured to compare the voltage on the first capacitor 705 to a second reference voltage 711. Although the embodiments of the present disclosure illustrate the comparator 706 as a voltage comparator, other embodiments of the comparator, analog and / or digital, consistent with the teachings of the present disclosure, can be used as will be appreciated by those skilled in the art. Figure 7

[0119] The volt-second on-time block 735 also includes a seventh transistor 709 configured to reset the voltage on the first capacitor 705 at each switching cycle. The volt-second on-time block 735 also includes a first inverter 714 and a second capacitor 708b coupled between the output of the comparator 706 and the seventh transistor 709. The volt-second on-time block 735 also includes a third resistor 708a coupled to the seventh transistor 709. The resistor 708a and the capacitor 708b collectively form a reset circuit configured to implement a reset pulse between a change in the output state of the comparator 706 and the switching of the seventh transistor 709 to effect a reset of the first capacitor 705.

[0120] ​​The volt-second on-time block 735 also includes an AND gate 712 configured to provide an output for controlling the on-time of a high-side switch of an AHB power converter, such as, for example, the high-side switch 351 of the example primary controller 350 of Figure 3 and the high-side switch 151 of the primary controller 150 of Figure 1 The first input of the AND gate 712 is coupled to the output of the comparator 706.

[0121] The volt-second on-time block 735 also includes an input for receiving a LS switch control signal 725b, which represents the timing of the turn-on and turn-off of a low-side switch of an AHB power converter, such as, for example, the low-side switch 353 of the example primary controller 350 of Figure 3 and the low-side switch 153 of the primary controller 150 of Figure 1 The LS switch control signal 725b is coupled to control a fifth transistor 703, such that the fifth transistor 703 is on when the low-side switch is on, and the fifth transistor 703 is off when the low-side switch is off. The LS switch control signal 725b is also coupled to a second inverter 713, the output of which is coupled to a second input of the AND gate 712. The output of the AND gate 712 is coupled as an output of the volt-second on-time block 735, and is also coupled to an input of a sixth transistor 704 to control the operation of the second integrator. The output of the AND gate 712 is the HS switch on-time signal.

[0122] Block 720 illustrates one example of the relative timing between the LS switch control signal 725b and the output of the AND gate 712.

[0123] In an example switching cycle of an AHB power converter, the volt-second on-time block 735 can operate as follows. At the beginning of the switching cycle, the LS switch control signal 725b changes state (e.g., from low to high as in the illustrated embodiment), indicating that the low-side switch has turned on. While the LS switch control signal 725b is at a high value, the output of the AND gate 712 is at a low value. The fifth transistor 703 is configured to turn on in response to the LS switch control signal 725b, and the first capacitor 705 is configured to begin charging. The rate at which the first capacitor 705 charges depends on the value of the input at the terminal AUX 730. During the on-time of the low-side switch, the voltage on the first capacitor 705 will rise from a low value to a higher value. The voltage on the first capacitor 705 is greater than the second reference voltage 711, and the output of the comparator 706 is at a high value.

[0124] At the end of the low-side switch on-time, the LS switch control signal 725b changes state (e.g., from high to low as in the illustrated embodiment), and the fifth transistor 703 is configured to turn off in response, which stops the charging of the first capacitor 705. After the LS switch control signal 725b transitions, which indicates the end of the low-side switch on-time, the output of the AND gate 712 transitions high, indicating the start of the high-side switch on-time. The output of the AND gate 712 going high turns on the sixth transistor 704. As explained previously in the discussion of Figure 2 A dead-time can be implemented between the end of the low-side switch on-time and the start of the high-side switch on-time.

[0125] When the sixth transistor 704 is turned on, the voltage on the first capacitor 705 will start to discharge. The rate at which the first capacitor 705 discharges depends on the value of the signal at the terminal AUX 730. During the on-time of the high-side switch, the voltage on the first capacitor 705 will decrease. When the voltage on the first capacitor 705 decreases below the threshold set by the second reference voltage 711, the output of the comparator 706 will change state (e.g., from high to low as in the illustrated embodiment), and thus, the output of the AND gate 712 will also go low. The output of the AND gate 712 is output from the volt-sec on-time block 735 to control the turn-off of the high-side switch.

[0126] When the output of the AND gate 712 changes state, the sixth transistor 704 will be turned off. Also, when the output of the comparator 706 changes state (e.g., from high to low in the illustrated embodiment), the seventh transistor 709 will be turned on after the reset circuit implemented by the third resistor 708a and the second capacitor 708b, resetting the voltage on the first capacitor 705 and preparing the volt-sec on-time block 735 for the next switching cycle.

[0127] Although Figure 7 A specific embodiment for controlling the first integrator 731 and the second integrator 732 and for the logic of the input signal and the output signal is illustrated, other configurations consistent with the teachings of the present disclosure are possible as will be appreciated by one skilled in the art. And although Figure 7 A particular example circuit structure for integrating the value of the input signal over time is illustrated, other structures— analog and / or digital— consistent with the teachings of the present disclosure are possible as will be appreciated by one skilled in the art.

[0128] Figure 8 A circuit diagram of an example proportional on-time block 840 is shown, which in one embodiment can correspond to the block 340 in the example primary controller 350 of Figure 3 and / or the block 340 in the example primary controller 350 of Figure 5The proportional conduction time block 540 is shown in FIG. 5B. The example proportional conduction time block 840 is substantially identical to the proportional conduction time block 540 of FIG. 5B and operates in substantially the same manner, but at least has one difference as discussed below. Figure 7 The proportional conduction time block 840 is substantially identical to the volt- second conduction time block 735 of FIG. 5A and operates in substantially the same manner, but at least has one difference as discussed below.

[0129] In the proportional conduction time block 840, the fifth transistor 803 is coupled to the ground reference 807 instead of the external terminal. In addition, the second resistor 842 is coupled to the voltage reference 800 instead of the external terminal. Thus, the proportional conduction time block is configured to control the high-side switch conduction time to be proportional to the low-side switch conduction time based on a proportional factor K instead of in response to a sensed auxiliary winding voltage. The proportional factor K is determined based on a ratio of the values of the first resistor 841 and the second resistor 842.

[0130] In the proportional conduction time block 840, the first integrator 831 integrates the value of the voltage reference 800 divided by the value of the first resistor 841 over the conduction time of the low-side switch. The second integrator 832 integrates the value of the voltage reference 800 divided by the value of the second resistor 842 over the conduction time of the high-side switch. When these integrated values are equal to each other, the output of the comparator 806 will change state and indicate that the high-side switch should be turned off.

[0131] In detail, the operation of the proportional conduction time block 840 tracks the operation of the volt-second conduction time block 735 as explained above with reference to FIG. 5A, and the reference numerals are also similarly numbered accordingly. Figure 7

[0132] In one embodiment, the value of K can equal 1, such that the conduction time of the high-side switch is controlled to be substantially the same as the conduction time of the low-side switch. In other embodiments, other values of K are possible. Ideally, the value of K equals 1. Due to potential mismatches in the charging and discharging circuits, in some embodiments, the value of K can be 0.95, 1.05, or some other value close to 1 to compensate for noise or mismatches in the circuit implementation. In some embodiments, the value of K can be a tunable or programmable parameter.

[0133] Figure 9 A circuit diagram is shown of an example maximum conduction time block 945, which in one embodiment can correspond to the block 345 in the example primary controller 350 of Figure 3 and / or the maximum conduction time block 645 of Figure 6 FIG. 5B.

[0134] ​The maximum on-time block 945 includes a first reference voltage source 900, a first transistor 901a, a second transistor 901b, a capacitor 905, and a comparator 906. The first reference voltage source 900, the first transistor 901a, the second transistor 901b, the capacitor 905, and the comparator 906 collectively form a timer. The maximum on-time block 945 also includes a second reference voltage 911 input to the comparator 906. The second reference voltage 911 is coupled to the non-inverting input of the comparator 906, while the capacitor 905 is coupled to the inverting input of the comparator 906.

[0135] The maximum on-time block 945 also includes a terminal HMX 961 configured to be coupled to an external resistor R HMX 971. The terminal HMX 961 can correspond to Figure 1 the terminal HMX 161 of the embodiment illustrated in FIG. 1, and the resistor R HMX 971 can correspond to Figure 1 the resistor R HMX 171. The maximum on-time block 945 also includes a switch 909 for resetting the voltage on the capacitor 905 during each switching cycle.

[0136] The maximum on-time block 945 also includes an input for receiving a LS switch control signal 925b, which represents the timing of the turn-on and turn-off of a low-side switch of the AHB power converter, such as, for example, the low-side switch 353 of the example primary controller 350 of Figure 3 and the low-side switch 153 of the primary controller 150 of Figure 1 . The LS switch control signal 925b is coupled to control the switch 909 such that the switch 909 is on when the low-side switch is on, and the switch 909 is off when the low-side switch is off. The LS switch control signal 925b is coupled to an inverter 913, and the output of the inverter 913 is coupled to one input of an AND gate 912. The output of the comparator 906 is coupled to a second input of the AND gate 912, and the output of the AND gate 912 is coupled to provide the high-side switch maximum on-time signal as an output of the maximum on-time block 945.

[0137] In an example switching cycle of the AHB power converter, the maximum on-time block 945 can operate as follows. At the beginning of the switching cycle, the LS switch control signal 925b will change state (e.g., from low to high as in the illustrated embodiment) indicating that the low-side switch has turned on. The LS switch control signal 925b will turn on the switch 909, resetting the voltage on the capacitor 905 to a low state. This low state is less than the voltage reference 911, and the output of the comparator 906 will be high. The output of the inverter 913 will be low, so the output of the AND gate 912 will also be low.

[0138] At the end of the low-side switch on-time, the LS switch control signal 925b will change state (e.g., from high to low as in the illustrated embodiment) indicating that the low-side switch has turned off. The LS switch control signal 925b going low will turn off the switch 909, allowing the capacitor 905 to begin charging. The voltage on the capacitor 905 is less than the second reference voltage 911, and the output of the comparator 606 is high. The output of the inverter 913 will be high, so the output of the AND gate 912 will also transition to a high state, indicating the start of the maximum high-side on-time.

[0139] The voltage on the capacitor 905 will rise from a low level to a higher level. When the voltage on the capacitor 905 reaches the second reference voltage 911, the output of the comparator 906 will go low, and the output of the AND gate 912 will thus also go low, indicating the expiration of the maximum on-time of the high-side switch.

[0140] In the disclosed Figure 9 embodiments, the first reference voltage 900 and the second reference voltage 911 have fixed values, so the rate at which the capacitor 905 charges and the time it takes for the capacitor 905 to charge to the second reference voltage 911 depends on the value of the external resistor R HMX 971 coupled to the terminal HMX 961. In this way, the maximum on-time of the high-side switch can be programmed by selecting the value of the resistor R HMX 971.

[0141] Although Figure 9 specific embodiments for controlling the operation of the maximum on-time block 945 and the circuit structure and logic for the input and output signals are illustrated, other structures and configurations— analog and / or digital— consistent with the teachings of the present disclosure are possible as will be appreciated by one skilled in the art.

[0142] Figure 10 A series of steps in an example method 1000 for controlling the on-time of the high-side switch of an AHB power converter using volt-second calculations is shown.

[0143] In step 1010, the low-side switch of the AHB power converter is turned on (e.g., Figure 1 The low-side switch 153 shown is used to measure the primary-side auxiliary winding (e.g., as shown in the diagram). Figure 1 The voltage (VAUX) on winding 106 shown. In step 1020, the VAUX measured during the low-side switch conduction time is integrated, and the resulting first integrated value is stored. In step 1030, the low-side switch is turned off and the dead time period is allowed to pass.

[0144] In step 1040, the high-side switch of the AHB power converter is turned on (e.g., Figure 1 The high-side switch 151 shown is used, and the voltage (VAUX) of the auxiliary winding is measured again. In step 1050, the VAUX measured during the high-side switch conduction time is integrated, and a second integral value is calculated. ).

[0145] In step 1060, ( )and( The comparison is performed. In step 1070, the result of the comparison is evaluated. If ( ) less than or equal to ( If (), then the method returns to step 1050 and continues integrating VAUX. If ( ) greater than ( In other words, when ( )Exceed( When the condition is met, method 1000 proceeds to step 1080. In step 1080, the high-side switch is turned off.

[0146] In this way, the on-time of the high-side switch is controlled based on the volt-second balance between the operation of the AHB power converter during the on-time of the low-side switch and the on-time of the high-side switch.

[0147] Figure 11 A flowchart of method 1100 is shown, which is used to control the on-time of the high-side switch of an AHB power converter in parallel using three different optional techniques: volt-second on-time, proportional on-time, and maximum on-time.

[0148] In step 1110, the low-side switch of the AHB power converter is turned on, for example... Figure 1 The low-side switch 153 is shown. After step 1110, method 1100 branches into two branches. In step 1111, the primary-side auxiliary winding (e.g., as shown) is measured. Figure 1 The voltage (VAUX) on the winding 106 shown. Essentially simultaneously with step 1111, in step 1112, a first reference voltage (V) is generated.REF5 ).

[0149] In step 1113, the VAUX measured during the low-side switch conduction time is integrated, and the resulting first integrated value is stored. ). Essentially simultaneously with step 1113, in step 1114, the V during the low-side switch on-time is... REF5 Perform integration and store the resulting third integral value. ).

[0150] In step 1120, the low-side switch is turned off, allowing the dead time period to pass. Afterward, the high-side switch of the AHB power converter is turned on, for example... Figure 1 The high-side switch 151 shown is illustrated.

[0151] In step 1121, the voltage (VAUX) of the auxiliary winding is measured again. Essentially simultaneously with step 1121, in step 1122, a second reference voltage (kV) is generated. REF5 Similarly, essentially simultaneously with steps 1121 and 1122, in step 1130, the timer is started.

[0152] In step 1123, the VAUX measured during the high-side switch conduction time is integrated, and a second integral value is calculated. ). Essentially simultaneously with step 1123, in step 1124, the KV during the low-side switch conduction time is... REF5 Perform integration and calculate the fourth integral value. In step 1125, ( )and( ) are compared, and in step 1126, ( )and( (Compare)

[0153] In step 1135, the elapsed time of the timer is compared with a predetermined maximum time period. If the maximum time period has not yet been exceeded, the timer continues to run and the method repeats step 1135. If at any time the elapsed time of the timer exceeds the predetermined maximum time period, method 1100 immediately proceeds to step 1150 and the high-side switch is turned off.

[0154] In step 1140, if the maximum time period has not yet been reached, the comparison results of steps 1125 and 1126 are evaluated. If ( ) greater than ( )and( ) greater than ( If (), then method 1100 proceeds to step 1150 and turns off the high-side switch. If ( ) less than or equal to ( ) or ) is less than or equal to ), the method 1100 returns to step 1123 or 1124, respectively. In this way, the longer of the time period determined by the volt-sec on-time or the proportional on-time (if both are shorter than the maximum time period) will control the turn-off of the high-side switch in any given switching cycle.

[0155] In some embodiments, the combination of the maximum on-time, the proportional on-time, and the volt-sec on-time implementation can provide more robust operation over a wide range of potential operating conditions of the AHB power converter. Moreover, as can be appreciated by those skilled in the art, there can be alternative ways to implement the various circuit blocks and circuitry described herein.

[0156] For example, Figure 12A A volt-sec on-time circuit 1235 according to another embodiment of the disclosure is illustrated. The volt-sec on-time circuit 1235 can be an alternative implementation of the volt-sec on-time block 335; however, unlike the previously described circuit implementations, the volt-sec on-time circuit 1235 can utilize a steady or fixed input bias voltage VA having a regulated value greater than or equal to zero volts. For example, the bias voltage VA can be two point five volts (2.5 V).

[0157] The volt-sec on-time circuit 1235 includes a buffer circuit 1201 and a trigger circuit 1202. In addition to providing the bias voltage VA, the buffer circuit 1201 can receive the external resistor current IA and provide a buffered current IAR. Referring to Figure 1 , the resistor current IA can be related to the resistance RA of the resistor 175 and the resistor voltage VRES according to Ohm's law; thus, the resistor current IA can be expressed by EQ. 1 with the auxiliary winding voltage VAUX and the bias voltage VA.

[0158] EQ. 1 The buffer circuit 1201 includes an offset correction circuit 1203 and a current buffer 1204. The offset correction circuit 1203 can provide an offset current IX to adjust the input current IAX relative to the resistor current IA. For example, if the offset current IX is equal to the bias voltage VA divided by the resistance RA, the input current IAX can be given by EQ. 2.

[0159] EQ. 2 The current buffer 1204 can receive the input current IAX and provide a buffer current IAR to the trigger circuit 1202. The buffer current IAR can be proportional to the input current IAX. For example, the buffer current IAR can be a replica of the input current IAX but with an opposite sign, as in EQ. 3.

[0160] EQ. 3 According to the teachings herein, the volt-second on-time circuit 1235 can receive the resistor current IA and in response provide a state voltage VCX that indicates when to turn off the high-side switch 151. For example, the trigger circuit 1202 can receive the buffer current IAR and cause the state voltage VCX to transition to indicate when to turn off the high-side switch 151.

[0161] Figure 12B A waveform 1225 of the resistor current IA and a waveform 1226 of the state voltage VCX are illustrated according to an embodiment of the disclosure. Referring to FIG. 12, the waveform 1225 of the resistor current IA can be similar to the waveform of the auxiliary winding voltage VAUX, which exhibits a transition within a switching period TSW from a time 211 to a time 215. During the switching period TSW, the low-side switch 153 is on from the time 211 to a time 212; and the high-side switch 151 is on from a time 213 to a time 214. During a time period TIR from the time 214 to the time 215, both the low-side switch 153 and the high-side switch 151 can be off. Figure 2 Similar to the waveform of the auxiliary winding voltage VAUX, the waveform 1225 can exhibit switching transitions at the times 211, 212, 214, and 215. For example, from the time 211 to the time 212, the resistor current IA can be approximately negative twenty-two point five microamperes (-22.5 uA) when the low-side switch 153 is on; and from the time 213 to the time 214, the resistor current IA can be approximately positive seventeen point five microamperes (17.5 uA) when the high-side switch 151 is on.

[0162] According to the teachings herein, the volt-second on-time circuit 1235 can indicate when to turn off the high-side switch 151 through the state voltage VCX. Accordingly, the waveform 1226 can exhibit a transition just prior to the time 214 so that at the time 214, the high-side switch 151 is off.

[0163]

[0164] ​As can be appreciated by those skilled in the art, the waveform 1225 of the resistor current IA, similar to the waveform of the auxiliary winding voltage VAUX, can depend on operating conditions and configurations. For example, when the auxiliary winding 106 is wound in the opposite direction, such that the winding "dot" is connected to ground, then the auxiliary winding voltage VAUX can have a polarity opposite to Figure 1 and Figure 2 Thus, the waveform of the auxiliary winding voltage VAUX and the corresponding resistor current IA can have opposite polarities.

[0165] Figure 12C A buffer circuit 1201 according to an embodiment of the disclosure is illustrated. As discussed above, the buffer circuit 1201 can include an offset correction circuit 1203 and a current buffer 1204. As illustrated, the offset correction circuit 1203 can include a p-channel field effect transistor (PFET) MP1. The gate of the PFET MP1 can receive a bias potential VGP, and the drain of the PFET MP1 can be coupled to the node NA to add an offset correction current IX to the resistor current IA.

[0166] Also as illustrated, the current buffer 1204 can be implemented with p-channel field effect transistors (PFETs) MP2-MP9 and n-channel field effect transistors (NFETs) MN1-MN9. A bias potential VGP can be provided to the gate of the PFET MP2, and a bias potential VGN can be provided to the gates of the NFETs MN6-MN8. During operation, due to feedback and circuit configuration, the current buffer 1204 can provide a bias voltage VA at the node NA that is substantially equal to the bias reference VCM at the gate of the NFET MN4. For example, if the bias reference VCM is equal to two point five volts (2.5V), then the bias voltage VA can be regulated to 2.5V plus or minus any offset.

[0167] Further, due to circuit configuration, the current buffer 1204 can provide a buffer current IAR from the drain of the NFET MN9 and the drain of the PFET MP7, both of which are coupled at the node ND. Although the sign of the buffer current IAR can be opposite to the sign of the input current IAX, as depicted by the waveforms 1250 and 1251 of the input current IAX and the buffer current IAR, respectively, other configurations are possible. For example, implementations of the current buffer 1201 can include additional components whereby the buffer current IAR replicates the input current IAX without reversing the polarity or direction of the current.

[0168] Figure 12DA trigger circuit 1202 according to an embodiment of the disclosure is illustrated. The trigger circuit 1202 includes a switched voltage source 1205, a capacitor CI, and a comparator circuit block 1210. The capacitor CI is connected at a node NC1 to an input of the comparator circuit block 1210 and to the switched voltage source 1205. Prior to the start of a switching cycle (e.g., a switching period TSW), a capacitor voltage VC1 at the node NC1 can be pre-charged to a reference voltage VR by the switched voltage source 1205; and during the switching cycle (e.g., the switching period TSW), the capacitor voltage VC1 can vary as a function of a buffer current IAR when the switch SI is open.

[0169] Accordingly, prior to the start of a switching cycle (e.g., a switching period TSW), the switch SI can be closed by the switch signal PS1; and during the switching cycle, the switch SI can be opened by the switch signal PS1.

[0170] As illustrated, the comparator circuit block 1210 can include a comparator 1211 and logic circuitry 1212. During a switching cycle (e.g., a switching period TSW), the comparator 1211 can compare the capacitor voltage VC1 to a comparator reference voltage VRN. The comparator reference voltage VRN can be selected, programmed, and / or derived so that the comparator 1211 changes state in response to the capacitor voltage VC1 crossing the reference voltage VR during the switching cycle. For example, the comparator reference voltage VRN can be set to a value equal to or substantially equal to the reference voltage VR plus or minus any offset.

[0171] The comparator circuit block 1210 can also include logic circuitry 1212. The logic circuitry 1212 can receive the comparator output voltage VC and provide a state voltage VCX. For example, the logic circuitry 1212 can include latches, switches, logic gates, and / or monostable circuits to ensure that the state voltage VCX is provided as a pulse after a transition of the comparator output voltage VC.

[0172] Figure 13A Waveforms 1301a-1304a corresponding to the capacitor voltage VC1, the low-side gate voltage VGL, the high-side gate voltage VGH, and the state voltage VCX according to an embodiment of the disclosure are illustrated. The waveforms 1301a-1304a are plotted from a time 1330. With reference to Figure 1 The low-side gate voltage VGL can drive the low-side switch 153, and the high-side gate voltage VGH can drive the high-side switch 151. For example, from the time 1330 to the time 1332, the low-side gate voltage VGL drives the low-side switch 153 to operate in an on state; and from the time 1333 to the time 1335, the high-side gate voltage VGH drives the high-side switch 151 to operate in an on state.

[0173] Furthermore, the switching period TSW can be conveniently defined as the time from when the low-side switch 153 is turned on (time 1330) to when the low-side switch 153 is turned on again (time 1337). Therefore, as depicted by waveform 1302a, the switching cycle can begin at time 1330 with a low-to-high transition of the low-side gate voltage VGL. Furthermore, as depicted by waveform 1301a, from time 1330 to time 1331, the capacitor voltage VC1 can be kept constant at the reference voltage VR.

[0174] Based on the teachings of this article, waveforms 1301a-1304a can also correspond to... Figure 1 The configuration presented is similar to the auxiliary winding configuration (i.e., the point winding direction configuration). Therefore, as depicted by waveform 1301a, after a short delay (e.g., a delay of one hundred nanoseconds), the capacitor voltage VC1 can increase from its initial value (e.g., the reference voltage VR). Then, at time 1332, the low-side switch 153 is turned off, and the capacitor voltage VC1 can reach its peak value Vpk1.

[0175] Referring to waveform 1303a, at time 1333, after a break-before-make delay (e.g., a delay of 250 nanoseconds), the high-side switch 151 can be turned on. As depicted by waveform 1301a, from time 1333 to time 1335, when the high-side switch 151 is on, the capacitor voltage VC1 can decrease.

[0176] Referring to waveform 1304a and in accordance with the teachings of this document, at time 1335, the state voltage VCX transitions high, thus indicating when the high-side switch 151 is turned off. Therefore, at time 1335 and immediately following the transition of the state voltage VCX, the high-side switch 151 turns off (i.e., the high-side voltage VGH transitions low). Although waveform 1304a exemplifies the state voltage VCX as exhibiting a short pulse between time 1335 and time 1336, other waveforms are possible as long as the transition edge at time 1335 triggers the high-side switch 151 to turn off.

[0177] As shown by waveform 1301a, an undershoot of the capacitor voltage VC1 may exist starting at time 1334. This undershoot can be at least partly due to the non-ideal behavior of the circuitry including comparator block 1210. Ideally, at time 1334, the state voltage VCX would transition high simultaneously with the crossover of the capacitor voltage VC1 and the reference voltage VR. However, due to circuit delays and / or offsets, comparator block 1210 may not respond until time 1335, resulting in a total undershoot voltage VUS.

[0178] During the time period TIR, from time 1335 to time 1337, both high-side switch 151 and low-side switch 153 are off. In addition, switch SI can conduct so that switch voltage source 1205 provides reference voltage VR to node NC1. Thus, as exemplified by waveform 1301a, capacitor voltage VC1 recovers (i.e., rises) toward its starting value (i.e., toward reference voltage VR). For stable operation and circuit performance, capacitor voltage VC1 should equal or substantially equal reference voltage VR by the start of the subsequent switching cycle.

[0179] Unfortunately, there can be system operating modes that include transient and / or heavy load conditions whereby time period TIR is relatively short (e.g., one hundred nanoseconds or less). In addition, due to process and / or device limitations, switch voltage source 1205 can not have sufficient bandwidth (i.e., can not be fast enough) to allow capacitor voltage VC1 to recover to reference voltage VR.

[0180] Thus, as exemplified by waveforms 1301a, 1302a, low-side switch 153 can turn on at time 1338 before capacitor voltage VC1 can reach its initial value corresponding to reference voltage VR. This, in turn, can create an undesirable offset error. Under these conditions, capacitor voltage VC1 can increase until it reaches its subsequent peak Vpk2 at time 1339; and due in part to the offset error, subsequent peak Vpk2 at time 1339 can be less than peak Vpk1 at time 1332. Eventually, after several switching cycles, the offset error can accumulate; and capacitor voltage VC1 and its subsequent peaks can decrease until capacitor voltage VC1 is no longer within the operating range.

[0181] Similar situations can exist for an alternative auxiliary winding configuration (i.e., a point winding direction configuration as opposed to the Figure 1 configuration).

[0182] For example, Figure 13B Waveforms 1301b-1304b corresponding to capacitor voltage VC1, low-side gate voltage VGL, high-side gate voltage VGH, and state voltage VCX are exemplified according to an embodiment in which auxiliary winding 106 has an opposite winding polarity. When auxiliary winding 106 has an opposite winding polarity (i.e., point side connected to ground 107), the corresponding auxiliary winding voltage VAUX and buffer current IAR can also be symbolically opposite. Thus, comparator circuit block 1210 and / or switch voltage source 1205 can be reconfigured to account for the opposite winding polarity.

[0183] Accordingly, waveforms 1301b-1304b can be similar to waveforms 1301a-1304a, except for waveform 1301b corresponding to capacitor voltage Vci; and the transitions and waveform behavior at times 1341-1349 can be similar to those at times 1331-1339, respectively, except for waveform 1301b. Moreover, as with waveforms 1301a-1304a, the switching period Tswmay be defined as the time from 1340 to 1347. Figure 13A Similarly, for waveforms 1301b-1304b, the switching period Tswmay be defined as the time from 1340 to 1347.

[0184] With respect to waveform 1301b, at time 1341, capacitor voltage Vci can decrease from its initial value (e.g., reference voltage Vr) and reach a valley value Vvali at the turn-off of low-side switch 153 at time 1342. Then, from time 1343 to 1345, capacitor voltage Vci can increase while high-side switch 151 is on.

[0185] As shown by waveform 1301b, starting at time 1344, there can be an overshoot of capacitor voltage Vci. Similar to undershoot, the overshoot can be due, at least in part, to non-ideal behavior of the circuitry including comparator circuit block 1210. Thus, comparator circuit block 1210 can not respond until time 1345, resulting in an overall overshoot voltage OOV.

[0186] As exemplified by waveforms 1301b, 1302b, low-side switch 153 can turn on at time 1348 before capacitor voltage Vci can reach its initial value corresponding to reference voltage Vr. Under these conditions, capacitor voltage Vci can decrease until it reaches its subsequent valley value Vval2 at time 1349. In contrast, due in part to the offset error, the subsequent valley value Vval2 at time 1349 can be greater than the valley value Vvali at time 1342. Eventually, after a few switching cycles, the offset error can accumulate; and capacitor voltage Vci and its subsequent valley values can increase until capacitor voltage Vci is no longer within the operating range.

[0187] Accordingly, there is a need to develop an implementation of the trigger circuit 1202 that reduces the offset error and allows capacitor voltage Vci to remain within the operating range.

[0188] In this regard, Figure 14 A trigger circuit 1402 according to the teachings herein is exemplified. Similar to trigger circuit 1202, trigger circuit 1402 includes switching voltage source 1205, comparator circuit block 1210, and capacitor Ci. In addition, trigger circuit 1402 further includes capacitor C2 and switches S2-S6. As exemplified, switches Si-S6 are controlled by switching signals PSi-PS6, respectively; and voltage source 1205 includes an additional switch S2.

[0189] As illustrated, capacitor CI is connected to switch SI at node NC1. Further, switch S3 is connected between node NR and node NC1, and switch S5 is connected between node NP and node NC1. Thus, switch SI can be closed so that switch voltage source 1205 provides reference voltage VR to capacitor CI. Then, when switch S3 and switch S5 are closed, buffer current IAR can be provided to capacitor CI; and capacitor voltage VCI can be provided to comparator circuit block 1210.

[0190] Likewise, capacitor C2 is connected to switch S2 at node NC2. Further, switch S4 is connected between node NR and node NC2, and switch S6 is connected between node NP and node NC2. Thus, switch S2 can be closed so that switch voltage source 1205 provides reference voltage VR to capacitor C2. Then, when switch S4 and switch S6 are closed, buffer current IAR can be provided to capacitor C2; and capacitor voltage VC2 can be provided to comparator circuit block 1210.

[0191] As described herein, using capacitor CI, capacitor C2, and switches SI-S6, it can be advantageously allowed for capacitor CI to be swapped with capacitor C2 within two switching cycles in a manner that allows sufficient time for switch voltage source 1205 to provide voltage VR.

[0192] Figure 15 Waveforms 1501-1505 corresponding to capacitor voltage VCI, capacitor voltage VC2, low-side gate voltage VGL, high-side gate voltage VGH, and state voltage VCX are illustrated for an embodiment in accordance with Figure 14 Switching period TSW can be defined as from time 1520 to time 1525. Low-side switch 153 can be on between time 1520 and time 1522; and high-side switch 151 can be on between time 1523 and time 1524. Comparator circuit block 1210 can apply state voltage VCX as high at time 1524; and a new switching cycle can begin at time 1525.

[0193] At time 1521, switch S3 and switch S5 can be closed, allowing capacitor voltage VCI to increase in response to buffer current IAR. As illustrated, capacitor voltage VCI can increase from its initial value (i.e., it is the initial value of reference voltage VR) at time 1521, and reach a peak Vpkci at time 1522.

[0194] According to the teachings herein, the switching voltage source 1205 can provide the reference voltage VR to the capacitor C2 prior to time 1525. In this manner, at time 1526, the capacitor voltage VC2 can equal or substantially equal the reference voltage VR. Then, at time 1527, the capacitor voltage VC2 can reach its peak value Vpkc2 without an offset error.

[0195] Figure 16 A trigger circuit 1602 according to another embodiment is illustrated. The trigger circuit 1602 is similar to the trigger circuit 1402, except that the switching voltage source 1205 and the comparator circuit block 1210 are replaced by a switching voltage source 1605 and a comparator circuit block 1610, respectively.

[0196] Similar to the switching voltage source 1205, the switching voltage source 1605 includes a switch SI and a switch S2. In addition, the switching voltage source 1605 includes a multiplexer 1615 and an operational transconductance amplifier (OTA) 1616. In response to a multiplexer control signal PSM, the multiplexer 1615 can select either the voltage VI or the voltage V2 and provide the voltage VI or the voltage V2 to the non-inverting input of the OTA 1616. The OTA 1616, in turn, can provide a reference voltage VR that equals or substantially equals the selected one of the voltage VI or the voltage V2.

[0197] For example, the voltage VI can be one and a half volts (1.5 V), and the voltage V2 can be three volts (3.0 V). Then, if the capacitor voltage VC1 is similar to the waveform of the waveform 1501, it can be advantageous to select the voltage VI to allow the capacitor voltage VC1 to increase from its initial value (i.e., from the reference voltage VR) with sufficient common mode range. Alternatively, if the auxiliary winding 106 has an opposite winding polarity and the capacitor voltage VC1 decreases from its initial value (i.e., from the reference voltage VR), it can be advantageous to select the voltage V2.

[0198] Although the switching voltage source 1205 is shown to allow selection of two voltages VI, V2, other configurations allowing more or less than two can be possible.

[0199] Similarly, comparator circuit block 1610 can include comparator 1211 and logic circuitry 1212, similar to comparator circuit block 1210. In addition, comparator circuit block 1610 can include capacitor CRN, switch S7, and switch S8. Switches S7, S8 can be controlled by switch signals PS7, PS8, respectively, so that during a switch cycle (e.g., switch period TSW), comparator reference voltage VR is provided to capacitor CRN. Then, due to autozeroing, comparator 1211 and logic circuitry 1212 can apply a transition of state voltage in response to a crossing of capacitor voltage (i.e., capacitor voltage VC1 and / or capacitor voltage VC2) and reference voltage VR.

[0200] Figure 17 Waveforms 1701-1705 corresponding to capacitor voltage VC1, capacitor voltage VC2, low-side gate voltage VGL, high-side gate voltage VGH, state voltage VCX, respectively, are illustrated, and waveforms 1706-1713 corresponding to switch signals PS1-PS8, respectively, are illustrated.

[0201] First switch period TSW1 can be defined as from time 1720 to time 1729; and second switch period TSW2 can be defined as from time 1729 to time 1738. Low-side gate voltage VGL transitions high at time 1720, completes a first switch cycle at time 1729, and completes a second switch cycle at time 1738. Both high-side switch 151 and low-side switch 153 are open during a time period TIR1 from time 1727 to time 1729 and a time period TIR2 from time 1735 to time 1738.

[0202] High-side gate voltage VGH transitions high at time 1723 and low at time 1727, and transitions high at time 1732 and low at time 1735. In accordance with the teachings herein, high-side gate voltage VGH transitions low (i.e., high-side switch 151 is off) in response to a transition of state voltage VCX at time 1727, and high-side gate voltage VGH also transitions low in response to a transition of state voltage VCX at time 1735.

[0203] Waveforms 1706-1713 of switch signals PS1-PS8 indicate a conduction state (i.e., on state or off state) of switches S1-S8, respectively, as a function of time. In Figure 17In embodiments, a switch (e.g., any one of switches S1-S8) can be on (i.e., conducting) when the switch's corresponding switch signal (e.g., the corresponding one of switch signals PS1-PS8) is high, and the switch can be off (i.e., nonconducting) when the switch's corresponding switch signal (e.g., the corresponding one of switch signals PS1-PS8) is low.

[0204] Thus, switch S1 turns on at time 1730 and turns off at time 1738. Switch S2 turns on at time 1721 and turns off at time 1729. Switch S3 turns on at time 1721 and turns off at time 1727. Switch S4 turns on at time 1730 and turns off at time 1735. Switch S5 turns on at time 1726 and turns off at time 1727. Switch S6 turns on at time 1734 and turns off at time 1735. Switch S7 turns off at time 1725, turns on at time 1729, turns off at time 1733, and turns on at time 1737; and switch S8 turns off at time 1724, turns on at time 1728, turns off at time 1732, and turns on at time 1736.

[0205] With reference to trigger circuit 1602, waveforms 1706-1707 can illustrate the conduction states of switches S1-S2, respectively, in relation to how switch voltage source 1605 provides reference voltage VR to capacitors C1, C2; and waveforms 1708-1711 can illustrate the conduction states of switches S3-S6 in relation to how buffer current IAR is provided to capacitors C1, C2 and how capacitors C1, C2 provide capacitor voltages VC1, VC2, respectively, to comparator circuit block 1610.

[0206] Thus, waveforms 1706-1711 can illustrate how switches S1-S6 alternate (i.e., swap) the function of capacitors C1, C2 within first switch period TSW1 and second switch period TSW2 to produce waveforms 1701-1702, respectively. Thus, as illustrated by waveform 1701 of capacitor voltage VC1 and waveform 1702 of capacitor voltage VC2, when capacitor C1 receives reference voltage VR, capacitor C2 can be provided with reference voltage VR.

[0207] As shown by waveforms 1701-1702, using capacitor CI to provide voltage VC1 during the first switching period TSW1 while capacitor C2 receives reference voltage VR, and then using capacitor C2 to provide voltage VC2 during the second switching period TSW2 while capacitor CI receives reference voltage VR advantageously allows sufficient time for the switching voltage source 1605 to provide voltage VR. For example, while capacitor CI provides capacitor voltage VC1 to the comparator circuit block 1610, capacitor C2 can receive reference voltage VR for nearly the entire switching period TSW1. Then, while capacitor C2 provides capacitor voltage VC2 to the comparator circuit block 1610, capacitor CI can receive reference voltage VR for nearly the entire switching period TSW2.

[0208] Further, with reference to the trigger circuit 1602, waveforms 1712-1713 can illustrate the conduction states of switches S7-S8, respectively, in relation to the auto-zero feature of the comparator circuit block 1610. Although the comparator circuit block 1610 is shown as having an auto-zero feature, other configurations of the comparator circuit block 1610 and the trigger circuit 1602 can be possible.

[0209] For example, the comparator circuit block 1610 can use a comparator 1211 that does not require auto-zeroing. Also, as can be appreciated by those skilled in the art, there can be configurations of the trigger circuit 1602 that allow for more than two capacitors CI, C2 to be swapped during more than two switching periods TSW1, TSW2.

[0210] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present teachings can be practiced without necessarily being limited to these specific details. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0211] In this specification, reference can be made to "one embodiment", "an embodiment", "one design" or "a design" meaning that a particular feature, structure, or characteristic described in connection with the embodiment or design is included in at least one embodiment of the disclosure. The appearance of the phrases "in one embodiment", "in an embodiment", "one design", or "a design" in various places in the specification are not necessarily all referring to the same embodiment or design. Furthermore, the particular features, structures, or characteristics can be combined in any suitable

[0212] The above description of illustrated embodiments of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the more general spirit and nature of the disclosure. Indeed, it will be understood that specific example voltages, currents, frequency, power range values, times, etc. are provided for illustrative purposes only and other values can be employed in other embodiments and examples in accordance with the teachings herein.

[0213] The foregoing description can refer to elements or features as being "connected", "electrically connected", and / or "coupled" together. As used herein, "connected" means that one element / feature is either directly or indirectly connected to another element / feature without necessarily being mechanically connected. Likewise, "coupled" means that one element / feature is either directly or indirectly coupled to another element / feature without necessarily being mechanically coupled. Thus, although the various diagrams can depict example arrangements of elements and components, additional intermediate elements, devices, features, or components (e.g., as examples of the depicted circuitry) can be present in an actual implementation so long as the functional outcome of the depicted circuits is not adversely affected.

[0214] Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for instance,” “like,” “such as,” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and / or states. Thus, such conditional language is not generally intended to imply that features, elements and / or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding, with or without user input or prompting, whether these features, elements and / or states are included or are to be performed in any particular embodiment.

[0215] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel devices, methods and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments can perform similar functions using different components and / or circuit topologies, and some elements can be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements can be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the application should be judged in terms of the claims that follow, rather than the description above.

[0216] While the claims presented herein are in a single dependent format for purposes of the United States Patent Office, it will be understood that any claim can be written in multiple dependent format unless technically infeasible.

Claims

1. A high-side switch on-time control circuit for use in an asymmetric half-bridge (AHB) power converter, the power converter including a high-side switch, a low-side switch, and a primary-side winding, the high-side switch on-time control circuit comprising: Terminals, which are coupled to receive signals representing the winding voltage on the primary-side winding; A first integrator is configured to integrate the signal during the on-time of the low-side switch and output a first integral value. A second integrator is configured to integrate the signal during the on-time of the high-side switch and output a second integral value. as well as A first comparator is configured to compare the first integral value and the second integral value and respond to the comparison to output a control signal, wherein the control signal is coupled to control the end of the on-time of the high-side switch.

2. The high-side switch conduction time control circuit according to claim 1, wherein the first integrator comprises: A first current source provides a first current proportional to the winding voltage during the on-time of the low-side switch; A first switch, which is coupled to the first current source; as well as A first capacitor, which is coupled to be charged by the first current source. The first current source is coupled to charge the first capacitor through the first switch, and the first integral value is the voltage on the first capacitor at the end of the on-time of the low-side switch.

3. The high-side switch conduction time control circuit according to claim 2, wherein the second integrator comprises: A second current source provides a second current proportional to the winding voltage during the on-time of the high-side switch; A second switch, which is coupled to the second current source; as well as The first capacitor is configured to discharge from the second current source. The second current source is coupled to discharge the first capacitor through the second switch.

4. The high-side switch conduction time control circuit according to claim 3, wherein the first comparator is configured to output the control signal to control the end of the conduction time of the high-side switch when the voltage on the first capacitor is discharged below the first reference voltage.

5. The high-side switch on-time control circuit according to claim 4 further includes a third switch, the third switch being configured to reset the voltage on the first capacitor once during each switching cycle in response to the output of the first comparator.

6. The high-side switch conduction time control circuit according to claim 5 further includes a reset circuit, the reset circuit being coupled between the output of the first comparator and the third switch.

7. The high-side switch conduction time control circuit according to claim 1, wherein the first comparator is a voltage comparator.

8. The high-side switch conduction time control circuit according to claim 1 further includes: First reference voltage; A third integrator is configured to integrate the first reference voltage during the on-time of the low-side switch and output a third integral value. A second reference voltage, wherein the second reference voltage is a constant K times the first reference voltage; A fourth integrator is configured to integrate the second reference voltage during the on-time of the high-side switch and output a fourth integrated value; as well as A second comparator is configured to compare the third integral value and the fourth integral value and output a second control signal in response to the comparison, wherein the second control signal is coupled to control the end of the on-time of the high-side switch.

9. The high-side switch conduction time control circuit according to claim 8, wherein K equals 1.

10. The high-side switch conduction time control circuit according to claim 8, wherein the third integrator comprises: A third current source provides a first current that is proportional to the first reference voltage; A third switch, which is coupled to the third current source; as well as The second capacitor is coupled to be charged by the third current source, and The third current source is coupled to charge the second capacitor through the third switch, and the third integral value is the voltage on the second capacitor at the end of the on-time of the low-side switch.

11. The high-side switch on-time control circuit according to claim 10, wherein the fourth integrator comprises: A fourth current source provides a current proportional to the second reference voltage; A fourth switch, which is coupled to the fourth current source; as well as The second capacitor, which is coupled to discharge by the fourth current source, and The fourth current source is coupled to discharge the second capacitor through the fourth switch.

12. The high-side switch conduction time control circuit according to claim 11, wherein the second comparator is configured to output the second control signal to control the end of the conduction time of the high-side switch when the voltage on the second capacitor is discharged below the third reference voltage.

13. The high-side switch on-time control circuit of claim 12 further includes a fifth switch, the fifth switch being configured to reset the voltage on the second capacitor once during each switching cycle in response to the output of the second comparator.

14. The high-side switch conduction time control circuit according to claim 13 further includes a reset circuit, the reset circuit being coupled between the output of the second comparator and the fifth switch.

15. The high-side switch conduction time control circuit according to claim 1, further comprising: Timer, The timer includes: an input coupled to receive a signal indicating when the high-side switch is turned on; and an output configured to provide a second control signal when a predetermined maximum time has elapsed since the high-side switch was turned on.

16. The high-side switch on-time control circuit according to claim 15, wherein the predetermined maximum time is programmable.

17. A primary controller for use in an asymmetric half-bridge (AHB) power converter, the power converter including a high-side switch, a low-side switch, and a primary-side winding, the primary controller comprising: A first terminal is coupled to receive a first signal representing the voltage on the primary side winding; The second terminal is coupled to receive a feedback signal representing the output of the AHB power converter; The third terminal is coupled to receive a second signal representing the voltage at the half-bridge node of the AHB power converter; A low-side control circuit is configured to respond to the feedback signal and the second signal, and to generate a low-side switching control signal in response to the feedback signal and the second signal; as well as A high-side control circuit is configured to respond to the first signal and the second signal, and to generate a high-side switch control signal in response to the first signal and the second signal; The high-side control circuit includes: A maximum on-time circuit is configured to generate a first high-side control signal for controlling the maximum on-time of the high-side switch; A proportional on-time circuit is configured to generate a second high-side control signal to control the on-time of the high-side switch to be proportional to the on-time of the low-side switch during the switching cycle of the AHB power converter; and A volt-second on-time circuit is configured to receive the first signal and generate a third high-side control signal in response to the first signal.

18. The primary controller of claim 17, further comprising a fourth terminal configured to receive a programming signal to program the duration of the maximum on-time.

19. The primary controller of claim 17, further comprising a fourth terminal for receiving a current sensing signal representing the current flowing through the low-side switch.

20. The primary controller of claim 19, wherein the low-side control circuit responds to the feedback signal to change the frequency at which the low-side switch is turned on, and wherein the low-side control circuit responds to the current sensing signal to turn off the low-side switch.

21. The primary controller of claim 17, further comprising a discontinuous conduction mode detection circuit configured to: respond to the second signal to realize a dead time period between the switching of the high-side switch and the low-side switch.

22. The primary controller of claim 17, further comprising a high-side communication circuit configured to generate a level-shifted control signal coupled from the output of the high-side control circuit to the high-side switch.

23. The primary controller of claim 17 further includes a logic circuit system configured to receive the first high-side control signal and the second high-side control signal, and output a signal indicating a longer on-time of the high-side switch as a fourth high-side control signal.

24. The primary controller of claim 23, wherein the logic circuit system is further configured to receive the third high-side control signal and the fourth high-side control signal, and output the signal indicating the shorter on-time of the high-side switch as the high-side switch control signal.

25. The primary controller according to claim 17, wherein the volt-second on-time circuit comprises: A first integrator is configured to integrate the first signal during the on-time of the low-side switch and output a first integrated value. A second integrator is configured to integrate the first signal during the on-time of the high-side switch and output a second integral value. as well as A first comparator is configured to compare the first integral value and the second integral value, and output the third high-side control signal in response to the comparison.

26. The primary controller according to claim 25, wherein the proportional on-time circuit comprises: First reference voltage; A third integrator is configured to integrate the first reference voltage during the on-time of the low-side switch and output a third integral value. A second reference voltage, wherein the second reference voltage is a constant K times the first reference voltage; A fourth integrator is configured to integrate the second reference voltage during the on-time of the high-side switch and output a fourth integrated value; as well as A second comparator is configured to compare the third integral value and the fourth integral value, and output the second high-side control signal in response to the comparison.

27. A method for controlling the on-time of a high-side switch in an asymmetric half-bridge power converter, the power converter comprising the high-side switch, a low-side switch, and a primary winding, the method comprising: Turn on the low-side switch; The measurement represents a first signal indicating the voltage on the primary winding during the on-time of the low-side switch; Integrate the first signal during the on-time of the low-side switch to generate a first integral value; Turn off the low-side switch and allow the dead time period to expire; Turn on the high-side switch; A second signal is measured, representing the voltage across the primary winding during the on-time of the high-side switch; The second signal during the on-time of the high-side switch is integrated to generate a second integral value; Compare the second integral value with the first integral value; as well as When the second integral value exceeds the first integral value, the high-side switch is turned off.

28. The method of claim 27, wherein integrating the first signal comprises charging the capacitor with a current proportional to the first signal.

29. The method of claim 27, wherein integrating the second signal comprises discharging the capacitor with a current proportional to the second signal.

30. The method of claim 29, further comprising resetting the capacitor after turning off the high-side switch and before turning on the low-side switch.

31. A method for controlling the on-time of a high-side switch in an asymmetric half-bridge power converter, the power converter comprising the high-side switch, a low-side switch, and a primary winding, the method comprising: Generate a first high-side control signal representing the maximum on-time of the high-side switch; The second high-side control signal is generated in the following manner: A first signal representing the voltage on the primary winding during the on-time of the low-side switch is integrated to generate a first integral value; A second integrated value is generated by integrating a second signal representing the voltage on the primary winding during the on-time of the high-side switch. as well as Compare the second integral value with the first integral value; The third high-side control signal is generated in the following manner: Integrate the first reference voltage during the on-time of the low-side switch to generate a third integral value; Integrate the second reference voltage, which is proportional to the first reference voltage, during the conduction time of the high-side switch to generate a fourth integral value; as well as Compare the third integral value with the fourth integral value; as well as The on-time of the high-side switch is controlled by selecting from the first high-side control signal, the second high-side control signal, and the third high-side control signal.

32. The method of claim 31, wherein selecting from the first high-side control signal, the second high-side control signal, and the third high-side control signal further comprises: If the maximum on-time has expired, the high-side switch is turned off in response to the first high-side control signal; Select the one that represents the longer on-time of the high-side switch, either the second high-side control signal or the third high-side control signal; as well as If the maximum on-time has not yet expired, the high-side switch is turned off in response to the selected signal.

33. A volt-second (volt-sec) on-time circuit for use in an asymmetric half-bridge (AHB) power converter, the power converter including a low-side switch and a high-side switch configured to alternately conduct primary-side current during at least one switching cycle, the volt-second on-time circuit comprising: A buffer circuit is configured to provide a buffer current proportional to the auxiliary winding voltage of the power converter. as well as A trigger circuit is configured to receive the buffer current and, in response, provide a state voltage to indicate when the high-side switch is turned off during the at least one switching cycle.

34. The volt-second on-time circuit of claim 33, wherein the buffer circuit is further configured to provide an input bias voltage and receive an external resistor current proportional to the difference between the auxiliary winding voltage and the input bias voltage.

35. The volt-second on-time circuit of claim 34, wherein the input bias voltage is substantially equal to 2.5 volts (2.5V).

36. The volt-second on-time circuit according to claim 34, wherein the buffer circuit further comprises: A current buffer is configured to provide the input bias voltage, receive the input current, and provide a buffer current proportional to the input current.

37. The volt-second on-time circuit of claim 36, wherein the input current includes the current of the external resistor.

38. The volt-second on-time circuit according to claim 37, wherein the buffer circuit further comprises: An offset correction circuit is configured to provide an offset current proportional to the input bias voltage.

39. The volt-second on-time circuit of claim 38, wherein the input current includes the offset current.

40. The volt-second on-time circuit according to claim 36, wherein the trigger circuit comprises: Switching voltage source; At least one capacitor; as well as A comparator circuit block configured to provide the stated state voltage.

41. The volt-second conduction time circuit according to claim 40, in, Prior to the at least one switching cycle, the switching voltage source is configured to charge the at least one capacitor to a reference voltage, and During the at least one switching cycle, the at least one capacitor is configured to receive the buffer current and provide a capacitor voltage to the comparator circuit block.

42. The volt-second conduction time circuit according to claim 41, wherein the reference voltage is between one volt (1V) and five volts (5V).

43. The volt-second on-time circuit of claim 41, wherein the comparator circuit block includes a comparator configured to apply a transition of the state voltage in response to a crossover of the capacitor voltage and the reference voltage.

44. The volt-second on-time circuit of claim 43, wherein the high-side switch is configured to turn off in response to a change in the state voltage.

45. The volt-second conduction time circuit according to claim 43, wherein, Before the capacitor voltage and the reference voltage cross, the capacitor voltage is less than the reference voltage.

46. ​​The volt-second conduction time circuit according to claim 43, wherein, Before the capacitor voltage and the reference voltage cross, the capacitor voltage is greater than the reference voltage.

47. The volt-second conduction time circuit according to claim 41, The at least one capacitor includes a first capacitor and a second capacitor; and The at least one switching cycle includes a first switching cycle and a second switching cycle following the first switching cycle.

48. The volt-second conduction time circuit according to claim 47, in, During the first switching cycle, the first capacitor is configured to receive the buffer current and provide the capacitor voltage to the comparator circuit block, and the switching voltage source is configured to provide the reference voltage to the second capacitor; as well as During the second switching cycle, the second capacitor is configured to receive the buffer current and provide the capacitor voltage to the comparator circuit block, and the switching voltage source is configured to provide the reference voltage to the first capacitor.

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