Bootstrap driving circuit, control method and converter

Abstract

The invention discloses a bootstrap driving circuit, a control method and a converter. The bootstrap driving circuit comprises a bootstrap power supply; the first end of each stage of bootstrap capacitor is connected to the bootstrap node of the corresponding gate driver, and the second end of each stage of bootstrap capacitor is connected to the source electrode reference node of the corresponding power switch; the plurality of synchronous bootstrap switches are arranged between two adjacent stages of bootstrap nodes and are used for charging the upper-stage bootstrap capacitor when the synchronous bootstrap switches are switched on; each level shifting and shaping network is correspondingly connected to the grid electrode of one synchronous bootstrap switch, the input end of each level shifting and shaping network is connected with the grid electrode driving signal of the adjacent next-stage power switch corresponding to the synchronous bootstrap switch, and the level shifting and shaping networks are used for generating grid electrode driving voltage for controlling the on and off of the synchronous bootstrap switches. According to the bootstrap driving circuit, the problem of driving voltage attenuation caused by multi-stage accumulation is solved, risks such as unexpected charging, energy recharging and misconduction are avoided, and the reliability of the bootstrap driving circuit is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of power electronics technology, and in particular to a bootstrap driving circuit, control method and converter. Background Technology

[0002] In multilevel converters and hybrid switching converters, the source reference potential of the upper-level power switch changes rapidly with the switching state. The corresponding gate driver needs to employ a floating power supply to achieve reliable potential isolation. Existing technologies commonly use a cascaded bootstrap scheme: a single low-voltage bootstrap power supply charges the bottom-level bootstrap capacitor, and cascaded diodes transfer energy upwards stage by stage to charge the upper-level bootstrap capacitors. This avoids configuring independent isolation power supplies for each floating driver, effectively reducing system size and cost.

[0003] However, traditional cascaded bootstrap schemes have the following significant drawbacks: First, since each stage's charging path includes the forward voltage drop of the bootstrap diode, this voltage drop accumulates stage by stage in multi-stage cascaded applications, leading to a significant decrease in the actual charging voltage of the upper-level bootstrap capacitor. This results in insufficient power supply margin for the upper-level gate driver, thereby reducing the reliability of the drive. Second, for gallium nitride (GaN) power switches with extremely fast switching speeds and extremely high switching node voltage change rates (dv / dt), traditional diode structures not only fail to suppress the risk of false turn-on caused by high dv / dt transients, but may also cause undesirable charging, energy backflow, and overcharging phenomena during high-frequency switching, severely limiting the reliability of the drive. Summary of the Invention

[0004] This invention provides a bootstrap driving circuit, a control method, and a converter, aiming to solve the problem of low reliability in existing bootstrap driving circuits.

[0005] In a first aspect, embodiments of the present invention provide a bootstrap driving circuit applied to a converter, the converter including a plurality of power switches connected in series, each power switch corresponding to a gate driver, the bootstrap driving circuit including: Self-booting power supply; Multiple cascaded bootstrap capacitors, with the first end of each bootstrap capacitor connected to the bootstrap node corresponding to the gate driver and the second end connected to the source reference node corresponding to the power switch. Multiple synchronous bootstrap switches are disposed between two adjacent bootstrap nodes to charge the upper-level bootstrap capacitor when it is turned on. Multiple level shifting and shaping networks are provided, each of which is connected to the gate of a synchronous bootstrap switch. Its input is connected to the gate drive signal of the power switch in the next adjacent stage corresponding to the synchronous bootstrap switch, and is used to generate the gate drive voltage that controls the synchronous bootstrap switch to turn on and off.

[0006] Secondly, embodiments of the present invention also provide a control method for a bootstrap driving circuit, comprising: After detecting that the switching node voltage of the adjacent next-stage power switch has completed the transition from high level to low level, the corresponding synchronous bootstrap switch is controlled to turn on after a first preset time window delay. Before the voltage of the switching node is detected to transition from low to high level, the synchronous bootstrap switch is controlled to turn off in advance by a second preset time window.

[0007] Thirdly, embodiments of the present invention also provide a converter, comprising: Multiple power switches connected in series, including at least one gallium nitride power switch; Multiple gate drivers, each of which is connected to the gate terminal of one of the power switches; As described in the first aspect above, in the bootstrap driving circuit, each bootstrap node of the bootstrap driving circuit is connected to the power supply terminal of the corresponding gate driver. This invention provides a bootstrap driving circuit, a control method, and a converter. The bootstrap driving circuit includes: a bootstrap power supply; multiple cascaded bootstrap capacitors, each bootstrap capacitor having a first terminal connected to a bootstrap node corresponding to the gate driver and a second terminal connected to a source reference node corresponding to the power switch; and multiple synchronous bootstrap switches disposed between adjacent bootstrap nodes for charging the upper-level bootstrap capacitor when it is turned on. Multiple level shifting and shaping networks are used, each connected to the gate of a corresponding synchronous bootstrap switch. The input of each network is connected to the gate drive signal of the adjacent next-stage power switch corresponding to the synchronous bootstrap switch, generating the gate drive voltage that controls the switching on and off of the synchronous bootstrap switch. In this embodiment, the gate drive voltage for switching the synchronous bootstrap switch on and off is generated by the gate signal of the next-stage power switch through the level shifting and shaping networks. Its on-state voltage drop is much lower than the forward voltage drop of a diode, solving the problem of drive voltage attenuation caused by multi-stage accumulation. Simultaneously, because the input of the level shifting and shaping network is connected to the gate drive signal of the adjacent next-stage power switch corresponding to the synchronous bootstrap switch, precise timing control can be achieved, ensuring that the synchronous bootstrap switch only turns on within a safe charging window, actively avoiding high dv / dt transients at the switching node. This avoids risks such as undesirable charging, energy backflow, and false turn-on, improving the reliability of the bootstrap drive circuit. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 Circuit diagram of the main power circuit of a four-level flying capacitor multilevel buck converter and the traditional diode-type cascaded bootstrap power supply; Figure 2 A circuit diagram of a bootstrap driving circuit in a cascaded bootstrap structure provided by an embodiment of the present invention; Figure 3 A flowchart illustrating a control method for a bootstrap driving circuit provided in an embodiment of the present invention; Figure 4 A schematic diagram of a converter provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the key timing waveforms between the synchronous bootstrap switch and the power switch. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0012] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0013] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0014] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0015] This invention proposes a bootstrap driving circuit, control method, and converter to address the low reliability of existing bootstrap driving circuits. In this embodiment, the gate drive voltage for the synchronous bootstrap switch to turn on and off is generated by the gate signal of the next-stage power switch through a level shifting and shaping network. Its on-state voltage drop is much lower than the forward voltage drop of the diode, solving the problem of drive voltage attenuation caused by multi-stage accumulation. At the same time, since the input of the level shifting and shaping network is connected to the gate drive signal of the adjacent next-stage power switch corresponding to the synchronous bootstrap switch, precise timing control can be achieved, ensuring that the synchronous bootstrap switch only turns on within a safe charging window, actively avoiding high dv / dt transients at the switching node. This avoids risks such as undesirable charging, energy backflow, and false turn-on, thus improving the reliability of the bootstrap driving circuit.

[0016] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0017] Please see Figure 1 , Figure 1 The circuit diagram shows the main power circuit of a four-level flying capacitor multilevel buck converter and the circuit diagram of a traditional diode-type cascaded bootstrap power supply. Figure 1 The multilevel buck converter in the middle includes a DC input terminal. V in Series power switches S 1. S 2. S 3. S 4. S 5. S 6. Gate drivers GD for each power switch, cascaded bootstrap nodes BST1~BST5, and bootstrap power supply. V P Bootstrap capacitor C 1~ C 6 and cascaded bootstrap diodes D 1~ D 5. It also includes two flying capacitors. C fly1 , C fly2 Output filter inductor L Output capacitor C and load R The intermediate nodes are respectively N 1~ N 5; Flying capacitor C fly1 and C fly2 This is used to establish a multi-level potential platform and achieve voltage balance under different switching states. Figure 1 In the process, the connection terminals of the flying capacitors are led out to the switching nodes to form several discrete potentials for four-level output; S The upper end of 6 is connected to the input terminal. V in , S The lower end of 1 is connected to ground; to avoid ambiguity, Figure 1 The intermediate node of a series power switch is uniformly defined as follows: S 1 and S The first intermediate node is between 2. N 1, S 2 and S The interval between 3 is the second intermediate node. N 2, S 3 and S The third intermediate node is between 4. N 3, S 4 and S The fourth intermediate node is between 5. N 4, S 5 and S The fifth intermediate node is between 6. N 5. Each power switch S kEach of the (k=1~6) nodes is equipped with a corresponding gate driver (GD) to output the gate drive signal for the corresponding power switch. Since the potential of the upper-level switch node changes with the switch state, the upper-level switch (e.g., S 2~ S 6) The power supply and reference point of the corresponding driver are floating potentials, and a floating power supply method is required to implement gate driving.

[0018] like Figure 1 As shown, to provide floating power to the upper-level floating gate driver, Figure 1 The cascaded bootstrap power supply structure includes: bootstrap power supply V P Bootstrap capacitor C 1~ C 6. and cascaded bootstrap diodes D 1~ D 5. Bootstrap power supply V P Provides power to the low-voltage drive, used for the lowest-level driver and the first-stage bootstrap capacitor. C 1. Provides charging power, including the first-stage bootstrap capacitor. C 1 with power switch S The reference node of 1 constitutes the power supply loop for the first-stage driver, that is... C One end of 1 is connected to the first power supply node of the driver (denoted as ). BST 1), the other end is connected to the ground (or to...) S 1. Reference point for source and electrode potential (i.e., the reference point for the same potential), thus providing S The driver in stage 1 provides the supply voltage to the reference ground. The second-stage bootstrap capacitor... C 2 is used for power switches S The driver 2 provides floating power, with one end connected to the power supply node of the second-stage driver. BST 2. The other end is connected to the node. N 1 (i.e.) S (Source node of 2). Diode D 1 is connected between the first-level power supply node and the second-level power supply node, and is used to supply power when charging conditions are met. C 2. Charging: Preferably, D The anode of 2 is connected to the first-stage power supply node. BST 1. Cathode connected to BST 2, so that when the first-level power supply node is relative to BST When the potential is higher, D 2. Forward conduction, thus leading to C 2. Charging. Similar to the second stage, the third to sixth stages each include a bootstrap capacitor. C 3~ C 6 and cascaded diodes D 3 ~D 6. This cascaded bootstrap structure transmits the drive power supply voltage step by step in a "next-level → previous-level" manner, so that the upper-level floating driver can obtain power without an independent isolated power supply.

[0019] However, due to the forward voltage drop of the bootstrap diode, and the accumulation of this voltage drop during cascading, the driving voltage of each stage... V BSTk The calculation formula is: (1); Among them, in formula (1) V P This is the bootstrap power supply voltage. V Di Let be the forward voltage drop of the i-th stage cascaded bootstrap diode. From equation (1), it can be seen that as the number of stages increases, V BSTk The effective driving voltage gradually decays, leading to high-d voltage in the upper layers (especially those using gallium nitride devices). v / d t The switch cannot obtain sufficient gate drive margin, which significantly reduces the charging voltage of the upper bootstrap capacitor.

[0020] Please see Figure 2 , Figure 2 This is a circuit diagram of a bootstrap driving circuit in a cascaded bootstrap structure provided by an embodiment of the present invention. Figure 2The bootstrap driving circuit is applied to a converter, which includes multiple power switches connected in series. Each power switch corresponds to a gate driver. The bootstrap driving circuit includes a bootstrap power supply, multiple cascaded bootstrap capacitors, multiple synchronous bootstrap switches, and multiple level shifting and shaping networks. The first terminal of each bootstrap capacitor is connected to the bootstrap node corresponding to the gate driver, and the second terminal is connected to the source reference node corresponding to the power switch. Multiple synchronous bootstrap switches are disposed between adjacent bootstrap nodes to charge the upper-level bootstrap capacitor when it is turned on. Each level shifting and shaping network is connected to the gate of a synchronous bootstrap switch, and its input terminal is connected to the gate drive signal of the adjacent next-level power switch corresponding to the synchronous bootstrap switch to generate a gate drive voltage that controls the synchronous bootstrap switch to turn on and off. It should be noted that the synchronous bootstrap switch is a SiN-channel MOSFET, with its source connected to the next-stage bootstrap node and its drain connected to the current-stage bootstrap node. The forward conduction direction of its internal body diode is consistent with the charging direction from the next-stage bootstrap node to the current-stage bootstrap node. The level shifting and shaping network includes a coupling capacitor, a first resistor, a second resistor, a first diode, and a second diode. The coupling capacitor couples the gate drive signal transition of the adjacent next-stage power switch to the gate of the corresponding synchronous bootstrap switch. The first resistor is connected between the gate of the corresponding synchronous bootstrap switch and a fixed reference potential. The second resistor is connected in series between the coupling capacitor and the gate of the corresponding synchronous bootstrap switch. The anode of the first diode is connected to the fixed reference potential, and the cathode is connected at the connection point of the coupling capacitor and the second resistor. The second diode is connected in parallel with the second resistor. It should also be noted that the fixed reference potential is the source potential of the adjacent next-stage power switch corresponding to the synchronous bootstrap switch. The positive output terminal of the bootstrap power supply is connected to the lowest-level bootstrap node, the negative output terminal is connected to the source reference node of the lowest-level power switch, and the lowest-level bootstrap node is connected to the first terminal of the lowest-level bootstrap capacitor.

[0021] Please continue reading. Figure 2 ,exist Figure 2 The circuit structure that replaces the existing cascaded bootstrap diodes with synchronous bootstrap switches, and the level shifting and shaping network for driving the synchronous bootstrap switches, the level shifting and shaping network including coupling capacitors. C First diode D 1. First resistor R 1. Second resistor R 2 and second diode D 2; The first-stage bootstrap capacitor is also shown. C 1. Second-stage bootstrap capacitor C 2. Corresponding gate driver GD and power switchS 1. S 2 and input terminal V in The connections between levels allow this structure to be cascaded and extended to higher levels. Take level 2 as an example (…). S 2) bootstrap power supply), which will connect the second diode originally located between the next stage power supply node and the current stage bootstrap node. D Replace 2 with a synchronous bootstrap switch M2. The synchronous bootstrap switch M2 is connected in series between the next-stage power supply node and the current-stage bootstrap node, with its source connected to the next-stage drive power supply node (e.g., V P or equivalent BST 1. Power supply node), the drain is connected to the upper node of the bootstrap capacitor of this stage (i.e. BST 2. This node is also S The gate driver power supply terminal of 2), the body diode direction is consistent with the original cascaded diode direction, that is, the current is allowed to naturally conduct from the "next stage power supply node to the current stage bootstrap node", so as to ensure that even if the synchronization control has not been established during the startup phase, the bootstrap capacitor can be initially charged through the body diode.

[0022] For each level of the upper level (corresponding to) S 3~ S The bootstrap power supply of 6 uses the same topology: each stage of the original cascaded diodes D k Replace them with synchronous NMOS M respectively k Connect its source to BST k-1 Drain connection BST k The body diode is kept aligned with the original diode, thus forming a "step-by-step synchronous bootstrapping" power supply chain. After this replacement, the original diode-fixed voltage drop charging path becomes a synchronous NMOS channel conduction path, with its voltage drop mainly determined by I×R. DS(on) The decision is made, where I represents the current flowing through the synchronous bootstrap switch; R DS(on) It represents the resistance when the synchronous bootstrap switch is turned on; it can significantly reduce the cumulative cascade voltage drop, which is particularly beneficial for the upper-layer GaN power switch to obtain sufficient gate drive voltage margin.

[0023] In this embodiment, the bootstrap driving circuit does not introduce an additional isolated power supply, but instead utilizes the adjacent lower-level power switch (e.g., S 1) The gate drive signal is used to generate the gate drive of the synchronous NMOS through a level shifting and shaping network, thereby enhancing the conduction of the synchronous NMOS during the "charge-enabled window". M For example, in case 2, its gate drive network consists of D 1. C , R 1. R 2.D It consists of 2 components, which are used to switch the power. S The gate drive signal of 1 (output from the lower-level driver GD) is coupled to the gate node of the synchronous NMOS to achieve level rise; when S When the gate drive signal of 1 experiences a rising / falling edge transition, C The transition is injected into the gate of the synchronous NMOS in the form of charge, causing the gate to rise positively relative to the source, thereby satisfying the synchronous NMOS turn-on condition. D 1 is a charging / reset diode. D 1 is used to provide a unidirectional charging and reset path for the coupled network. When the low-side drive signal is low, it... M The gate node of 2 is pulled back to the safe reference to ensure that the starting point of each cycle is consistent, so that... C The gate is pre-charged when the lower-level drive signal is in a steady state, thus effectively raising the gate during the next transition; simultaneously, it limits the reverse sway of the gate node, improving turn-off reliability. (Resistor) R 1. It serves to discharge / prevent gate descent, ensuring that the gate does not remain suspended for an extended period under conditions of switch stoppage or abnormal operation, thus preventing false continuity. C Provides a controlled discharge path, preventing the gate platform from drifting into hazardous areas during long-term operation due to parasitic coupling. Second resistor R 2 serves as a "delayed turn-on" mechanism, preventing the gate node from immediately reaching its position when the low-side drive just flips, but instead... R 2. Charge the coupled network to create a designable delay: T on,delay Mainly composed of R 2* C eq Decision, among which C eq Gate equivalent capacitance (including) M 2 input capacitors C iss as well as C (Equivalent quantity coupled to the gate). Second diode. D 2. Form a "fast shutdown" bypass channel when the low-side drive is pulled down, or V S1 Will rise (high d) v / d t )Before, D 2. Provides a low-resistance, fast-release path for the gate charge, bypassing... R 2, make M 2. Fast turn-off. This allows for a gate drive power supply closer to the target value for the upper-layer GaN power switch in the multilevel converter, improving efficiency and reliability.

[0024] Please refer to Figure 3, Figure 3 A flowchart illustrating a control method for a bootstrap driving circuit provided in an embodiment of the present invention is shown below. Figure 3 As shown, the control method of the bootstrap driving circuit includes steps S110-S120.

[0025] S110. After detecting that the switching node voltage of the adjacent next-stage power switch has completed the transition from high level to low level, control the corresponding synchronous bootstrap switch to turn on after a first preset time window. S120. Before the voltage of the switching node is detected to transition from low level to high level, the synchronous bootstrap switch is controlled to turn off in advance by a second preset time window.

[0026] In this embodiment, the length of the first preset time window is greater than the ringing duration of the falling edge of the switching node voltage; the length of the second preset time window ensures that the synchronous bootstrap switch remains off during the high voltage change rate period of the rising edge of the switching node voltage. Specifically, when the power switch S 1. When in the off state, V S1 That is, the high-level state, synchronous bootstrap switch. M 2 of V GS,M2 pass D 2, R 1, D 1. Pull back to low level, therefore M 2 is in the off state, avoiding [the situation where] V S1 A backfeed / false charge path is formed during the high level or rising edge. When V GS,S1 When it begins to rise, the power switch S 1 conduction to V S1 Pull it down, but at this time V S1 There are often falling edge spikes / ringing / negative pressure, which is undesirable. M 2. It conducts immediately, therefore through R 2* C eq form T on,delay (First preset time window) makes V GS,M2 Latency increases. Once the node stabilizes, M 2. Turn on the drive power supply C 2. Charging, after the delay ends, V GS,M2 Rise to the turn-on threshold voltage M 2. Enhanced conduction: The charging path becomes a low-voltage-drop channel. C2 was quickly charged to near V P The potential after deducting the synchronous NMOS on-state voltage drop, thereby improving S 2. Effective driving voltage. When S 1. Imminent shutdown or upper-level commutation leading to V S1 When it is about to rise, it must be turned off first. M 2, D 2. Provides a fast discharge bypass to achieve T off,pre (This is the second preset time window, to shut off the margin in advance) to avoid backfilling / overcharging / high d v / d t Misleading.

[0027] To balance low-dropout charging, suppress mis-conduction, and adapt to high-speed GaN power switches v / d t Characteristics of the above-mentioned components D 1. C , R 1. R 2. D The two parameters are determined according to the following principles. For ease of explanation, the equivalent gate input capacitance of the synchronous NMOS is denoted as... C eq (This can be obtained from the device input capacitance or by calculating the gate charge), at the target on-gate source voltage. V GS,on The gate charge below is denoted as Q g,sync The amplitude of the coupling drive signal transition is denoted as Δ. V drv Coupling capacitor C Gate charge constraints must be met. C To provide sufficient gate charge, the following conditions must be met: (2); In formula (2), k g The margin factor is typically taken as 1.5~3; considering the capacitive voltage divider formed by the gate equivalent capacitance and the coupling capacitance, the gate rise amplitude approximately satisfies: (3); In formula (3), to improve coupling efficiency and reduce parasitic sensitivity, the preferred choice is to take... C ≥ (5~10) C eq The synchronous NMOS delay turn-on time is mainly determined by the equivalent time constant of the gate charging path, and the second resistor... R The size of 2 determines M 2. Delayed opening time: (4); In formula (4) α It is usually taken between 0.7 and 2.2. Meanwhile, M 2. The delayed activation time must meet the requirements of allowing T on,delay Greater than V S1 The time required for the falling edge ringing to decay to the safety threshold. Diode. D 1. D 2. It is preferable to use fast devices with low junction capacitance and low reverse recovery charge to reduce high d v / d t Under certain conditions, there is a risk of charge injection and false triggering; its reverse withstand voltage should cover the maximum potential difference that may occur in this stage (including transient margin). D 2. Used to provide a fast turn-off bypass channel to quickly release the gate charge within the inhibit window, meeting the early turn-off requirement. Resistor R 1. It serves as a gate discharge / anti-floating device, ensuring reset under shutdown or extreme duty cycle conditions, while preventing the conduction platform from descending too quickly. Therefore, it needs to meet the following requirements. (5); Among them, ensuring the coupling capacitance C Energy storage in synchronous bootstrap switch M 2. During conduction (conduction time of the low-side switch conduction interval) t on,M2 ) Non-discharge resistor R 1. Significantly consumes power, maintaining the stability of the gate drive signal. C Energy storage will not be R 1. Obvious leakage.

[0028] Please refer to Figure 4 , Figure 4 A schematic diagram of a converter provided in an embodiment of the present invention is shown below. Figure 4 As shown, the converter includes multiple power switches, multiple gate drivers, and the aforementioned bootstrap driving circuit connected in series. At least one of the power switches is a gallium nitride (GaN) power switch. Each gate driver is connected to the gate terminal of one of the power switches. Each bootstrap node of the bootstrap driving circuit is connected to the power supply terminal of the corresponding gate driver. It should be noted that the bootstrap driving circuit provides floating power to all gate drivers except the lowest-level power switch. It should also be noted that the converter is a multilevel converter or a hybrid switching converter.

[0029] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the key timing waveforms between the synchronous bootstrap switch and the power switch. Figure 5The switching node voltage is given in the figure. V S1 Power switch S Gate-source voltage of 1 V GS,S1 and synchronous bootstrap switch M 2 Gate-source voltage V GS,M2 The relative timing relationship is indicated, and the delayed turn-on time of the synchronous bootstrap switch is marked. T on,delay With early shutdown time T off,pre This is used to explain the control principle of the synchronous bootstrap switch being turned on within the allowable charging window and turned off before the switching node transition. Specifically, Figure 5 The curve in the figure represents the power switch S 1. Power switch under ideal conditions during turn-on and turn-off operations S 1. Switching node voltage V S1 Drive voltage V GS,S1 and synchronous bootstrap switch M 2 driving voltage V GS,M2 The changes. S 1. Just opened. V S1 It is rapidly changing from high to low, accompanied by ringing / negative pressure spikes. If at this time... M 2. Immediate conduction can lead to the following problems: uncontrolled charging current spikes during transients; and even short-term loops / false charging in some topologies; d v / d t Coupling causes gate anomalies. Therefore V GS,M2 Deliberate comparison V GS,S1 It rises a little later, that's it. T on,delay .when V S Before rising from low to high, if M If step 2 is still conducting, the following problems will occur: C 2. It may cause current to flow back to the downstream level; V BSTk It may be abnormally pulled, causing high-side drive overvoltage / undervoltage; high d v / d t pass M Parasitic capacitance coupling at 2 increases the risk of false triggering. Therefore... V GS,M2 To V S A rapid pullback to the support level before an upward move, allowing for advance preparation. Toff,pre .

[0030] like Figure 5 As shown, synchronous bootstrap switch M 2 Gate-source voltage V GS,M2 Gate-source voltage of power switch (or adjacent lower-level switch) V GS,S1 The specific windowed timing relationship between them is as follows: Delayed activation rules: When V S1 After the transition from high level to low level, M 2. It does not conduct immediately, but is delayed. T on,delay Only then was it allowed V GS,M2 Rise to the conduction platform to avoid falling edge ringing, negative voltage spikes, and high dv / dt intervals. For example... Figure 5 , t M2↑ For synchronous bootstrap switch M 2 Gate-source voltage V GS,M2 The moment when the voltage rises to the conduction threshold voltage ( M 2. The moment when it is fully opened. For the adjacent next stage power switch S 1 Switching node voltage V S1 The moment after the transition from high level to low level is completed: (6); Early shutdown rules: In V S1 Before the transition from low to high level, M 2. Must be done at least in advance T off,pre Turn off, so that it is on the rising edge at height d v / d t The interval remains closed to suppress backflow and overfilling. t M2↓ For synchronous bootstrap switch M 2 Gate-source voltage V GS,M2 The moment when the voltage drops to the turn-off threshold voltage ( M 2. The moment of complete shutdown. For the adjacent next stage power switch S 1 Switching node voltage V S1 The moment when the transition from low to high level begins: (7); It should be noted that during the converter startup phase or before synchronization control is established, synchronous NMOS... M k The body diode provides a unidirectional pre-charge path, allowing the upper bootstrap capacitor to obtain an initial voltage; once the control conditions meet the allowable window, it is driven by the gate-coupled network. M k It enters enhanced conduction mode, taking over the main charging current to reduce losses and voltage drop.

[0031] In summary, this embodiment utilizes existing cascaded bootstrap diodes (e.g. D 1~ D 5) Replace with controlled synchronous SiNMOS switches (e.g.) M 2~ M 6), and through a level shifting and shaping network composed of diodes, resistors, and capacitors (e.g. D 1. C , R 1. R 2. D 2) Implement windowed conduction control of the synchronous bootstrap switch, ensuring that the synchronous bootstrap switch only enhances conduction within the bootstrap-allowed charging window and turns off before switching node transitions and power switch commutation. Compared with existing cascaded bootstrap diode power supply methods, this has at least the following advantages: (1) When the synchronous bootstrap switch is turned on, the voltage drop in the charging path changes from the fixed forward voltage drop of the diode to the channel conduction voltage drop. I × R DS(on) This significantly reduces the cumulative cascade voltage drop and increases the upper-layer bootstrap power supply voltage margin, thereby enhancing the ability of the upper-layer GaN power switch to obtain sufficient gate drive voltage. (2) By setting a delayed activation T on,delay With early shutdown T off,pre The timing rules ensure that the synchronous bootstrap switch avoids ringing / negative voltage spikes on the falling edge and high d on the rising edge of the switching node. v / d t Transient, suppresses the risks of misleading conduction, unintended charging, backfeedback and overcharging, and improves high-d v / d t Robustness and reliability in various environments; (3) No separate isolated power supply is required for each level of floating driver. It can provide floating gate drive power supply in a cascaded manner in topologies such as multilevel converters and hybrid switching converters, which reduces system complexity and volume cost, while improving efficiency and stability. (4) In this embodiment, Si MOSFET is used as a synchronous bootstrap switch to replace the bootstrap diode system. The system is mature, has a wide selection range, and the gate drive and protection design is easier to implement in engineering. The cost is lower and the supply chain is more stable.

[0032] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A bootstrap driving circuit applied to a converter, the converter comprising a plurality of power switches connected in series, each power switch corresponding to a gate driver, characterized in that, The bootstrap driving circuit includes: Self-booting power supply; Multiple cascaded bootstrap capacitors, with the first end of each bootstrap capacitor connected to the bootstrap node corresponding to the gate driver and the second end connected to the source reference node corresponding to the power switch. Multiple synchronous bootstrap switches are disposed between two adjacent bootstrap nodes to charge the upper-level bootstrap capacitor when it is turned on. Multiple level shifting and shaping networks are provided, each of which is connected to the gate of a synchronous bootstrap switch. Its input is connected to the gate drive signal of the power switch in the next adjacent stage corresponding to the synchronous bootstrap switch, and is used to generate the gate drive voltage that controls the synchronous bootstrap switch to turn on and off.

2. The bootstrap driving circuit according to claim 1, characterized in that, The synchronous bootstrap switch is a SiN channel MOSFET, with its source connected to the next stage bootstrap node and its drain connected to the current stage bootstrap node. The forward conduction direction of its internal body diode is consistent with the charging direction from the next stage bootstrap node to the current stage bootstrap node.

3. The bootstrap driving circuit according to claim 1, characterized in that, The level shifting and shaping network includes: Coupling capacitors are used to couple the gate drive signal of the adjacent next-stage power switch to the gate of the corresponding synchronous bootstrap switch. The first resistor is connected between the gate of the corresponding synchronous bootstrap switch and the fixed reference potential; The second resistor is connected in series between the coupling capacitor and the gate of the corresponding synchronous bootstrap switch; The first diode has its anode connected to the fixed reference potential and its cathode connected at the connection node between the coupling capacitor and the second resistor. The second diode is connected in parallel with the second resistor.

4. The bootstrap driving circuit according to claim 3, characterized in that, The fixed reference potential is the source potential of the adjacent next-stage power switch corresponding to the synchronous bootstrap switch.

5. The bootstrap driving circuit according to any one of claims 1-4, characterized in that, The positive output terminal of the bootstrap power supply is connected to the lowest-level bootstrap node, the negative output terminal is connected to the source reference node of the lowest-level power switch, and the lowest-level bootstrap node is connected to the first terminal of the lowest-level bootstrap capacitor.

6. A control method for a bootstrap driving circuit, applied to the bootstrap driving circuit as described in any one of claims 1-5, characterized in that, include: After detecting that the switching node voltage of the adjacent next-stage power switch has completed the transition from high level to low level, the corresponding synchronous bootstrap switch is controlled to turn on after a first preset time window delay. Before the voltage of the switching node is detected to transition from low to high level, the synchronous bootstrap switch is controlled to turn off in advance by a second preset time window.

7. The method according to claim 6, characterized in that, The length of the first preset time window is greater than the ringing duration of the falling edge of the switching node voltage.

8. The method according to claim 6, characterized in that, The length of the second preset time window ensures that the synchronous bootstrap switch remains off during the high voltage change rate period of the rising edge of the switching node voltage.

9. A converter, characterized in that, include: Multiple power switches connected in series, including at least one gallium nitride power switch; Multiple gate drivers, each of the gate drivers being connected to the gate terminal of one of the power switches; The bootstrap driving circuit according to any one of claims 1 to 5, wherein each bootstrap node of the bootstrap driving circuit is connected to the power supply terminal of the corresponding gate driver.

10. The converter according to claim 9, characterized in that, The bootstrap drive circuit provides floating power to all the gate drivers except for the lowest-level power switch.

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