Hybrid switching converter with single inductor and multiple outputs and control method thereof

Abstract

The invention discloses a single-inductor multi-output hybrid switching converter and a control method thereof, which are used for converting an input voltage into a first output voltage and a second output voltage. The hybrid switching converter includes: a sub-switching converter that converts an input voltage into a relay voltage; the first output switch and the second output switch conduct the relay voltage in a first inductance period and a second inductance period respectively to generate a first output voltage and a second output voltage. The sub-switching converter comprises a switching capacitance voltage division circuit which controls a plurality of switches through a plurality of groups of pulse width modulation signals so as to respectively generate two divided voltages with different levels in different inductance periods so as to supply the divided voltages to inductors in the sub-switching converter; and a control circuit which generates a pulse width modulation signal, controls the plurality of switches and the output switch in a time-sharing manner, and adjusts the output voltage to a target voltage based on the output voltage feedback signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a hybrid switching converter with single inductor multiple outputs and its control method, in particular to a hybrid switching converter with single inductor multiple outputs capable of generating multiple output voltages and its control method. BACKGROUND

[0002] Nowadays, data centers, servers, electric vehicles, and various mobile devices often require power converters with multiple output voltages, and in the case of increasingly stringent space and heat dissipation environments, how to design high power density and high efficiency power converters becomes an important research topic. Traditionally, the common solution is to use multiple power converter architectures, which configure multiple independent inductors and switches to support different outputs.

[0003] In the prior art, as shown in a switching converter 10 with multiple outputs, multiple outputs are provided by different combinations of switches and inductors. Figure 1 In the prior art, as shown in a switching converter 10 with multiple outputs, multiple outputs are provided by different combinations of switches and inductors. Figure 1 In the prior art, as shown in a switching converter 10 with multiple outputs, multiple outputs are provided by different combinations of switches and inductors. In the input part, input capacitor Cin1 is coupled to the input end of the first buck converter, and input capacitor Cin2 is coupled to the input end of the second buck converter, to filter out voltage ripple on the input side. In the output part, output capacitor Co1 is coupled to the output end of the first buck converter to stabilize the output voltage of the first buck converter, and output capacitor Co3 is coupled to the output end of the second buck converter to stabilize the output voltage of the second buck converter; at the same time, output capacitor Co2 is coupled to the first output voltage Vout1, and output capacitor Co4 is coupled to the second output voltage Vout2, to further reduce output noise and stabilize each output voltage. It is worth noting that output switch Q5 is coupled between the first buck converter and the first output voltage Vout1, to convert the output voltage of the first buck converter to the first output voltage Vout1; output switch Q6 is coupled between the second buck converter and the second output voltage Vou2, to convert the output voltage of the second buck converter to the second output voltage Vout2.

[0004] In the prior art, as shown in a switching converter 10 with multiple outputs, multiple outputs are provided by different combinations of switches and inductors. Figure 1In the shown multi-output switching converter 10, each of the switches Q1-Q4 in each of the buck converters needs to be able to withstand the highest value of the input voltage Vin to ensure stable operation. Since the input voltage Vin can be quite high, the voltage withstand capability requirement of the switches Q1-Q4 is increased, which means that the on-resistance of the switches Q1-Q4 is higher and the on-loss is larger. In addition, in order to be able to perform energy conversion at high voltage, the conventional buck converter also needs to be equipped with larger inductors L1, L2 to cope with the voltage difference between the input voltage Vin and the first output voltage Vout1 and the second output voltage Vout2. The volume and cost of the inductors L1, L2 are thus increased, making it difficult to further reduce the overall power supply volume or improve the power density.

[0005] Since each output needs an independent buck converter and inductor, higher challenges are posed to the system layout and heat dissipation. In order to ensure stable and long-term reliability in a high-temperature environment or a limited heat dissipation space, additional heat dissipation design or higher specification components are often needed, further increasing the cost and complexity.

[0006] In multi-voltage output applications, the conventional method needs to repeatedly use multiple power converters. If the system wants to support multiple groups of different voltage outputs at the same time (such as USB ports, system core voltage, peripheral power supply voltage, etc.), the number of devices, the complexity of wiring are significantly increased, and it is not easy to integrate into a single chip (Monolithic) or module.

[0007] Therefore, in order to solve the above problems and at the same time achieve the goals of high density, high efficiency and easy integration, the present application proposes a hybrid switching converter with single-inductor multi-output and a control method thereof, so as to greatly reduce the voltage stress of the switching elements and the inductor requirement under the premise of maintaining stable output and high efficiency, and further improve the integration and reliability of the system. SUMMARY

[0008] In one viewpoint, the present invention provides a hybrid switching converter with a single inductor and multiple outputs for converting an input voltage into a first output voltage and a second output voltage. The hybrid switching converter with a single inductor and multiple outputs includes: a sub-switching converter for converting the input voltage into a relay voltage; a first output switch for conducting the relay voltage during a first inductor cycle according to a first time-division signal to generate the first output voltage; and a second output switch for conducting the relay voltage during a second inductor cycle according to a second time-division signal to generate the second output voltage; wherein the sub-switching converter includes: a switching capacitor voltage divider circuit, in... During the first inductor cycle, a plurality of switches are controlled according to a first set of pulse width modulation signals to perform a switching capacitor operation, thereby converting a first voltage into a first group of voltages at two different levels. During the second inductor cycle, the plurality of switches are controlled according to a second set of pulse width modulation signals to perform a switching capacitor operation, thereby converting the first voltage into a second group of voltages at two different levels. An inductor has a first terminal coupled to the switching capacitor voltage divider circuit and a second terminal coupled to a second voltage. During the first inductor cycle, according to the first set of pulse width modulation signals, the first terminal of the inductor switches between two different levels of the first group of voltages. During the second inductor cycle, according to the second set of pulse width modulation signals, the first terminal of the inductor switches between two different levels of the second voltage group; and a control circuit is used to generate the first set of pulse width modulation signals, the second set of pulse width modulation signals, the first time-division signal, and the second time-division signal to time-division control the plurality of switches, the first output switch, and the second output switch, and periodically perform magnetization and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage, and periodically generate the first output voltage and the second output voltage accordingly during the first inductor cycle and the second inductor cycle. The second output voltage; wherein the first voltage and the second voltage correspond to one of the input voltage and the other of the relay voltage, respectively; wherein the control circuit is further configured to, during the first inductor cycle, adjust the first output voltage to a first target voltage based on a first feedback signal related to the first output voltage, and during the second inductor cycle, adjust the second output voltage to a second target voltage based on a second feedback signal related to the second output voltage; wherein the hybrid switching converter with single inductor multiple outputs operates in a boundary conduction mode (BCM) or a discontinuous conduction mode (DCM) during the first inductor cycle and the second inductor cycle.

[0009] In another viewpoint, the present invention provides a control method for a hybrid switching converter with a single inductor and multiple outputs, comprising: converting an input voltage into a relay voltage; according to a first time-division signal, during a first inductor cycle, turning on a first output switch to output the relay voltage as a first output voltage; and according to a second time-division signal, during a second inductor cycle, turning on a second output switch to output the relay voltage as a second output voltage; wherein, The steps of converting the input voltage into the relay voltage include: controlling multiple switches according to a first set of pulse width modulation signals during the first inductor cycle to perform switched capacitor operation, thereby converting a first voltage into a first group of voltages at two different levels; and controlling the multiple switches according to a second set of pulse width modulation signals during the second inductor cycle to perform switched capacitor operation, thereby converting the first voltage into a second group of voltages at two different levels; switching a first terminal of an inductor between two different levels of the first group of voltages according to the first set of pulse width modulation signals during the first inductor cycle; switching the first terminal of the inductor between two different levels of the second group of voltages according to the second set of pulse width modulation signals during the second inductor cycle; and using the first set of pulse width modulation signals and the second set of pulse width modulation signals to time-division control the multiple switches, thereby periodically stimulating the same inductor during the first inductor cycle and the second inductor cycle. Magnetizing and demagnetizing operations are performed to convert power between the first voltage and the second voltage; wherein the first voltage and the second voltage correspond to one of the input voltage and the other of the relay voltage, respectively; the first output switch and the second output switch are controlled in a time-division manner using the first time-division signal and the second time-division signal, and the first output voltage and the second output voltage are generated periodically in the first inductor cycle and the second inductor cycle, respectively; and in the first inductor cycle, the first output voltage is adjusted to a first target voltage based on a first feedback signal related to the first output voltage, and in the second inductor cycle, the second output voltage is adjusted to a second target voltage based on a second feedback signal related to the second output voltage; wherein the hybrid switching converter with single inductor multiple outputs operates in a boundary conduction mode (BCM) or a discontinuous conduction mode (DCM) in the first inductor cycle and the second inductor cycle.

[0010] In one embodiment, any two sequential cycles of the first inductor achieve a capacitor balance state, and any two sequential cycles of the second inductor achieve a capacitor balance state.

[0011] In one embodiment, the control circuit includes: a first error amplifier for amplifying the difference between the first output voltage feedback signal and a first reference signal to generate a first error amplification signal; a second error amplifier for amplifying the difference between the second output voltage feedback signal and a second reference signal to generate a second error amplification signal; and a modulation circuit for generating the first set of pulse width modulation signals according to the first error amplification signal during the first inductor cycle, and generating the second set of pulse width modulation signals according to the second error amplification signal during the second inductor cycle.

[0012] In one embodiment, the control circuit further includes a current sensing circuit to sense the inductor current and generate an inductor current signal, and the modulation circuit further generates the first set of pulse width modulation signals and the second set of pulse width modulation signals based on the inductor current signal.

[0013] In one embodiment, the current sensing circuit further generates a zero-current signal when the inductor current is zero; wherein the control circuit further includes a logic circuit for generating the first time-division signal and the second time-division signal based on the zero-current signal.

[0014] In one embodiment, the control circuit further includes a logic circuit for generating the first time-division signal and the second time-division signal according to a clock signal.

[0015] In one embodiment, the control circuit further includes a logic circuit for generating a time-division switching control signal, the first time-division signal, and the second time-division signal based on the first error amplification signal, the second error amplification signal, and a clock signal or a zero-current signal; wherein the time-division switching control signal, the first time-division signal, and the second time-division signal are all triggered by the clock signal or the zero-current signal, and the first time-division signal and the second time-division signal are out of phase with each other; wherein the logic circuit further determines whether the hybrid switching converter with single inductor multiple outputs enters a skip mode based on the difference between a first output current and a second output current; wherein in the skip mode, the difference between the number of times the first inductor cycle and the number of times the second inductor cycle are positively correlated with the difference between the first output current and the second output current within a unit cycle.

[0016] In one embodiment, the current sensing circuit includes a sensing resistor and a sensing capacitor, wherein the sensing resistor and the sensing capacitor are connected in series and coupled to the inductor. The inductor current is sensed by the voltage across the sensing capacitor to generate the inductor current signal. A time constant of the sensing resistor and the sensing capacitor is matched with a time constant of the inductor and the DC resistance of the inductor.

[0017] In one embodiment, the power supply between the first voltage and the second voltage is converted into a boost converter or a buck converter.

[0018] In one embodiment, when the switching capacitor voltage divider circuit and the inductor are configured in a buck configuration, the sub-switching converter further includes a boost switch coupled between the second terminal of the inductor and a reference potential, so that the hybrid switching converter with single inductor multiple outputs can select to operate in a boost conversion or a buck conversion according to the first target voltage or the second target voltage.

[0019] In one embodiment, the first set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the first voltage group, and the second set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the second voltage group.

[0020] In one embodiment, at the end of two consecutive first inductor cycles, a first start point of a first ramp signal is triggered, and at the end of two consecutive second inductor cycles, another first start point of the first ramp signal is triggered; wherein at the end of the first of the two consecutive first inductor cycles, a second start point of a second ramp signal is triggered, and at the end of the first of the two consecutive second inductor cycles, another second start point of the second ramp signal is triggered; wherein the modulation circuit compares the first ramp signal with the first error amplification signal and compares the second ramp signal with the first error amplification signal in the first inductor cycle to generate the first set of pulse width modulation signals; wherein the modulation circuit compares the first ramp signal with the second error amplification signal and compares the second ramp signal with the second error amplification signal in the second inductor cycle to generate the second set of pulse width modulation signals; wherein the two consecutive first inductor cycles and the two consecutive second inductor cycles are alternately arranged and repeated periodically in sequence.

[0021] This invention offers significant improvements over existing technologies, particularly in reducing system size, increasing efficiency, and enhancing power density. Firstly, compared to traditional methods requiring multiple buck converters (each with its own inductor and switch), the single-inductor configuration proposed in this invention supports multiple output voltage conversions, simplifying circuit design and significantly reducing the number of components required, thereby improving overall system integration and saving space. This innovation not only reduces the physical size of the system but also further improves power density and operating efficiency. Furthermore, since only a single inductor is needed, the inductor size in this system is significantly reduced compared to traditional multi-inductor operation, reducing space requirements and manufacturing costs, thus simplifying design and maintenance. Simultaneously, the switching capacitor voltage divider circuit effectively reduces the voltage stress applied to the inductor, reducing the need for high-voltage switching components and extending the overall system lifespan. Lower-voltage switching components can then be used, further reducing system cost. Finally, compared to the potentially high losses in traditional technologies, this technology helps improve system energy efficiency. In this case, the system's ZCS (Zero Current Switching) operating mode is actively utilized. These high-efficiency soft-switching technologies allow switching elements to switch near zero current, significantly reducing switching losses and electromagnetic interference (EMI), thereby improving overall operating efficiency. This not only optimizes the energy conversion process in existing systems but also demonstrates the energy-saving potential of this solution. Finally, this technology eliminates the need for additional capacitor balancing control circuitry, a challenge often encountered in traditional multi-capacitor systems. The absence of an additional control system to manage voltage balance in the flight capacitors greatly simplifies control circuit design, improves system stability and reliability, and reduces design complexity. In summary, this technology overcomes the limitations of existing technologies, providing a more efficient, compact, and easy-to-use solution.

[0022] Compared to traditional multi-output buck converters that require a separate inductor for each output, this design uses a single inductor to support multiple outputs simultaneously. By integrating inductor resources and a switched capacitor architecture, not only is the amount of bulky inductors reduced, but also the layout space wasted by stacking multiple inductors is avoided. As the overall system component count decreases, mutual interference between components is also reduced, thereby improving overall design efficiency and reliability.

[0023] In terms of power density, by retaining only one inductor and effectively reducing its value, the converter's size can be significantly reduced, contributing to an improvement in overall power density. Furthermore, this design employs a high-efficiency switching capacitor conversion mechanism, which minimizes conduction and switching losses during energy transfer, further enhancing system efficiency. Since high efficiency means less heat generation, it also simplifies the heat dissipation design, improving the overall system reliability and portability.

[0024] In terms of switching element design, hybrid switching converters significantly reduce voltage stress on the switches through boosting or voltage division. On the one hand, switches with lower withstand voltage ratings can be selected, reducing component cost and size; on the other hand, combined with zero-current or zero-voltage switching (ZCS / ZVS) technology, switching losses and electromagnetic interference during switching operation are also relatively reduced, which helps to further improve efficiency and suppress noise.

[0025] Furthermore, this design eliminates the need for additional flying capacitor balancing control circuitry in its system architecture. The switching capacitor's operation automatically achieves dynamic charge balance in each switching cycle, significantly simplifying design complexity and reducing hardware costs. Combining these advantages, this design not only achieves higher power density and efficiency but also reduces system complexity, thus demonstrating superior overall benefits compared to existing technologies in multi-output power supply applications.

[0026] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features and effects achieved by the present invention. Attached Figure Description

[0027] Figure 1 This is a circuit diagram showing a known switching converter with multiple outputs.

[0028] Figure 2A and Figure 2B This is a circuit block diagram showing a hybrid switching converter with a single inductor and multiple outputs according to an embodiment of the present invention.

[0029] Figure 3 show Figure 2A and Figure 2B A circuit diagram of a more specific embodiment of a hybrid switching converter 20 with single inductor and multiple outputs and a neutron switching converter 21.

[0030] Figure 4 show Figure 2A and Figure 2B A circuit diagram of a more specific embodiment of the control circuit 213 in a hybrid switching converter 20 with single inductor and multiple outputs.

[0031] Figure 5 show Figure 2A and Figure 2BA circuit diagram of another specific embodiment of the control circuit 213 in the hybrid switching converter 20 with single inductor and multiple outputs.

[0032] Figure 6 This is a circuit diagram of a ramp signal generation circuit for a display control circuit according to an embodiment of the present invention.

[0033] Figure 7 show Figure 2A and Figure 2B A circuit diagram of another specific embodiment of the control circuit 213 in the hybrid switching converter 20 with single inductor and multiple outputs.

[0034] Figure 8 This is a circuit diagram of the logic circuit of the display control circuit according to an embodiment of the present invention.

[0035] Figure 9 This is a circuit diagram of the current sensing circuit of the display control circuit according to an embodiment of the present invention.

[0036] Figure 10 This is a schematic diagram of the signal waveforms of a hybrid switching converter with a single inductor and multiple outputs, according to an embodiment of the present invention.

[0037] Figure 11 This is a schematic diagram of the signal waveforms of a hybrid switching converter with a single inductor and multiple outputs, according to an embodiment of the present invention.

[0038] Figure 12 This is a schematic diagram of the signal waveforms of a hybrid switching converter with a single inductor and multiple outputs, according to an embodiment of the present invention.

[0039] Figure 13 show Figure 2A and Figure 2B A circuit diagram of another more specific embodiment of the hybrid switching converter 20 with single inductor and multiple outputs and the neutron switching converter 21.

[0040] Figure 14A This is a schematic diagram of a display logic circuit according to an embodiment of the present invention.

[0041] Figure 14B This is a schematic diagram illustrating the time-sharing switch control signal Sab of a hybrid switching converter with single inductor and multiple outputs operating in normal mode according to an embodiment of the present invention.

[0042] Figure 14C This is a schematic diagram illustrating the time-division switching control signal Sab of a hybrid switching converter with single inductor and multiple outputs operating in skip mode according to an embodiment of the present invention.

[0043] Figure 14D This is a schematic diagram illustrating the time-sharing switch control signal Sab of a hybrid switching converter with single inductor and multiple outputs operating in another skip mode, according to an embodiment of the present invention.

[0044] Explanation of symbols in the diagram

[0045] 10: Switching converter with multiple outputs

[0046] 20: Hybrid switching converter with single inductor and multiple outputs

[0047] 21: Sub-switching converter

[0048] 211: Switching capacitor voltage divider circuit

[0049] 213: Control Circuit

[0050] 2131: Modulation circuit

[0051] 2132: Current sensing circuit

[0052] 2133: Ramp signal generation circuit

[0053] 21331: Logic Control Circuit

[0054] 21334: Time-sharing control logic circuit

[0055] 21341: First Type D flip-flop

[0056] 21342: Second Type D flip-flop

[0057] C1: Flying capacitor

[0058] Cin, Cin1, Cin2: Input capacitors

[0059] Co1, Co2, Co3, Co4: Output capacitors

[0060] iL: Inductor current

[0061] Iout1: First output current

[0062] Iout2: Second output current

[0063] Is1, Is2: Current sources

[0064] L1, L2: Inductors

[0065] Co: Output capacitor

[0066] Crp1, Crp2: Reset capacitors

[0067] Cx: Sensing capacitance

[0068] Q1, Q2, Q3, Q4: Switches

[0069] Q5, Q6: Output switches

[0070] Rx: Sensing resistance

[0071] S1~S4: Pulse width modulation signals

[0072] S5: First time-sharing control signal

[0073] S6: Second time-sharing control signal

[0074] Sab: Time-sharing switch control signal

[0075] Scom1: First error amplification signal

[0076] Scom2: Second error amplification signal

[0077] SiL: Inductor current signal

[0078] SL: Inductor current signal

[0079] Stg1, Stg2: Trigger signals

[0080] Szc: Zero Current Signal

[0081] Srp1, Srp2: Reset switches

[0082] t0~t12: Time points

[0083] Tsw: Cell period

[0084] V1: First voltage

[0085] V2: Second voltage

[0086] Vin: Input voltage

[0087] Vout1: First output voltage

[0088] Vout2: Second output voltage

[0089] Vref1: First reference signal

[0090] Vref2: Second reference signal

[0091] Vramp1: First ramp signal

[0092] Vramp2: Second ramp signal

[0093] Vcomp: Error amplification output signal Detailed Implementation

[0094] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0095] Figure 2A and Figure 2B This is a circuit block diagram illustrating a hybrid switching converter with a single inductor and multiple outputs according to an embodiment of the present invention. Figure 2A As shown, the hybrid switching converter 20 with a single inductor and multiple outputs of the present invention is used to convert the input voltage Vin into a first output voltage Vout1 and a second output voltage Vout2, and correspondingly generate a first output current Iout1 and a second output current Iout2. The hybrid switching converter 20 with a single inductor and multiple outputs includes a sub-switching converter 21, a first output switch Q5, and a second output switch Q6. The sub-switching converter 21 is used to convert the input voltage Vin into a relay voltage Vm. The first output switch Q5 is coupled between the relay voltage Vm and the first output voltage Vout1, and is turned on during a first inductor cycle according to a first time-division signal S5, so as to convert the relay voltage Vm into the first output voltage Vout1. The second output switch Q6 is coupled between the relay voltage Vm and the second output voltage Vout2, and is turned on during a second inductor cycle according to a second time-division signal S6, so as to convert the relay voltage Vm into the second output voltage Vout2.

[0096] Next, please refer to Figure 2B ,like Figure 2BAs shown, the sub-switching converter 21 includes a switching capacitor voltage divider circuit 211, an inductor L1, and a control circuit 213. During the first inductor cycle, the switching capacitor voltage divider circuit 211 controls multiple switches (not shown, but detailed later) according to a first set of pulse width modulation signals PWM1 to perform a switching capacitor operation, converting the first voltage V1 into two different levels of the first voltage group. During the second inductor cycle, it controls multiple switches (not shown, but detailed later) according to a second set of pulse width modulation signals PWM2 to perform a switching capacitor operation, converting the first voltage V1 into two different levels of the second voltage group. The inductor L1 has a first terminal N1 and a second terminal N2. The first terminal N1 is coupled to the switching capacitor voltage divider circuit 211, and the second terminal N2 is coupled to the second voltage V2. During the first inductor cycle, the first terminal N1 of inductor L1 switches between two different levels of the first voltage group according to the duty cycle of the first pulse width modulation signal PWM1; during the second inductor cycle, the first terminal N1 of inductor L1 switches between two different levels of the second voltage group according to the duty cycle of the second pulse width modulation signal PWM2. In other words, the first pulse width modulation signal PWM1 determines the duty cycle of the first terminal N1 of inductor L1 switching between the two different levels of the first voltage group, and the second pulse width modulation signal PWM2 determines the duty cycle of the first terminal N1 of inductor L1 switching between the two different levels of the second voltage group. The control circuit 213 generates a first set of pulse width modulation signals PWM1, a second set of pulse width modulation signals PWM2, a first time-division signal S5, and a second time-division signal S6 to control the switching of multiple switches in the capacitor voltage divider circuit 211, the first output switch Q5, and the second output switch Q6 in a time-division manner. It periodically magnetizes and demagnetizes the same inductor L1 during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage V1 and the second voltage V2, and periodically generates the first output voltage Vout1 and the second output voltage Vout2 during the first inductor cycle and the second inductor cycle, respectively.

[0097] The first voltage V1 and the second voltage V2 correspond to one of the input voltage Vin and the other of the relay voltage Vm, respectively. In one embodiment, the first voltage V1 is the input voltage Vin, and the second voltage V2 is the relay voltage Vm. In this case, the switching capacitor voltage divider circuit 211 and the inductor L1 are configured in a buck configuration, meaning that in some embodiments without additional switches, the relay voltage Vm is lower than the input voltage Vin. In another embodiment, the first voltage V1 is the relay voltage Vm, and the second voltage V2 is the input voltage Vin. In this case, the switching capacitor voltage divider circuit 211 and the inductor L1 are configured in a boost configuration, meaning that Vm is higher than the input voltage Vin.

[0098] The control circuit 213 is also used to adjust the first output voltage Vout1 to a first target voltage based on a first feedback signal Vfb1 related to the first output voltage Vout1 during the first inductor cycle, and to adjust the second output voltage Vout2 to a second target voltage based on a second feedback signal Vfb2 related to the second output voltage Vout2 during the second inductor cycle. The hybrid switching converter 20 with single inductor multiple outputs operates in boundary conduction mode (BCM) or discontinuous conduction mode (DCM) during the first and second inductor cycles.

[0099] Figure 3 show Figure 2A and Figure 2B A circuit diagram of a more specific embodiment of a hybrid switching converter 20 with single inductor and multiple outputs, and a neutron switching converter 21. (See diagram for example.) Figure 3 As shown, the sub-switching converter 21 includes a switching capacitor voltage divider circuit 211, an inductor L1, and a control circuit 213. In this embodiment, the first voltage V1 is, for example, the input voltage Vin, and the second voltage V2 is, for example, the relay voltage Vm. The switching capacitor voltage divider circuit 211 and the inductor L1 are configured in a step-down configuration. The switching capacitor voltage divider circuit 211 includes, for example, switches Q1, Q2, Q3, and Q4, and a flying capacitor C1. The switching capacitor voltage divider circuit 211 converts the input voltage Vin into two voltage dividers at different levels using a switching capacitor voltage divider method. Switches Q1, Q2, Q3, and Q4 are connected in series between the input voltage Vin and the ground potential; and the flying capacitor C1 is connected in parallel with the series-connected switches Q2 and Q3. By appropriately operating switches Q1-Q4, the flying capacitor C1 can be charged to a specific potential in different time intervals. Then, in the next stage, this potential is reconfigured to the output node of the switching capacitor voltage divider circuit 211 to convert the input voltage Vin into two different voltage levels. In this embodiment, under steady state, the switching capacitor voltage divider circuit 211 can convert the input voltage Vin into two different levels out of three different voltage levels, that is, the three voltage divisions of the input voltage Vin, including two of the input voltage Vin, half of the input voltage Vin, and the ground potential, and provide them to the first terminal N1 of the inductor L1, so that the first terminal N1 of the inductor L1 switches between two different levels.

[0100] It should be noted that the present invention is not limited to the configuration of the switching capacitor voltage divider circuit 211 having only one flying capacitor C1, but may include more flying capacitors to provide more different voltage divisions, and is not limited to three voltage divisions. That is to say, the switching capacitor voltage divider circuit 211 can convert the input voltage Vin into two different levels out of at least three different voltage levels and provide them to the first terminal N1 of the inductor L1, so that the first terminal N1 of the inductor L1 switches between two different levels.

[0101] In this embodiment, the first set of pulse width modulation signals PWM1 refers to pulse width modulation signals S1-S4 within the first inductor cycle, and the second set of pulse width modulation signals PWM2 refers to pulse width modulation signals S1-S4 within the second inductor cycle; wherein pulse width modulation signals S1-S4 correspond to control switches Q1-Q4. In this embodiment, the first group of voltages at two different levels is, for example, half of the input voltage Vin and the ground potential; the second group of voltages at two different levels is also, for example, half of the input voltage Vin and the ground potential. That is, within the first inductor cycle, the first set of pulse width modulation signals, for example, converts the input voltage Vin into two different levels: half of the input voltage Vin and the ground potential; and within the second inductor cycle, the second set of pulse width modulation signals, for example, also converts the input voltage Vin into two different levels: half of the input voltage Vin and the ground potential. The operational details will be described in detail later.

[0102] Figure 4 show Figure 2A and Figure 2B A circuit diagram of a more specific embodiment of the control circuit 213 in a hybrid switching converter 20 with single inductor and multiple outputs. (See diagram for example.) Figure 4 As shown, the control circuit 213 includes a first error amplifier EA1, a second error amplifier EA2, and a modulation circuit 2131. The first error amplifier EA1 amplifies the difference between the first output voltage feedback signal Vfb1 and the first reference signal Vref1 to generate a first error amplified signal Scom1. The second error amplifier EA2 amplifies the difference between the second output voltage feedback signal Vfb2 and the second reference signal Vref2 to generate a second error amplified signal Scom2. The first reference signal Vref1 is related to the first target voltage of the first output voltage Vout1; the second reference signal Vref2 is related to the second target voltage of the second output voltage Vout2.

[0103] The modulation circuit 2131 is used to generate a first set of pulse width modulation signals PWM1 based on the first error amplification signal Scom1 during the first inductor cycle, and to generate a second set of pulse width modulation signals PWM2 based on the second error amplification signal Scom2 during the second inductor cycle. The first set of pulse width modulation signals PWM1 refers to the pulse width modulation signals S1-S4 within the first inductor cycle, and the second set of pulse width modulation signals PWM2 refers to the pulse width modulation signals S1-S4 within the second inductor cycle.

[0104] Please continue reading. Figure 4In this embodiment, the modulation circuit 2131 includes a time-division switch SWab, comparators CP1 and CP2, and two PWM signal generation circuits PWMGen. During the first inductor cycle, the time-division switch SWab electrically connects the first error amplifier EA1 to comparators CP1 and CP2 to transmit the first error amplification signal Scom1 to comparators CP1 and CP2. The first error amplification signal Scom1 is used as the error amplification signal Vcomp and compared with the first ramp signal Vramp1 and the second ramp signal Vramp2, respectively. During the second inductor cycle, the second error amplifier EA2 is electrically connected to comparators CP1 and CP2 to transmit the second error amplification signal Scom2 to comparators CP1 and CP2. The second error amplification signal Scom2 is used as the error amplification signal Vcomp and compared with the first ramp signal Vramp1 and the second ramp signal Vramp2, respectively.

[0105] In this embodiment, during the first inductor cycle, comparator CP1 compares the first error amplification signal Scom1 with the first ramp signal Vramp1. The comparison result is then processed by the corresponding PWM signal generation circuit PWMGen to generate pulse width modulation signals S1 and S4 for the first inductor cycle. Comparator CP2 compares the first error amplification signal Scom1 with the second ramp signal Vramp2. The comparison result is then processed by the corresponding PWM signal generation circuit PWMGen to generate pulse width modulation signals S2 and S3 for the first inductor cycle. The pulse width modulation signals S1-S4 generated during the first inductor cycle are used as the first set of pulse width modulation signals PWM1.

[0106] In this embodiment, during the second inductor cycle, comparator CP1 compares the second error amplification signal Scom2 with the first ramp signal Vramp1. The comparison result is then processed by the corresponding PWM signal generation circuit PWMGen to generate pulse width modulation signals S1 and S4 for the second inductor cycle. Comparator CP2 compares the second error amplification signal Scom2 with the second ramp signal Vramp2. The comparison result is then processed by the corresponding PWM signal generation circuit PWMGen to generate pulse width modulation signals S2 and S3 for the second inductor cycle. The pulse width modulation signals S1-S4 generated during the second inductor cycle are used as the second set of pulse width modulation signals PWM2.

[0107] Figure 5 show Figure 2A and Figure 2B A circuit diagram of another more specific embodiment of the control circuit 213 in a hybrid switching converter 20 with a single inductor and multiple outputs. This embodiment is similar to... Figure 4The difference in the embodiment shown is that in this embodiment, the control circuit 213 further includes a current sensing circuit 2132 to sense the inductor current iL flowing through the inductor L1 and generate an inductor current signal SiL. The modulation circuit 2131 also generates a first set of pulse width modulation signals PWM1 and a second set of pulse width modulation signals PWM2 based on the inductor current signal SiL.

[0108] For example, comparator CP1 can compare the result of superimposing the inductor current signal SiL and the first ramp signal Vramp1 with the error amplification signal Vcomp to generate pulse width modulation signals S1 and S4. Similarly, comparator CP1 can compare the result of superimposing the inductor error amplification signal Vcomp and the inductor current signal SiL with the first ramp signal Vramp1 to generate pulse width modulation signals S1 and S4. Furthermore, comparator CP1 can compare the result of comparing the error amplification signal Vcomp and the first ramp signal Vramp1 with the inductor current signal SiL to generate pulse width modulation signals S1 and S4.

[0109] Similarly, comparator CP2 can compare the result of superimposing the inductor current signal SiL and the second ramp signal Vramp2 with the error amplification signal Vcomp to generate pulse width modulation signals S2 and S3. As another example, comparator CP2 can superimpose the inductor error amplification signal Vcomp and the inductor current signal SiL with the second ramp signal Vramp2 to generate pulse width modulation signals S2 and S3. Furthermore, comparator CP2 can compare the error amplification signal Vcomp with the second ramp signal Vramp1, superimpose the result with the inductor current signal SiL, and generate pulse width modulation signals S2 and S3.

[0110] Figure 6 This is a circuit diagram of a ramp signal generation circuit for a display control circuit according to an embodiment of the present invention. The control circuit 213 may also include, for example, a ramp signal generation circuit 2133. Figure 6As shown, the ramp signal generation circuit 2133 includes a logic control circuit 21331, two pulse generators PG, a first current source Is1, a first reset switch Srp1, a capacitor Crp1, a second current source Is2, a second reset switch Srp2, and a capacitor Crp2. In boundary conduction mode (BCM) operation, the logic control circuit 21331 generates switching clock signals Ck1 and Ck2 based on the zero current signal Szc. In discontinuous conduction mode (DCM) operation, the logic control circuit 21331 generates switching clock signals Ck1 and Ck2 based on the clock signal Clk. In one embodiment, the clock signal Clk can be a clock signal with a fixed period, or a clock signal determined by the zero current signal Szc and the control loop. The two pulse generators PG generate trigger signals Stg1 and Stg2 respectively based on the switching clock signals Ck1 and Ck2. The first current source Is1 and the second current source Is2 are both coupled to the internal voltage Vcc and powered by the internal power supply in the circuit.

[0111] The first reset switch Srp1 operates according to the trigger signal Stg1 to control the first current source Is1 to charge and discharge the capacitor Crp1, thereby generating a first ramp signal Vramp1 on the capacitor Crp1. In one embodiment, after the trigger signal Stg1 is triggered, when the first ramp signal Vramp1 is lower than the error amplification signal Vcomp, the comparator CP1 generates a first comparison signal Scp1 to control the corresponding PWM signal generation circuit PWMGen to generate pulse width modulation signals S1 and S4.

[0112] The second reset switch Srp2 operates according to the trigger signal Stg2 to control the second current source Is2 to charge and discharge the capacitor Crp2, thereby generating a second ramp signal Vramp2 on the capacitor Crp2. In one embodiment, after the trigger signal Stg2 is triggered, when the second ramp signal Vramp2 is lower than the error amplification signal Vcomp, the comparator CP2 generates a second comparison signal Scp2 to control the corresponding PWM signal generation circuit PWMGen to generate pulse width modulation signals S2 and S3.

[0113] In this embodiment, there is a phase shift between the first ramp signal Vramp1 and the second ramp signal Vramp2. The first ramp signal Vramp1 and the second ramp signal Vramp2 are synchronized with the switching clock signals Ck1 and Ck2. Therefore, the phase shift between the first ramp signal Vramp1 and the second ramp signal Vramp2 is related to the phase shift between the switching clock signals Ck1 and Ck2.

[0114] Figure 7 show Figure 2A and Figure 2BA circuit diagram of another specific embodiment of the control circuit 213 in a hybrid switching converter 20 with single inductor and multiple outputs. Compared to Figure 5 The control circuit 213 shown in this embodiment, the current sensing circuit 2132, also generates a zero-current signal Szc when the inductor current iL is zero current Izc. The control circuit 213 further includes a logic circuit 2134, which generates a first time-sharing signal S5, a second time-sharing signal S6, and a time-sharing switch control signal Sab based on the zero-current signal Szc. The time-sharing switch control signal Sab controls the time-sharing switch SWab, so that during the first inductor cycle, the time-sharing switch SWab electrically connects the first error amplifier EA1 to comparators CP1 and CP2, and during the second inductor cycle, the second error amplifier EA2 is electrically connected to comparators CP1 and CP2.

[0115] Figure 8 This is a circuit diagram of the logic circuit of the display control circuit according to an embodiment of the present invention. Figure 7 In the illustrated embodiment, the control circuit 213 further includes, for example, logic circuit 2134. In this embodiment, as... Figure 8 As shown, the logic circuit 2134 includes, for example, two D-type flip-flops 21341 and 21342 connected in series. The input pin D of the D-type flip-flop 21341 receives the inverted signal from its output pin Q. When the clock pin of the D-type flip-flop 21341 receives a zero-current signal Szc or a clock signal Clk, its internal logic circuit performs state transitions according to preset trigger conditions. Based on the result of its digital logic operation, it generates a switching clock signal Ck1 at the output pin Q and a switching clock signal Ck2 at the inverted output pin Q'. The input pin D of the D-type flip-flop 21342 receives the inverted signal from its output pin Q. The clock pin of the D-type flip-flop 21342 receives the switching clock signal Ck1 as its trigger signal and generates a first time-sharing signal S5 and a time-sharing switch control signal Sab at its output pin Q. The first time-sharing signal S5 controls the first output switch Q5, while the time-sharing switch control signal Sab controls the time-sharing switch SWab. The inverting output pin Q' of the D-type flip-flop 21342 generates a second time-division signal S6, which is used to control the second output switch Q6.

[0116] When the switching clock signal Ck1 enters the second D-type flip-flop 21342, the second D-type flip-flop 21342 updates its internal state according to a predetermined timing relationship and generates a first time-division signal S5 and a second time-division signal S6 based on its positive and negative output characteristics. In this way, the two time-division signals (the first time-division signal S5 and the second time-division signal S6) can alternately control the first output switch Q5 and the second output switch Q6 in a time-division manner, thereby generating the corresponding first output voltage Vout1 and second output voltage Vout2 in the periodic first inductor cycle and the second inductor cycle, respectively.

[0117] In addition to controlling the first output switch Q5 and the second output switch Q6, the time-sharing switch control signal Sab generated by the output pin Q of the second D-type flip-flop 21342 can be used to operate the time-sharing switch SWab as described above.

[0118] Figure 9 This is a circuit diagram of a current sensing circuit for a display control circuit according to an embodiment of the present invention. Figure 5 In the illustrated embodiment, the control circuit 213 further includes, for example, a current sensing circuit 2132. In this embodiment, as... Figure 9 As shown, the current sensing circuit 2132 includes a sensing resistor Rx and a sensing capacitor Cx, wherein the sensing resistor Rx and the sensing capacitor Cx are connected in series and coupled to the inductor L1. The inductor current iL is sensed by the voltage across the sensing capacitor Cx to generate an inductor current signal SiL. The time constant of the sensing resistor Rx and the sensing capacitor Cx is matched with the time constant of the inductor L1 and the DC resistance DCR of the inductor L1.

[0119] Figure 10 This is a schematic diagram of signal waveforms of a hybrid switching converter with a single inductor and multiple outputs, according to an embodiment of the present invention. The horizontal axis represents time t, and the vertical axis displays the signal waveforms corresponding to each signal. This embodiment uses the periodic repetition of two first inductor cycles and two second inductor cycles as an example. Time points t0 to t12 represent one unit cycle Tsw, comprising two consecutive first inductor cycles and two consecutive second inductor cycles. In this embodiment, the hybrid switching converter with a single inductor and multiple outputs operates in boundary conduction mode (BCM) during each first inductor cycle and each second inductor cycle. It should be noted that the unit cycle Tsw refers to a complete cycle in the hybrid switching converter with a single inductor and multiple outputs, during which all output switching operations and energy conversion processes are completed. This cycle repeats continuously and periodically during the operation of the hybrid switching converter with a single inductor and multiple outputs.

[0120] Between time points t0 and t3, the hybrid switching converter with a single inductor and multiple outputs is in the first inductor cycle. During this period, the time-division switch control signal Sab controls the time-division switch SWab to a high level, for example, to electrically connect the first error amplifier EA1 to comparators CP1 and CP2. The first time-division signal S5 turns on the first output switch Q5, and the second time-division signal S6 does not turn on the second output switch Q6. Between time points t0 and t1, the first error amplifier signal Scom1 is higher than the first ramp signal Vramp1, causing the pulse width modulation (PWM) signal S1 to be at a high level, thereby turning on switch Q1. Simultaneously, the first error amplification signal Scom1 is lower than the second ramp signal Vramp2, and the PWM signal S2 is at a low level, so switch Q2 is not turned on; the PWM signal S3 is the inverted signal of the PWM signal S2, so the PWM signal S3 is at a high level, and switch Q3 is turned on; the PWM signal S4 is the inverted signal of the PWM signal S1, so the PWM signal S4 is at a low level, and switch Q4 is not turned on. Therefore, from time point t0 to time point t1, switch Q1 is turned on, switch Q2 is not turned on, switch Q3 is turned on, and switch Q4 is not turned on, so that inductor L1 and flying capacitor C1 are connected in series between the input voltage Vin and the first output voltage Vout1. At this time, flying capacitor C1 is charged, and the voltage at the first terminal N1 of inductor L1 is half of the input voltage Vin (that is, the difference between the input voltage Vin and the voltage across flying capacitor C1: Vin-Vin / 2). Inductor L1 is energized, and the inductor current iL gradually increases, and the first output current Iout1 also gradually increases at the same time.

[0121] During the time interval from time t1 to time t2, the first error amplification signal Scom1 is lower than the first ramp signal Vramp1, and the PWM signal S1 is at a low level, causing switch Q1 to not conduct. Simultaneously, the first error amplification signal Scom1 is lower than the second ramp signal Vramp2, and the PWM signal S2 is at a low level, therefore switch Q2 is not conduct. The PWM signal S3 is the inverted signal of PWM signal S2, therefore the PWM signal S3 is at a high level, and therefore switch Q3 conducts. The PWM signal S4 is the inverted signal of PWM signal S1, therefore the PWM signal S4 is at a high level, and therefore switch Q4 conducts. Therefore, from time t1 to time t2, switches Q1 and Q2 are not conducting, switches Q3 and Q4 are conducting, causing the first terminal N1 of inductor L1 to be electrically connected to the reference potential (in this embodiment, the reference potential is ground potential), inductor L1 is demagnetized, the inductor current iL gradually decreases, and the first output current Iout1 also gradually decreases simultaneously. In other words, during the time interval from time t0 to time t2, the first terminal N1 of inductor L1 switches between half of the input voltage Vin and the reference potential.

[0122] At time t2, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. The logic control circuit 21331 switches the clock signals Ck1 and Ck2 according to the zero current signal Szc, thereby ending the first inductor cycle. Between time t2 and time t3, the system enters a preset dead time, which maintains the inductor current iL at zero current Izc. Subsequently, another first inductor cycle begins at time t3. It should be noted that between time point t0 and time point t3, a complete excitation (from the time point when the inductor current iL is zero current Izc to the time point when the first error amplification signal Scom1 exceeds the first ramp signal Vramp1) and demagnetization (from the time point when the first error amplification signal Scom1 exceeds the first ramp signal Vramp1 to the time point when the inductor current iL is zero current Izc), plus a preset idle time, is defined as a first inductor cycle.

[0123] Between time points t3 and t6, the hybrid switching converter with single inductor and multiple outputs is in another first inductor cycle. During this period, the time-sharing switch control signal Sab controls the time-sharing switch SWab to a high level, for example, to electrically connect the first error amplifier EA1 to comparators CP1 and CP2. The first time-sharing signal S5 turns on the first output switch Q5, and the second time-sharing signal S6 does not turn on the second output switch Q6. Between time points t3 and t4, the first error amplifier signal Scom1 is lower than the first ramp signal Vramp1, and the PWM signal S1 is at a low level, causing switch Q1 to not conduct. Simultaneously, the first error amplifier signal Scom1 is higher than the second ramp signal Vramp2, and the PWM signal S2 is at a high level, thus turning on switch Q2. The PWM signal S3 is at a low level, causing switch Q3 to not conduct; while the PWM signal S4 is at a high level, causing switch Q4 to conduct. Therefore, from time point t3 to time point t4, switch Q1 is not conducting, switch Q2 is conducting, switch Q3 is not conducting, and switch Q4 is conducting, so that inductor L1 and flying capacitor C1 are connected in parallel. At this time, flying capacitor C1 discharges, and the voltage at the first terminal N1 of inductor L1 is half of the input voltage Vin (that is, the voltage across flying capacitor C1: Vin / 2). Inductor L1 is energized, and the inductor current iL gradually increases, and the first output current Iout1 also gradually increases at the same time.

[0124] During the time interval from time t4 to time t5, the first error amplification signal Scom1 is lower than the first ramp signal Vramp1, and the PWM signal S1 is at a low level, therefore switch Q1 is not turned on. Simultaneously, the first error amplification signal Scom1 is lower than the second ramp signal Vramp2, and the PWM signal S2 is at a low level, therefore switch Q2 is not turned on. The PWM signal S3 is the inverted signal of PWM signal S2, therefore the PWM signal S3 is at a high level, therefore switch Q3 is turned on. The PWM signal S4 is the inverted signal of PWM signal S1, therefore the PWM signal S4 is at a high level, therefore switch Q4 is turned on. Therefore, from time t4 to time t5, switches Q1 and Q2 are not turned on, switches Q3 and Q4 are turned on, causing the first terminal N1 of inductor L1 to be electrically connected to the reference potential, inductor L1 to demagnetize, and the inductor current iL gradually decreases, and the first output current Iout1 also gradually decreases simultaneously. In other words, during the time interval from time t3 to time t5, the first terminal N1 of inductor L1 switches between half of the input voltage Vin and the reference potential. Since the first terminal N1 of inductor L1 switches between half of the input voltage Vin and the reference potential during the two consecutive first inductor cycles, the resulting first output voltage Vout1 will be between half of the input voltage Vin and the reference potential (ground potential in this embodiment).

[0125] At time t5, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. The logic control circuit 21331 switches clock signals Ck1 and Ck2 based on the zero current signal Szc, thereby ending another first inductor cycle. Between time t5 and time t6, the system enters a preset dead time, which maintains the inductor current iL at zero current Izc. Subsequently, at time t6, the second inductor cycle begins.

[0126] Between time points t6 and t9, the hybrid switching converter with single inductor and multiple outputs is in the second inductor cycle. During this period, the time-sharing switch control signal Sab controls the time-sharing switch SWab to a low level, for example, to electrically connect the second error amplifier EA2 to comparators CP1 and CP2. The first time-sharing signal S5 does not turn on the first output switch Q5, and the second time-sharing signal S6 turns on the second output switch Q6. Between time points t6 and t7, the second error amplifier signal Scom2 is higher than the first ramp signal Vramp1, causing the PWM signal S1 to be at a high level, thereby turning on switch Q1. Simultaneously, the second error amplification signal Scom2 is lower than the second ramp signal Vramp2, and the PWM signal S2 is at a low level, so switch Q2 is not turned on; the PWM signal S3 is the inverted signal of the PWM signal S2, so the PWM signal S3 is at a high level, and switch Q3 is turned on; the PWM signal S4 is the inverted signal of the PWM signal S1, so the PWM signal S4 is at a low level, and switch Q4 is not turned on. Therefore, from time point t6 to time point t7, switch Q1 is turned on, switch Q2 is not turned on, switch Q3 is turned on, and switch Q4 is not turned on, so that inductor L1 and flying capacitor C1 are connected in series between the input voltage Vin and the first output voltage Vout1. At this time, flying capacitor C1 is charged, and the voltage at the first terminal N1 of inductor L1 is half of the input voltage Vin (that is, the difference between the input voltage and the voltage across flying capacitor C1: Vin-Vin / 2). Inductor L1 is energized, and the inductor current iL gradually increases, and the second output current Iout2 also gradually increases at the same time.

[0127] During the time interval from time t7 to time t8, the second error amplification signal Scom2 is lower than the first ramp signal Vramp1, and the PWM signal S1 is at a low level, causing switch Q1 to not conduct. Simultaneously, the second error amplification signal Scom2 is lower than the second ramp signal Vramp2, and the PWM signal S2 is at a low level, therefore switch Q2 is not conducted. PWM signal S3 is the inverted signal of PWM signal S2, therefore PWM signal S3 is at a high level, and therefore switch Q3 conducts. PWM signal S4 is the inverted signal of PWM signal S1, therefore PWM signal S4 is at a high level, and therefore switch Q4 conducts. Therefore, from time t7 to time t8, switches Q1 and Q2 are not conducted, switches Q3 and Q4 are conducted, causing the first terminal N1 of inductor L1 to be electrically connected to the reference potential (in this embodiment, the reference potential is ground potential), inductor L1 is demagnetized, the inductor current iL gradually decreases, and the second output current Iout2 also gradually decreases simultaneously. In other words, during the time interval from time t6 to time t8, the first terminal N1 of inductor L1 switches between half of the input voltage Vin and the reference potential.

[0128] At time t8, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. The logic control circuit 21331 switches the clock signals Ck1 and Ck2 according to the zero current signal Szc, thereby ending the second inductor cycle. Between time t8 and time t9, the system enters a preset dead time, which maintains the inductor current iL at zero current Izc. Subsequently, another second inductor cycle begins at time t9. It should be noted that between time point t6 and time point t9, a complete excitation (from the time when the inductor current iL is zero current Izc to the time when the second error amplification signal Scom2 exceeds the first ramp signal Vramp1) and demagnetization (from the time when the second error amplification signal Scom2 exceeds the first ramp signal Vramp1 to the time when the inductor current iL is zero current Izc) of the inductor L1 is completed, plus the preset idle time, which is defined as a second inductor cycle.

[0129] Between time points t9 and t12, the hybrid switching converter with single inductor and multiple outputs is in another second inductor cycle. During this period, the time-sharing switch control signal Sab controls the time-sharing switch SWab to, for example, a low level, to electrically connect the second error amplifier EA2 to comparators CP1 and CP2. The first time-sharing signal S5 does not turn on the first output switch Q5, and the second time-sharing signal S6 turns on the second output switch Q6. Between time points t9 and t10, the second error amplifier signal Scom2 is lower than the first ramp signal Vramp1, and the PWM signal S1 is at a low level, causing switch Q1 to not turn on. Simultaneously, the second error amplifier signal Scom2 is higher than the second ramp signal Vramp2, and the PWM signal S2 is at a high level, thus turning on switch Q2. The PWM signal S3 is at a low level, causing switch Q3 to not turn on; while the PWM signal S4 is at a high level, causing switch Q4 to turn on. Therefore, from time point t9 to time point t10, switch Q1 is not conducting, switch Q2 is conducting, switch Q3 is not conducting, and switch Q4 is conducting, so that the first terminal N1 of inductor L1 is connected in parallel with the flying capacitor C1. At this time, the flying capacitor C1 discharges, and the voltage of the first terminal N1 of inductor L1 is half of the input voltage Vin (that is, the voltage across the flying capacitor C1: Vin / 2). Inductor L1 is energized, and the inductor current iL gradually increases, and the second output current Iout2 also gradually increases at the same time.

[0130] During the time interval from time t10 to time t11, the second error amplification signal Scom2 is lower than the first ramp signal Vramp1, and the PWM signal S1 is at a low level, therefore switch Q1 is not turned on. Simultaneously, the second error amplification signal Scom2 is lower than the second ramp signal Vramp2, and the PWM signal S2 is at a low level, therefore switch Q2 is not turned on. The PWM signal S3 is the inverted signal of PWM signal S2, therefore the PWM signal S3 is at a high level, therefore switch Q3 is turned on. The PWM signal S4 is the inverted signal of PWM signal S1, therefore the PWM signal S4 is at a high level, therefore switch Q4 is turned on. Therefore, from time t10 to time t11, switches Q1 and Q2 are not turned on, switches Q3 and Q4 are turned on, causing the first terminal N1 of inductor L1 to be electrically connected to the reference potential, inductor L1 to demagnetize, and the inductor current iL gradually decreases, and the second output current Iout2 also gradually decreases simultaneously. In other words, during the time interval from time t9 to time t11, the first terminal N1 of inductor L1 switches between half of the input voltage Vin and the reference potential. Since the first terminal N1 of inductor L1 switches between half of the input voltage Vin and the reference potential during the two consecutive first inductor cycles, the resulting first output voltage Vout1 will be between half of the input voltage Vin and the reference potential.

[0131] At time t11, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. The logic control circuit 21331 switches the clock signals Ck1 and Ck2 according to the zero current signal Szc, thereby ending another second inductor cycle. Between time t11 and time t12, the system enters a preset deadtime, which maintains the inductor current iL at zero current Izc. Subsequently, the first inductor cycle begins at time t12.

[0132] In this embodiment, the flying capacitor C1 is charged and discharged in two consecutive first inductor cycles (e.g., time points t0 to t3 and t3 to t6), thereby reaching a balance state and ensuring stable operation. On the other hand, the flying capacitor C1 is charged and discharged in two consecutive second inductor cycles (e.g., time points t6 to t9 and t9 to t12), thereby reaching a balance state and ensuring stable operation.

[0133] Furthermore, in this embodiment, the start point of the first ramp signal Vramp1 is triggered at the end of every two consecutive first inductor cycles and at the end of every two consecutive second inductor cycles; the start point of the second ramp signal Vramp2 is triggered at the end of the first of two consecutive first inductor cycles, and another second start point of the second ramp signal Vramp2 is triggered at the end of the first of two consecutive second inductor cycles.

[0134] Figure 11 This is a schematic diagram of the signal waveforms of a hybrid switching converter with a single inductor and multiple outputs, according to an embodiment of the present invention. This embodiment, for example, uses the periodic repetition of two first inductor cycles and two second inductor cycles as an example, where time points t0 to t12 represent one unit cycle Tsw, comprising two consecutive first inductor cycles and two consecutive second inductor cycles. In each first inductor cycle, the hybrid switching converter with a single inductor and multiple outputs operates in boundary conduction mode (BCM) operation. This embodiment and... Figure 10 The difference from the illustrated embodiment is that in this embodiment, each second inductor cycle operates in discontinuous conduction mode (DCM) operation mode.

[0135] In this embodiment, at time t8, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. However, the logic control circuit 21331 switches clock signals Ck1 and Ck2 based on the clock signal Clk instead of the zero current signal Szc to end the second inductor cycle. Therefore, the dead time between time t8 and time t9 is relatively long. Figure 10 In the illustrated embodiment, a long dead time is preset, which maintains the inductor current iL at zero current Izc. Similarly, at time t11, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. However, the logic control circuit 21331 switches the clock signals Ck1 and Ck2 based on the clock signal Clk instead of the zero current signal Szc to end the second inductor cycle. Therefore, the dead time between time t11 and time t12 is relatively long. Figure 10 In the illustrated embodiment, a long preset idle time is used to maintain the inductor current iL at zero current Izc. Other parts (i.e., time points t0 to t6, t6 to t8, and t9 to t11) and... Figure 10 The embodiments shown are the same; please refer to [link / reference]. Figure 12 The illustrated examples are as follows.

[0136] Figure 11This is a schematic diagram of signal waveforms showing the relevant signals of a hybrid switching converter with a single inductor and multiple outputs, according to an embodiment of the present invention. Figure 11 The similarity between the illustrated embodiments is that this embodiment also uses the periodic repetition of two first inductor cycles and two second inductor cycles as an example, where time points t0 to t12 represent one unit cycle Tsw, which includes two consecutive first inductor cycles and two consecutive second inductor cycles. In each first inductor cycle, the hybrid switching converter with single inductor multiple outputs operates in boundary conduction mode (BCM), and in each second inductor cycle, it operates in discontinuous conduction mode (DCM).

[0137] This embodiment and Figure 11 The difference from the illustrated embodiment is that in this embodiment, the output voltage Vout1 is between the input voltage Vin and half of the input voltage Vin. Therefore, the level of the first error amplification signal Scom1 is higher, so that the first terminal N1 of the inductor L1 can switch between the input voltage Vin and half of the input voltage Vin, rather than between half of the input voltage Vin and the reference potential, as detailed below.

[0138] Between time points t0 and t3, the hybrid switching converter with a single inductor and multiple outputs is in the first inductor cycle. During this period, the time-division switch control signal Sab controls the time-division switch SWab to a high level, for example, to electrically connect the first error amplifier EA1 to comparators CP1 and CP2. The first time-division signal S5 turns on the first output switch Q5, and the second time-division signal S6 does not turn on the second output switch Q6. Between time points t0 and t1, the first error amplifier signal Scom1 is higher than the first ramp signal Vramp1, causing the pulse width modulation (PWM) signal S1 to be at a high level, thereby turning on switch Q1. Simultaneously, the first error amplification signal Scom1 is higher than the second ramp signal Vramp2, and the PWM signal S2 is at a high level, therefore switch Q2 is turned on; the PWM signal S3 is the inverted signal of the PWM signal S2, therefore the PWM signal S3 is at a low level, and switch Q3 is not turned on; the PWM signal S4 is the inverted signal of the PWM signal S1, therefore the PWM signal S4 is at a low level, and switch Q4 is not turned on. Therefore, from time point t0 to time point t1, switch Q1 is turned on, switch Q2 is turned on, switch Q3 is not turned on, and switch Q4 is not turned on, causing the first terminal N1 of inductor L1 to be coupled to the input voltage Vin, inductor L1 to be energized, and the inductor current iL gradually increases, and the first output current Iout1 also gradually increases at the same time.

[0139] During the time interval from time point t1 to time point t2, the first error amplification signal Scom1 is higher than the first ramp signal Vramp1, and the PWM signal S1 is at a high level, causing switch Q1 to turn on; at the same time, the first error amplification signal Scom1 is lower than the second ramp signal Vramp2, and the PWM signal S2 is at a low level, so switch Q2 does not turn on; the PWM signal S3 is the inverted signal of the PWM signal S2, so the PWM signal S3 is at a high level, and therefore switch Q3 turns on; the PWM signal S4 is the inverted signal of the PWM signal S1, so the PWM signal S4 is at a low level, and therefore switch Q4 does not turn on. Therefore, from time t1 to time t2, switch Q1 is on, switch Q2 is off, switch Q3 is on, and switch Q4 is off. This causes inductor L1 and flying capacitor C1 to be connected in series between the input voltage Vin and the first output voltage Vout1. At this time, flying capacitor C1 is charging, and the voltage across the first terminal N1 of inductor L1 is half of the input voltage Vin (i.e., the difference between the input voltage Vin and the voltage across flying capacitor C1: Vin - Vin / 2). Inductor L1 is demagnetized, and the inductor current iL gradually decreases. The first output current Iout1 also gradually decreases at the same time. In other words, during the time period from time t0 to time t2, the first terminal N1 of inductor L1 switches between the input voltage Vin and half of the input voltage Vin.

[0140] At time t2, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. The logic control circuit 21331 switches the clock signals Ck1 and Ck2 according to the zero current signal Szc, thereby ending the first inductor cycle. Between time t2 and time t3, the system enters a preset dead time, which maintains the inductor current iL at zero current Izc. Subsequently, another first inductor cycle begins at time t3. It should be noted that between time point t0 and time point t3, a complete excitation (from the time point when the inductor current iL is zero current Izc to the time point when the second error amplification signal Scom2 exceeds the second ramp signal Vramp2) and demagnetization (from the time point when the second error amplification signal Scom2 exceeds the second ramp signal Vramp2 to the time point when the inductor current iL is zero current Izc) of the inductor L1 is completed, plus the preset idle time, which is defined as a first inductor cycle.

[0141] Between time points t3 and t6, the hybrid switching converter with single inductor and multiple outputs is in another first inductor cycle. During this period, the time-sharing switch control signal Sab controls the time-sharing switch SWab to a high level, for example, to electrically connect the first error amplifier EA1 to comparators CP1 and CP2. The first time-sharing signal S5 turns on the first output switch Q5, and the second time-sharing signal S6 does not turn on the second output switch Q6. Between time points t3 and t4, the first error amplifier signal Scom1 is higher than the first ramp signal Vramp1, and the PWM signal S1 is at a high level, causing switch Q1 to turn on. Simultaneously, the first error amplifier signal Scom1 is higher than the second ramp signal Vramp2, and the PWM signal S2 is at a high level, thus turning on switch Q2. The PWM signal S3 is at a low level, causing switch Q3 to turn off, and the PWM signal S4 is at a low level, causing switch Q4 to turn off. Therefore, from time point t3 to time point t4, switch Q1 is on, switch Q2 is on, switch Q3 is off, and switch Q4 is off, so that the first terminal N1 of inductor L1 is coupled to the input voltage Vin, inductor L1 is energized, the inductor current iL gradually increases, and the first output current Iout1 also gradually increases at the same time.

[0142] During the time interval from time point t4 to time point t5, the first error amplification signal Scom1 is lower than the first ramp signal Vramp1, and the PWM signal S1 is at a low level, so switch Q1 is not turned on; at the same time, the first error amplification signal Scom1 is higher than the second ramp signal Vramp2, and the PWM signal S2 is at a high level, so switch Q2 is turned on; the PWM signal S3 is the inverted signal of the PWM signal S2, so the PWM signal S3 is at a low level, so switch Q3 is not turned on; the PWM signal S4 is the inverted signal of the PWM signal S1, so the PWM signal S4 is at a high level, so switch Q4 is turned on. Therefore, between time points t4 and t5, switch Q1 is off, switch Q2 is on, switch Q3 is off, and switch Q4 is on, causing the first terminal N1 of inductor L1 to be connected in parallel with the flying capacitor C1. At this time, the flying capacitor C1 discharges, and the voltage across the first terminal N1 of inductor L1 is half of the input voltage Vin (i.e., the voltage across the flying capacitor C1: Vin / 2). Inductor L1 demagnetizes, and the inductor current iL gradually decreases, while the first output current Iout1 also gradually decreases. In other words, between time points t3 and t5, the first terminal N1 of inductor L1 switches between the input voltage Vin and half of the input voltage Vin.

[0143] At time t5, the current sensing circuit 2132 detects that the inductor current iL is zero current Izc and generates a zero current signal Szc. The logic control circuit 21331 switches clock signals Ck1 and Ck2 based on the zero current signal Szc, thereby ending another first inductor cycle. Between time t5 and time t6, the system enters a preset dead time, which maintains the inductor current iL at zero current Izc. Subsequently, at time t6, the second inductor cycle begins.

[0144] Between time point t6 and time point t12, the hybrid switching converter with single inductor multiple outputs is in two consecutive second inductor cycles, and its operation during this period is similar to... Figure 11 The operations between time point t6 and time point t12 are the same; please refer to [link / reference]. Figure 13 The explanation will not be repeated here.

[0145] In this embodiment, the capacitor reaches a balanced state during two consecutive first inductor cycles (e.g., time points t0 to t3 and t3 to t6), ensuring stable operation. Similarly, the capacitor reaches a balanced state during two consecutive second inductor cycles (e.g., time points t6 to t9 and t9 to t12), ensuring stable operation.

[0146] The first ramp signal Vramp1 is triggered at the end of every two consecutive first inductor cycles and at the end of every two consecutive second inductor cycles; the second ramp signal Vramp2 is triggered at the end of the first of two consecutive first inductor cycles, and another second ramp signal Vramp2 is triggered at the end of the first of two consecutive second inductor cycles.

[0147] Figure 2A show Figure 2B and Figure 3 A circuit diagram of another more specific embodiment of the hybrid switching converter 21 with a single inductor and multiple outputs in the hybrid switching converter 20. This embodiment is similar to... Figure 14A The sub-switching converter 21 in the hybrid switching converter 20 with single inductor and multiple outputs shown is different in that, in this embodiment, the sub-switching converter 21 also includes a boost switch Q7, which is coupled between the second terminal N2 of the inductor L1 and the reference potential (ground potential in this embodiment), so that the hybrid switching converter 20 with single inductor and multiple outputs can select to operate in boost conversion or buck conversion according to whether the first target voltage or the second target voltage is higher than the input voltage Vin.

[0148] The boost switch Q7 provides flexibility for the hybrid switching converter 20 with multiple outputs from a single inductor under different target voltage requirements. For example, when the first or second target voltage is higher than the input voltage Vin, the boost switch Q7 switches with either the first output switch Q5 or the second output switch Q6 to achieve boost power conversion. This configures the switching capacitor voltage divider circuit 211, inductor L1, and boost switch Q7 in a boost configuration. In this configuration, the first terminal N1 of inductor L1 can be electrically connected to the input voltage Vin, and the energy of inductor L1 can be stored and released to the output voltage terminal to increase the output voltage Vin to the target value.

[0149] On the other hand, when the first target voltage or the second target voltage is lower than the input voltage Vin, the boost switch Q7 is turned off, and the switching capacitor voltage divider circuit 211 and the inductor L1 are directly configured in a buck configuration. In this configuration, the inductor L1, in conjunction with the switching capacitor voltage divider circuit 211, reduces the input voltage Vin, providing a stable target voltage lower than the input voltage Vin.

[0150] In one embodiment, the first terminal N1 of inductor L1 can be switched to half of the input voltage Vin by switching capacitor conversion. At the same time, it can be switched between the aforementioned boost switch Q7 and the first output switch Q5 or the second output switch Q6 to perform boost power conversion of half of the input voltage Vin.

[0151] Figure 14B - Figure 14D This is a schematic diagram of a display logic circuit according to an embodiment of the present invention. Figure 14A This diagram shows the Sab waveform of the time-sharing switch control signal with normal mode and skip mode. (Example) Figure 8 As shown, the logic circuit 2134 of the control circuit 213 is used to generate a time-sharing switch control signal Sab, a first time-sharing signal S5, and a second time-sharing signal S6 based on the first error amplification signal Scom1, the second error amplification signal Scom2, and the clock signal Clk or the zero-current signal Szc. The time-sharing switch control signal Sab, the first time-sharing signal S5, and the second time-sharing signal S6 are all triggered by the clock signal Clk or the zero-current signal Szc, and the first time-sharing signal S5 and the second time-sharing signal S6 are inverted, while the time-sharing switch control signal Sab and the first time-sharing signal S5 are synchronized. Compared to... Figure 14A The embodiment of the logic circuit 2134 shown is as follows: Figure 14BIn the embodiment of the logic circuit 2134 shown, the voltage difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 is used to determine whether the hybrid switching converter 20 with single inductor multiple outputs enters skip mode. In skip mode, the difference between the number of first inductor cycles and the number of second inductor cycles within a unit cycle is positively correlated with the difference between the first output current Iout and the second output current Iout. In one embodiment, particularly in BCM and DCM, the voltage difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 is positively correlated with the difference between the first output current Iout and the second output current Iout.

[0152] Figure 14B This is a schematic diagram illustrating the time-sharing switch control signal Sab of a hybrid switching converter with a single inductor and multiple outputs operating in normal mode according to an embodiment of the present invention. In this embodiment, when the hybrid switching converter with a single inductor and multiple outputs is in normal mode, the time-sharing switch control signal Sab periodically and sequentially alternates between a logic high level and a logic low level between the first output (the output terminal that generates the first output voltage Vout1) and the second output (the output terminal that generates the second output voltage Vout2), so that the two output terminals sequentially generate stable and continuous waveforms, thereby meeting the requirements of load demand and stable system operation. Figure 10 The time-sharing switch control signal Sab waveform shown illustrates this, exhibiting the characteristic of alternating high and low levels within a fixed period.

[0153] In one embodiment, when the first output load corresponding to the first output voltage Vout1 and the first output current Iout1, and the second output load corresponding to the second output voltage Vout2 and the second output current Iout2, are both not light loads and the difference is less than a load threshold, for example, when the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 is less than a threshold, the logic circuit 2134 periodically and alternately sets the first time-sharing signal S5 and the second time-sharing signal S6 to the enable level, so that the hybrid switching converter with single inductor and multiple outputs operates in normal mode. For example, Figure 14C The illustrated embodiment illustrates that the process involves periodically repeating two consecutive first inductor cycles followed by two consecutive second inductor cycles.

[0154] Figure 14D This is a schematic diagram illustrating a time-division switching control signal Sab of a hybrid switching converter with single inductor and multiple outputs operating in a skip mode according to an embodiment of the present invention. Figure 14CThis is a schematic diagram illustrating a time-sharing switch control signal Sab of a hybrid switching converter with a single inductor and multiple outputs operating in a skip mode according to an embodiment of the present invention. For example, when the hybrid switching converter with a single inductor and multiple outputs senses that the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 exceeds a preset first threshold, the logic circuit 2134 will activate the skip mode, such as... Figure 14D The time-sharing switch control signal Sab shown indicates that in each unit cycle Tsw, a high-order quasi-pulse of the second time-sharing signal S6 is skipped. For example, in one embodiment, each unit cycle Tsw skips two sequential second inductor cycles, that is, it periodically repeats four consecutive first inductor cycles followed by two consecutive second inductor cycles.

[0155] When the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 continuously increases and remains above a preset second threshold for a preset period, the logic circuit 2134 dynamically adjusts the high and low level time ratio of the time-sharing switch control signal Sab according to the change in the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2. Specifically, as the difference between the first error amplification signal Scom1 and the second error amplification signal Scom2 continuously increases, the duration or proportion of the logic high level in the time-sharing switch control signal Sab will gradually increase, while the proportion of the logic low level will relatively decrease. ​ The time-sharing switch control signal Sab shown indicates that each unit cycle Tsw skips two high-order quasi-pulses of the second time-sharing signal S6. For example, in one embodiment, each unit cycle Tsw skips four second inductor cycles, that is, periodically repeating six consecutive first inductor cycles followed by two consecutive second inductor cycles.

[0156] This adjustment mechanism is called skip mode. Its function is to reduce the number of switching cycles by deliberately skipping some switching cycles when the output load is light, thereby reducing energy loss and electromagnetic interference caused by frequent switching, while still maintaining basic control over the output voltage.

[0157] Of course, when both the first output load and the second output load are lightly loaded, the logic circuit 2134 can also skip at least one high-level pulse of the first time-sharing signal S5 and at least one high-level pulse of the second time-sharing signal S6 in each unit cycle Tsw.

[0158] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the broadest scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. For example, a unit cycle Tsw can also include a combination of a single first inductor cycle and a single second inductor cycle, that is, a single first inductor cycle and a single second inductor cycle are periodically alternated, as long as a capacitor balance state can be achieved. Furthermore, within the same spirit of the present invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the present invention's statement of "processing or calculating based on a signal or generating an output result" is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the present invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many ways to combine them, which will not be listed here. Therefore, the scope of this invention should cover the above and all other equivalent variations.

Claims

1. A hybrid switching converter with a single inductor and multiple outputs for converting an input voltage into a first output voltage and a second output voltage, the hybrid switching converter with a single inductor and multiple outputs comprising: A sub-switching converter is used to convert the input voltage into a relay voltage; A first output switch is configured to be turned on during a first inductor cycle according to a first time-division signal, so as to convert the relay voltage into the first output voltage. as well as A second output switch is configured to be turned on during a second inductor cycle according to a second time-division signal, so as to convert the relay voltage into the second output voltage; The sub-switching converter includes: A switching capacitor voltage divider circuit controls multiple switches according to a first set of pulse width modulation signals during a first inductor cycle to perform switching capacitor operation, thereby converting a first voltage into a first group of voltages at two different levels. During a second inductor cycle, the circuit controls the multiple switches according to a second set of pulse width modulation signals to perform switching capacitor operation, thereby converting the first voltage into a second group of voltages at two different levels. An inductor, one first terminal of which is coupled to the switching capacitor voltage divider circuit, and the other second terminal of which is coupled to a second voltage; During the first inductor cycle, the first terminal of the inductor switches between two different voltage levels of the first group according to the first set of pulse width modulation signals; During the second inductor cycle, according to the second set of pulse width modulation signals, the first terminal of the inductor switches between two different levels of the second voltage group; and A control circuit is used to generate the first set of pulse width modulation signals, the second set of pulse width modulation signals, the first time-division signal, and the second time-division signal to control the multiple switches, the first output switch, and the second output switch in a time-division manner. It periodically performs magnetization and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage. It also periodically generates the first output voltage and the second output voltage during the first inductor cycle and the second inductor cycle, respectively. The first voltage and the second voltage respectively correspond to one of the input voltage and the other of the relay voltage; The control circuit is further configured to, during the first inductor cycle, adjust the first output voltage to a first target voltage based on a first feedback signal related to the first output voltage, and during the second inductor cycle, adjust the second output voltage to a second target voltage based on a second feedback signal related to the second output voltage; The hybrid switching converter with single inductor and multiple outputs operates in a boundary conduction mode (BCM) or a discontinuous conduction mode (DCM) during the first inductor cycle and the second inductor cycle.

2. The hybrid switching converter with single inductor and multiple outputs as described in claim 1, wherein, Any two sequential cycles of the first inductor cycle achieve a capacitor balance state, and any two sequential cycles of the second inductor cycle achieve a capacitor balance state.

3. The hybrid switching converter with single inductor and multiple outputs as described in claim 1, wherein, The control circuit includes: A first error amplifier is used to amplify the difference between the first output voltage feedback signal and a first reference signal to generate a first error amplification signal; A second error amplifier is used to amplify the difference between the second output voltage feedback signal and a second reference signal to generate a second error amplification signal; and A modulation circuit is used to generate the first set of pulse width modulation signals according to the first error amplification signal during the first inductor cycle, and to generate the second set of pulse width modulation signals according to the second error amplification signal during the second inductor cycle.

4. The hybrid switching converter with single inductor and multiple outputs as described in claim 3, wherein, The control circuit also includes a current sensing circuit to sense the inductor current and generate an inductor current signal, and the modulation circuit generates the first set of pulse width modulation signals and the second set of pulse width modulation signals based on the inductor current signal.

5. The hybrid switching converter with single inductor and multiple outputs as described in claim 4, wherein, The current sensing circuit also generates a zero-current signal when the inductor current is zero. The control circuit also includes a logic circuit for generating the first time-division signal and the second time-division signal based on the zero current signal.

6. The hybrid switching converter with single inductor and multiple outputs as described in claim 3, wherein, The control circuit also includes a logic circuit for generating the first time-division signal and the second time-division signal according to a clock signal.

7. The hybrid switching converter with single inductor and multiple outputs as described in claim 3, wherein, The control circuit also includes a logic circuit for generating a time-division switching control signal, the first time-division signal and the second time-division signal based on the first error amplification signal and the second error amplification signal, as well as a clock signal or a zero current signal. The time-sharing switch control signal, the first time-sharing signal, and the second time-sharing signal are all triggered by the clock signal or the zero-current signal, and the first time-sharing signal and the second time-sharing signal are inverses of each other; The logic circuit also determines whether the hybrid switching converter with single inductor and multiple outputs enters a skip mode based on the difference between a first output current and a second output current. In this skip mode, the difference between the number of times the first inductor cycle and the number of times the second inductor cycle are positively correlated with the difference between the first output current and the second output current within a unit cycle.

8. The hybrid switching converter with single inductor and multiple outputs as described in claim 4, wherein, The current sensing circuit includes a sensing resistor and a sensing capacitor, wherein the sensing resistor and the sensing capacitor are connected in series and coupled to the inductor. The inductor current is sensed by the voltage across the sensing capacitor to generate the inductor current signal. The time constant of the sensing resistor and the sensing capacitor is matched with the time constant of the inductor and the DC resistance of the inductor.

9. The hybrid switching converter with single inductor and multiple outputs as described in claim 1, wherein, The power supply between the first voltage and the second voltage is converted into a boost converter or a buck converter.

10. The hybrid switching converter with single inductor and multiple outputs as described in claim 1, wherein, When the switching capacitor voltage divider circuit and the inductor are configured in a buck configuration, the sub-switching converter also includes a boost switch coupled between the second terminal of the inductor and a reference potential, so that the hybrid switching converter with single inductor multiple outputs can select to operate in a boost conversion or a buck conversion according to the first target voltage or the second target voltage.

11. The hybrid switching converter with single inductor and multiple outputs as described in claim 1, wherein, The first set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the first voltage group, and the second set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the second voltage group.

12. The hybrid switching converter with single inductor and multiple outputs as described in claim 5, wherein, At the end of two consecutive first inductor cycles, a first ramp signal is triggered at a first start point, and at the end of two consecutive second inductor cycles, the first ramp signal is triggered at another first start point. Wherein, at the end of the first of two consecutive first inductor cycles, a second starting point of a second ramp signal is triggered, and at the end of the first of two consecutive second inductor cycles, another second starting point of the second ramp signal is triggered. The modulation circuit compares the first ramp signal with the first error amplification signal during the first inductor cycle, and compares the second ramp signal with the first error amplification signal to generate the first set of pulse width modulation signals. The modulation circuit compares the first ramp signal with the second error amplification signal during the second inductor cycle, and compares the second ramp signal with the second error amplification signal to generate the second set of pulse width modulation signals. In this configuration, two consecutive first inductor cycles and two consecutive second inductor cycles are alternately arranged and repeated periodically in sequence.

13. A control method for a hybrid switching converter with single inductor and multiple outputs, comprising: Convert an input voltage to a relay voltage; According to a first time-division signal, within a first inductor cycle, a first output switch is turned on to output the relay voltage as a first output voltage; and According to a second time-division signal, within a second inductor cycle, a second output switch is turned on to output the relay voltage as a second output voltage; in, The steps for converting the input voltage to the relay voltage include: During the first inductor cycle, multiple switches are controlled according to a first set of pulse width modulation signals to perform switching capacitor operation, thereby converting a first voltage into a first set of voltages at two different levels. During the second inductor cycle, the multiple switches are controlled according to a second set of pulse width modulation signals to perform switching capacitor operation, thereby converting the first voltage into a second set of voltages at two different levels. During the first inductor cycle, according to the first set of pulse width modulation signals, a first terminal of an inductor is switched between two different voltage levels of the first set of voltage. During the second inductor cycle, the first terminal of the inductor is switched between two different voltage levels of the second group according to the second set of pulse width modulation signals; The first set of pulse width modulation signals and the second set of pulse width modulation signals are used to control the multiple switches in a time-division manner, and the same inductor is periodically magnetized and demagnetized during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage. The first voltage and the second voltage respectively correspond to one of the input voltage and the other of the relay voltage; Using the first time-division signal and the second time-division signal, the first output switch and the second output switch are controlled in a time-division manner, and the first output voltage and the second output voltage are generated periodically during the first inductor cycle and the second inductor cycle, respectively; and During the first inductor cycle, the first output voltage is adjusted to a first target voltage based on a first feedback signal related to the first output voltage, and during the second inductor cycle, the second output voltage is adjusted to a second target voltage based on a second feedback signal related to the second output voltage; The hybrid switching converter with single inductor and multiple outputs operates in a boundary conduction mode (BCM) or a discontinuous conduction mode (DCM) during the first inductor cycle and the second inductor cycle.

14. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 13, wherein, Any two sequential cycles of the first inductor cycle achieve a capacitor balance state, and any two sequential cycles of the second inductor cycle achieve a capacitor balance state.

15. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 13, wherein, The steps of time-division controlling the multiple switches, the first output switch, and the second output switch, and periodically performing magnetization and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage include: The difference between the first output voltage feedback signal and a first reference signal is amplified to generate a first error amplification signal; Amplify the difference between the second output voltage feedback signal and a second reference signal to generate a second error amplification signal; and During the first inductor cycle, the first set of pulse width modulation signals is generated based on the first error amplification signal, and during the second inductor cycle, the second set of pulse width modulation signals is generated based on the second error amplification signal.

16. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 15, wherein, The step of time-division controlling the multiple switches, the first output switch and the second output switch, and periodically performing excitation and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage further includes: sensing the inductor current and generating an inductor current signal, and generating the first set of pulse width modulation signals and the second set of pulse width modulation signals based on the inductor current signal.

17. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 16, wherein, The step of time-division controlling the multiple switches, the first output switch, and the second output switch, and periodically performing excitation and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage further includes: Furthermore, based on the inductor current signal, a zero-current signal is generated when the inductor current is zero; and Based on the zero-current signal, the first time-division signal and the second time-division signal are generated.

18. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 15, wherein, The step of time-division control of the multiple switches, the first output switch and the second output switch, and periodically magnetizing and demagnetizing the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage further includes: generating the first time-division signal and the second time-division signal according to a clock signal.

19. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 15, wherein, The step of time-division controlling the multiple switches, the first output switch, and the second output switch, and periodically performing excitation and demagnetization operations on the same inductor during the first inductor cycle and the second inductor cycle to perform power conversion between the first voltage and the second voltage further includes: Based on the first error amplification signal, the second error amplification signal, and a clock signal or a zero-current signal, a time-division switching control signal, the first time-division signal, and the second time-division signal are generated; and Based on a voltage difference between the first error amplification signal and the second error amplification signal, it is determined whether the hybrid switching converter with single inductor and multiple outputs enters a skip mode. The time-sharing switch control signal, the first time-sharing signal, and the second time-sharing signal are all triggered by the clock signal or the zero-current signal, and the first time-sharing signal and the second time-sharing signal are inverses of each other; In this skip mode, the difference between the number of times the first inductor cycle and the number of times the second inductor cycle are positively correlated with the difference between a first output current and a second output current within a unit cycle.

20. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 16, wherein, The step of sensing the inductor current and generating an inductor current signal includes: providing a sensing resistor and a sensing capacitor, wherein the sensing resistor and the sensing capacitor are connected in series and coupled to the inductor, and sensing the inductor current through the voltage across the sensing capacitor to generate the inductor current signal, wherein a time constant of the sensing resistor and the sensing capacitor is matched with a time constant of the inductor and the DC resistance of the inductor.

21. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 13, wherein, The power supply between the first voltage and the second voltage is converted into a boost converter or a buck converter.

22. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 13, wherein, The first set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the first voltage group, and the second set of pulse width modulation signals determines the duty cycle of the first terminal of the inductor switching between two different levels of the second voltage group.

23. The control method for a hybrid switching converter with single inductor and multiple outputs as described in claim 17, wherein, At the end of two consecutive first inductor cycles, a first ramp signal is triggered at a first start point, and at the end of two consecutive second inductor cycles, the first ramp signal is triggered at another first start point. Wherein, at the end of the first of two consecutive first inductor cycles, a second starting point of a second ramp signal is triggered, and at the end of the first of two consecutive second inductor cycles, another second starting point of the second ramp signal is triggered. During the first inductor cycle, the first ramp signal is compared with the first error amplification signal, and the second ramp signal is compared with the first error amplification signal to generate the first set of pulse width modulation signals; During the second inductor cycle, the first ramp signal is compared with the second error amplification signal, and the second ramp signal is compared with the second error amplification signal to generate the second set of pulse width modulation signals; In this configuration, two consecutive first inductor cycles and two consecutive second inductor cycles are alternately arranged and repeated periodically in sequence.

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