Engine distributed system fault tolerance method based on braided ring network

Abstract

The invention discloses an engine distributed system fault tolerance method based on a braided ring network, the system adopts a braided ring topological structure to construct a communication network, the communication network comprises a sending node, a primary forwarding node, a verification forwarding node and a receiving node, and multi-path data transmission is realized through a direct link and an indirect link. The system is based on FPGA hardware platform design, integrates a data verification module, a data conversion module and a mode selection module, and realizes high-speed parallel data verification, serial-parallel data conversion and real-time mode switching. Through a dual fault-tolerant mechanism of self-checking data forwarding and data integrity reconstruction, the system can automatically check, select or reconstruct correct data when a node fails or a communication link is interrupted, and the communication reliability is guaranteed. The scheme has the characteristics of high real-time performance, strong fault-tolerant capability and low resource occupation, and is suitable for high-performance distributed control systems such as aero-engines and the like.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of aero-engine control, and particularly relates to an engine distributed system fault-tolerant method based on a woven ring network. BACKGROUND

[0002] As the "heart" of an airplane, an aero-engine is long-term operated in a harsh environment of high temperature, high pressure, strong vibration and complex electromagnetic interference, and puts forward strict requirements on communication stability and anti-interference capability. In the control system, analog signals collected by speed, temperature, fuel flow and other sensors are deeply coupled with digital signals such as control instructions and state feedbacks of an executing mechanism, forming a multi-dimensional communication network. With the development of aero-engines towards high thrust-to-weight ratio, low fuel consumption and long service life, the control variables continue to increase, and the application of advanced control algorithms further aggravates the communication transmission pressure of the control system, and puts forward higher standards for the reliability of communication.

[0003] The traditional centralized architecture faces an algorithm bottleneck because the central controller needs to bear the processing and control of all signals, and the laying of a large number of cables also seriously increases the weight of the fuselage, directly affecting the maneuverability and fuel economy of the airplane. The distributed architecture effectively reduces the load of the central controller by decentralizing signal preprocessing, local control and other primary functions to local nodes in each region of the engine, and the reduction of cable usage also significantly optimizes the thrust-to-weight ratio. However, the distributed architecture faces problems such as insufficient clock synchronization accuracy and node data interaction delay fluctuation due to its decentralized node characteristics, and the high-temperature corrosion near the combustion chamber of the engine and the strong vibration in the fan area and other local harsh environments easily lead to problems such as communication interface damage and signal attenuation, and the existing fault-tolerant mechanism is difficult to cope with complex faults or interference problems that may occur.

[0004] At present, the communication bus of the aero-engine control system usually adopts a star structure or a bus structure. Although the dual-channel redundancy design can ensure the continuity of communication when a single channel fails, the additional hardware deployment increases the system complexity and maintenance cost. The detection technologies such as CRC encoding and parity check used in the data link layer can only identify part of the transmission errors, and the detection coverage of multi-bit errors and burst errors is limited, and error automatic correction cannot be realized. Once an undetected error or an uncorrectable fault occurs, it may lead to distortion of the control instruction, directly threatening the safety of engine operation, so it is urgent to explore more efficient fault-tolerant communication technologies and architecture design. SUMMARY

[0005] The technical problem solved by the present application is to overcome the shortcomings of the prior art, and to provide an engine distributed system fault-tolerant method based on a braided network, aiming at the shortcomings of the communication reliability and fault coverage of the distributed control system of an aero-engine.

[0006] Technical scheme: In order to achieve the above-mentioned purpose, the present application adopts the following technical scheme:

[0007] The present application provides an engine distributed system fault-tolerant method based on a braided ring network, comprising the following steps:

[0008] Step 1, overall architecture design of braided ring fault-tolerant network:

[0009] The braided ring network fault-tolerant system is composed of network communication cables and intelligent communication nodes, and the network communication cables in the present scheme include direct links and indirect links; the intelligent communication nodes are composed of a data verification module, a data conversion module and a mode selection module.

[0010] The braided ring network fault-tolerant system adopts a communication architecture based on a time-triggered protocol, the physical layer communication cable adopts an RS-485 differential serial communication standard for asynchronous communication, data is transmitted in bytes, and the data frame of serial communication includes 1 start bit, 8 data bits and 1 stop bit, so that 10bit serial data stream is transmitted in a single communication of the physical bus in the present system. The network communication cable is designed based on a braided ring topology, each intelligent communication node contains two direct links and two indirect links, forming a ring network and a braided ring network.

[0011] The intelligent communication node is based on a high-performance ZYNQ7020 development platform, which integrates ARM and FPGA, and the node fault-tolerant function in the present scheme is designed based on the FPGA end. The serial data from the communication bus is transmitted to the node, converted to parallel data recognizable by the processor and protocol controller through the data conversion module; the real-time function is switched through the mode selection module; the corresponding data verification and forwarding operation is performed through the data verification module; and finally the serial signal is converted through the data conversion module and sent to the communication bus.

[0012] Step 2, design of the data verification module of the intelligent communication node:

[0013] Step 2.1, the data verification module is designed based on the FPGA lookup table, and the comparison is performed in units of 16-bit parallel data. The module adopts a lookup table cascade structure and realizes the verification function through the design of a truth table;

[0014] Step 2.2, design truth table based on six-input lookup table. The first-level lookup table compares the input data, and the two-way input data is grouped into A[0:2], B[0:2], A[3:5], B[3:5], …, A

[16] , B

[16] by bit. A single lookup table has a total of 64 states according to the different inputs, and when the corresponding bits of A and B inputs are equal, the lookup table outputs the result as 1, and the remaining 63 states output 0. The second-level lookup table summarizes the first-level output results, and the 16-bit data is divided into 6 groups for lookup table comparison, and its output is used as the input of the second-level lookup table, which has a total of 64 possibilities. When all inputs are 1, the second-level lookup table outputs 1, and the remaining 63 cases output 0.

[0015] Step 2.3, when the module receives two-way data A and B, it will be verified according to the lookup table and output the verification result: when all bits of input data A and B are equal, the module outputs 1; when A and B are not equal, the module outputs 0.

[0016] Step 3, intelligent communication node data conversion module design:

[0017] Step 3.1, the data conversion module is designed based on shift register and finite state machine. The shift register realizes the mutual conversion of serial data and parallel data through the characteristics of bit-by-bit input or output; the finite state machine realizes the splicing or splitting conversion of 8-bit data and 16-bit data through the strict unification of state and behavior;

[0018] Step 3.2, serial data is input to the module port, and the module receives the start bit flag to generate the baud rate clock according to the preset communication rate. On the next clock rising edge, the bus data is collected and stored in the first bit of the shift register; on the subsequent clock rising edge, the current bus data is collected and stored in the first bit of the shift register, and the data in the register moves one bit backward; when 8-bit data collection is completed, the register outputs all data bits to the state machine at the next clock rising edge;

[0019] Step 3.3, after receiving the first 8-bit data, the state machine stores it in the temporary register and transfers from state 0 to state 1; when receiving the second 8-bit data, the data is output to the 16-bit register along with the data in the temporary register, and returns to state 0, completing the data splicing process;

[0020] Step 3.4, when the module receives 16-bit parallel data, it is latched into a 16-bit register; on the first clock rising edge, the state machine outputs the low 8-bit data to the cache register and transfers from state 0 to state 1; on the next clock rising edge, the state machine outputs the high 8-bit data to the cache register and returns to state 0.

[0021] Step 3.5, data in the cache register is transmitted to the shift register, the shift register pulls the interface level low at the first clock rising edge, forming the start bit of the serial signal; at the subsequent clock rising edge, the first data in the register is output to the serial port, and the data in the register is moved to the port one bit at a time until all the data is output; at the next clock rising edge, the level is pulled high to generate the serial data stop bit.

[0022] Step 4, the intelligent communication node mode selection module is designed:

[0023] Step 4.1, the mode selection module switches the mode according to the mode identification carried by the data and the identity identification of the node itself. The mode switching identification includes a forwarding identification and a receiving identification, both of which are 4-bit binary codes. The forwarding identification indicates the number of times of forwarding the current data in the system, and the receiving identification represents the receiving node information corresponding to the current data. The identity identification represents the identity information of the node itself, which is allocated at the beginning of the design of all nodes in the system;

[0024] Step 4.2, after the node receives the mode identification, it first judges the receiving identification of the high 4 bits. If it is the same as the identity identification of the node itself, the node switches to the receiving mode. If the receiving identification does not match the identity identification of the node, the current mode is judged according to the forwarding identification. The initial identification is 0x1. When the node receives 0x1, the mode is switched to the primary forwarding mode, and the forwarding identification value in the mode identification is increased by 0x1 and forwarded to the downstream node. When the node receives the forwarding identification as other values, the mode is switched to the check forwarding mode, and the forwarding identification value in the mode identification is increased by 0x1 and forwarded to the downstream node.

[0025] The beneficial effects of the present application are:

[0026] (1) The present application adopts a woven ring topology for communication network design, which improves the redundancy without increasing the hardware overhead, and improves the reliability of the communication system.

[0027] (2) The present application uses high-performance ZYNQ7020 as an intelligent node processing platform, which has fast system response speed, strong fault tolerance and low failure rate, thereby improving the system reliability; through real-time local processing of data, the computing burden of the central controller is reduced, thereby improving the performance of the distributed control system.

[0028] (3) The present application adopts modular design, and the communication node is divided into three parts, which reduces the volume and weight of the node and is convenient to maintain; the design idea of state machine is adopted, which simplifies the processing logic and has high reliability; through parallel check design, the speed limitation of serial data check is overcome, and the real-time performance of the system is improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1Self-checking data forwarding mechanism for a woven ring fault-tolerant network.

[0030] Figure 2 Data integrity reconstruction mechanism for a woven ring fault-tolerant network.

[0031] Figure 3 Overall architecture design schematic diagram of the intelligent communication node of the present application.

[0032] Figure 4 Check function simulation result schematic diagram of the data check module of the present application.

[0033] Figure 5 Serial-to-parallel function simulation result schematic diagram of the data conversion module of the present application.

[0034] Figure 6 Parallel-to-serial function simulation result schematic diagram of the data conversion module of the present application.

[0035] Figure 7 Data splicing function simulation result schematic diagram of the data conversion module of the present application.

[0036] Figure 8 Data splitting function simulation result schematic diagram of the data conversion module of the present application.

[0037] Figure 9 Mode switching function simulation result schematic diagram of the mode selection module of the present application.

[0038] Figure 10 Physical development achievement and communication fault-tolerant experimental verification environment of the present application.

[0039] Figure 11 Communication fault-tolerant experimental verification result of the present application.

[0040] Figure 12 BRAIN intelligent node working mechanism schematic diagram of the present application. DETAILED DESCRIPTION

[0041] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings:

[0042] Figure 1Self-checking data forwarding is one of the two core fault-tolerant mechanisms of the woven ring network topology. The embodiment takes a woven ring network composed of 8 nodes as an example, in which node 1 is the sending node and node 5 is the receiving node. In the communication process, data is sent by the sending node, propagates in two directions of the network, and is finally received by the receiving node after being forwarded by the forwarding nodes. When the intelligent communication nodes in the network fail to send error data, the downstream nodes can check the received data in real time and judge the correctness of the data. The specific working process is as follows: nodes 7 and 8 in the counterclockwise direction of the figure fail, causing the data sent by them to be incorrect; the check forwarding node (node 6) downstream checks the consistency of the data from the direct link and the indirect link through the data checking module, identifies that the data is different, sets the data integrity flag from the fault path (counterclockwise direction) to be invalid, and continues to forward the data and the flag. The data propagates in two directions to the receiving node, and the receiving node (node 5) receives the data and the integrity flag from the two directions at the same time, and makes a decision according to the flag: judges that the data from the counterclockwise direction is invalid and discards it, and selects the correct data from the clockwise direction for subsequent processing.

[0043] Figure 2 Data integrity reconstruction is another core fault-tolerant mechanism of the woven ring network topology. In the normal communication process, the flow of data can be regarded as two bidirectional parallel paths of direct ring type and woven ring type, and the correctness of the data is guaranteed through intermediate node checking. When communication path interruption faults occur in the network, due to the existence of the two parallel paths, the direct link and the indirect link can be flexibly recombined to form new available paths, thereby improving data availability. As shown in Figure 2 When multiple communication path interruptions occur in the network (for example, between nodes 2-2, 2-4, 5-7, and 6-7), the system can dynamically form new effective communication paths such as “recombined path 1” (via nodes 1-8-6-5) and “recombined path 2” (via nodes 1-3-5) through the combination of the direct link and the indirect link, thereby ensuring that data can reach the receiving node through at least one path. However, the recombined path cannot perform data checking, so after the receiving node receives data from two directions, the node checks and compares the data bit by bit, and if two or more of the data are the same, the data is regarded as correct data for data integrity reconstruction. In the figure, four communication path interruptions are represented by dashed lines, and after recombination of the direct link and the indirect link, recombined path 1 and recombined path 2 are formed. The receiving node receives data from two directions and checks it, and since the path interruption faults do not cause errors in the available data itself, the received data is the same, and the node can achieve data integrity reconstruction.

[0044] Figure 3This invention relates to an intelligent communication node design based on the ZYNQ7020 platform and VIVADO development software. The red box indicates the module design involved in this invention; the green box indicates the functional configuration necessary for the ZYNQ7020 platform to function.

[0045] Figure 4 This is a simulation result of the data verification module's verification function for two input data channels A and B. When input signals A and B are not equal, the data integrity flag is invalid; when input signals A and B are equal, the data integrity flag is valid. In the figure, when input data A=0x0000 and B=0xffff, A≠B, and the output flag AEQB=0; when input data A=B=0x00ff, the output flag AEQB=1.

[0046] Figure 5 This is a simulation result of the serial-to-parallel conversion function of the serial-to-parallel conversion module in the data conversion module. When a 10-bit serial data stream, including start and stop bits, is input, the module can extract 8 data bits and convert them into parallel data output. In the figure, the input serial data stream is 0110100111, and the output is 0xd3 valid data bits; when the input serial data stream is 0011010101, the output is 0x6a valid data bits.

[0047] Figure 6 This is the simulation result of the parallel-to-serial conversion function of the serial-to-parallel conversion module in the data conversion module. When parallel data is input to the module, the module starts outputting the data bit by bit on the rising edge of the clock, adding a start bit and a stop bit, until all data is serially output. For example, in the figure, if parallel data 0xd3 is input, the corresponding serial data 0110100111 is output; if parallel data 0x9a is input, the corresponding serial data 0100110101 is output.

[0048] Figure 7 This is a simulation result of the data concatenation function of the bit-width conversion module in the data conversion module. When the module receives 8 bits of data, it operates according to its current state: when in state 0, it stores the data in a temporary register; when in state 1, it concatenates and outputs 16 bits of parallel data. Due to the strict correspondence between state machine states and operations, the module can still complete the data concatenation process based on the data validity flag even when the data input is not continuous. In the figure, continuous inputs of 0xab, 0xcd, 0x56, and 0x78 result in outputs of 0xabcd and 0x5678; non-continuous inputs of 0x11 and 0x22 result in an output of 0x1122.

[0049] Figure 8This is a simulation result of the data splitting function of the bit-width conversion module in the data conversion module. When the module receives 16-bit data, it latches it into a register to prevent the data from being overwritten during the splitting process; subsequently, the lower 8 bits and the higher 8 bits of the data are output separately on the rising edge of the clock. In the figure, consecutive inputs of 0xabcd and 0x5678 result in outputs of 0xab, 0xcd, 0x56, and 0x78; non-consecutive inputs of 0xa5b5 and 0x5a5b result in outputs of 0xa5, 0xb5, 0x5a, and 0x5b.

[0050] Figure 9 This is a simulation result of the mode selection module's function in parsing mode identifiers. The module has a unique built-in identifier. When it receives a mode identifier signal, if the received identifier matches its own identifier, it switches to receive mode; if the received identifier differs from the identifier, it switches modes based on the forwarding identifier. If the forwarding identifier is 0x1, it switches to primary forwarding mode; otherwise, it switches to check forwarding mode. In the diagram, the node's own identifier is 0x5. When the mode identifier is 0x31, the node switches to primary forwarding mode; when the mode identifier is 0x62, the node switches to check forwarding mode; and when the mode identifier is 0x52, the node switches to receive mode.

[0051] Figure 10 This invention presents the physical development results and the experimental verification environment for communication fault tolerance. During the development process, the system network consisted of eight intelligent communication nodes. When verifying the development results experimentally, the results were observed by outputting data to a host computer via a serial port, and the system's fault tolerance function was verified through simulated fault injection.

[0052] Figure 11 This is the result of a communication fault tolerance experiment. Figure 10 Communication fault tolerance experiments were conducted in the experimental environment, and the final results are as follows: Figure 11 As shown. During the functional design and experimentation, it is assumed that the sending and receiving nodes can function normally. Communication line interruption faults are simulated by powering down the forwarding nodes and cutting off their input or output paths. Node faults are simulated by changing the logic commands of individual nodes to cause them to send erroneous data. When the number of faulty nodes does not exceed two, the system is fault-tolerant and the receiving node can receive correct data. When the number of faulty nodes exceeds two, the system can achieve fault tolerance even when the faulty nodes are not adjacent, and can tolerate a maximum of four node faults. Figure 1 Even when the sequence numbers are 2 / 4 / 6 / 8, the node can still achieve fault tolerance. When a node experiences a path interruption failure, if a complete path can be reconstructed in both clockwise and counterclockwise directions from the sending node to the receiving node, the system can perform data integrity reconstruction and achieve fault tolerance. Figure 11When the final received data is 0x00ff, the integrity flag is 1, indicating that the system fault tolerance was successful; when the integrity flag is 0, it indicates that the system fault tolerance failed.

[0053] Figure 12 The internal functional modules of the intelligent communication node in this invention and its basic data flow are shown.

[0054] As shown in the figure, the external connection part of the node includes input and output interfaces for node identification, serial data, and integrity flags. The internal components of the node mainly contain the core functional modules defined in the manual:

[0055] Power supply system: Provides working power for each module of the node.

[0056] Data transceiver: Responsible for physical signal transmission and reception with the communication link.

[0057] ARM+FPGA core processing platform: The integrated platform such as ZYNQ7020 described in the specification is adopted, wherein the FPGA side is used to implement the real-time fault-tolerant processing logic of the present invention.

[0058] Data conversion module: responsible for the conversion between serial and parallel data.

[0059] Mode selection module: Based on the mode identifier carried in the input data and the node's preset identity identifier, determine and switch the node's working mode.

[0060] Protocol Controller and Data Verification Module (BRAIN Data Verification): Performs real-time consistency verification on data from different paths and generates data integrity flags.

[0061] Its basic workflow is as follows: Nodes receive serial data containing identifiers and flags from the network link. After processing by the data conversion module, the mode selection module parses the working mode and guides the data to the verification module for corresponding processing. The processed valid data and the updated identifier are restored to serial format by the data conversion module and then forwarded to the downstream network link.

Claims

1. A fault-tolerant method for a distributed engine system based on braided ring networks, characterized in that, The method is executed in a braided ring network consisting of multiple intelligent communication nodes connected by direct and indirect links, and includes the following steps: Step 1: Nodes in the network receive data and parse the pattern identifier carried in the data; the pattern identifier includes a forwarding identifier and a receiving identifier; Step 2: The sending node simultaneously sends the same data carrying the initial mode identifier to both the direct and indirect links of the braided ring network; Step 3: Based on the parsed pattern identifier, the node that receives the data acts as a primary forwarding node, updates the forwarding identifier in the pattern identifier, and forwards the data. Step 4: Based on the parsed pattern identifier, the node receiving the data acts as a verification and forwarding node and performs the following operations: converting the received serial data into parallel data; performing real-time consistency verification on the two parallel data streams from the direct link and the indirect link based on the lookup table cascade structure in the FPGA, and generating a data integrity flag; updating the forwarding flag in the pattern identifier; and forwarding the verified data, the data integrity flag, and the updated pattern identifier together. Step 5: Based on the parsed pattern identifier, when the receiving identifier in the pattern identifier matches the node's own preset identity identifier, the node acts as the receiving node and performs the following operations: receiving data and its data integrity flag from both directions of the network; if the data integrity flag is valid, then adopting the data corresponding to the flag; if the data integrity flag is invalid or missing, then comparing the data content from both directions and adopting consistent data to achieve data integrity reconstruction.

2. The method according to claim 1, characterized in that, The consistency check in step 4 is implemented in the following way: The parallel data A and B from the two paths are grouped bit by bit; Each group of data is input into multiple first-level lookup tables for parallel comparison. When all corresponding bits of the data in a group are equal, the first-level lookup table outputs the first valid signal. All the first valid signals are input into the second-level lookup table. When all the first valid signals are valid, the second-level lookup table outputs the second valid signal as the data integrity flag.

3. The method according to claim 2, characterized in that, The bit-by-bit grouping involves dividing the data into groups of three and inputting them into a six-input lookup table for parallel comparison.

4. The method according to claim 1, characterized in that, The conversion from serial data to parallel data in step 4, and the subsequent conversion from parallel data to serial data, are achieved in the following way: After receiving the start bit of the serial data, a baud rate clock is generated; Driven by the baud rate clock, the serial data stream is converted into 8-bit parallel data through a shift register; Two consecutive 8-bit parallel data are concatenated into a 16-bit parallel data using a finite state machine; During data output, the 16-bit parallel data is split into two 8-bit parallel data using the finite state machine. After adding start and stop bits to the 8-bit parallel data through the shift register, it is converted into a serial data stream for output.

5. The method according to claim 1, characterized in that, In steps 3, 4, and 5, the node's self-configuration rules are as follows: If the receiving identifier of the data parsed by a node matches its own identity identifier, then it is considered a receiving node. If there is no match, the value of the forwarding identifier is used to determine the primary forwarding node: if the value of the forwarding identifier is 0x1, it is used as the primary forwarding node; if the value of the forwarding identifier is not 0x1, it is used as the verification forwarding node. In this process, both the primary forwarding node and the verification forwarding node increment the value of the forwarding identifier by 0x1 before forwarding the data.

6. The method according to claim 1, characterized in that, In step 4, the verification forwarding node selects data from the indirect link for forwarding.

7. The method according to claim 1, characterized in that, The intelligent communication nodes in the braided ring network implement the data conversion, verification, and forwarding functions based on the FPGA terminal of the ZYNQ7020 platform.

8. The method according to claim 4, characterized in that, The serial data follows the RS-485 communication standard, and its data frame format includes 1 start bit, 8 data bits, and 1 stop bit.

9. The method according to claim 1, characterized in that, The braided ring network consists of 8 intelligent communication nodes.

10. The method according to claim 1, characterized in that, Based on the topology of the braided ring network and the data integrity reconstruction mechanism, the method can tolerate no more than two node failures at any arbitrary location.

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