Message verification system and method
By using a simulation model for table lookup operations and Scoreboard verification in the message verification system, the dependence on internal signals of the DUT in traditional methods is solved, achieving efficient and accurate verification results and improving simulation speed and environment reusability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-05
- Publication Date
- 2026-04-07
AI Technical Summary
Traditional message verification methods rely heavily on the internal signals of the DUT, resulting in problems such as signal correctness dependence, poor adaptability to gate-level simulation, low simulation efficiency, high resource consumption, and insufficient maintainability and versatility.
The simulation model receives the excitation signal and performs a lookup operation to generate the target excitation signal. After the DUT performs the lookup operation, the Scoreboard performs the comparison and verification. This approach is independent of the internal signal and timing dependencies. A proxy is used to cache the lookup results and simulate out-of-order return, which improves the independence and versatility of the verification environment.
It significantly improves simulation speed and verification accuracy, reduces dependence on internal signals, lowers system complexity and resource consumption, and enhances the reusability and independence of the verification environment.
Smart Images
Figure CN121814652A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of message verification, and more specifically, to a message verification system and method. Background Technology
[0002] In existing network environments, to effectively manage data traffic and avoid network congestion, network chips typically employ various mechanisms such as Access Control Lists (ACLs) and token bucket algorithms to implement fine-grained control over data flows across different channels. To achieve precise traffic control, the chip needs to frequently initiate lookup requests to external storage modules or other traffic management units. However, due to differences in storage architecture, processing logic, and real-time load among external modules, the processing time for different lookup requests fluctuates significantly, resulting in inconsistent lookup latency and even situations where the order of returned results differs from the order of requests. After obtaining the lookup results, the chip also needs to combine dynamically updated configuration information to execute corresponding traffic control strategies for different channels.
[0003] To improve data processing efficiency, chips generally adopt a pipelined processing approach, which divides long processing paths into multiple stages, allowing each stage to process different data in parallel, thereby significantly improving system throughput and processing speed. However, in the chip verification stage, reference models typically use a serial processing approach, that is, processing each input request sequentially, and only starting the processing flow of the next request after the current request has been completely processed.
[0004] Because the Design Under Test (DUT) processes multiple lookup requests in parallel, each request may be at a different stage of the pipeline. Furthermore, the external lookup process involves latency uncertainties and out-of-order results, leading to a discrepancy between the DUT's processing order of lookup results and the original input order. In contrast, the serial processing logic upon which the validation model relies strictly requires a strict correspondence between the input and lookup result order, thus creating a fundamental contradiction between the DUT's behavior and the reference model.
[0005] Traditional verification methods typically capture internal signals from the Device Under Test (DUT) and cache some information to accommodate the aforementioned behavioral differences. For example, the model extracts channel identifier registers or cached index information to determine the actual processing order of the DUT after receiving the lookup result. The model adjusts the order of cached information to match the subsequent processing order of the DUT (i.e., the out-of-order return of results), thereby simulating the DUT behavior and completing the result comparison. This method requires verification personnel to have a deep understanding of the DUT's internal identifier signals and their design logic, and to break down the verification model into multiple stages to simulate the pipeline processing, caching relevant information at each stage. During DUT processing, by capturing its internal trigger signals and related configuration signals, the verification model keeps its processing synchronized with the DUT. Figure 1As shown.
[0006] The existing technology simulation process is as follows: Start: Simulation begins; Input: Send input stimuli to the reference model and the DUT in the order of 1, 2, 3, 4… S1: Complete the logical processing before looking up the external table, with the execution order being 1, 2, 3, 4... and cache the subsequent required information in the reference model; S2: Capture internal signals of the DUT and identify the actual execution order after the search results are out of order; S3: Retrieve the corresponding information from the cache according to the new order and complete the subsequent processing.
[0007] In summary, traditional verification methods rely heavily on the internal signals of the DUT to construct an accurate simulation timing model, and have the following inherent drawbacks: Dependence on signal correctness: If the captured internal signals themselves contain design errors, the verification model will lose its reference value. Furthermore, the selection of internal signals depends entirely on the verification personnel's understanding of the DUT, which carries the risk of overlooking design flaws due to misunderstandings.
[0008] Gate-level simulation has poor adaptability: During the gate-level simulation stage, some internal signals may be optimized during the synthesis process, causing the verification environment to be unable to capture the corresponding signals, thus rendering traditional verification methods ineffective in the Gate-level simulation stage.
[0009] Low simulation efficiency and high resource consumption: The verification model needs to frequently wait for internal signals as trigger conditions, causing the model execution to lag behind the DUT and reducing the simulation speed. At the same time, caching information at each stage will consume a large amount of storage resources, affecting system performance.
[0010] Insufficient maintainability and versatility: Once the internal signals or processing logic of the DUT change, the verification environment needs to be adjusted accordingly, resulting in high maintenance costs. Furthermore, due to the module-specific nature of the internal signals, this verification method is difficult to directly migrate to other modules with similar query behaviors. Summary of the Invention
[0011] The purpose of this invention is to provide a message verification system and method that can improve verification efficiency and accuracy.
[0012] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a message verification system, the system comprising: a simulation model, a DUT, and a Scoreboard; The simulation model is used to receive the excitation signal sent by the excitation transmitter, and when a lookup operation is required on the excitation signal, it generates the result of an external lookup table to obtain the first target excitation signal; The DUT is used to receive the excitation signal sent by the excitation transmitter, and when it is necessary to perform a table lookup operation on the excitation signal, it performs a table lookup operation based on the excitation signal to obtain the second target excitation signal; The scoreboard is used to compare the first target excitation signal with the second target excitation signal to complete the verification.
[0013] In an optional implementation, the simulation model is specifically used to perform a first logical processing based on the excitation signal to obtain a first excitation signal, determine whether the first excitation signal needs to perform an external table lookup, and if so, perform an internal table lookup operation and generate a table lookup result to obtain a second excitation signal, and perform a second logical processing on the second excitation signal to obtain a first target excitation signal, wherein the first logical processing is a logical processing operation before looking up the external table, and the second logical processing is other functional logic.
[0014] In an optional implementation, the device further includes a proxy; The agent is used to receive the lookup results generated by the simulation model and cache them in a two-dimensional cache queue, wherein the two-dimensional cache queue includes data cached in different channels.
[0015] In an optional implementation, the DUT is specifically used to perform a first logical processing based on the stimulus signal to obtain a third stimulus signal, determine whether the third stimulus signal needs to perform an external table lookup, and if so, perform a table lookup operation based on the proxy and determine the lookup result to obtain a fourth stimulus signal, and perform a second logical processing on the fourth stimulus signal to obtain a second target stimulus signal. The first logical processing is a logical processing operation before looking up the external table, and the second logical processing is other functional logic.
[0016] In an optional implementation, the agent is used to receive a lookup validity signal sent by the DUT, and obtain the lookup result from the two-dimensional cache queue based on the lookup validity signal; The lookup result is sent to the DUT.
[0017] In an optional implementation, the agent is further configured to determine a random delay and send the lookup result to the DUT based on the random delay.
[0018] In an optional implementation, the two-dimensional cache queue is generated earlier than the time when the valid lookup result sent by the DUT is received.
[0019] In an optional implementation, the Scoreboard is specifically used for: Store the first target excitation signal into the first two-dimensional queue; The second target excitation signal is stored in the second two-dimensional queue; The verification is completed by comparing the first two-dimensional queue with the second two-dimensional queue.
[0020] In an optional implementation, the Scoreboard is specifically used for: Determine the first data in each channel of the first two-dimensional queue; Determine the second data for each channel in the second two-dimensional queue; Compare the first and second data in the channels with the same channel index in the first two-dimensional queue and the second two-dimensional queue; If the first data and the second data in the channel with the same channel index in the first two-dimensional queue and the second two-dimensional queue are consistent, then the verification is considered successful. If the first and second data in a channel with the same channel index in the first two-dimensional queue and the second two-dimensional queue are inconsistent, then the verification is determined to have failed.
[0021] Thirdly, embodiments of this application provide a message verification method, which verifies messages through the message verification system.
[0022] This application has the following beneficial effects: This application receives the excitation signal sent by the excitation transmitter through a simulation model. When a lookup operation is required on the excitation signal, it generates the result of an external lookup table to obtain the first target excitation signal. The DUT (Device Under Test) receives the excitation signal sent by the excitation transmitter and performs a lookup operation based on the excitation signal when a lookup operation is required to obtain the second target excitation signal. The Scoreboard is used to compare the first target excitation signal and the second target excitation signal to complete the verification. This application eliminates the dependence on internal signals and timing, ensuring the independence and versatility of the verification environment, significantly improving simulation speed, and reducing dependence on internal signals, thereby improving the accuracy of verification. Attached Figure Description
[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a flowchart of the simulation process for existing technologies; Figure 2 A block diagram of an electronic device provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a message verification system provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the execution logic of a message verification system provided in an embodiment of the present invention; Figure 5 A schematic diagram of the execution logic of the simulation model provided in the embodiments of the present invention; Figure 6 This is a schematic diagram of the structure of a message verification system provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the execution logic of the DUT provided in an embodiment of the present invention; Figure 8 A schematic diagram illustrating the interaction between the Agent, the Model, and the DUT provided in an embodiment of the present invention; Figure 9 This invention provides a schematic diagram illustrating the interaction between the Agent and the DUT in an embodiment of the invention. Figure 10 This is a schematic diagram of the execution logic of the Scoreboard provided in an embodiment of the present invention. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0026] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0027] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0028] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.
[0029] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0030] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0031] Extensive research by the inventors revealed that traditional verification methods typically capture internal signals from the Device Under Test (DUT) and cache some information to accommodate the aforementioned behavioral differences. For example, the model extracts channel identifier registers or cached index information to determine the actual processing order of the DUT after receiving the lookup results. The model adjusts the order of cached information to match the subsequent processing order of the DUT (i.e., the out-of-order return of results), thereby simulating the DUT's behavior and completing the result comparison. This new method requires verification personnel to have a deep understanding of the DUT's internal identifier signals and their design logic, and to break down the verification model into multiple stages to simulate a pipelined processing flow, caching relevant information at each stage. During DUT processing, by capturing its internal trigger signals and related configuration signals, the verification model maintains synchronous processing with the DUT.
[0032] Traditional verification methods rely heavily on the internal signals of the DUT to construct an accurate simulation timing model, which has the following inherent drawbacks: Dependence on signal correctness: If the captured internal signals themselves contain design errors, the verification model will lose its reference value. Furthermore, the selection of internal signals depends entirely on the verification personnel's understanding of the DUT, which carries the risk of overlooking design flaws due to misunderstandings.
[0033] Gate-level simulation has poor adaptability: During the gate-level simulation stage, some internal signals may be optimized during the synthesis process, causing the verification environment to be unable to capture the corresponding signals, thus rendering traditional verification methods ineffective in the Gate-level simulation stage.
[0034] Low simulation efficiency and high resource consumption: The verification model needs to frequently wait for internal signals as trigger conditions, causing the model execution to lag behind the DUT and reducing the simulation speed. At the same time, caching information at each stage will consume a large amount of storage resources, affecting system performance.
[0035] Insufficient maintainability and versatility: Once the internal signals or processing logic of the DUT change, the verification environment needs to be adjusted accordingly, resulting in high maintenance costs. Furthermore, due to the module-specific nature of the internal signals, this verification method is difficult to directly migrate to other modules with similar query behaviors.
[0036] In view of the above problems, this embodiment provides a message verification system and method. It can receive excitation signals sent by an excitation transmitter through a simulation model, and when a lookup operation is required on the excitation signal, perform an internal lookup operation within the simulation model to obtain a first target excitation signal. The DUT (Distributed Under Test) receives the excitation signal sent by the excitation transmitter and, when a lookup operation is required on the excitation signal, performs a lookup operation based on the excitation signal to obtain a second target excitation signal. The Scoreboard is used to compare the first target excitation signal and the second target excitation signal to complete the verification. This application eliminates the dependence on internal signals and timing, ensuring the independence and universality of the verification environment, significantly improving simulation speed, and reducing dependence on internal signals, thereby improving the accuracy of verification. The solution provided in this embodiment will be described in detail below.
[0037] This embodiment provides an electronic device capable of verifying messages. In one possible implementation, the electronic device can be a user terminal, such as, but not limited to, a server, smartphone, personal computer (PC), tablet computer, personal digital assistant (PDA), mobile internet device (MID), etc.
[0038] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the electronic device 100 provided in the embodiments of this application.
[0039] The electronic device 100 includes a message verification device 110, a memory 120, and a processor 130.
[0040] The components of the memory 120 and processor 130 are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The message verification device 110 includes at least one software function module that can be stored in the memory 120 in the form of software or firmware or embedded in the operating system (OS) of the electronic device 100. The processor 130 is used to execute executable modules stored in the memory 120, such as the software function modules and computer programs included in the message verification device 110.
[0041] The memory 120 may be, but is not limited to, random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc. The memory 120 is used to store programs, and the processor 130 executes these programs after receiving execution instructions. Understandable. Figure 2 The structure shown is for illustrative purposes only. Electronic devices may also have more advanced features. Figure 2 Showing more or fewer components, or having with Figure 2 The different configurations shown are worth noting. Figure 2 The components shown can be implemented in hardware, software, or a combination thereof. That is to say, the implementation of the processing flow in the above embodiments is not limited to the processor reading and running purely computer-readable program code from memory, but can also be implemented through hardware or logic devices.
[0042] It should be understood here that improvements to a technology can be divided into hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) and software improvements (improvements to the methodology). However, with technological advancements, many improvements to the methodology can now be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that an improvement to the methodology cannot be implemented using a hardware entity module. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog are the most commonly used. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.
[0043] Please refer to Figure 3The diagram shows the structure of a message verification system. The following section will describe in detail the various components of the system.
[0044] The message verification system 10 includes: a simulation model 101, a DUT 102, and a Scoreboard 103; The simulation model 101 is used to receive the excitation signal sent by the excitation transmitter, and when a table lookup operation is required on the excitation signal, it generates the result of an external table lookup to obtain a first target excitation signal; the DUT 102 is used to receive the excitation signal sent by the excitation transmitter, and when a table lookup operation is required on the excitation signal, it performs a table lookup operation based on the excitation signal to obtain a second target excitation signal; the Scoreboard 103 is used to compare the first target excitation signal and the second target excitation signal to complete the verification.
[0045] like Figure 4 The diagram shows the execution logic of the message verification system. Since the simulation model simulates the behavior logic of the chip, it can predict whether the current input needs to look up an external table entry and which external table entry to look up in advance, thus generating the lookup result in the simulation model in advance.
[0046] Traditional verification requires sequential pairing of input and external lookup results to ensure that the verification platform does not completely lose its simulation behavior due to pairing errors during serial simulation.
[0047] In this invention, the simulation model pre-generates search results, ignoring interference factors such as out-of-order search results and uncertain return delays, directly achieving the pairing of input and search results. The verification model no longer relies on external stimuli, operating as an independent system, and feeds back the results to the verification environment and DUT through components by generating search results. This mechanism allows the verification model to operate completely without relying on internal indicator signals, reducing the complexity of the verification environment for acquiring internal signals and the time spent waiting for signals, significantly improving the verification speed and reducing verification costs.
[0048] Specifically, for Figure 4 Explanation: --Start: Simulation of this invention begins; --Input: Simultaneously sends input excitation signals to both the simulation model and the DUT, in the order of 1, 2, 3, 4… The execution logic for the simulation model is as follows: -SIM_S1: The simulation model completes the logical processing work before looking up the external table, and the execution order is 1, 2, 3, 4… -SIM_D1: Determines whether an external table lookup is required based on the result of SIM_S1. If an external table lookup is required, execute SIM_S2; otherwise, execute SIM_S4 directly. -SIM_S2: The simulation model directly generates the results of the external lookup table and directly pairs the lookup results with the input. The execution order is 1, 2, 3, 4… -SIM_S3: Directly generates the external lookup table results from the simulation model to complete subsequent operations; -SIM_S4: Completes the remaining operations of the function and outputs the first target excitation signal, with the output sequence being 1, 2, 3, 4… For the execution logic of the DUT: -DUT_S1: The DUT completes the logical processing work before looking up the external table. The execution order is consistent with the input order, which is 1, 2, 3, 4… -DUT_D1: Determines whether an external table lookup is required based on the result of DUT_S1. If an external table lookup is required, execute DUT_S2; otherwise, execute DUT_S4 directly. -DUT_S2: The DUT sends table lookup requests to external table entries, with the request sending order being 1, 2, 3, 4… -DUT_S3: Due to the unpredictable return order of external table entries, the current return result is parsed to complete subsequent operations; the return result is inconsistent with the request sending order due to differences in external table entry load. In the diagram, the return order is 2, 4, 1, 3… -DUT_S4: Completes the remaining operations of the function and outputs the second target excitation signal. The output order is consistent with the order of the lookup table results: 2, 4, 1, 3… The scoreboard is used to compare the first target excitation signal with the second target excitation signal to complete the verification. Once the lookup result is generated by the simulation model, the matching of the lookup result with the input is directly achieved. It is no longer necessary to cache the input information within the simulation model and wait for subsequent captured internal signals to perform the matching.
[0049] like Figure 5 As shown, the execution logic of the simulation model may specifically include the following: S201: Perform first logic processing based on the excitation signal to obtain the first excitation signal.
[0050] S202: Determine whether the first excitation signal requires an external table lookup.
[0051] S203: If so, perform an internal table lookup operation and generate the lookup result to obtain the second excitation signal.
[0052] S204: Perform second logic processing on the second excitation signal to obtain the first target excitation signal.
[0053] The first logical processing is the logical processing operation before looking up the external table, and the second logical processing is other functional logic.
[0054] For example, there are multiple ways to obtain the first excitation signal by performing the first logic processing based on the excitation signal. If the DUT is a network routing lookup chip, the first logic processing can be to extract the destination IP address, VLAN ID, etc. If the DUT is a processor, the first logic processing is to parse the simulation model instruction, determine whether it is a load instruction or a store instruction, and calculate the virtual address.
[0055] For operations requiring external table lookup, the simulation model performs an internal table lookup and generates the lookup result. The simulation model then directly uses the lookup result for subsequent processing to obtain the second excitation signal.
[0056] Meanwhile, the simulation model will send the generated table lookup results to the agent.
[0057] There are various ways to perform second logic processing on the second excitation signal to obtain the first target excitation signal, such as data processing and encapsulation, metadata appending and tag transmission, and state update operations.
[0058] like Figure 6 As shown, the verification system 10 also includes an agent 104; the agent 104 is used to receive the lookup results generated by the simulation model and cache them in a two-dimensional cache queue, wherein the two-dimensional cache queue includes data cached in different channels.
[0059] The lookup results in the two-dimensional cache queue are used for subsequent DUT calls.
[0060] like Figure 7 As shown, the execution logic of the DUT can specifically include the following: S301: Perform first logic processing based on the excitation signal to obtain the third excitation signal.
[0061] S302: Determine whether the third excitation signal requires an external table lookup.
[0062] S303: If so, then perform a table lookup operation based on the agent, determine the lookup result, and obtain the fourth excitation signal.
[0063] S304: Perform second logic processing on the fourth excitation signal to obtain the second target excitation signal.
[0064] The first logical processing is the logical processing operation before looking up the external table, and the second logical processing is other functional logic.
[0065] The first and second logic processing in the execution logic of the DUT are similar to those in the execution logic of the simulation model, and will not be elaborated here.
[0066] The method for determining whether the third excitation signal needs to perform an external table lookup can be as follows: when it is determined that the external table lookup behavior sent by the DUT contains a valid table lookup signal, the table lookup result is obtained from the two-dimensional cache queue in the agent based on the valid table lookup signal.
[0067] like Figure 8 The diagram shows the interaction between the Agent, the Model, and the DUT. In traditional UVM models, the Driver obtains the stimuli passed to the DUT from the sequencer. In this application, there is no need to obtain the lookup results from the outside. The model is directly generated based on the Model and sent to the Driver of the Agent. The lookup results are then sent to the DUT through the Driver of the Agent.
[0068] Specifically, such as Figure 9 As shown, the DUT completes the preprocessing and sends a lookup valid signal to the Agent. The lookup valid signal contains PI.LPBK (channel information). The Agent receives the lookup valid signal and uses the channel information as an index to find the lookup result generated by the simulation model Model stored in the two-dimensional queue, thus obtaining the fourth excitation signal. The fourth excitation signal is then subjected to the second logic processing to obtain the second target excitation signal.
[0069] When the Agent sends the table lookup result to the DUT, a random delay is determined, and the table lookup result is sent to the DUT based on the random delay to simulate the out-of-order situation caused by the uncertain return time in the actual situation.
[0070] For example, the agent receives request 1 at time 1 and request 2 at time 2; under random delay, the result of request 2 may be returned first.
[0071] It should be noted that the agent's two-dimensional cache queue is generated earlier than the time when the valid lookup result sent by the DUT is received.
[0072] Since the simulation model is processed by software, it can instantly complete the first logical processing based on the excitation signal to obtain the first excitation signal, determine whether the first excitation signal needs to perform an external table lookup, and if so, perform an internal table lookup operation and generate the lookup result to obtain the second excitation signal. Then, perform the second logical processing on the second excitation signal to obtain the first target excitation signal.
[0073] The DUT is hardware code, and its simulation speed is slower than that of the simulation model. Therefore, the agent's two-dimensional cache queue will be generated earlier than the time when it receives the valid lookup result sent by the DUT.
[0074] like Figure 10 As shown, the execution logic of Scoreboard can specifically include the following: S401: Store the first target excitation signal into the first two-dimensional queue.
[0075] S402: Store the second target excitation signal into the second two-dimensional queue.
[0076] S403: The verification is completed by comparing the first two-dimensional queue with the second two-dimensional queue.
[0077] Specifically, the first data in each channel of the first two-dimensional queue is determined, and the second data in each channel of the second two-dimensional queue is determined. The first data and the second data in the channels with the same channel index in the first two-dimensional queue and the second two-dimensional queue are compared. If the first data and the second data in the channels with the same channel index in the first two-dimensional queue and the second two-dimensional queue are consistent, the verification is determined to be successful. If the first data and the second data in the channels with the same channel index in the first two-dimensional queue and the second two-dimensional queue are inconsistent, the verification is determined to be unsuccessful.
[0078] The simulation model's first target stimulus signal and the DUT's second target stimulus signal are out of order. The simulation model maintains the order in which it receives the stimulus signals, while the DUT maintains the order in which the agent returns the lookup results. When the scoreboard verifies based on the first and second target stimulus signals, the order is ignored, and only the correctness of the data is verified.
[0079] This application also provides a message verification method, which verifies messages through a message verification system.
[0080] This application employs an innovative verification method that significantly reduces system complexity and increases simulation speed compared to traditional methods, while also reducing reliance on internal signals: 1) Existing inventions eliminate the need to capture the DUT's internal signals, treating the DUT as a black box for testing, thus preserving its encapsulation. Furthermore, verification personnel are not required to have a deep understanding of the DUT, segment the simulation model, or cache large amounts of intermediate information. System complexity and simulation-consuming cache resources are significantly reduced. 2) The automated generation of lookup results in the simulation environment eliminates the need to wait for external table entries, reducing waiting time during serial execution and significantly increasing serial simulation speed. Simultaneously, the optimized comparison mechanism avoids duplicate comparisons and data waiting that may occur between sequential and out-of-order comparisons, improving data comparison efficiency. 3) The reusability of the verification environment is greatly improved. The elimination of internal signals significantly enhances environment reusability, freeing it from the limitations of different internal signals and processing logic within different DUTs. Moreover, the adaptive loopback result return mechanism and channel-specific comparison mechanism for out-of-order comparisons can serve as standardized modules for arbitrary delay return scenarios, making them easy to integrate into different verification platforms or other module verification schemes.
[0081] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
[0082] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part. If the function is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.
[0083] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0084] The above descriptions are merely various embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A message verification system, characterized in that, The system includes: a simulation model, a DUT, and a scoreboard; The simulation model is used to receive the excitation signal sent by the excitation transmitter, and when a lookup operation is required on the excitation signal, it generates the result of an external lookup table to obtain the first target excitation signal; The DUT is used to receive the excitation signal sent by the excitation transmitter, and when it is necessary to perform a table lookup operation on the excitation signal, it performs a table lookup operation based on the excitation signal to obtain the second target excitation signal; The scoreboard is used to compare the first target excitation signal with the second target excitation signal to complete the verification.
2. The system according to claim 1, characterized in that, The simulation model is specifically used to perform a first logical processing based on the excitation signal to obtain a first excitation signal, determine whether the first excitation signal needs to perform an external table lookup, and if so, perform an internal table lookup operation and generate a table lookup result to obtain a second excitation signal, and perform a second logical processing on the second excitation signal to obtain a first target excitation signal. The first logical processing is a logical processing operation before looking up the external table, and the second logical processing is other functional logic.
3. The system according to claim 1, characterized in that, The system also includes an agent; The agent is used to receive the lookup results generated by the simulation model and cache them in a two-dimensional cache queue, wherein the two-dimensional cache queue includes data cached in different channels.
4. The system according to claim 3, characterized in that, The DUT is specifically used to perform a first logical processing based on the stimulus signal to obtain a third stimulus signal, determine whether the third stimulus signal needs to perform an external table lookup, and if so, perform a table lookup operation based on the proxy and determine the lookup result to obtain a fourth stimulus signal, and perform a second logical processing on the fourth stimulus signal to obtain a second target stimulus signal. The first logical processing is a logical processing operation before looking up the external table, and the second logical processing is other functional logic.
5. The system according to claim 3, characterized in that, The agent is used to receive the lookup validity signal sent by the DUT, and obtain the lookup result from the two-dimensional cache queue based on the lookup validity signal; The lookup result is sent to the DUT.
6. The system according to claim 5, characterized in that, The agent is also used to determine a random delay and send the lookup result to the DUT based on the random delay.
7. The system according to claim 5, characterized in that, The two-dimensional cache queue is generated earlier than the time when the valid lookup result sent by the DUT is received.
8. The system according to claim 1, characterized in that, The Scoreboard is specifically used for: Store the first target excitation signal into the first two-dimensional queue; The second target excitation signal is stored in the second two-dimensional queue; The verification is completed by comparing the first two-dimensional queue with the second two-dimensional queue.
9. The system according to claim 8, characterized in that, The Scoreboard is specifically used for: Determine the first data in each channel of the first two-dimensional queue; Determine the second data for each channel in the second two-dimensional queue; Compare the first and second data in the channels with the same channel index in the first two-dimensional queue and the second two-dimensional queue; If the first data and the second data in the channel with the same channel index in the first two-dimensional queue and the second two-dimensional queue are consistent, then the verification is considered successful. If the first and second data in a channel with the same channel index in the first two-dimensional queue and the second two-dimensional queue are inconsistent, then the verification is determined to have failed.
10. A message verification method, characterized in that, The message is verified using the message verification system of any one of claims 1-9.