Semiconductor structure, chip packaging structure and storage system

Abstract

The invention provides a semiconductor structure, a chip packaging structure and a storage system, relates to the technical field of semiconductors, and aims to improve the signal transmission quality of a bare chip in the semiconductor structure during signal transmission, reduce the production cost of the semiconductor structure and reduce the size of the semiconductor structure. The semiconductor structure comprises a plurality of bare chips, a connecting structure, a bonding layer and a first bonding part which are arranged in a stacked mode. A connection structure is located within the die and extends along a first direction, the first direction being a thickness direction of the die. The bonding layer is located between two adjacent bare chips. The first bonding part is located in the bonding layer and penetrates through the bonding layer. And along the first direction, the connecting structures in the two adjacent bare chips are connected through the first bonding parts. Comprising the semiconductor structure can be applied to a storage system to realize data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a chip packaging structure, and a memory system. Background Technology

[0002] Planar memory cells can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly, and the memory density for planar memory cells approaches its upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells. A 3D memory architecture can include arrays of memory cells.

[0004] It should be noted that the information disclosed in the background section is only used to enhance the understanding of the background art of the technology described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0005] On one hand, a semiconductor structure is provided. The semiconductor structure includes a plurality of stacked dies, interconnect structures, a bonding layer, and a first bonding portion. The interconnect structures are located within the dies and extend along a first direction, the first direction being the thickness direction of the dies. The bonding layer is located between two adjacent dies. The first bonding portion is located within the bonding layer and extends through the bonding layer. Along the first direction, the interconnect structures within two adjacent dies are connected through the first bonding portion.

[0006] The semiconductor structure provided in the above embodiments of this disclosure, by stacking multiple dies within the semiconductor structure, and connecting structures extending along a first direction (i.e., the thickness direction of the dies) within adjacent dies, are connected by a first bonding portion within a bonding layer located between the two adjacent dies, enabling signal transmission through the dies within the semiconductor structure via the connecting structures. Since the connecting structures extend along the first direction (i.e., the thickness direction of the dies), the overall connecting structure is linearly arranged, resulting in a shorter length. This not only helps reduce the production cost of the connecting structures, but also helps reduce the production cost of the semiconductor structure and the chip packaging structure. Furthermore, it shortens the signal transmission distance of the dies within the semiconductor structure when transmitting signals through the connecting structures, reducing transmission delay and signal attenuation, thereby improving signal transmission quality and ultimately enhancing the performance of the semiconductor structure.

[0007] Since the connection structures extending along the first direction (i.e., the thickness direction of the die) in two adjacent dies within a semiconductor structure are connected by a first bonding portion in the bonding layer located between the two adjacent dies, direct short-distance (e.g., micrometer-level) electrical connections can be achieved between the connection structures extending along the first direction (i.e., the thickness direction of the die) in two adjacent dies, which is beneficial for reducing the power consumption of the semiconductor structure and achieving high-speed I / O throughput.

[0008] Since the interconnect structure within the semiconductor structure is located within the die, and the interconnect structure extending along the first direction (i.e., the thickness direction of the die) within two adjacent dies is connected by a first bonding portion within the bonding layer between the two adjacent dies, multiple dies within the semiconductor structure do not need to be stacked in a staggered manner to ensure that the bonding pads on the top surface of each die are exposed for further wire bonding (WB). This allows multiple dies within the semiconductor structure to be stacked vertically, which can reduce the size of the semiconductor structure, facilitate the miniaturization of the semiconductor structure, and improve the integration density of the semiconductor structure.

[0009] In some embodiments, two adjacent dies are designated as a first die and a second die. The first bonding portion includes a first sub-part and a second sub-part arranged along the first direction. The first sub-part is connected to a connection structure in the first die, and the second sub-part is connected to a connection structure in the second die. The first sub-part and the second sub-part are at least partially in contact.

[0010] In some embodiments, in a cross-section of the semiconductor structure parallel to the first direction, both the first sub-part and the second sub-part are trapezoidal. The dimension of the first sub-part along the second direction at the end near the second sub-part is greater than the dimension of the first sub-part along the second direction at the end away from the second sub-part, where the second direction is perpendicular to the first direction. Similarly, the dimension of the second sub-part along the second direction at the end near the first sub-part is greater than the dimension of the second sub-part along the second direction at the end away from the first sub-part.

[0011] In some embodiments, the dimension of the first sub-part near the end of the second sub-part along the second direction is greater than the dimension of the second sub-part near the end of the first sub-part along the second direction, wherein the second direction is perpendicular to the first direction.

[0012] In some embodiments, the semiconductor structure further includes a conductive layer. The conductive layer is located within the die and extends along a second direction perpendicular to the first direction. One end of the connection structure is connected to the conductive layer.

[0013] In some embodiments, at least one end of the first bonding portion is connected to the conductive layer and the connection structure.

[0014] In some embodiments, the die further includes a connector. The connector is located on the side of the conductive layer away from the connection structure. The first bonding portion is connected to the conductive layer via the connector.

[0015] In some embodiments, at least one end of the first bonding portion is directly connected to the connection structure.

[0016] In some embodiments, the semiconductor structure includes a connection unit that connects the plurality of dies along the first direction. The connection unit includes a plurality of connection structures located within the plurality of dies, and a first bonding portion located between any two adjacent dies. The plurality of connection structures and the plurality of first bonding portions included in the connection unit are connected in series along the first direction.

[0017] In some embodiments, the semiconductor structure further includes a second bonding portion. The second bonding portion is located within the bonding layer and is spaced apart from the first bonding portion. The second bonding portion is insulated from the bare die.

[0018] In some embodiments, the semiconductor structure includes a functional region and a connection region. In a cross-section of the semiconductor structure perpendicular to the first direction, the functional region and the connection region are adjacent to each other. The first bonding portion is located in the connection region, and the second bonding portion is located in the functional region.

[0019] In some embodiments, the material of the second bonding portion is the same as the material of the first bonding portion.

[0020] In some embodiments, the second bonding portion includes a third sub-portion and a fourth sub-portion arranged along the first direction. The third sub-portion and the fourth sub-portion are at least partially in contact.

[0021] In some embodiments, the die is one of ferroelectric random access memory, resistive random access memory, magnetic random access memory, phase change memory, and dynamic random access memory.

[0022] On the other hand, a semiconductor structure is provided. The semiconductor structure includes a stacked structure and at least one conductive pillar. The stacked structure includes a plurality of dies stacked together. The stacked structure includes a first surface and a second surface opposite each other in a first direction, the first direction being the thickness direction of the dies. The dies are one of ferroelectric random access memory (RAM), resistive random access memory (RAM), magnetic random access memory (RAM), phase-change memory (PCM), and dynamic random access memory (DRAM). The conductive pillar is located within the stacked structure and extends along the first direction. The conductive pillar includes a first end and a second end opposite each other in the first direction, the first end being located on the first surface, and the second end being located within the target die corresponding to the conductive pillar.

[0023] The semiconductor structure provided in the above embodiments of this disclosure forms a stacked structure by stacking multiple dies within the semiconductor structure. The semiconductor structure also includes at least one conductive pillar. The first end of the conductive pillar is located on the first surface of the stacked structure, and the second end of the conductive pillar is located within the target die corresponding to the conductive pillar. This allows the target die corresponding to the conductive pillar to transmit signals through the conductive pillar. Since the conductive pillar extends along a first direction (i.e., the thickness direction of the die), it is generally linear, resulting in a shorter length. This reduces the production cost of the conductive pillar, thereby reducing the production cost of the semiconductor structure and the chip packaging structure. It also shortens the signal transmission distance of the target die corresponding to the conductive pillar, reducing transmission delay and signal attenuation, thus improving the signal transmission quality and ultimately enhancing the performance of the semiconductor structure.

[0024] Because the conductive pillars within the semiconductor structure are located within the stacked structure, multiple dies within the semiconductor structure do not need to be stacked in a staggered manner to ensure that the bonding pads on the top surface of each die are exposed for further wire bonding (WB). This allows multiple dies within the semiconductor structure to be stacked vertically, which can reduce the size of the semiconductor structure, facilitate the miniaturization of the semiconductor structure, and improve the integration density of the semiconductor structure.

[0025] In another aspect, a chip packaging structure is provided. The chip packaging structure includes a base die and a semiconductor structure as described in any of the above embodiments. The semiconductor structure is stacked on one side of the base die.

[0026] In another aspect, a storage system is provided. The storage system includes a chip package structure and a controller as described in the above embodiments. The controller is connected to the chip package structure.

[0027] It is understood that the beneficial effects of the chip packaging structure and storage system provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0029] Figure 1 This is a structural diagram of an electronic device provided according to some embodiments;

[0030] Figure 2 This is a structural diagram of a storage system provided according to some embodiments;

[0031] Figure 3 This is a structural diagram of a chip packaging structure provided according to some embodiments;

[0032] Figure 4 This is a structural diagram of a memory cell array within a die according to some embodiments;

[0033] Figure 5A This is an equivalent circuit diagram of memory cells, word lines, and bit lines within a memory cell array according to some embodiments;

[0034] Figure 5B This is another equivalent circuit diagram of memory cells, word lines, and bit lines within a memory cell array provided according to some embodiments;

[0035] Figure 5C This is yet another equivalent circuit diagram of memory cells, word lines, and bit lines within a memory cell array provided according to some embodiments;

[0036] Figure 5D This is another equivalent circuit diagram of memory cells, word lines, and bit lines within a memory cell array provided according to some embodiments;

[0037] Figure 6 This is another structural diagram of the chip packaging structure provided according to some embodiments;

[0038] Figure 7A A structural diagram of a partial region of a semiconductor structure provided according to some embodiments;

[0039] Figure 7B This is another structural diagram of a partial region of a semiconductor structure provided according to some embodiments;

[0040] Figure 7C This is another structural diagram of a partial region of a semiconductor structure provided according to some embodiments;

[0041] Figure 8 A cross-sectional view of a first bonding portion within a semiconductor structure provided according to some embodiments;

[0042] Figure 9 This is yet another structural diagram of a chip packaging structure provided according to some embodiments;

[0043] Figure 10 This is another structural diagram of the chip packaging structure provided according to some embodiments;

[0044] Figure 11 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0045] Figure 12 for Figure 11 A structural diagram of a semiconductor structure corresponding to step S1 in the flowchart of the semiconductor structure fabrication method;

[0046] Figure 13 for Figure 11 A structural diagram of a semiconductor structure corresponding to step S2 in the flowchart of the semiconductor structure fabrication method;

[0047] Figure 14 for Figure 11 The flowchart of the semiconductor structure preparation method is shown in a diagram of a semiconductor structure corresponding to step S3. Detailed Implementation

[0048] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0049] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0050] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0052] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0053] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0054] In this disclosure, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned, or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0055] In this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0056] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] For ease of description below, an XYZ coordinate system is established. The first direction Z represents the thickness direction of the wafer, the XY plane is perpendicular to the first direction Z, and the second direction X intersects the third direction Y. For example, the second direction X and the third direction Y are perpendicular to each other.

[0058] It should be noted that, for example, G / WL in the accompanying drawings of this disclosure indicates that a component is both G and WL. For example, 11(1) indicates that component 11 belongs to component 1. Other similar reference numerals appearing in the drawings also follow the above description.

[0059] like Figure 1As shown, this application provides an electronic device 1000. The electronic device 1000 may include a mobile phone, a tablet computer, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, etc. This application does not impose any special limitations on the specific form of the aforementioned electronic device 1000.

[0060] In some embodiments, please continue reading Figure 1 The aforementioned electronic device 1000 may include a storage system 100 and a processor 200. The processor 200 is coupled to the storage system 100 to interact with the storage system 100.

[0061] For example, the processor 200 within the electronic device 1000 can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0062] The storage system 100 described above will be described in detail below.

[0063] like Figure 2 As shown, Figure 2 This is a structural diagram of a storage system 100 provided according to some embodiments. The storage system 100 may include a chip package structure 10 and a controller 20. The chip package structure 10 and the controller 20 are electrically connected, and the controller 20 can control the chip package structure 10 to store data.

[0064] For example, the storage system 100 described above can be integrated into a memory card. Memory cards include, for example, any of the following: PC card (Personal Computer Memory Card International Association, PCMCIA), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0065] The aforementioned storage system 100 can also be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0066] The aforementioned storage system 100 can also be integrated into a solid state drive (SSD).

[0067] For example, the controller 20 within the storage system 100 can be configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0068] The controller 20 within the storage system 100 can also be configured to operate in high duty cycle environments using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0069] For example, the controller 20 within the storage system 100 can be configured to manage data stored in the chip package structure 10 and communicate with external devices (e.g., a host).

[0070] The controller 20 within the storage system 100 can also be configured to control the operation of the chip package structure 10, such as read, erase, and program operations.

[0071] The controller 20 within the storage system 100 can also be configured to manage various functions related to data stored or to be stored in the chip package structure 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling.

[0072] The controller 20 within the storage system 100 can also be configured to process error correction codes for data read from or written to the chip package structure 10.

[0073] Of course, the controller 20 within the storage system 100 can also perform any other suitable functions. For example, the controller 20 within the storage system 100 can format the chip package structure 10; or, for example, the controller 20 within the storage system 100 can communicate with external devices (e.g., a host) through at least one of various interface protocols.

[0074] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0075] The chip packaging structure 10 described above will be explained in detail below.

[0076] In some embodiments, such as Figure 3 As shown, Figure 3 This is a structural diagram of a chip package structure 10 provided according to some embodiments. The chip package structure 10 includes a base die J and a semiconductor structure D. The semiconductor structure D may be stacked on one side of the base die J.

[0077] For example, the base die J within the chip package structure 10 can implement several logic functions. The base die J may include a circuit region. The circuit region may be a region including a wafer and circuits provided by elements formed on the wafer. Some circuits may constitute physical layer circuitry. When the physical layer circuitry is a transmitting circuit, it may be configured as a driver; when it is a receiving circuit, it may be configured as a buffer. The circuit region may be formed of silicon or the like.

[0078] The semiconductor structure D described above will be explained in detail below.

[0079] In some embodiments, please continue reading Figure 3 The semiconductor structure D includes multiple bare dies 1.

[0080] It should be noted that, Figure 3The illustrated embodiment only uses the example of a semiconductor structure D including 4 bare dies 1. However, the number of bare dies 1 in the semiconductor structure D is not limited to this. The number of bare dies 1 in the semiconductor structure D can be set according to actual needs. For example, the number of bare dies 1 in the semiconductor structure D can be 2, 3, 5, 6, 7 or 8, etc.

[0081] For example, please continue reading Figure 3 The die 1 within the semiconductor structure D can be a memory.

[0082] When the die 1 within the semiconductor structure D is a memory, the storage density of the single semiconductor structure D can be increased by placing multiple dies 1 within the single semiconductor structure D. The increased number of dies 1 relative to a single die 1 will correspondingly increase the storage capacity.

[0083] For example, if the die 1 in the semiconductor structure D is a memory, the die 1 in the semiconductor structure D can be one of the following: ferroelectric random access memory (FRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), phase change memory (PCM), dynamic random access memory (DRAM), and static random access memory (SRAM).

[0084] For example, such as Figure 4 As shown, Figure 4 This is a structural diagram of a memory cell array 11 within a die 1 according to some embodiments. When the die 1 within the semiconductor structure D is a memory, the die 1 within the semiconductor structure D may include a memory cell array 11.

[0085] Please continue reading. Figure 4 The memory cell array 11 within die 1 may include a plurality of memory cells MC arranged in an array. Each memory cell MC may include a capacitor C for storing data bits as positive or negative charges and one or more transfer transistors T1 for controlling (e.g., switching and selecting) access to it.

[0086] The capacitor C in the memory cell MC can be set to a charging state or a discharging state, using these two states to represent the two values ​​of the bit, which are usually referred to as zero and one.

[0087] The transfer transistor T1 in the memory cell MC can be a vertical transistor. For example, the transfer transistor T1 in the memory cell MC can be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET).

[0088] Using a vertical transistor as the transmission transistor T1 in the memory cell MC can reduce the area occupied by the transmission transistor T1, the coupling capacitance, and the complexity of the interconnect wiring.

[0089] The following uses a vertical transistor as an example to illustrate some embodiments of this disclosure. However, the type of the transmission transistor T1 in the memory cell MC is not limited to this. The transmission transistor T1 in the memory cell MC can also be other suitable transistor types.

[0090] Please continue reading. Figure 4 The transfer transistor T1 in the memory cell MC includes a semiconductor pillar TC extending along the first direction (i.e., the thickness direction of the die 1) Z.

[0091] The semiconductor pillar TC within the transmission transistor T1 can have any suitable 3D shape. For example, the semiconductor pillar TC within the transmission transistor T1 can have a polyhedral shape or a cylindrical shape.

[0092] Please continue reading. Figure 4 The transfer transistor T1 in the memory cell MC also includes a gate G. The gate G of the transfer transistor T1 is located on at least one side of the semiconductor pillar TC of the transfer transistor T1.

[0093] The gate G of the transmission transistor T1 is made of a conductive material. For example, the gate G of the transmission transistor T1 may be made of polysilicon, metal, metal compound, or silicide.

[0094] The gate G of the transmission transistor T1 may include multiple conductive layers. For example, the gate G of the transmission transistor T1 may include a titanium nitride (TiN) layer and a tungsten (W) layer stacked together.

[0095] Please continue reading. Figure 4 The memory cell array 11 within the die 1 may also include multiple word lines WL. The word lines WL in the memory cell array 11 may be coupled to the gate G of the transfer transistor T1 in the memory cell MC to control the transfer transistor T1 to turn on or off.

[0096] The gate G of the transfer transistor T1 in the memory cell MC and the word line WL in the memory cell array 11 can be a continuous conductive structure. That is, the gate G of the transfer transistor T1 can be regarded as part of forming the word line WL, or the word line WL can be regarded as an extension of the gate G of the transfer transistor T1.

[0097] Please continue reading. Figure 4 The memory cell array 11 within the die 1 may also include multiple bit lines BL. The bit lines BL within the memory cell array 11 may be coupled to the source or drain region of the semiconductor pillar TC within the transfer transistor T1 in the memory cell MC, for charging or discharging the capacitor C in the memory cell MC.

[0098] It should be noted that, Figure 4 In the illustrated embodiment, only the die 1 within the semiconductor structure D is used as a Dynamic Random Access Memory (DRAM), and the memory cell array 11 within the die 1 is illustrated as a DRAM cell array. However, the type of die 1 within the semiconductor structure D in this disclosure is not limited to this, nor is the type of memory cell array 11 within the die 1. The memory cell array 11 within the die 1 can include any suitable type of memory cell array using transistors as switching and selection devices. For example, the memory cell array 11 within the die 1 can include a ferroelectric random access memory (FRAM) cell array, a resistive random access memory (RRAM) cell array, a magnetic random access memory (MRAM) cell array, a phase change memory (PCM) cell array, or a static random access memory (SRAM) cell array, etc.

[0099] Specifically, such as Figure 5A , Figure 5B , Figure 5C and Figure 5D As shown, Figure 5A , Figure 5B , Figure 5C and Figure 5DAll of these are equivalent circuit diagrams of the memory cells MC, word lines WL, and bit lines BL within the memory cell array 11 provided according to some embodiments. In the case where the die 1 within the semiconductor structure D is a ferroelectric random access memory (FRAM), the memory cell array 11 within the die 1 may include a ferroelectric random access memory (FRAM) cell array.

[0100] In the case where the memory cell array 11 within the die 1 includes a ferroelectric random access memory (FRAM) cell array, the memory cell array 11 within the die 1 may include memory cells MC, word lines WL, and bit lines BL.

[0101] The memory cell MC within the memory cell array 11 may include at least one first transistor T2 and at least one ferroelectric capacitor C'.

[0102] For example, please continue reading Figure 5A In the case where the memory cell array 11 within the die 1 includes a ferroelectric random access memory (FRAM) cell array, the memory cell MC within the memory cell array 11 may include a first transistor T2 and a ferroelectric capacitor C'.

[0103] For example, please continue reading Figure 5B In the case where the memory cell array 11 in the die 1 includes a ferroelectric random access memory (FRAM) cell array, the memory cell MC in the memory cell array 11 may include a first transistor T2 and a plurality of ferroelectric capacitors C'.

[0104] For example, please continue reading Figure 5C In the case where the memory cell array 11 in the die 1 includes a ferroelectric random access memory (FRAM) cell array, the memory cell MC in the memory cell array 11 may include two first transistors T2 and multiple ferroelectric capacitors C'.

[0105] For example, please continue reading Figure 5DIn the case where the memory cell array 11 in the die 1 includes a ferroelectric random access memory (FRAM) cell array, the memory cell MC in the memory cell array 11 may include a plurality of first transistors T2 and a plurality of ferroelectric capacitors C'.

[0106] The writing and reading processes in a ferroelectric random access memory (FRAM) cell array primarily rely on the polarization state of the ferroelectric capacitor C' within the memory cell MC. When a voltage is applied to the word line WL, the first transistor T2 within the memory cell MC, connected to the word line WL, is turned on, allowing current to flow into or out of the ferroelectric capacitor C' within the memory cell MC through the bit line BL. This causes a change in the polarization state of the ferroelectric material within the ferroelectric capacitor C', thereby altering the data stored in the memory cell MC. During data reading, the polarization state of the ferroelectric capacitor C' within the memory cell MC is detected by measuring the current or voltage change on the bit line BL, thus determining the stored data.

[0107] In some embodiments, please continue reading Figure 3 In the case where the semiconductor structure D includes multiple dies 1, the multiple dies 1 within the semiconductor structure D can be staggered and stacked in a first direction (i.e., the thickness direction of the die 1) Z. That is, each die 1 in the semiconductor structure D is sequentially offset a certain distance in a certain direction (e.g., a second direction X), so that the orthographic projections of the multiple dies 1 in the semiconductor structure D onto a plane perpendicular to the first direction (i.e., the thickness direction of the die 1) Z do not completely overlap, ensuring that the bonding pads 91 disposed on the top surface of each die 1 are exposed for further wire bonding (WB). In other words, the dies 1 within the semiconductor structure D can be connected via bonding pads 91 and leads 92, facilitating signal transmission via the leads 92.

[0108] For example, please continue reading Figure 3 The die 1 in the semiconductor structure D can be connected to the base die J in the chip package structure 10 via lead 92, thereby realizing the electrical connection between the base die J in the chip package structure 10 and the die 1 in the semiconductor structure D, so as to facilitate signal transmission between the base die J in the chip package structure 10 and the die 1 in the semiconductor structure D.

[0109] Please continue reading. Figure 3When a die 1 within a semiconductor structure D transmits signals via a lead 92, the signal transmission quality of the die 1 within the semiconductor structure D is limited by the physical properties of the lead 92. For example, when the die 1 within the semiconductor structure D transmits signals, the transmission bandwidth and signal transmission speed are limited by the physical properties of the lead 92.

[0110] It is understandable that when the base die J within the chip package structure 10 and the die 1 within the semiconductor structure D are electrically connected by leads 92, the signal transmission between the base die J within the chip package structure 10 and the die 1 within the semiconductor structure D is limited by the physical properties of the leads 92. For example, the transmission bandwidth and signal transmission speed between the base die J within the chip package structure 10 and the die 1 within the semiconductor structure D are limited by the physical properties of the leads 92.

[0111] Therefore, when the die 1 in the semiconductor structure D transmits signals via the lead 92 (for example, the die 1 in the semiconductor structure D and the basic die J in the chip package structure 10 are electrically connected via the lead 92, and the die 1 in the semiconductor structure D and the basic die J in the chip package structure 10 transmit signals via the lead 92), in order to ensure the signal transmission quality of the die 1 in the semiconductor structure D during signal transmission (for example, the signal transmission quality between the die 1 in the semiconductor structure D and the basic die J in the chip package structure 10 during signal transmission), the material of the lead 92 usually needs to be a metal with good conductivity and good ductility (for example, gold (Au)).

[0112] Since the lead 92 is usually curved and long, and the material of the lead 92 includes metals with good conductivity and good plasticity (e.g., gold (Au)), the production cost of the lead 92 is high, which in turn leads to a higher production cost of the semiconductor structure D and the chip package structure 10.

[0113] Based on this, in some embodiments, such as Figure 6 As shown, Figure 6 This is a structural diagram of a chip package structure 10 provided according to some embodiments. In the case where the semiconductor structure D includes a plurality of dies 1, the plurality of dies 1 within the semiconductor structure D can be stacked.

[0114] It should be noted that, Figure 6 The illustrated embodiment only uses the example of a semiconductor structure D including 4 bare dies 1. However, the number of bare dies 1 in the semiconductor structure D is not limited to this. The number of bare dies 1 in the semiconductor structure D can be set according to actual needs. For example, the number of bare dies 1 in the semiconductor structure D can be 2, 3, 5, 6, 7 or 8, etc.

[0115] Please continue reading. Figure 6 The semiconductor structure D may further include a connection structure 5, a bonding layer 31, and a first bonding portion 61. The connection structure 5 within the semiconductor structure D may be located within the die 1 and extend along a first direction (i.e., the thickness direction of the die 1) Z. The bonding layer 31 within the semiconductor structure D may be located between two adjacent dies 1. The first bonding portion 61 within the semiconductor structure D may be located within the bonding layer 31 and penetrate the bonding layer 31. Along the first direction (i.e., the thickness direction of the die 1) Z, the connection structures 5 within two adjacent dies 1 are connected through the first bonding portion 61.

[0116] In the case where the semiconductor structure D includes multiple dies 1, by stacking the multiple dies 1 within the semiconductor structure D, and connecting structures 5 extending along the first direction (i.e., the thickness direction of the die 1) Z within adjacent dies 1, are connected by a first bonding portion 61 within a bonding layer 31 located between the two adjacent dies 1, allowing the dies 1 within the semiconductor structure D to transmit signals through the connecting structures 5. On one hand, since the connecting structures 5 extend along the first direction (i.e., the thickness direction of the die 1) Z, the connecting structures 5 are arranged in a straight line, resulting in a shorter length. This not only helps reduce the production cost of the connecting structures 5, but also helps reduce the production cost of the semiconductor structure D and the chip packaging structure 10. Furthermore, it shortens the signal transmission distance of the dies 1 within the semiconductor structure D when transmitting signals through the connecting structures 5, which helps reduce the transmission delay and signal attenuation of the dies 1 within the semiconductor structure D during signal transmission, thereby improving the signal transmission quality of the dies 1 within the semiconductor structure D and ultimately enhancing the performance of the semiconductor structure D.

[0117] On the other hand, since the connection structures 5 extending along the first direction (i.e., the thickness direction of the die 1) in two adjacent dies 1 within the semiconductor structure D are connected by the first bonding portion 61 in the bonding layer 31 located between the two adjacent dies 1, a direct short-distance (e.g., micrometer-level) electrical connection can be achieved between the connection structures 5 extending along the first direction (i.e., the thickness direction of the die 1) in the two adjacent dies 1, which is beneficial to reduce the power consumption of the semiconductor structure D and achieve high-speed I / O throughput.

[0118] On the other hand, since the connection structure 5 in the semiconductor structure D is located within the die 1, and the connection structure 5 extending along the first direction (i.e. the thickness direction of the die 1) Z in two adjacent dies 1 are connected by the first bonding portion 61 in the bonding layer 31 located between the two adjacent dies 1, the multiple dies 1 in the semiconductor structure D do not need to be stacked in a staggered manner to ensure that the bonding pads 91 provided on the top surface of each die 1 are exposed for further wire bonding (WB). This allows the multiple dies 1 in the semiconductor structure D to be stacked vertically, which can reduce the size of the semiconductor structure D, which is beneficial to the miniaturization of the semiconductor structure D and improves the integration of the semiconductor structure D.

[0119] For example, please continue reading Figure 6 The semiconductor structure D includes a connection unit L. The connection unit L within the semiconductor structure D may include a plurality of connection structures 5 located within a plurality of dies 1, and a first bonding portion 61 located between any two adjacent dies 1.

[0120] The multiple connection structures 5 and multiple first bonding portions 61 included in the connection unit L in the semiconductor structure D are connected in series in the first direction (i.e. the thickness direction of the bare die 1) Z, so that the connection unit L in the semiconductor structure D can connect multiple bare dies 1 along the first direction (i.e. the thickness direction of the bare die 1) Z.

[0121] By connecting multiple connection structures 5 and multiple first bonding portions 61 included in the connection unit L within the semiconductor structure D in series along the first direction (i.e., the thickness direction of the die 1) Z, the connection unit L within the semiconductor structure D extends along the first direction (i.e., the thickness direction of the die 1) Z. When multiple dies 1 connected by the connection unit L within the semiconductor structure D along the first direction (i.e., the thickness direction of the die 1) Z transmit signals through the connection unit L, the signal transmission distance of the multiple dies 1 connected by the connection unit L along the first direction (i.e., the thickness direction of the die 1) Z can be shortened. This helps to reduce the transmission delay of the multiple dies 1 connected by the connection unit L along the first direction (i.e., the thickness direction of the die 1) Z during signal transmission and reduces the signal attenuation of the multiple dies 1 connected by the connection unit L along the first direction (i.e., the thickness direction of the die 1) Z during signal transmission. This, in turn, helps to improve the signal transmission quality of the multiple dies 1 connected by the connection unit L along the first direction (i.e., the thickness direction of the die 1) Z during signal transmission, thereby improving the performance of the semiconductor structure D.

[0122] For example, please continue reading Figure 6Signal transmission can be achieved between the multiple bare dies 1 connected by the connection unit L in the semiconductor structure D along the first direction (i.e., the thickness direction of the bare die 1) Z and the basic bare die J in the chip package structure 10 through the connection unit L. By extending the connection unit L in the semiconductor structure D along the first direction (i.e., the thickness direction of the bare die 1) Z, when signal transmission is achieved between the multiple bare dies 1 connected by the connection unit L in the semiconductor structure D along the first direction (i.e., the thickness direction of the bare die 1) Z and the basic bare die J in the chip package structure 10 through the connection unit L, the length of the connection unit L connected along the first direction (i.e., the thickness direction of the bare die 1) Z and the basic bare die J in the chip package structure 10 can be shortened. The signal transmission distance between the wafers J is beneficial to reduce the transmission delay between the multiple wafers 1 connected by the connection unit L along the first direction (i.e., the thickness direction of the wafer 1) Z and the basic wafer J in the chip package structure 10 during signal transmission, and to reduce the signal attenuation between the multiple wafers 1 connected by the connection unit L along the first direction (i.e., the thickness direction of the wafer 1) Z and the basic wafer J in the chip package structure 10 during signal transmission. This is beneficial to improve the signal transmission quality between the multiple wafers 1 connected by the connection unit L along the first direction (i.e., the thickness direction of the wafer 1) Z and the basic wafer J in the chip package structure 10 during signal transmission, thereby improving the performance of the semiconductor structure D.

[0123] For example, please continue reading Figure 6 The interconnect structure 5 within the semiconductor structure D includes conductive material.

[0124] For example, please continue reading Figure 6 The material of the interconnect structure 5 within the semiconductor structure D may include one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and titanium nitride (TiN).

[0125] For example, please continue reading Figure 6 The first bonding portion 61 within the semiconductor structure D includes a conductive material.

[0126] For example, please continue reading Figure 6 The material of the first bonding portion 61 within the semiconductor structure D may include one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and titanium nitride (TiN).

[0127] For example, please continue reading Figure 6 The bonding layer 31 within the semiconductor structure D includes a dielectric material.

[0128] For example, please continue reading Figure 6The material of the bonding layer 31 within the semiconductor structure D may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectrics.

[0129] For example, please continue reading Figure 6 In the case where multiple dies 1 are stacked within a semiconductor structure D, and the dies 1 within the semiconductor structure D are Dynamic Random Access Memory (DRAM), the semiconductor structure D including the stacked dies 1 can be High Bandwidth Memory (HBM). High Bandwidth Memory (HBM) is a high-performance random access memory (RAM) that stacks multiple Dynamic Random Access Memory (DRAM). High Bandwidth Memory (HBM) is typically used in conjunction with high-performance graphics accelerators and network devices that access large datasets. High Bandwidth Memory (HBM) typically achieves higher bandwidth while using less power in smaller form factors.

[0130] In some embodiments, such as Figure 7A , Figure 7B and Figure 7C As shown, Figure 7A , Figure 7B and Figure 7C All of these are structural diagrams of a partial region of a semiconductor structure D provided according to some embodiments. In the case where multiple bare dies 1 are stacked in the semiconductor structure D, and the connection structure 5 extending along the first direction (i.e., the thickness direction of the bare die 1) Z in two adjacent bare dies 1 is connected by a first bonding portion 61 in the bonding layer 31 located between the two adjacent bare dies 1, the two adjacent bare dies 1 in the semiconductor structure D can be a first bare die 1m and a second bare die 1n, respectively.

[0131] The first bonding portion 61 within the semiconductor structure D may include a first sub-portion 611 and a second sub-portion 612 arranged along a first direction (i.e., the thickness direction of the die 1) Z. The first sub-portion 611 within the first bonding portion 61 is connected to the connection structure 5 in the first die 1m, and the second sub-portion 612 within the first bonding portion 61 is connected to the connection structure 5 in the second die 1n. The first sub-portion 611 and the second sub-portion 612 within the first bonding portion 61 are at least partially in contact.

[0132] By making the first sub-part 611 and the second sub-part 612 within the first bonding portion 61 at least partially in contact, the first sub-part 611 and the second sub-part 612 within the first bonding portion 61 can be interconnected to form the first bonding portion 61, which facilitates the connection structure 5 within two adjacent dies 1 (i.e., the first die 1m and the second die 1n) within the semiconductor structure D to be connected through the first bonding portion 61.

[0133] For example, such as Figure 8 As shown, and in combination Figure 7A , Figure 7B and Figure 7C , Figure 8 This is a cross-sectional view of a first bonding portion 61 within a semiconductor structure D according to some embodiments. In a cross-section of the semiconductor structure D parallel to the first direction (i.e., the thickness direction of the die 1) Z, both the first sub-portion 611 and the second sub-portion 612 within the first bonding portion 61 are trapezoidal.

[0134] The dimension h2 of the end of the first sub-part 611 within the first bonding portion 61 that is closer to the second sub-part 612 within the first bonding portion 61 along the second direction X is greater than the dimension h1 of the end of the first sub-part 611 within the first bonding portion 61 that is farther away from the second sub-part 612 within the first bonding portion 61 along the second direction X. The second direction X is perpendicular to the first direction (i.e., the thickness direction of the die 1) Z. In other words, the dimension h2 of the end of the first sub-part 611 within the first bonding portion 61 that is closer to the second sub-part 612 within the first bonding portion 61 along the second direction X is larger.

[0135] The dimension h3 of the second sub-part 612 within the first bonding portion 61, near the end of the first sub-part 611 within the first bonding portion 61, along the second direction (i.e., the direction perpendicular to the first direction Z), is greater than the dimension h4 of the second sub-part 612 within the first bonding portion 61, away from the end of the first sub-part 611 within the first bonding portion 61, along the second direction (i.e., the direction perpendicular to the first direction Z), in the second direction. In other words, the dimension h3 of the second sub-part 612 within the first bonding portion 61, near the end of the first sub-part 611 within the first bonding portion 61, along the second direction (i.e., the direction perpendicular to the first direction Z), is larger.

[0136] By making the dimension h2 of the end of the first sub-part 611 in the first bonding portion 61 near the end of the second sub-part 612 in the first bonding portion 61 along the second direction X, and the dimension h3 of the end of the second sub-part 612 in the first bonding portion 61 near the end of the first sub-part 611 in the first bonding portion 61 along the second direction X (i.e., the direction perpendicular to the first direction Z) both large, the connection area of ​​the end of the first sub-part 611 near the end of the second sub-part 612 in the first bonding portion 61, and the connection area of ​​the end of the second sub-part 612 near the end of the first bonding portion 61 are both large. The connection area at one end of the first sub-part 611 is relatively large. On the one hand, this can reduce the probability of disconnection between the first sub-part 611 and the second sub-part 612 in the first bonding part 61 due to connection misalignment during connection. This facilitates the connection between the first sub-part 611 and the second sub-part 612 in the first bonding part 61, and further facilitates the connection structure 5 in two adjacent dies 1 (i.e., the first die 1m and the second die 1n) in the semiconductor structure D through the first bonding part 61 and enables signal transmission.

[0137] On the other hand, it is beneficial to increase the contact area between the first sub-part 611 and the second sub-part 612 within the first bonding portion 61, thereby improving the connection reliability between the first sub-part 611 and the second sub-part 612 within the first bonding portion 61, and thus improving the stability of the first bonding portion 61.

[0138] For example, please continue reading Figure 8 The dimension h2 of the first sub-part 611 in the first bonding part 61 near the end of the second sub-part 612 in the first bonding part 61 along the second direction (i.e., the direction perpendicular to the first direction Z) X can be greater than the dimension h3 of the second sub-part 612 in the first bonding part 61 near the end of the first sub-part 611 in the first bonding part 61 along the second direction (i.e., the direction perpendicular to the first direction Z) X.

[0139] In some embodiments, please continue reading Figure 7A , Figure 7B and Figure 7C The semiconductor structure D also includes a conductive layer 7. The conductive layer 7 in the semiconductor structure D can be located within the die 1, and the conductive layer 7 in the semiconductor structure D can extend along the second direction (i.e., the direction perpendicular to the first direction Z) X.

[0140] When the semiconductor structure D includes a conductive layer 7, one end of the connection structure 5 within the semiconductor structure D can be connected to the conductive layer 7.

[0141] For example, please continue reading Figure 7A and Figure 7BWhen the semiconductor structure D includes a conductive layer 7, at least one end of the first bonding portion 61 in the semiconductor structure D can be connected to the connection structure 5 through the conductive layer 7.

[0142] Alternatively, please continue reading Figure 7A and Figure 7C At least one end of the first bonding portion 61 within the semiconductor structure D can be directly connected to the connection structure 5.

[0143] For example, please continue reading Figure 7A When the semiconductor structure D includes a conductive layer 7, one end of the first bonding portion 61 in the semiconductor structure D can be connected to the connection structure 5 through the conductive layer 7, and the other end of the first bonding portion 61 can be directly connected to the connection structure 5.

[0144] For example, please continue reading Figure 7B When the semiconductor structure D includes a conductive layer 7, both ends of the first bonding portion 61 in the semiconductor structure D can be connected to the connection structure 5 through the conductive layer 7.

[0145] For example, please continue reading Figure 7C Both ends of the first bonding portion 61 within the semiconductor structure D can be directly connected to the connecting structure 5.

[0146] For example, please continue reading Figure 7A , Figure 7B and Figure 7C The conductive layer 7 within the semiconductor structure D comprises a conductive material.

[0147] For example, please continue reading Figure 7A , Figure 7B and Figure 7C The material of the conductive layer 7 within the semiconductor structure D may include one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and titanium nitride (TiN).

[0148] In some embodiments, please continue reading Figure 7A and Figure 7B In the case where the semiconductor structure D includes a conductive layer 7, and at least one end of the first bonding portion 61 within the semiconductor structure D is connected to the connection structure 5 via the conductive layer 7, the semiconductor structure D may further include a connection portion 21. The connection portion 21 within the semiconductor structure D may be located on the side of the conductive layer 7 away from the connection structure 5.

[0149] The first bonding portion 61 within the semiconductor structure D can be connected to the conductive layer 7 via the connecting portion 21.

[0150] For example, please continue reading Figure 7A and Figure 7BThe connection portion 21 within the semiconductor structure D includes a conductive material.

[0151] For example, please continue reading Figure 7A and Figure 7B The material of the interconnect 21 within the semiconductor structure D may include one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and titanium nitride (TiN).

[0152] In some embodiments, please continue reading Figure 6 , Figure 7A , Figure 7B and Figure 7C In the case where the semiconductor structure D includes a first bonding portion 61 located within the bonding layer 31, the semiconductor structure D may further include a second bonding portion 62. The second bonding portion 62 within the semiconductor structure D may be located within the bonding layer 31 and spaced apart from the first bonding portion 61. The second bonding portion 62 within the semiconductor structure D is insulated from the die 1. That is, the second bonding portion 62 within the semiconductor structure D is not used to connect the connection structures 5 within two adjacent dies 1.

[0153] By including a second bonding portion 62 in the semiconductor structure D, and having the second bonding portion 62 located within the bonding layer 31, the bonding strength between two adjacent dies 1 within the semiconductor structure D can be improved when they are connected through the bonding layer 31, thereby improving the stability of the semiconductor structure D.

[0154] For example, please continue reading Figure 7A , Figure 7B and Figure 7C The second bonding portion 62 within the semiconductor structure D may include a third sub-portion 613 and a fourth sub-portion 614 arranged along the first direction (i.e., the thickness direction of the die 1) Z. The third sub-portion 613 and the fourth sub-portion 614 within the second bonding portion 62 are at least partially in contact.

[0155] For example, please continue reading Figure 6 , Figure 7A , Figure 7B and Figure 7C The second bonding portion 62 within the semiconductor structure D includes a conductive material.

[0156] For example, please continue reading Figure 6 , Figure 7A , Figure 7B and Figure 7C The material of the second bonding portion 62 within the semiconductor structure D may include one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and titanium nitride (TiN).

[0157] For example, please continue reading Figure 6 , Figure 7A , Figure 7B and Figure 7C The material of the second bonding portion 62 in the semiconductor structure D can be the same as the material of the first bonding portion 61 in the semiconductor structure D.

[0158] When the material of the second bonding portion 62 in the semiconductor structure D is the same as the material of the first bonding portion 61 in the semiconductor structure D, the second bonding portion 62 and the first bonding portion 61 in the semiconductor structure D can be formed in the same process, which is beneficial to simplify the fabrication process of the semiconductor structure D and improve the fabrication efficiency of the semiconductor structure D.

[0159] For details, please continue reading Figure 7A , Figure 7B and Figure 7C In the case where the first bonding portion 61 in the semiconductor structure D includes a first sub-portion 611 and a second sub-portion 612 arranged along the first direction (i.e., the thickness direction of the die 1) Z, and the second bonding portion 62 in the semiconductor structure D includes a third sub-portion 613 and a fourth sub-portion 614 arranged along the first direction (i.e., the thickness direction of the die 1) Z, the first sub-portion 611 in the first bonding portion 61 and the third sub-portion 613 in the second bonding portion 62 can be formed in the same process, and the shapes of the first sub-portion 611 in the first bonding portion 61 and the third sub-portion 613 in the second bonding portion 62 can be the same.

[0160] The second sub-part 612 in the first bonding portion 61 and the fourth sub-part 614 in the second bonding portion 62 can be formed in the same process, and the shapes of the second sub-part 612 in the first bonding portion 61 and the fourth sub-part 614 in the second bonding portion 62 can be the same.

[0161] In some embodiments, such as Figure 9 As shown, Figure 9 This is a structural diagram of a chip package structure 10 provided according to some embodiments. In the case where the semiconductor structure D includes a plurality of dies 1, the plurality of dies 1 within the semiconductor structure D can be stacked.

[0162] It should be noted that, Figure 9 The illustrated embodiment only uses the example of a semiconductor structure D including 4 bare dies 1. However, the number of bare dies 1 in the semiconductor structure D is not limited to this. The number of bare dies 1 in the semiconductor structure D can be set according to actual needs. For example, the number of bare dies 1 in the semiconductor structure D can be 2, 3, 5, 6, 7 or 8, etc.

[0163] Please continue reading. Figure 9The semiconductor structure D may further include a connection structure 5, a connection layer 32, and a first micro bump 63. The connection structure 5 within the semiconductor structure D may be located within the die 1 and extend along a first direction (i.e., the thickness direction of the die 1) Z. The connection layer 32 within the semiconductor structure D may be located between two adjacent dies 1. The first micro bump 63 within the semiconductor structure D may be located within the connection layer 32 and penetrate the connection layer 32. Along the first direction (i.e., the thickness direction of the die 1) Z, the connection structures 5 within two adjacent dies 1 are connected through the first micro bump 63.

[0164] In the case where the semiconductor structure D includes multiple dies 1, by stacking the multiple dies 1 within the semiconductor structure D, and connecting structures 5 extending along the first direction (i.e., the thickness direction of the die 1) Z within adjacent dies 1, are connected by a first micro bump 63 located within the connecting layer 32 between the two adjacent dies 1, allowing the dies 1 within the semiconductor structure D to transmit signals through the connecting structures 5. On one hand, since the connecting structures 5 extend along the first direction (i.e., the thickness direction of the die 1) Z, the connecting structures 5 are arranged in a straight line, resulting in a shorter length. This not only helps reduce the production cost of the connecting structures 5, but also helps reduce the production cost of the semiconductor structure D and the chip packaging structure 10. Furthermore, it shortens the signal transmission distance of the dies 1 within the semiconductor structure D when transmitting signals through the connecting structures 5, which helps reduce the transmission delay and signal attenuation of the dies 1 within the semiconductor structure D during signal transmission, thereby improving the signal transmission quality of the dies 1 within the semiconductor structure D and ultimately enhancing the performance of the semiconductor structure D.

[0165] On the other hand, since the connection structures 5 extending along the first direction (i.e., the thickness direction of the die 1) in two adjacent dies 1 within the semiconductor structure D are connected by the first micro bump 63 located in the connection layer 32 between the two adjacent dies 1, a direct short-distance (e.g., micrometer-level) electrical connection can be achieved between the connection structures 5 extending along the first direction (i.e., the thickness direction of the die 1) in the two adjacent dies 1, which is beneficial to reduce the power consumption of the semiconductor structure D and achieve high-speed I / O throughput.

[0166] On the other hand, since the connection structure 5 in the semiconductor structure D is located within the die 1, and the connection structures 5 extending along the first direction (i.e., the thickness direction of the die 1) Z in two adjacent dies 1 are connected by the first micro bump 63 located in the connection layer 32 between the two adjacent dies 1, the multiple dies 1 in the semiconductor structure D do not need to be stacked in a staggered manner to ensure that the bonding pads 91 provided on the top surface of each die 1 are exposed for further wire bonding (WB). This allows the multiple dies 1 in the semiconductor structure D to be stacked vertically, which can reduce the size of the semiconductor structure D, which is beneficial to the miniaturization of the semiconductor structure D and improves the integration of the semiconductor structure D.

[0167] For example, please continue reading Figure 9 The semiconductor structure D includes conductive units M. The conductive units M within the semiconductor structure D may include multiple connection structures 5 located within multiple dies 1, and a first micro bump 63 located between any two adjacent dies 1.

[0168] The conductive unit M in the semiconductor structure D includes multiple connection structures 5 and multiple first microbumps 63 connected in series in the first direction (i.e., the thickness direction of the die 1) Z, so that the conductive unit M in the semiconductor structure D can connect multiple dies 1 along the first direction (i.e., the thickness direction of the die 1) Z.

[0169] By connecting multiple connection structures 5 and multiple first micro bumps 63 included in the conductive unit M within the semiconductor structure D in series along the first direction (i.e., the thickness direction of the die 1) Z, the conductive unit M within the semiconductor structure D extends along the first direction (i.e., the thickness direction of the die 1) Z. When multiple dies 1 connected by the conductive unit M within the semiconductor structure D along the first direction (i.e., the thickness direction of the die 1) Z transmit signals through the conductive unit M, the signal transmission distance of the multiple dies 1 connected by the conductive unit M along the first direction (i.e., the thickness direction of the die 1) Z can be shortened. This helps to reduce the transmission delay of the multiple dies 1 connected by the conductive unit M along the first direction (i.e., the thickness direction of the die 1) Z during signal transmission and reduces the signal attenuation of the multiple dies 1 connected by the conductive unit M along the first direction (i.e., the thickness direction of the die 1) Z during signal transmission. This, in turn, helps to improve the signal transmission quality of the multiple dies 1 connected by the conductive unit M along the first direction (i.e., the thickness direction of the die 1) Z during signal transmission, thereby improving the performance of the semiconductor structure D.

[0170] For example, please continue reading Figure 9Signal transmission can be achieved between the multiple bare dies 1 connected to the conductive unit M in the semiconductor structure D along the first direction (i.e., the thickness direction of the bare die 1) Z and the basic bare die J in the chip package structure 10 through the conductive unit M. By extending the conductive unit M in the semiconductor structure D along the first direction (i.e., the thickness direction of the bare die 1) Z, when signal transmission occurs between the multiple bare dies 1 connected to the conductive unit M in the semiconductor structure D along the first direction (i.e., the thickness direction of the bare die 1) Z and the basic bare die J in the chip package structure 10 through the conductive unit M, the distance between the multiple bare dies 1 connected to the conductive unit M along the first direction (i.e., the thickness direction of the bare die 1) Z and the basic bare die J in the chip package structure 10 can be shortened. The signal transmission distance between the wafers J is beneficial to reducing the transmission delay between the multiple wafers 1 connected to the conductive unit M along the first direction (i.e., the thickness direction of the wafer 1) Z and the basic wafer J in the chip package structure 10 during signal transmission, and reducing the signal attenuation between the multiple wafers 1 connected to the conductive unit M along the first direction (i.e., the thickness direction of the wafer 1) Z and the basic wafer J in the chip package structure 10 during signal transmission. This is beneficial to improving the signal transmission quality between the multiple wafers 1 connected to the conductive unit M along the first direction (i.e., the thickness direction of the wafer 1) Z and the basic wafer J in the chip package structure 10 during signal transmission, thereby improving the performance of the semiconductor structure D.

[0171] For example, please continue reading Figure 9 The first microbump 63 within the semiconductor structure D comprises a conductive material.

[0172] For example, please continue reading Figure 9 The material of the first micro bump 63 within the semiconductor structure D may include one or more of copper (Cu), nickel (Ni), and gold (Au).

[0173] In some embodiments, please continue reading Figure 9 In the case where the semiconductor structure D includes a first microbump 63 located within the interconnect layer 32, the semiconductor structure D may also include a second microbump 64. The second microbump 64 within the semiconductor structure D may be located within the interconnect layer 32 and spaced apart from the first microbump 63. The second microbump 64 within the semiconductor structure D is insulated from the die 1. That is, the second microbump 64 within the semiconductor structure D is not used to connect the interconnect structures 5 within two adjacent dies 1.

[0174] By including a second microbump 64 in the semiconductor structure D, and having the second microbump 64 located within the interconnect layer 32, the bonding strength between two adjacent dies 1 within the semiconductor structure D can be improved when they are connected through the interconnect layer 32, thereby improving the stability of the semiconductor structure D.

[0175] For example, please continue reading Figure 9 The second microbump 64 within the semiconductor structure D comprises a conductive material.

[0176] For example, please continue reading Figure 9 The material of the second micro bump 64 within the semiconductor structure D may include one or more of copper (Cu), nickel (Ni), and gold (Au).

[0177] For example, please continue reading Figure 9 The material of the second microbump 64 in the semiconductor structure D can be the same as the material of the first microbump 63 in the semiconductor structure D.

[0178] When the material of the second microbump 64 in the semiconductor structure D is the same as that of the first microbump 63 in the semiconductor structure D, the second microbump 64 and the first microbump 63 in the semiconductor structure D can be formed in the same process, which helps to simplify the fabrication process of the semiconductor structure D and improve the fabrication efficiency of the semiconductor structure D.

[0179] In some embodiments, such as Figure 10 As shown, Figure 10 This is a structural diagram of a chip package structure 10 provided according to some embodiments. When the semiconductor structure D includes a plurality of dies 1, the plurality of dies 1 within the semiconductor structure D can be stacked to form a stacked structure 8. The stacked structure 8 within the semiconductor structure D may include a first surface 8a and a second surface 8b opposite each other in a first direction (i.e., the thickness direction of the dies 1) Z.

[0180] It should be noted that, Figure 10The embodiment shown is illustrated by taking the stacked structure 8 in the semiconductor structure D as an example, which includes 4 bare dies 1. However, the number of bare dies 1 in the stacked structure 8 in the semiconductor structure D is not limited to this. The number of bare dies 1 in the stacked structure 8 in the semiconductor structure D can be set according to actual needs. For example, the number of bare dies 1 in the semiconductor structure D can be 2, 3, 5, 6, 7 or 8, etc.

[0181] Please continue reading. Figure 10 The semiconductor structure D may further include at least one conductive post 81. The conductive post 81 in the semiconductor structure D is located within the stacked structure 8 and extends along a first direction (i.e., the thickness direction of the die 1) Z. The conductive post 81 in the semiconductor structure D may include a first end 81a and a second end 81b opposite each other in the first direction (i.e., the thickness direction of the die 1) Z. The first end 81a of the conductive post 81 may be located on the first surface 8a of the stacked structure 8, and the second end 81b of the conductive post 81 may be located within the target die 1F corresponding to the conductive post 81.

[0182] When the semiconductor structure D includes multiple bare dies 1, a stacked structure 8 is formed by stacking the multiple bare dies 1 in the semiconductor structure D. The semiconductor structure D also includes at least one conductive post 81. The first end 81a of the conductive post 81 is located on the first surface 8a of the stacked structure 8, and the second end 81b of the conductive post 81 is located in the target bare die 1F corresponding to the conductive post 81, so that the target bare die 1F corresponding to the conductive post 81 can transmit signals through the conductive post 81. On the one hand, since the conductive post 81 extends along the first direction (i.e., the thickness direction of the die 1) Z, the conductive post 81 is arranged in a straight line, which makes the length of the conductive post 81 smaller. This is beneficial to reducing the production cost of the conductive post 81, and thus the production cost of the semiconductor structure D and the chip packaging structure 10. It can also shorten the signal transmission distance of the target die 1F corresponding to the conductive post 81 when transmitting signals through the conductive post 81. This is beneficial to reduce the transmission delay of the target die 1F corresponding to the conductive post 81 when transmitting signals, and reduce the signal attenuation of the target die 1F corresponding to the conductive post 81 when transmitting signals. This is beneficial to improve the signal transmission quality of the target die 1F corresponding to the conductive post 81 when transmitting signals, thereby improving the performance of the semiconductor structure D.

[0183] On the other hand, since the conductive pillars 81 in the semiconductor structure D are located within the stacked structure 8, the multiple dies 1 in the semiconductor structure D do not need to be stacked in a staggered manner to ensure that the bonding pads 91 set on the top surface of each die 1 are exposed for further wire bonding (WB). This allows the multiple dies 1 in the semiconductor structure D to be stacked vertically, which can reduce the size of the semiconductor structure D, facilitate the miniaturization of the semiconductor structure D, and improve the integration of the semiconductor structure D.

[0184] For example, please continue reading Figure 10 The first end 81a of the conductive post 81 in the semiconductor structure D can be electrically connected to the base die J in the chip package structure 10. When the first end 81a of the conductive post 81 in the semiconductor structure D is electrically connected to the base die J in the chip package structure 10, signal transmission can be performed between the target die 1F corresponding to the conductive post 81 and the base die J in the chip package structure 10 through the conductive post 81. By extending the conductive pillars 81 within the semiconductor structure D along the first direction (i.e., the thickness direction of the die 1) Z, when signal transmission occurs between the target die 1F corresponding to the conductive pillar 81 and the base die J within the chip package structure 10, the signal transmission distance between them can be shortened. This helps reduce the transmission delay and signal attenuation during signal transmission, thereby improving the signal transmission quality and ultimately enhancing the performance of the semiconductor structure D.

[0185] For example, please continue reading Figure 10 The conductive pillars 81 within the semiconductor structure D comprise conductive material.

[0186] For example, please continue reading Figure 10 The material of the conductive pillars 81 in the semiconductor structure D may include one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and titanium nitride (TiN).

[0187] For example, please continue reading Figure 10In the case where the semiconductor structure D includes at least one conductive post 81, and the conductive post 81 in the semiconductor structure D includes a first end 81a and a second end 81b opposite each other in the first direction (i.e. the thickness direction of the die 1), the first end 81a of the conductive post 81 is located on the first surface 8a of the stacked structure 8, and the second end 81b of the conductive post 81 is located in the target die 1F corresponding to the conductive post 81, the connection between two adjacent dies 1 can be direct bonding.

[0188] Direct bonding refers to the process of directly contacting the surfaces of two adjacent bare wafers 1 within a semiconductor structure D after cleaning and planing, and then subjecting them to heat and pressure. This causes interdiffusion or the formation of chemical bonds between atoms or molecules on both sides of the interface between the two adjacent bare wafers 1, thereby achieving a strong connection. This bonding method relies on the microscopic mechanical forces (such as van der Waals forces) on the material surface and the possibility of chemical bonding.

[0189] In some embodiments, please continue reading Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 9 and Figure 10 The semiconductor structure D may include a functional region 1a and a connection region 1b. In a cross-section of the semiconductor structure D perpendicular to the first direction (i.e., the thickness direction of the die 1) Z, the functional region 1a and the connection region 1b of the semiconductor structure D are adjacent to each other.

[0190] Please continue reading. Figure 6 , Figure 7A , Figure 7B , Figure 7C , Figure 9 and Figure 10 and combined Figure 4 When the die 1 in the semiconductor structure D is a memory, the memory cell array 11 in the die 1 can be located in the functional area 1a of the semiconductor structure D.

[0191] Please continue reading. Figure 6 , Figure 7A , Figure 7B and Figure 7C In the case where the semiconductor structure D includes a first bonding portion 61 and a second bonding portion 62, the first bonding portion 61 in the semiconductor structure D may be located in the connection region 1b of the semiconductor structure D, and the second bonding portion 62 in the semiconductor structure D may be located in the functional region 1a of the semiconductor structure D.

[0192] Please continue reading. Figure 9In the case where the semiconductor structure D includes a first micro bump 63 and a second micro bump 64, the first micro bump 63 in the semiconductor structure D can be located in the connection region 1b of the semiconductor structure D, and the second micro bump 64 in the semiconductor structure D can be located in the functional region 1a of the semiconductor structure D.

[0193] Please continue reading. Figure 9 In the case where the semiconductor structure D includes conductive pillars 81, the conductive pillars 81 in the semiconductor structure D can be located in the connection region 1b of the semiconductor structure D.

[0194] The following is a preparation Figure 6 Taking the semiconductor structure D in the illustrated embodiment as an example, the preparation method of the semiconductor structure D will be described in detail.

[0195] In some embodiments, such as Figure 11 As shown, Figure 11 This is a flowchart illustrating a method for fabricating a semiconductor structure D according to some embodiments. It should be noted that... Figure 11 The method for fabricating the semiconductor structure D shown is not exclusive and can also be used in... Figure 11 Other steps are performed before, after, or between any step in the fabrication method of the semiconductor structure D shown.

[0196] The method for preparing semiconductor structure D includes steps S1 to S3.

[0197] S1: As Figure 12 As shown, Figure 12 for Figure 11 The flowchart of the method for fabricating semiconductor structure D shows a structural diagram of semiconductor structure D corresponding to step S1. Multiple bare wafers 1 are provided. Each bare wafer 1 has a connecting structure 5 extending along a first direction Z, where Z is the thickness direction of the bare wafer 1.

[0198] S2: As Figure 13 As shown, Figure 13 for Figure 11 The flowchart of the method for fabricating semiconductor structure D shows a structural diagram of semiconductor structure D corresponding to step S2. A bonding sublayer 31a is formed on one side of the bare die 1. A sub-part 61a is provided in the bonding sublayer 31a, and the sub-part 61a is electrically connected to the connection structure 5 in the bare die 1.

[0199] S3: As Figure 14 As shown, and in combination Figure 13 , Figure 14 for Figure 11The flowchart of the method for fabricating semiconductor structure D shows the structure of semiconductor structure D corresponding to step S3. The bonding sublayers 31a of two bare wafers 1 are joined together to form a bonding layer 31. Sub-parts 61a of the two bonding sublayers 31a are joined together to form a first bonding part 61.

[0200] In the case where the semiconductor structure D includes multiple dies 1, by stacking the multiple dies 1 within the semiconductor structure D, and connecting structures 5 extending along the first direction (i.e., the thickness direction of the die 1) Z within adjacent dies 1, are connected by a first bonding portion 61 within a bonding layer 31 located between the two adjacent dies 1, allowing the dies 1 within the semiconductor structure D to transmit signals through the connecting structures 5. On one hand, since the connecting structures 5 extend along the first direction (i.e., the thickness direction of the die 1) Z, the connecting structures 5 are arranged in a straight line, resulting in a shorter length. This not only helps reduce the production cost of the connecting structures 5, but also helps reduce the production cost of the semiconductor structure D and the chip packaging structure 10. Furthermore, it shortens the signal transmission distance of the dies 1 within the semiconductor structure D when transmitting signals through the connecting structures 5, which helps reduce the transmission delay and signal attenuation of the dies 1 within the semiconductor structure D during signal transmission, thereby improving the signal transmission quality of the dies 1 within the semiconductor structure D and ultimately enhancing the performance of the semiconductor structure D.

[0201] On the other hand, since the connection structures 5 extending along the first direction (i.e., the thickness direction of the die 1) in two adjacent dies 1 within the semiconductor structure D are connected by the first bonding portion 61 in the bonding layer 31 located between the two adjacent dies 1, a direct short-distance (e.g., micrometer-level) electrical connection can be achieved between the connection structures 5 extending along the first direction (i.e., the thickness direction of the die 1) in the two adjacent dies 1, which is beneficial to reduce the power consumption of the semiconductor structure D and achieve high-speed I / O throughput.

[0202] On the other hand, since the connection structure 5 in the semiconductor structure D is located within the die 1, and the connection structure 5 extending along the first direction (i.e. the thickness direction of the die 1) Z in two adjacent dies 1 are connected by the first bonding portion 61 in the bonding layer 31 located between the two adjacent dies 1, the multiple dies 1 in the semiconductor structure D do not need to be stacked in a staggered manner to ensure that the bonding pads 91 provided on the top surface of each die 1 are exposed for further wire bonding (WB). This allows the multiple dies 1 in the semiconductor structure D to be stacked vertically, which can reduce the size of the semiconductor structure D, which is beneficial to the miniaturization of the semiconductor structure D and improves the integration of the semiconductor structure D.

[0203] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple bare dies stacked together; A connecting structure is located within the bare die and extends along a first direction; The first direction is the thickness direction of the bare wafer; A bonding layer is located between two adjacent dies; A first bonding portion is located within the bonding layer and penetrates the bonding layer; along the first direction, the connection structures in two adjacent dies are connected through the first bonding portion.

2. The semiconductor structure according to claim 1, characterized in that, The two adjacent bare wafers are referred to as the first bare wafer and the second bare wafer, respectively; The first bonding portion includes a first sub-portion and a second sub-portion arranged along the first direction. The first sub-portion is connected to the connection structure in the first die, and the second sub-portion is connected to the connection structure in the second die. The first sub-part and the second sub-part are at least partially in contact.

3. The semiconductor structure according to claim 2, characterized in that, In a cross-section of the semiconductor structure parallel to the first direction, both the first sub-part and the second sub-part are trapezoidal. The dimension of the first sub-part near the second sub-part along the second direction is greater than the dimension of the first sub-part away from the second sub-part along the second direction; the second direction is perpendicular to the first direction; The dimension of the second sub-part along the second direction at the end closer to the first sub-part is greater than the dimension of the second sub-part along the second direction at the end farther from the first sub-part.

4. The semiconductor structure according to claim 2, characterized in that, The dimension of the first sub-part near the end of the second sub-part along the second direction is greater than the dimension of the second sub-part near the end of the first sub-part along the second direction; the second direction is perpendicular to the first direction.

5. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes a conductive layer located within the die; the conductive layer extends along a second direction, which is perpendicular to the first direction; One end of the connection structure is connected to the conductive layer.

6. The semiconductor structure according to claim 5, characterized in that, At least one end of the first bonding portion is connected to the conductive layer and the connection structure.

7. The semiconductor structure according to claim 6, characterized in that, The die also includes a connector located on the side of the conductive layer away from the connector structure; The first bonding portion is connected to the conductive layer through the connecting portion.

8. The semiconductor structure according to claim 5, characterized in that, At least one end of the first bonding portion is directly connected to the connection structure.

9. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a connection unit that connects the plurality of dies along the first direction; The connection unit includes a plurality of connection structures located within the plurality of dies, and a first bonding portion located between any two adjacent dies in the plurality of dies; the plurality of connection structures and the plurality of first bonding portions included in the connection unit are connected in series in the first direction.

10. The semiconductor structure according to any one of claims 1 to 9, characterized in that, The semiconductor structure further includes a second bonding portion located within the bonding layer and spaced apart from the first bonding portion; The second bonding portion is insulated from the bare die.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure includes a functional region and a connection region; in a cross-section of the semiconductor structure perpendicular to the first direction, the functional region and the connection region are adjacent to each other. The first bonding portion is located in the connection area, and the second bonding portion is located in the functional area.

12. The semiconductor structure according to claim 10, characterized in that, The material of the second bonding portion is the same as the material of the first bonding portion.

13. The semiconductor structure according to claim 10, characterized in that, The second bonding portion includes a third sub-portion and a fourth sub-portion arranged along the first direction; The third sub-part and the fourth sub-part are at least in contact.

14. The semiconductor structure according to any one of claims 1 to 9, characterized in that, The bare die is one of ferroelectric random access memory, resistive random access memory, magnetic random access memory, phase change memory, and dynamic random access memory.

15. A semiconductor structure, characterized in that, include: A stacked structure includes a plurality of bare dies stacked together; the stacked structure includes a first surface and a second surface opposite each other in a first direction, the first direction being the thickness direction of the bare dies; the bare dies are one of ferroelectric random access memory, resistive random access memory, magnetic random access memory, phase change memory, and dynamic random access memory. At least one conductive post is located within the stacked structure and extends along the first direction; the conductive post includes a first end and a second end opposite to each other in the first direction, the first end being located on the first surface and the second end being located within the target die corresponding to the conductive post.

16. A chip packaging structure, characterized in that, include: Basic nude film; The semiconductor structure as described in any one of claims 1 to 15 is stacked on one side of the base die.

17. A storage system, characterized in that, include: The chip packaging structure as described in claim 16; The controller is connected to the chip package structure.

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