Composite passivation TSS diode with special structure and preparation method thereof

Abstract

The invention discloses a composite passivation TSS diode with a special structure and a preparation method thereof, and belongs to the technical field of semiconductor electronic components, the composite passivation TSS diode comprises an N-type substrate, two sides of the N-type substrate are symmetrically provided with an N + heavily doped region and a P + heavily doped region, and a P-lightly doped region is arranged between the P + heavily doped region and the N-type substrate; a groove structure is formed in the surface of the diode, and a Sipos deposition layer, a photoresist passivation protection layer and an LTO deposition layer are sequentially arranged in the groove structure from inside to outside to form a composite passivation system. The composite passivation TSS diode with the special structure has a bidirectional symmetrical switching characteristic, absorbs transient surge voltage in the positive direction and the negative direction at the same time, and meets the overvoltage protection requirement of an alternating current / bidirectional signal circuit. According to the invention, through the collaborative design of the symmetrical doping structure and the composite passivation system, the bidirectional symmetrical surge absorption capability is realized, and the large current resistance and environmental adaptability of the device are improved at the same time.

Description

Technical Field

[0001] This invention relates to a special structure composite passivated TSS diode and its preparation method, belonging to the field of semiconductor electronic components technology. Background Technology

[0002] Transient Suppression Schottky (TSS) diodes are core components for overvoltage protection and circuit regulation in power electronics, widely used in surge protection scenarios for AC / bidirectional signal lines. With the rapid development of new energy storage, automotive electronics, 5G base stations, and other fields, higher requirements are being placed on the high current withstand capability, high temperature resistance, and insulation stability of TSS diodes.

[0003] Existing TSS devices suffer from the following technical bottlenecks: Structural design limitations: Traditional TSS devices mostly adopt conventional layered or simple trench structures, which have poor adaptability to interlayer current carrying paths and are prone to uneven current distribution and limited current carrying capacity; some devices only have unidirectional surge absorption capability and cannot meet the overvoltage protection requirements of bidirectional signal lines.

[0004] Insufficient passivation process: GPP (Glass Passivated) chips prepared by traditional blade scraping process are prone to damage to the glass passivation layer during packaging. When operating under high current conditions, the damaged area is prone to breakdown, leading to diode failure. Therefore, the chip size is generally no more than 84mil and the forward current is no more than 3A. Moreover, blade scraping process chips can only work stably at 125℃. As the working time increases, the high-temperature leakage will gradually increase, posing a safety hazard.

[0005] Lack of composite passivation system: Although some existing technologies use a composite structure of SIPOS (Semi-Insulating Polycrystalline Silicon) and glass passivation, they have not been optimized for the electric field distribution characteristics of bidirectional symmetric devices, making it difficult to balance high current resistance, high temperature resistance and insulation stability.

[0006] For example, patent application publication number CN111370301A discloses a manufacturing process for ultra-high power photoresist glass chips. This process involves removing residual metal ions from trench corrosion using HCl cleaning, and employing a composite passivation system of SIPOS + glass passivation + LTO to fabricate ultra-high power chips with dimensions of 100-135 mils and a forward current reaching 15A. However, this technology still has the following shortcomings: The design does not involve the structural design of bidirectional symmetrical TSS diodes, which cannot meet the overvoltage protection requirements of AC / bidirectional signal lines; The surge absorption capability and stability of the device still have room for improvement because the design did not optimize the electric field distribution of the PN junction. The method for forming the P-lightly doped region is not clearly defined in the fabrication process, which limits the means of controlling the electrical performance of the device. Summary of the Invention

[0007] The purpose of this invention is to propose a special structure composite passivated TSS diode and its preparation method. Through the synergistic design of symmetrical doping structure and composite passivation system, bidirectional symmetrical surge absorption capability is achieved, while improving the device's high current withstand performance and environmental adaptability.

[0008] The present invention discloses a special structure composite passivated TSS diode, comprising: The N-type substrate has N+ heavily doped regions and P+ heavily doped regions symmetrically arranged on both sides, with a P- lightly doped region between the P+ heavily doped region and the N-type substrate. A trench structure is formed on the surface of the special structure composite passivated TSS diode. Within the trench structure, from the inside out, a Sipos deposition layer, a photoresist passivation protection layer, and an LTO deposition layer are sequentially arranged to form a composite passivation system. This special structure composite passivated TSS diode exhibits bidirectional symmetrical switching characteristics and absorbs transient surge voltages in both positive and negative directions, making it suitable for overvoltage protection of AC / bidirectional signal lines.

[0009] Preferably, the P-lightly doped region is formed by a light boron diffusion process.

[0010] Preferably, the thickness of the Sipos deposit is 6500~8000 Å, and it is formed by depositing silane and nitrous oxide at a pressure ratio of 1:3 for 40~80 min.

[0011] Preferably, the thickness of the photoresist passivation protective layer is 40~60μm, which is formed by mixing glass powder and photoresist, followed by homogenization, exposure, development, and sintering at 800~820℃.

[0012] Preferably, the thickness of the LTO deposition layer is 2500~5000 Å, and it is formed by deposition for 40~60 min using a low-temperature oxidation process.

[0013] The method for manufacturing the special structure composite passivated TSS diode of the present invention includes the following steps: S1: Secondary oxidation: Growing an oxide masking layer on the silicon wafer surface; S2: Concentrated boron diffusion: High-concentration boron diffusion is performed on the silicon wafer surface to form a P+ heavily doped region; S3: Light boron diffusion: Low-concentration boron secondary diffusion is performed on the basis of the P+ heavily doped region to form the P- lightly doped region. The concentration gradient and distribution of boron doping are finely adjusted to optimize the semiconductor electrical performance parameters of the corresponding region. S4: Photolithography of N+ doped regions and phosphorus diffusion: forming heavily doped N+ regions; S5: Photolithography of the trench area and etching to form the trench; S6: Sequentially deposit a Sipos deposition layer, prepare a photoresist passivation protective layer, and deposit an LTO deposition layer in the trench; S7: Surface metallization: Metal is deposited on the device mesa and then vacuum alloyed. S8: Testing and dicing: After electrical performance testing, the wafer is diced into individual device dies.

[0014] Preferably, in step S2, the P+ region on the left half is defined by photolithography, and a B30 boron source at 2200 RPM is used for double-sided coating. The P+ region is formed by diffusion at 1000~1100℃ for 60 min, and oxidation is performed at 1270℃ to advance the junction depth of the P+ region.

[0015] Preferably, in step S3, the light boron diffusion process involves photolithography to define the entire area, double-sided coating with a B30 boron source at 2200 RPM, diffusion at 1100°C for 60 min, and oxidation at 1250°C to optimize the PN junction structure.

[0016] Preferably, in step S4, phosphorus diffusion, the N-region is formed by diffusion in an environment of 1000~1160℃ for 60 minutes.

[0017] Preferably, in step S6, the area where trenches need to be formed is precisely defined by photoresist coating, alignment exposure, and development operations, clarifying the location and range of the trenches, and providing a precise processing benchmark for subsequent etching.

[0018] Preferably, in step S7, surface metallization, after depositing a silver metal layer, a vacuum alloying process is performed at 500°C for 30 minutes to form a low-resistance ohmic contact between the metal and silicon; in step S8, testing and dicing, the wafer undergoes 100% electrical performance testing, and qualified wafers are diced into independent device dies.

[0019] Compared with existing technologies, the special structure composite passivated TSS diode and its preparation method of the present invention exhibit the following beneficial effects in terms of technical performance and practical applications: 1. Bidirectional symmetrical surge absorption capability This invention achieves bidirectional symmetrical switching characteristics through a symmetrical structure design of N+ heavily doped regions, P+ heavily doped regions, and an N-type substrate. It can simultaneously absorb transient surge voltages in both positive and negative directions, meeting the overvoltage protection requirements of AC / bidirectional signal lines. Compared to traditional unidirectional TSS devices, this invention eliminates the need for additional reverse protection devices, simplifying circuit design and reducing system costs.

[0020] 2. Composite passivation system enhances environmental adaptability This invention employs a three-layer composite passivation system consisting of a Sipos deposition layer, a photoresist passivation protection layer, and an LTO deposition layer, achieving comprehensive protection of the device's terminal region. The Sipos deposition layer possesses high resistance and excellent interface state passivation capabilities, homogenizing the surface electric field and suppressing localized breakdown. The photoresist passivation protection layer, formed by the sintering of glass powder and photoresist, creates a dense glass passivation layer that effectively blocks environmental moisture and ion contamination. The LTO deposition layer provides excellent step coverage and stress buffering, offering a planarized surface and electrical isolation for subsequent metallization. This composite passivation system results in extremely low batch-to-batch dispersion of the device's breakdown voltage, maintaining stability under harsh environments such as high temperature and high humidity, with precise and reliable threshold voltage.

[0021] 3. Optimization of electrical properties by P-lightly doped regions This invention sets a lightly doped P- region between the heavily P+ doped region and the N-type substrate, and finely adjusts the concentration gradient and distribution of boron doping through a light boron diffusion process, thereby optimizing the semiconductor electrical performance parameters of the PN junction region. The lightly doped P-region makes the depletion region easier to expand, enabling it to withstand higher voltages at lower electric field strengths and significantly improving the reverse blocking capability of the device. The P-region ensures that the electric field is evenly distributed over a wider range, avoiding local electric field concentration, preventing premature breakdown, and enhancing the stability and reliability of the device. Light doping reduces junction capacitance, decreases displacement current during switching, improves current withstand capability of the device, and helps to shorten turn-off time and increase switching speed.

[0022] 4. The preparation process ensures performance stability and large-scale production. The fabrication process of this invention ensures the stability of device performance and its adaptability to large-scale production through the following measures: The oxide masking layer formed by the secondary oxidation process effectively prevents boron impurities from penetrating into the N+ region, ensuring the clarity of the boundary of the doped region. The stepwise process of concentrated boron diffusion and dilute boron diffusion enables precise control of the P-type doped region and optimizes the electrical performance of the device. Precise control of photolithography and etching processes ensures the dimensional accuracy and positional precision of the trench structure, providing a solid foundation for the fabrication of composite passivation systems. The surface metallization process, through vacuum evaporation and alloy treatment, forms low-resistance ohmic contacts, ensuring the effective transmission of electrical signals in the device.

[0023] Compared with existing technologies, the special structure composite passivated TSS diode of the present invention has the characteristics of strong bidirectional symmetrical surge absorption capability, good environmental adaptability, and excellent electrical performance. It is suitable for overvoltage protection scenarios under complex working conditions such as new energy storage, automotive electronics, and 5G base stations, and has significant technical advantages and broad application prospects. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the device structure after the composite passivation layer of the present invention has been prepared; Figure 2 This is a schematic diagram of the structure after concentrated boron diffusion according to the present invention; Figure 3 This is a schematic diagram of the structure after diffusing boron according to the present invention; Figure 4 This is a schematic diagram of the structure after phosphorus diffusion according to the present invention; Figure 5 This is a schematic diagram of the overall structure of the present invention without passivation; Figure 6 This is a flowchart illustrating the fabrication method of the special structure composite passivated TSS diode of the present invention; In the figure: 1. N+ heavily doped region; 2. P+ heavily doped region; 3. P- lightly doped region; 4. Sipos deposition layer; 5. N-type substrate; 6. Photoresist passivation protection layer; 7. LTO deposition layer. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0026] Example 1: like Figure 1 As shown, the present invention discloses a special structure composite passivated TSS diode, comprising: an N-type substrate 5, wherein N+ heavily doped regions 1 and P+ heavily doped regions 2 are symmetrically disposed on both sides of the N-type substrate 5, and a P- lightly doped region 3 is disposed between the P+ heavily doped regions 2 and the N-type substrate 5; a trench structure is formed on the surface of the diode, wherein a Sipos deposition layer 4, a photoresist passivation protection layer 6, and an LTO deposition layer 7 are sequentially disposed from the inside to the outside of the trench structure to form a composite passivation system; the special structure composite passivated TSS diode has bidirectional symmetrical switching characteristics and absorbs transient surge voltages in both positive and negative directions, adapting to overvoltage protection of AC / bidirectional signal lines.

[0027] The P-lightly doped region 3 is formed by a light boron diffusion process.

[0028] The Sipos deposition layer 4 has a thickness of 6500~8000 Å and is formed by depositing silane and nitrous oxide at a pressure ratio of 1:3 for 40~80 minutes.

[0029] The photoresist passivation protective layer 6 has a thickness of 40~60μm and is formed by mixing glass powder and photoresist, followed by homogenization, exposure, development, and sintering at 800~820℃.

[0030] The thickness of LTO deposition layer 7 is 2500~5000 Å, and it is formed by low-temperature oxidation process for 40~60 min.

[0031] The addition of a p-lightly doped region 3 to different structures serves the following purpose: Increased blocking voltage: The P-lightly doped region 3 makes it easier for the depletion region to expand, enabling it to withstand higher voltages at lower electric field strengths, thereby significantly improving the reverse blocking capability of the device.

[0032] In some implementation cases, the reverse blocking capability of the device is as follows: Table 1 Reverse blocking capability of the devices

[0033] Optimized electric field distribution: The P-lightly doped region 3 makes the electric field uniformly distributed over a wider range, avoiding local electric field concentration, preventing premature breakdown, and enhancing the stability and reliability of the device.

[0034] Improved dynamic characteristics: Light doping reduces junction capacitance, decreases displacement current during switching, improves the current withstand capability of the device, and helps to shorten turn-off time and increase switching speed.

[0035] In some implementations, the junction capacitance is 45~70pF; In some implementation cases, the surge withstand capability of the device is as follows: Table 2 Surge withstand capability of devices

[0036] Example 2: like Figure 6 As shown, the manufacturing method of the special structure composite passivated TSS diode of the present invention includes the following steps: (1) Secondary oxidation: Secondary oxidation is a critical masking step. It involves two photolithography processes on the silicon wafer surface where N+ regions need to be formed, followed by two high-temperature (1160℃) wet oxidation cycles of 9 hours and 4.5 hours to grow a thick silicon dioxide layer. This oxide layer serves as a masking layer for subsequent concentrated boron diffusion, effectively preventing boron impurities from penetrating into the N+ region. Before oxidation, the wafer must be thoroughly cleaned to eliminate the impact of surface contaminants on the oxide layer quality. The masking effect of this step directly determines the clarity of the doped region boundaries, which is fundamental to ensuring device isolation and performance controllability.

[0037] (2) Concentrated boron diffusion: Concentrated boron diffusion is a core process for achieving heavily doped P-type regions. Wafers alternating with boron paper are placed in a high-temperature diffusion furnace (1000~1100℃), allowing boron atoms to diffuse deep into the silicon lattice driven by a high concentration gradient. This process forms a high-concentration acceptor impurity region. The diffusion depth and surface concentration are precisely controlled by temperature, time, and gas flow rate. The P+ regions formed by concentrated boron diffusion are used in devices requiring low contact resistance or high electric field tolerance. Figure 2 The diagram shown is a structural diagram of the present invention after concentrated boron diffusion. In some implementation cases, the diffusion conditions for boron diffusion were 1050℃. 60 minutes.

[0038] In some implementation cases, the diffusion conditions for boron diffusion were 1100℃. 60 minutes.

[0039] In some implementation cases, the diffusion conditions for boron diffusion were 1000℃. 60 minutes.

[0040] In some implementation cases, the diffusion conditions for boron diffusion were 1000℃. 70 minutes.

[0041] In some implementation cases, the diffusion conditions for boron diffusion were 1100℃. 70 minutes.

[0042] (3) Dilute boron diffusion: Dilute boron diffusion is a fine-tuning of doping based on concentrated boron diffusion. It involves shortening the diffusion time and lowering the diffusion temperature to perform mild compensatory doping on the surface of the affected region, aiming to adjust the impurity concentration distribution gradient. This step optimizes junction depth and surface concentration, improves electric field distribution, and reduces peak electric field intensity, thereby enhancing device breakdown voltage and stability.

[0043] (4) Photolithography (N+ doped region): This photolithography step is used to define the N+ doped region pattern. First, a positive photoresist is uniformly spin-coated onto the wafer surface. After pre-baking, it is exposed to ultraviolet light through a mask. The pattern on the mask blocks the light, causing a photochemical reaction in the photoresist in the target area. After development, the photoresist in the exposed area is dissolved, and after chemical etching, the underlying silicon layer is exposed, forming a precise window pattern. This window is the subsequent phosphorus diffusion region. Figure 3 The diagram shown is a structural diagram of the dilute boron after diffusion according to the present invention.

[0044] (5) Phosphorus diffusion: Phosphorus diffusion is a crucial step in forming heavily doped N-type regions. In a high-temperature diffusion furnace (1050~1160℃), phosphorus paper is used. P₂O₅ in the phosphorus paper displaces phosphorus atoms from silicon and then diffuses into the silicon through a photolithographic window, forming a high-concentration donor impurity region. After phosphorus diffusion, a push-in annealing process is required to activate the impurities and repair lattice damage. The formed N⁺ region and the P-type substrate constitute a PN junction, which is the core structure for the device's switching function. After diffusion, the phosphorus-silicon glass layer formed on the surface needs to be removed, and the device needs to be cleaned. The overall structure after phosphorus diffusion, before passivation, is shown below. Figures 4-5 As shown; In some implementation cases, the diffusion conditions for phosphorus diffusion were 1050℃. 60 minutes.

[0045] In some implementation cases, the diffusion conditions for phosphorus diffusion were 1100℃. 60 minutes.

[0046] In some implementation cases, the diffusion conditions for phosphorus diffusion were 1150℃. 60 minutes.

[0047] In some implementation cases, the diffusion conditions for phosphorus diffusion were 1160℃. 60 minutes.

[0048] (6) Photolithography (groove area): This photolithography step defines the trench etching area. Photoresist is coated onto the wafer surface, exposed through a high-precision mask, and developed to form windows for the trench pattern. Since the trench structure directly affects the device's breakdown voltage and electric field distribution, photolithography must ensure precise pattern dimensions, steep edges, and strict alignment with the underlying pattern. After exposure, a hardening process is performed to enhance the photoresist's resistance to etching.

[0049] (7) Sipos deposition: Sipos (semi-insulating polycrystalline silicon) deposition is a process of forming an amorphous silicon-oxygen alloy film on the surface of trenches through chemical vapor deposition. Silane (SiH4) and nitrous oxide (N2O) are used as reactant gases, and deposition is carried out at a medium temperature of 675°C. By adjusting the gas ratio, the oxygen content in the film can be controlled, thereby adjusting the film resistivity. Sipos films exhibit high resistivity and good interface passivation capabilities, homogenizing the surface electric field and suppressing localized breakdown. The deposited film must be dense, non-porous, and of uniform thickness to ensure its reliability in high-voltage devices.

[0050] In some implementations, SIPOS has a film thickness of 6500 Å.

[0051] In some implementation cases, SIPOS has a film thickness of 7000 Å.

[0052] In some implementations, SIPOS has a film thickness of 7400 Å.

[0053] In some implementations, SIPOS has a film thickness of 8000 Å.

[0054] (8) Photoresist passivation: Photoresist passivation is a process of patterning a composite material consisting of glass powder and photoresist. The mixture is spin-coated onto the trench area, exposed and developed to form a predetermined pattern, and then sintered at high temperature (820°C) to melt and solidify the glass powder, forming a dense glass passivation layer. This layer effectively fills the trenches, covers the device edges, provides excellent mechanical protection and chemical stability, and inhibits external moisture and ion contamination. Photoresist passivation combines the patterning precision of photolithography with the passivation advantages of glass, making it particularly suitable for the terminal protection of high-voltage devices and significantly improving long-term reliability.

[0055] In some implementation cases, the film thickness of the photoresist glass is 40~44μm.

[0056] In some implementation cases, the film thickness of the photoresist glass is 45~46μm.

[0057] In some implementation cases, the film thickness of the photoresist glass is 47~49μm.

[0058] In some implementation cases, the film thickness of the photoresist glass is 50~52μm.

[0059] (9) LTO deposition: LTO (Low-Temperature Silicon Oxide) deposition is a process that grows a thin film of silicon dioxide at 420°C using low-pressure chemical vapor deposition (LPCVD), with silane and oxygen or nitrous oxide as the reactant gases, to form an amorphous SiO2 film. The low-temperature process avoids the damage to the existing doping distribution caused by high temperatures. LTO films have a relatively loose texture, good step coverage, and stress buffering properties, and are commonly used as interlayer dielectrics, passivation layers, or insulating metal layers. Post-deposition annealing can improve film density. This step provides a planarized surface and electrical isolation for subsequent metallization.

[0060] In some implementation cases, the film thickness of LTO is 2500~2700 Å.

[0061] In some implementation cases, the film thickness of LTO is 3200~3500 Å.

[0062] In some implementation cases, the film thickness of LTO is 3700~4200 Å.

[0063] In some implementation cases, the film thickness of LTO is 4500~5000 Å.

[0064] (10) Surface metallization: Surface metallization involves depositing a silver metal layer on the mesa area of ​​the device via vacuum evaporation to form electrode contacts. After evaporation, a trench pattern is etched, and the metal deposited in the trenches is removed. The wafer then undergoes an alloying process (500℃ / 30min) in a vacuum or inert atmosphere, causing a eutectic reaction between the metal and silicon to form low-resistance ohmic contacts. The alloying temperature and time must be precisely controlled to avoid over-penetration. The key to this step is reducing contact resistance and ensuring strong adhesion. The metal layer pattern is typically defined through photolithography and etching, ultimately forming the pad area, providing a bonding interface for device packaging and ensuring effective current collection and dissipation.

[0065] (11) Testing and Slicing: After 100% electrical performance testing of the wafers, qualified wafers are selected and then divided into individual device dies through a dicing process for subsequent packaging.

[0066] The fabrication process in this embodiment ensures the stability of device performance and its suitability for large-scale production through the following measures: The oxide masking layer formed by the secondary oxidation process effectively prevents boron impurities from penetrating into the N+ region, ensuring the clarity of the boundary of the doped region. The stepwise process of concentrated boron diffusion and dilute boron diffusion enables precise control of the P-type doped region and optimizes the electrical performance of the device. Precise control of photolithography and etching processes ensures the dimensional accuracy and positional precision of the trench structure, providing a solid foundation for the fabrication of composite passivation systems. The surface metallization process, through vacuum evaporation and alloy treatment, forms low-resistance ohmic contacts, ensuring the effective transmission of electrical signals in the device.

[0067] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A special structure composite passivated TSS diode, characterized in that, include: The N-type substrate (5) has N+ heavily doped regions (1) and P+ heavily doped regions (2) symmetrically arranged on both sides. A P- lightly doped region (3) is arranged between the P+ heavily doped region (2) and the N-type substrate (5). A trench structure is formed on the surface of the special structure composite passivated TSS diode. A Sipos deposition layer (4), a photoresist passivation protection layer (6) and an LTO deposition layer (7) are arranged sequentially from the inside to the outside of the trench structure to form a composite passivation system. The special structure composite passivated TSS diode has bidirectional symmetrical switching characteristics and absorbs transient surge voltages in both positive and negative directions, which is suitable for overvoltage protection of AC / bidirectional signal lines.

2. The special structure composite passivated TSS diode according to claim 1, characterized in that: The P-lightly doped region (3) is formed by a light boron diffusion process.

3. The special structure composite passivated TSS diode according to claim 1, characterized in that: The Sipos deposition layer (4) has a thickness of 6500~8000 Å and is formed by depositing silane and nitrous oxide at a pressure ratio of 1:3 for 40~80 min.

4. The special structure composite passivated TSS diode according to claim 1, characterized in that: The photoresist passivation protective layer (6) has a thickness of 40~60μm and is formed by mixing glass powder and photoresist, followed by homogenization, exposure, development, and sintering at 800~820℃.

5. A special structure composite passivated TSS diode according to claim 1, characterized in that: The thickness of the LTO deposition layer (7) is 2500~5000Å, and it is formed by low-temperature oxidation process for 40~60 minutes.

6. A method for manufacturing a special structure composite passivated TSS diode according to any one of claims 1-5, characterized in that, Includes the following steps: S1: Secondary oxidation: Growing an oxide masking layer on the silicon wafer surface; S2: Concentrated boron diffusion: High-concentration boron diffusion is performed on the surface of the silicon wafer to form a P+ heavily doped region (2); S3: Light boron diffusion: Based on the P+ heavily doped region (2), a low-concentration boron secondary diffusion is carried out to form a P- lightly doped region (3), and the concentration gradient and distribution of boron doping are finely adjusted to optimize the semiconductor electrical performance parameters of the corresponding region. S4: Photolithography of N+ doped region and phosphorus diffusion: forming N+ heavily doped region (1); S5: Photolithography of the trench area and etching to form the trench; S6: Sequentially deposit a Sipos deposition layer (4), prepare a photoresist passivation protective layer (6), and deposit an LTO deposition layer (7) in the trench. S7: Surface metallization: Metal is deposited on the device mesa and then vacuum alloyed. S8: Testing and dicing: After electrical performance testing, the wafer is diced into individual device dies.

7. The method for manufacturing a special structure composite passivated TSS diode according to claim 6, characterized in that: In step S2, the concentrated boron diffusion process, photolithography defines the P+ region in the left half, and a B30 boron source at 2200 RPM is used for double-sided coating. The P+ region is formed by diffusion at 1000~1100℃ for 60 minutes, and oxidation is performed at 1270℃ to advance the junction depth of the P+ region.

8. The method for manufacturing a special structure composite passivated TSS diode according to claim 6, characterized in that: In step S3, the light boron diffusion, the entire area is defined by photolithography, a B30 boron source at 2200 RPM is used for double-sided coating, diffusion is performed at 1100℃ for 60 min, and oxidation is performed at 1250℃ to optimize the PN junction structure; in step S4, the phosphorus diffusion is performed at 1000~1160℃ for 60 min to form the N region.

9. The method for manufacturing a special structure composite passivated TSS diode according to claim 6, characterized in that: In step S6, the area where trenches need to be formed is precisely defined through photoresist coating, alignment exposure, and development operations, clarifying the location and range of the trenches and providing a precise processing benchmark for subsequent etching.

10. The method for manufacturing a special structure composite passivated TSS diode according to claim 6, characterized in that: In step S7, surface metallization, after depositing a silver metal layer, vacuum alloying is performed at 500°C for 30 minutes to form a low-resistance ohmic contact between the metal and silicon. In step S8, testing and dicing, 100% electrical performance testing is performed on the wafer, and qualified wafers are diced into independent device dies.

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