Preparation method of semiconductor structure and semiconductor structure

Abstract

The invention relates to the technical field of semiconductors, and discloses a preparation method of a semiconductor structure and the semiconductor structure, and the method comprises the steps: sequentially forming an initial base region layer and an initial emitter structure on a substrate layer; the initial emitter structure comprises a body part located at the middle position and an edge part located at the side part; the body part protrudes out of the edge part; a first protective layer covers the side part, protruding out of the edge part, of the body part; removing the edge part and a part of the body part, forming an inner groove in the side part of the body part which is not covered by the first protection layer, and forming an emitter structure by the residual initial emitter structure; forming a second protection layer on the outer side of the first protection layer and in the inner groove; a base region is formed in the initial base region layer. According to the invention, the number of photoetching times and the number of photomasks for forming the emitter structure can be reduced, the preparation process flow of the emitter structure is simplified, the process complexity is reduced, and the process cost is further reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Currently, the emitter formation process for heterojunction bipolar transistors (HBTs) requires first depositing a first polysilicon layer and then photolithographically lithographically lithographically as a sacrificial layer. Next, a protective layer is formed, followed by a second photolithography process to create the emitter window. Finally, a second polysilicon layer is deposited within the emitter window, and a third photolithography process is performed to form the emitter polysilicon. Therefore, the emitter polysilicon formation process requires two polysilicon deposition processes and three photolithography processes, necessitating three photomasks, resulting in high costs and a high degree of process complexity.

[0003] Therefore, a solution is needed to minimize the number of photolithography steps and photomasks in the emitter fabrication process, thereby reducing fabrication costs. Summary of the Invention

[0004] This invention provides a method for fabricating a semiconductor structure and the semiconductor structure itself, in order to solve the problem that the formation process of the emitter of HBT devices requires two polysilicon deposition processes and three photolithography processes, necessitating three photomasks, resulting in high costs and a high degree of process complexity.

[0005] In a first aspect, the present invention provides a method for preparing a semiconductor structure, the method comprising: An initial base region layer and an initial emitter structure are sequentially formed on the base layer; the initial emitter structure includes a body portion located in the middle and an edge portion on the side; the body portion protrudes from the edge portion; the side portion of the body portion protruding from the edge portion is covered with a first protective layer; Remove the edge portion and part of the body portion, form an inner groove on the side of the body portion not covered by the first protective layer, and form an emitter structure with the remaining initial emitter structure; A second protective layer is formed on the outside of the first protective layer and inside the inner groove; a base region is formed in the initial base region layer.

[0006] The semiconductor structure fabrication method provided by this invention requires only one photolithography step to form the initial emitter structure. This is achieved by forming an inner trench on the side of the body portion not covered by the first protective layer, and filling the outer side of the first protective layer and the interior of the inner trench to form a second protective layer. Compared to a three-step photolithography process for emitter structures, this invention reduces the number of photolithography steps and the number of photomasks, simplifies the emitter structure fabrication process, reduces process complexity, and consequently lowers process costs.

[0007] In one optional embodiment, an initial base region layer and an initial emitter structure are sequentially formed on the substrate layer, including: A substrate layer is provided, on which an initial base region layer, a polysilicon layer and an initial barrier layer are sequentially formed; The first photomask is used to perform photolithography on the barrier layer and the polysilicon layer, removing the initial barrier layer and a portion of the polysilicon layer corresponding to the edge; the remaining polysilicon layer forms the initial emitter structure; the remaining initial barrier layer forms the barrier layer; the barrier layer covers the body of the initial emitter structure. A first protective layer is formed on the side of the body portion of the initial emitter structure that protrudes from the edge portion.

[0008] The semiconductor structure fabrication method provided by this invention, on the one hand, improves photolithography resolution and pattern accuracy by setting an initial barrier layer as a buffer layer on the surface of the polysilicon layer and forming photoresist on the corresponding initial barrier layer in the body, while protecting the polysilicon layer and the subsequently formed emitter structure from damage, thereby improving device performance. On the other hand, it only requires one polysilicon layer deposition and one photolithography step, eliminating the need for sacrificial polysilicon and emitter windows in related technologies, reducing the number of photomasks and photolithography steps, simplifying the emitter structure fabrication process, reducing process complexity, and thus reducing process costs.

[0009] In one alternative embodiment, a first protective layer is formed on the side of the body portion of the initial emitter structure that protrudes from the edge portion, comprising: A first initial protective layer is formed over the entire surface of the initial emitter structure; the first initial protective layer covers the body portion, the edge portion, and the side portion of the body portion that protrudes from the edge portion; Remove the first initial protective layer above the body and the edge, and retain the first initial protective layer on the side to form a first protective layer.

[0010] The semiconductor structure fabrication method provided by this invention first forms a first initial protective layer on the entire surface, and then uses a dry etching process to remove the first initial protective layer above the body and the edge. This eliminates the need for a photomask, simplifies the process flow, and reduces process costs. At the same time, by forming the first protective layer, the emitter structure can be protected from the influence of subsequent processes, preventing dopant atoms from entering the emitter structure when ion implantation doping is performed on the initial base layer.

[0011] In one alternative embodiment, a second protective layer is formed outside the first protective layer and inside the inner groove, comprising: A second initial protective layer is formed above the initial base region layer, the barrier layer, and outside the first protective layer; the second initial protective layer also fills the inner groove. The second initial protective layer is removed above the barrier layer and above the initial base region layer, and the second initial protective layer outside the first protective layer is retained to form the second protective layer.

[0012] The semiconductor structure fabrication method provided by this invention first forms a second initial protective layer over the entire surface, and then uses a dry etching process to remove the second initial protective layer above the barrier layer and above the initial base region layer. This eliminates the need for a photomask, simplifies the process flow, and reduces process costs. At the same time, by forming the second protective layer, the base region can be made unaffected by the emitter structure.

[0013] In one alternative embodiment, the edge portion and part of the body portion are removed, and an inner groove is formed on the side of the body portion not covered by the first protective layer. The remaining initial emitter structure forms an emitter structure, including: The edge of the initial emitter structure is etched using a wet etching process, and a portion of the body is etched away to the side to form an inner groove. The remaining initial emitter structure forms the emitter structure. The emitter structure includes a first portion covered by a first protective layer and a second portion exposed by an inner groove; the width of the second portion is smaller than the width of the first portion.

[0014] The semiconductor structure fabrication method provided by this invention simultaneously removes the edge portion and forms an inner trench through anisotropic wet etching, thereby forming the second part of the emitter structure. This eliminates the need for a photomask, simplifying the process and reducing costs. Furthermore, the width of the second part of the formed emitter structure is smaller than that of the first part, reducing the contact area between the emitter structure and the base region, thus lowering the parasitic capacitance of the device.

[0015] In one alternative embodiment, the ratio of the lateral depth of the inner groove to the thickness of the edge portion is 1:0.8 to 1:1.2; the thickness of the edge portion is 100 Å to 200 Å; and the lateral depth of the inner groove is 80 Å to 240 Å.

[0016] In one alternative embodiment, a shallow trench isolation structure is formed within the substrate layer; two shallow trench isolation structures separate the substrate layer into an active region; The initial emitter structure is located above the active region; the width of the initial emitter structure is smaller than the width of the active region.

[0017] In one alternative implementation, forming a base region in the initial base region layer includes: Ion implantation doping was performed on the initial base layer on the side of the emitter structure. The initial base region layer is photolithographically lithographically formed using a second photomask, retaining a portion of the width of the initial base region layer to form the base region; the width of the base region is greater than the width of the active region; the base region covers the active region and a portion of the shallow trench isolation structure on both sides of the active region.

[0018] In one alternative implementation, the material of the initial emitter structure includes polycrystalline silicon; The material of the first protective layer includes silicon nitride; The material of the second protective layer includes silicon dioxide; The initial base layer is made of germanium-silicon.

[0019] The present invention provides a semiconductor structure prepared by the semiconductor structure preparation method of the first aspect described above. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a specific process for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure forming the initial barrier layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the formation of the first photoresist layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the formation of an initial emitter structure in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the formation of a first initial protective layer in the fabrication of a semiconductor structure according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure forming the first protective layer in a method for preparing a semiconductor structure according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the formation of an inner trench and an emitter structure in a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the formation of a second initial protective layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the formation of a second protective layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the initial base region being ion-doped and implanted during a semiconductor structure fabrication method according to an embodiment of the present invention. Figure 12 This is a schematic diagram of the formation of a second photoresist layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 13 This is a schematic diagram of the formation of the base region in a semiconductor structure fabrication method according to an embodiment of the present invention.

[0022] Figure label: 10. Substrate layer; 110. Initial base region layer; 11. Base region; 120. Initial emitter structure; 101. Body portion; 102. Edge portion; 121. Polysilicon layer; 12. Emitter structure; 21. First part; 22. Second part; 130. Initial barrier layer; 13. Barrier layer; 140. First initial protective layer; 14. First protective layer; 150. Second initial protective layer; 15. Second protective layer; 91. First photoresist layer; 92. Second photoresist layer; 100. Shallow trench isolation structure; 200. Active region. Detailed Implementation

[0023] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the invention and not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0024] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0025] In related technologies, the process for forming the emitter of a SiGe HBT device includes: (1) depositing a first polysilicon layer; (2) performing a first photolithography on the first polysilicon layer to form sacrificial polysilicon; (3) forming a protective layer on the sacrificial polysilicon; (4) performing a second photolithography to remove the upper protective layer, leaving only the side protective layer to form an emitter window; (5) depositing a second polysilicon layer, which fills the emitter window and is surrounded by the protective layer; (6) performing a first photolithography on the second polysilicon layer to form emitter polysilicon; the width of the lower half of the emitter polysilicon is smaller than the width of the upper half.

[0026] The fabrication process of the emitter in this HBT device requires first depositing a first polysilicon layer and then photolithographically lithographically lithographically as a sacrificial layer. After forming a protective layer, a second photolithography process is used to form the emitter window. Finally, a second polysilicon layer is deposited within the emitter window, and a third photolithography process is performed to form the emitter polysilicon. Therefore, the fabrication process of the emitter polysilicon requires two polysilicon deposition processes and three photolithography processes, necessitating three photomasks, resulting in high costs and a high level of process complexity. Furthermore, the subsequent fabrication process of the base region in the SiGe HBT device requires sequential photolithography and another photomask, resulting in a total of four photomasks needed for the entire SiGe HBT device fabrication process, further complicating the process and increasing costs.

[0027] Therefore, a solution is needed to minimize the number of photolithography steps and photomasks in the emitter fabrication process, thereby reducing fabrication costs.

[0028] like Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor structure, which includes, but is not limited to, steps S101 to S103.

[0029] Step S101, as follows Figures 3-7 As shown, an initial base region layer 110 and an initial emitter structure 120 are sequentially formed on the base layer 10. The initial emitter structure 120 includes a body portion 101 located in the middle and an edge portion 102 on the side. The height of the body portion 101 is greater than that of the edge portion 102. The body portion 101 protrudes from the edge portion 102. The side of the body portion 101 protruding from the edge portion 102 is covered with a first protective layer 14.

[0030] Step S102, as follows Figure 8 As shown, the edge portion 102 and part of the body portion 101 are removed, and an inner groove is formed on the side of the body portion 101 that is not covered by the first protective layer 14. The remaining initial emitter structure 120 forms the emitter structure 12.

[0031] Step S103, as follows Figures 9-10 As shown, a second protective layer 15 is formed on the outer side of the first protective layer 14 and inside the inner groove; as Figures 11-13 As shown, a base region 11 is formed in the initial base region layer 110.

[0032] In practice, the side portion of the main body 101 protruding from the edge portion 102 is covered by a first protective layer 14. During the removal of the edge portion 102, the side portion of the main body 101 not covered by the first protective layer 14 is exposed. Therefore, the exposed side portion of the main body 101 is removed simultaneously, ultimately forming an inner groove at the location of the removed portion of the main body 101. The inner groove is relatively recessed into the remaining main body 101.

[0033] In step S101, an initial emitter structure 120 is formed using a first photomask; in step S102, the emitter structure 12 can be formed without using a photomask; in step S103, a base region 11 is formed using a second photomask. Compared with the related technologies that use three photomasks to form the emitter structure 12, this application only requires one photomask to form the emitter structure 12, which simplifies the fabrication process of the emitter structure 12 and reduces the process cost.

[0034] The semiconductor structure fabrication method provided in this embodiment requires only one photolithography step to form the initial emitter structure. An inner trench is formed on the side of the body portion not covered by the first protective layer, and a second protective layer is formed by filling the outer side of the first protective layer and the interior of the inner trench, thereby forming the emitter structure. Compared to a three-step photolithography process for emitter structures, this embodiment reduces the number of photolithography steps and the number of photomasks required to form the emitter structure, simplifies the fabrication process, reduces process complexity, and consequently lowers process costs.

[0035] In some alternative implementations, the semiconductor structure is an HBT device structure. The emitter structure 12 is made of polysilicon and is a polysilicon emitter (EMP); the base region 11 is made of germanium-silicon.

[0036] In some alternative embodiments, an initial base region layer 110 and an initial emitter structure 120 are sequentially formed on the base layer 10, as detailed below.

[0037] like Figure 3 As shown, a substrate layer 10 is provided, on which an initial base region layer 110, a polysilicon layer 121, and an initial barrier layer 130 are sequentially formed; the initial base region layer 110 is made of germanium-silicon; the polysilicon layer 121 is made of polysilicon; and the initial barrier layer 130 is made of silicon nitride. Figure 4 and Figure 5As shown, a first photomask is used to perform photolithography on the initial blocking layer 130 and the polysilicon layer 121, removing the initial blocking layer 130 and a portion of the polysilicon layer 121 corresponding to the edge portion 102; the remaining polysilicon layer 121 forms the initial emitter structure 120; the remaining initial blocking layer 130 forms the blocking layer 13; the blocking layer 13 covers the body portion 101 of the initial emitter structure 120. Figure 7 As shown, a first protective layer 14 is formed on the side of the body portion 101 of the initial emitter structure 120 that protrudes from the edge portion 102.

[0038] In practice, due to the presence of a natural oxide layer (SiO2) on the surface of polysilicon, the photoresist (PR) cannot adhere tightly to the oxide layer during subsequent formation. Direct application of the photoresist can easily lead to problems such as peeling or edge shrinkage, affecting lithographic resolution and pattern accuracy. Furthermore, the resin and photosensitizer components in the photoresist may chemically react with impurities on the surface of the polysilicon layer 121, generating compounds that are difficult to remove, causing surface contamination and affecting device performance. Therefore, by setting an initial barrier layer 130 as a buffer layer on the surface of the polysilicon layer 121, and forming the photoresist above the initial barrier layer 130 corresponding to the body portion 101, lithographic resolution and pattern accuracy can be improved, while protecting the polysilicon layer 121 and the subsequently formed emitter structure 12 from damage, thereby improving device performance.

[0039] The semiconductor structure fabrication method provided in this embodiment, on the one hand, improves photolithographic resolution and pattern accuracy by setting an initial barrier layer as a buffer layer on the surface of the polysilicon layer and forming photoresist on the corresponding initial barrier layer of the body, while protecting the polysilicon layer and the subsequently formed emitter structure from damage, thereby improving device performance. On the other hand, it only requires one polysilicon layer deposition and one photolithography step, eliminating the need for sacrificial polysilicon and emitter windows in related technologies, reducing the number of photomasks and photolithography steps, simplifying the emitter structure fabrication process, reducing process complexity, and thus reducing process costs.

[0040] In some alternative embodiments, a first protective layer 14 is formed on the side of the body portion 101 of the initial emitter structure 120 that protrudes from the edge portion 102, including: Figure 6 As shown, a first initial protective layer 140 is formed over the entire surface of the initial emitter structure 120; the first initial protective layer 140 covers the body portion 101, the edge portion 102, and the side portion of the body portion 101 that protrudes from the edge portion 102; as shown Figure 7 As shown, the first initial protective layer 140 above the body portion 101 and above the edge portion 102 is removed, and the first initial protective layer 140 on the side portion is retained to form the first protective layer 14.

[0041] In practice, the first initial protective layer 140 above the body portion 101 and the edge portion 102 is removed directly using a dry etching process, without the need for a photomask or photolithography. The dry etching process used to form the first protective layer 140 is anisotropic etching. The dry etching direction is predominantly vertically downwards, as the vertical bombardment and etching capabilities are far stronger than the horizontal direction. During the etching process, the first initial protective layer 140 above the body portion 101 and the edge portion 102 is completely removed. However, the first initial protective layer 140 on the side of the device structure (i.e., the side of the body portion 101 protruding from the edge portion 102) is completely preserved due to obstruction and weak horizontal etching effect. These remaining vertical film layers on the sidewalls constitute the second protective layer 15. The entire process requires no additional mask or photomask, relying on the directionality of the etching to achieve self-alignment.

[0042] The semiconductor structure fabrication method provided in this embodiment first forms a first initial protective layer on the entire surface, and then uses a dry etching process to remove the first initial protective layer above the body and the edge. This eliminates the need for a photomask, simplifies the process flow, and reduces process costs. At the same time, by forming the first protective layer, the emitter structure can be protected from the influence of subsequent processes, preventing dopant atoms from entering the emitter structure when ion implantation doping is performed on the initial base layer.

[0043] In some alternative embodiments, a second protective layer 15 is formed on the outer side of the first protective layer 14 and inside the inner groove, including: Figure 9 As shown, a second initial protective layer 150 is formed above the initial base layer 110, the barrier layer 13, and outside the first protective layer 14; the second initial protective layer 150 also fills the inner groove; as Figure 10 As shown, the second initial protective layer 150 above the barrier layer 13 and above the initial base layer 110 is removed, and the second initial protective layer 150 outside the first protective layer 14 is retained to form the second protective layer 15.

[0044] In practice, the first initial protective layer 140 above the barrier layer 13 and the initial base layer 110 is directly etched using a dry etching process, without the need for a photomask or photolithography. The second protective layer 15 is formed using anisotropic dry etching. The dry etching direction is predominantly vertically downwards, as the vertical bombardment and etching capabilities are far stronger than the horizontal direction. During the etching process, the second initial protective layer 150 above the barrier layer 13 and the initial base layer 110 is completely removed. However, the second initial protective layer 150 outside the first protective layer 14 is completely preserved due to the obstruction and the weak horizontal etching effect; these remaining vertical sidewall layers constitute the second protective layer 15. The entire process requires no additional mask or photomask, relying on the directionality of the etching to achieve self-alignment. The second protective layer 15 is an oxide layer (OX); the material of the second protective layer 15 is silicon dioxide.

[0045] The semiconductor structure fabrication method provided in this embodiment first forms a second initial protective layer over the entire surface, and then uses a dry etching process to remove the second initial protective layer above the barrier layer and above the initial base layer. This eliminates the need for a photomask, simplifies the process flow, and reduces process costs. At the same time, by forming the second protective layer, the base region can be made unaffected by the emitter structure.

[0046] In some alternative implementations, the thickness of the second protective layer 15 is greater than or equal to 1400 Å.

[0047] Since ion implantation causes lateral thermal diffusion into the base region, the thickness of the second protective layer 15 is greater than or equal to 1400 Å. This ensures that doped atoms will not diffuse into the base region during subsequent ion doping processes, thereby protecting the emitter and base region from the effects of ion implantation.

[0048] In some alternative implementations, such as Figure 8 As shown, the edge portion 102 and part of the body portion 101 are removed, and an inner groove is formed on the side of the body portion 101 not covered by the first protective layer 14. The remaining initial emitter structure 120 forms the emitter structure 12. This includes: using a wet etching process to remove part of the width of the body portion 101 from the side to form an inner groove, and the remaining initial emitter structure 120 forms the emitter structure 12. The emitter structure 12 includes a first portion 21 covered by the first protective layer 14 and a second portion 22 exposed by the inner groove. The width of the second portion 22 is smaller than the width of the first portion 21.

[0049] In related technologies, the width of the lower half of the emitter polysilicon layer is controlled by the width of the sacrificial polysilicon layer formed after the first etching. This application forms the inner trench using wet etching, thereby forming the second part 22 of the emitter structure 12, without the need for a photomask. The wet etching is anisotropic etching, where the etching solution reacts with the initial emitter structure 120 in both the vertical and horizontal directions. After the vertical edge portion 102 is completely removed, the etching solution simultaneously forms the inner trench within the body portion 101 on the side.

[0050] The semiconductor structure fabrication method provided in this embodiment simultaneously removes the edge portion and forms an inner trench through anisotropic wet etching, thereby forming the second part of the emitter structure. This eliminates the need for a photomask, simplifying the process flow and reducing costs. Furthermore, the width of the second part of the formed emitter structure is smaller than the width of the first part, reducing the contact area between the emitter structure and the base region, thus lowering the parasitic capacitance of the device.

[0051] In some alternative embodiments, the ratio of the lateral depth of the inner groove to the thickness of the edge portion 102 is 1:0.8 to 1:1.2; the thickness of the edge portion 102 is 100 Å to 200 Å; and the lateral depth of the inner groove is 80 Å to 240 Å.

[0052] In some alternative implementations, the thickness of the edge portion 102 of the initial emitter structure 120 is 100 Å, and the depth of the inner groove recessed to the side after the wet etching process also reaches 100 Å.

[0053] In some alternative implementations, such as Figure 3 As shown, a shallow trench isolation structure 100 is formed in the substrate 10; two shallow trench isolation structures 100 separate the substrate 10 into an active region 200; an emitter structure 12 is located above the active region 200; the width of the emitter structure 12 is smaller than the width of the active region 200.

[0054] In some alternative implementations, a base region 11 is formed in the initial base region layer 110, as detailed below.

[0055] like Figure 11 As shown, the initial base layer 110 on the side of the emitter structure 12 is ion-implanted and doped, wherein, Figure 11 The arrows in the diagram indicate the location and direction of ion implantation doping.

[0056] like Figure 12 and Figure 13 As shown, the initial base layer 110 is photolithographically ...

[0057] In related technologies, the entire SiGe HBT device fabrication process requires four photomasks (three for the emitter and one for the base region). This application, however, requires only two photomasks (one for the emitter structure and one for the base region), effectively reducing fabrication costs and process complexity. Furthermore, this application only requires the deposition of a polycrystalline silicon layer 121 and a germanium-silicon initial base region layer 110 once, further simplifying the process flow.

[0058] In some alternative embodiments, the initial emitter structure 120 is made of polycrystalline silicon; the initial base layer 110 is made of germanium-silicon. The first initial protective layer 140 is made of silicon nitride; and the second initial protective layer 150 is made of silicon dioxide.

[0059] In some alternative embodiments, the emitter structure 12 is made of polycrystalline silicon; the base region 11 is made of germanium-silicon. The first protective layer 14 is made of silicon nitride; and the second protective layer 15 is made of silicon dioxide.

[0060] The present invention provides a semiconductor structure prepared by the semiconductor structure preparation method of the first aspect described above.

[0061] like Figure 2 As shown, the present invention also provides a specific flowchart of a method for preparing a semiconductor structure, including but not limited to steps S201 to S209.

[0062] Step S201, as follows Figure 3 As shown, a substrate layer 10 is provided, and an initial base region layer 110, a polysilicon layer 121 and an initial barrier layer 130 are sequentially formed on the substrate layer 10.

[0063] In specific implementation, the substrate layer 10 is made of silicon; the initial base layer 110 is made of germanium-silicon; the polycrystalline silicon layer 121 is made of polycrystalline silicon; and the initial barrier layer 130 is made of silicon nitride. The initial barrier layer 130 has a thickness of approximately 200 Å to 500 Å, and its deposition conditions are: temperature 400℃ to 600℃, main reactant gases SiH4+NH3+N2, pressure 3 Torr to 5 Torr, and deposition rate 20 Å / s to 40 Å / s.

[0064] Step S202, as follows Figure 4 and Figure 5 As shown, a first photomask is used to perform photolithography on the initial blocking layer 130 and the polysilicon layer 121, removing the initial blocking layer 130 and a portion of the polysilicon layer 121 corresponding to the edge portion 102; the remaining polysilicon layer 121 forms the initial emitter structure 120; the remaining initial blocking layer 130 forms the blocking layer 13; the blocking layer 13 covers the body portion 101 of the initial emitter structure 120.

[0065] In specific implementation, such as Figure 4 As shown, a first photoresist layer 91 is disposed above the initial barrier layer 130 corresponding to the body portion 101. The initial barrier layer 130 serves as a buffer layer between the first photoresist layer 91 and the polysilicon layer 121, improving photolithographic resolution and pattern accuracy, and preventing surface contamination of the polysilicon layer 121. Figure 5 As shown, etching removes the initial barrier layer 130 and a portion of the polysilicon layer 121 corresponding to the edge portion 102. The initial barrier layer 130 corresponding to the body portion 101 is not etched under the protection of the first photoresist layer 91, forming the barrier layer 13. After etching, the thickness of the edge portion 102 of the initial emitter structure 120 is 100 Å.

[0066] Step S203, as follows Figure 6As shown, a first initial protective layer 140 is formed on the entire surface above the initial emitter structure 120; the first initial protective layer 140 covers the body portion 101, the edge portion 102, and the side portion of the body portion 101 protruding from the edge portion 102.

[0067] Step S204, as follows Figure 7 As shown, the first initial protective layer 140 above the body portion 101 and above the edge portion 102 is removed, and the first initial protective layer 140 on the side portion is retained to form the first protective layer 14.

[0068] Step S205, as follows Figure 8 As shown, the edge portion 102 of the initial emitter structure 120 is etched using a wet etching process, and a portion of the width of the body portion 101 is etched away to the side to form an inner groove. The remaining initial emitter structure 120 forms the emitter structure 12. The emitter structure 12 includes a first portion 21 covered by a first protective layer 14 and a second portion 22 exposed by the inner groove. The width of the second portion 22 is smaller than the width of the first portion 21.

[0069] In specific implementation, the wet etching process conditions are as follows: the etchant is ammonia water of a certain concentration, and the etching rate is 700~1000 Å / min. Wet etching is anisotropic etching, and the acid will react with the initial emitter structure 120 in both the vertical and horizontal directions. After the 100 Å thick edge portion 102 in the vertical direction is completely removed, the etching depth corresponding to the side of the body portion 101 (i.e., the lateral depth of the inner trench) is also 100 Å.

[0070] Step S206, as follows Figure 9 As shown, a second initial protective layer 150 is formed above the initial base layer 110, the barrier layer 13 and outside the first protective layer 14; the second initial protective layer 150 also fills the inner groove.

[0071] In practice, the material of the second initial protective layer 150 is silicon dioxide. The formation of the second initial protective layer 150 includes two depositions. The first deposition of silicon dioxide covers the surface of the initial base layer 110 and fills the inner trench; the second deposition of silicon dioxide covers the outer side of the first protective layer 14 and the surface of the barrier layer 13.

[0072] In practice, the material of the second initial protective layer 150 is silicon dioxide. The deposition of the second initial protective layer 150 includes two depositions. The first deposition of silicon dioxide covers the surface of the initial base layer 110 and fills the inner trench, and the second deposition of silicon dioxide covers the outer side of the first protective layer 14 and the surface of the barrier layer 13.

[0073] Step S207, as follows Figure 10As shown, the second initial protective layer 150 above the barrier layer 13 and above the initial base layer 110 is removed, and the second initial protective layer 150 outside the first protective layer 14 is retained to form the second protective layer 15.

[0074] Step S208, as follows Figure 11 As shown, the initial base layer 110 on the side of the emitter structure 12 is ion implanted and doped.

[0075] Step S209, as Figure 12 and Figure 13 As shown, the initial base layer 110 is photolithographically ...

[0076] In specific implementation, such as Figure 12 As shown, a second photoresist layer 92 is disposed above the initial base region layer 110, which has a partial width. The width of the second photoresist layer 92 is greater than the width of the active region 200. Figure 13 As shown, the initial base region layer 110 not covered by the second photoresist layer 92 is etched away, and the remaining portion forms the base region 11. The base region 11 covers the active region 200 and the shallow trench isolation structures 100 on both sides of the active region 200.

[0077] The present invention also provides a semiconductor structure, such as Figure 13 As shown, it is prepared by the above-described semiconductor structure preparation method.

[0078] In some alternative implementations, the semiconductor structure is an HBT device structure.

[0079] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0080] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0081] The above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of protection of the present invention is determined by the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: An initial base region layer and an initial emitter structure are sequentially formed on the base layer; the initial emitter structure includes a body portion located in the middle and an edge portion on the side; the body portion protrudes from the edge portion; the side portion of the body portion protruding from the edge portion is covered with a first protective layer; Remove the edge portion and part of the body portion, form an inner groove on the side of the body portion not covered by the first protective layer, and form an emitter structure with the remaining initial emitter structure; A second protective layer is formed on the outside of the first protective layer and inside the inner groove; a base region is formed in the initial base region layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The process of sequentially forming an initial base region layer and an initial emitter structure on the base layer includes: A substrate layer is provided, on which an initial base region layer, a polysilicon layer and an initial barrier layer are sequentially formed; The first photomask is used to perform photolithography on the barrier layer and the polysilicon layer to remove the initial barrier layer and a portion of the polysilicon layer corresponding to the edge portion; the remaining polysilicon layer forms the initial emitter structure; the remaining initial barrier layer forms the barrier layer; the barrier layer covers the body portion of the initial emitter structure. A first protective layer is formed on the side of the body portion of the initial emitter structure that protrudes from the edge portion.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The first protective layer is formed on the side of the body portion of the initial emitter structure that protrudes from the edge portion, including: A first initial protective layer is formed over the entire surface of the initial emitter structure; the first initial protective layer covers the body portion, the edge portion, and the side portion of the body portion that protrudes from the edge portion; Remove the first initial protective layer above the body portion and above the edge portion, and retain the first initial protective layer on the side portion to form a first protective layer.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The formation of a second protective layer on the outside of the first protective layer and inside the inner groove includes: A second initial protective layer is formed above the initial base region layer, the barrier layer, and outside the first protective layer; the second initial protective layer also fills the inner groove. The second initial protective layer above the barrier layer and above the initial base layer is removed, and the second initial protective layer outside the first protective layer is retained to form a second protective layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The edge portion and part of the body portion are removed, and an inner groove is formed on the side of the body portion not covered by the first protective layer. The remaining initial emitter structure forms an emitter structure, including: The edge of the initial emitter structure is etched using a wet etching process, and a portion of the body portion is etched away to the side to form an inner groove. The remaining initial emitter structure forms the emitter structure. The emitter structure includes a first portion covered by a first protective layer and a second portion exposed by the inner groove; the width of the second portion is smaller than the width of the first portion.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The ratio of the lateral depth of the inner groove to the thickness of the edge portion is 1:0.8 to 1:1.2; the thickness of the edge portion is 100 Å to 200 Å; and the lateral depth of the inner groove is 80 Å to 240 Å.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, A shallow trench isolation structure is formed within the substrate layer; two of the shallow trench isolation structures separate the substrate layer into an active region. The initial emitter structure is located above the active region; the width of the initial emitter structure is smaller than the width of the active region.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, A base region is formed in the initial base region layer, including: Ion implantation doping is performed on the initial base region layer on the side of the emitter structure; The initial base region layer is photolithographically lithographically formed using a second photomask, retaining a portion of the width of the initial base region layer to form a base region; the width of the base region is greater than the width of the active region; the base region covers the active region and a portion of the shallow trench isolation structure on both sides of the active region.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that, The material of the initial emitter structure includes polycrystalline silicon; The material of the first protective layer includes silicon nitride; The material of the second protective layer includes silicon dioxide; The material of the initial base layer is a germanium-silicon layer.

10. A semiconductor structure, characterized in that, It is prepared by the method of any one of claims 1 to 9.

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