Semiconductor device
By designing the cell structure of the insulated gate bipolar transistor and the fast recovery diode, and optimizing signal transmission and current distribution, the problem that semiconductor devices cannot simultaneously achieve low turn-on stress and low loss of IGBTs was solved, thus realizing the efficient and reliable operation of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2026-04-07
AI Technical Summary
Semiconductor devices cannot simultaneously meet the requirements of low turn-on stress and low loss of IGBTs.
Design a semiconductor device comprising interconnected insulated gate bipolar transistors (IGBTs) and fast recovery diodes. By setting different structural resistances, Miller capacitances, and saturation current values of IGBTs with different cell structures, the IGBT's turn-on and turn-off processes can be controlled under different current conditions using different cell structures, thereby optimizing signal transmission and current distribution.
This achieves both low turn-on stress and low loss of IGBTs under different current conditions, improving device reliability and stability, reducing the need for external drive resistors, and increasing integration density and conversion efficiency.
Smart Images
Figure CN121815682A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology
[0002] As a gate-controlled device, the switching speed of an IGBT (Insulated Gate Bipolar Transistor) is controlled by an external drive resistor and is limited by application boundaries. In semiconductor devices, the collector of the IGBT is connected to the anode of the FRD (Fast Recovery Diode). The turn-off resistance of the IGBT is determined by the peak value of the IGBT turn-off voltage under high current, while the turn-on resistance is determined by the peak value of the FRD reverse recovery voltage under low current.
[0003] Currently, semiconductor devices cannot simultaneously meet the requirements of low turn-on stress and low loss of IGBTs. Summary of the Invention
[0004] The purpose of this invention is to provide at least one semiconductor device that can solve the problem that semiconductor devices cannot simultaneously meet the requirements of low turn-on stress and low loss of IGBTs, and can at least achieve the effect of improving the semiconductor device to meet the requirements of low turn-on stress and low loss of IGBTs.
[0005] To address the aforementioned technical problems, the present invention provides a semiconductor device comprising: an insulated-gate bipolar transistor (IGBT) and a fast recovery diode interconnected thereto. The IGBT includes: a cell unit comprising a first cell structure and a second cell structure; a gate transmission line located on the cell unit; the gate transmission line includes a first gate transmission line and a second gate transmission line spaced apart; the first gate transmission line is connected to the gate of the first cell structure, and the second gate transmission line is connected to the gate of the second cell structure; and a resistor lead located on the cell unit, the resistor lead including a first resistor lead and a second resistor lead spaced apart. The system includes: a first resistance lead connected to the structural resistance of the first cell structure, and a second resistance lead connected to the structural resistance of the second cell structure; a gate pad located on the cell unit, wherein a first gate transmission line is connected to the gate pad via the first resistance lead; a second gate transmission line is connected to the gate pad via the second resistance lead; wherein the equivalent value of the structural resistance of the first cell structure is less than the equivalent value of the structural resistance of the second cell structure; the Miller capacitance value of the first cell structure is greater than the Miller capacitance value of the second cell structure; and the saturation current value of the first cell structure is less than the saturation current value of the second cell structure.
[0006] The semiconductor device provided by this invention has a gate pad that is suitable for electrical connection with an external driving circuit. When an on signal is applied to the gate pad, since the equivalent value of the structural resistance of the first cell structure is less than the equivalent value of the structural resistance of the second cell structure, the time for the on signal to be transmitted from the second resistor lead to the second gate transmission line is delayed compared to the time for the on signal to be transmitted from the first resistor lead to the first gate transmission line. The first gate transmission line is connected to the gate of the first cell structure, and the second gate transmission line is connected to the gate of the second cell structure, so that the first gate transmission line controls the conduction speed of the first cell structure faster than the second gate transmission line controls the conduction speed of the second cell structure. When a small current is applied to the gate pad as the turn-on signal, the first cell structure plays a major role. That is, when the second cell structure is turned on, the insulated-gate bipolar transistor (IGBT) is essentially turned on. Under small current, the turn-on stress of the IGBT is mainly controlled by the first cell structure. Because the Miller capacitance of the first cell structure is relatively large, the current change rate within it is relatively small, effectively suppressing the reverse recovery voltage of the fast recovery diode. This allows for the use of a smaller external drive resistor, reducing the turn-on stress of the IGBT. When a large current is applied to the gate pad as the turn-on signal, the first cell structure turns on first. Since the saturation current of the first cell structure is smaller than that of the second cell structure, it only plays a major role in the initial stage. As the second cell structure turns on, the turn-on process of the IGBT is mainly controlled by it. The Miller capacitance of the second cell structure is relatively small, and the current change rate within it is relatively large, significantly improving the turn-on speed of the IGBT and thus reducing its turn-on losses. When a turn-off signal is applied to the gate pad, as described above, the first cell structure turns off first. Under the premise that the total current of the semiconductor device remains constant, since the current proportion of the first cell structure is relatively small, the turn-off process of the insulated-gate bipolar transistor (IGBT) is mainly controlled by the second cell structure. The Miller capacitance value of the second cell structure is relatively small, and the current change rate in the second cell structure is relatively large, which can significantly improve the turn-off speed of the IGBT, thereby reducing the turn-off loss of the IGBT. In summary, the semiconductor device provided by this invention can meet the requirements of low turn-on stress and low loss of the IGBT.
[0007] Furthermore, the equivalent value of the structural resistance of the second cell structure is greater than 1 times the equivalent value of the structural resistance of the first cell structure, and less than or equal to 3 times the equivalent value of the structural resistance of the first cell structure. This balances the difference in conduction speed between the second and first cell structures with the requirement for low power consumption in semiconductor devices.
[0008] Furthermore, the Miller capacitance value of the first cell structure is greater than 1 times that of the second cell structure, and less than or equal to 3 times that of the second cell structure. This achieves a balance between the low turn-on stress of the insulated-gate bipolar transistor and the low power consumption of the first cell structure.
[0009] Furthermore, the saturation current value of the second cell structure is greater than 1 times the saturation current value of the first cell structure, and less than or equal to 3 times the saturation current value of the first cell structure. This achieves a balance between the requirements of low turn-on loss, low turn-off loss of the insulated gate bipolar transistor, and low power consumption of the second cell structure.
[0010] Furthermore, there are multiple first cell structures and second cell structures, which are alternately arranged along a first direction; wherein the extension direction of the gate of the first cell structure is the same as the extension direction of the gate of the second cell structure, and the first direction is perpendicular to the extension direction of the gate. The uniform distribution of the first cell junction and the second cell structure in the cell unit can respond promptly to signal changes on the gate transmission line, thereby enhancing the effect of reducing the turn-on stress and switching losses of the insulated gate bipolar transistor.
[0011] In addition, the first cell structure includes a plurality of first sub-cell structures continuously arranged along the second direction; the second cell structure includes a plurality of second sub-cell structures continuously arranged along the second direction; the extension direction of the gate of the first cell structure is the same as the extension direction of the gate of the second cell structure, and the second direction is parallel to the extension direction of the gate.
[0012] Additionally, the cell unit includes: a substrate; an emitter located on the substrate and a collector located on the side of the substrate opposite to the emitter; the collector of the insulated-gate bipolar transistor is connected to the anode of the fast recovery diode; the surface of the substrate facing the emitter has a first trench, a second trench, a third trench, and a fourth trench spaced apart, the gate of the first cell structure is located in the first trench, the structural resistor of the first cell structure is located in the second trench; the gate of the second cell structure is located in the third trench, and the structural resistor of the second cell structure is located in the fourth trench; the insulated-gate bipolar transistor further includes: an emitter pad located on the cell unit and corresponding to the emitter, the emitter pad being connected to the emitter, and a gate transmission line surrounding the emitter pad. By embedding the gate and structural resistor inside the substrate to form longitudinal trenches, the density of the cell structure can be significantly increased, thereby improving the integration density of the insulated-gate bipolar transistor; and the effect of improving the switching loss of the collector of the insulated-gate bipolar transistor is enhanced. The gate transmission line surrounding the emitter pad can enhance the signal coupling between the gate and the emitter, optimize the current distribution in the semiconductor device, and improve the reliability and stability of the semiconductor device.
[0013] Furthermore, the emitter pad includes a plurality of emitter pads spaced apart along a second direction, with at least the gate transmission line located between adjacent emitter pads; wherein the extension direction of the gate of the first cell structure is the same as the extension direction of the gate of the second cell structure, and the second direction is parallel to the extension direction of the gate. This can compensate for the deficiency in signal transmission capability caused by the long gate length.
[0014] In addition, the insulated-gate bipolar transistor (IGBT) further includes an insulating dielectric layer located between the cell and the gate transmission line, between the cell and the resistor lead, and between the cell and the gate pad. The insulating dielectric layer has a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole. The gate of the first cell structure is connected to the first gate transmission line through the first contact hole, the structural resistor of the first cell structure is connected to the first resistor lead through the second contact hole, the gate of the second cell structure is connected to the second gate transmission line through the third contact hole, and the structural resistor of the second cell structure is connected to the second resistor lead through the fourth contact hole. The insulating dielectric layer can prevent short circuits in the IGBT and improve its reliability.
[0015] Furthermore, the number of gates connected to the first gate transmission line is greater than the number of gates connected to the second gate transmission line. The Miller capacitance value used to characterize the first cell structure is greater than the Miller capacitance value of the second cell structure.
[0016] Furthermore, there are multiple second contact holes and multiple fourth contact holes, and the spacing between adjacent second contact holes is smaller than the spacing between adjacent fourth contact holes. The equivalent value of the structural resistance used to characterize the first cell structure is smaller than the equivalent value of the structural resistance of the second cell structure. Attached Figure Description
[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0018] Figure 1 This is a schematic diagram showing the change of turn-off voltage of an insulated gate bipolar transistor with current and the change of reverse recovery voltage of a fast recovery diode with current in existing semiconductor devices.
[0019] Figure 2 A top view of an insulated gate bipolar transistor provided in an embodiment of the present invention;
[0020] Figure 3 for Figure 2 A magnified view of a portion of region A in the middle;
[0021] Figure 4 for Figure 2 A magnified view of a portion of region B in the middle;
[0022] Figure 5 for Figure 2 A magnified view of a portion of region C. Detailed Implementation
[0023] like Figure 1 As shown, the horizontal axis represents the current of the IGBT (Insulated Gate Bipolar Transistor) and FRD (Fast Recovery Diode), and the vertical axis represents the turn-off voltage of the IGBT or the reverse recovery voltage of the FRD. The solid line represents a schematic diagram of the IGBT's turn-off voltage changing with current; the dashed line represents a schematic diagram of the FRD's reverse recovery voltage changing with current. Figure 1 It is known that under high current, the IGBT's turn-off voltage is relatively low, and a small adjustment to the IGBT's turn-off resistor is usually sufficient to effectively suppress the reverse recovery voltage of the FRD. However, under low current, the FRD's reverse recovery voltage is very high. To suppress the excessively high FRD reverse recovery voltage, a larger external drive resistor is typically required, which leads to a significant increase in the IGBT's turn-on losses under high current. When the IGBT is turned on, if a smaller external drive resistor is used, the IGBT's turn-on losses are low under high current, but the FRD's reverse recovery voltage is high under low current; if a larger external drive resistor is used, the FRD's reverse recovery voltage is low under low current, but the IGBT's turn-on losses are very high under high current. The high FRD reverse recovery voltage results in high IGBT turn-on stress. By adjusting the external drive resistor, semiconductor devices cannot simultaneously achieve both low IGBT turn-on stress and low losses.
[0024] Therefore, there is an urgent need to provide a semiconductor device to solve the problem that semiconductor devices cannot simultaneously meet the requirements of low turn-on stress and low loss of IGBTs.
[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand the present invention. However, the technical solutions claimed in the present invention can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0026] One embodiment of the present invention provides a semiconductor device, comprising: an insulated-gate bipolar transistor and a fast recovery diode interconnected, referenced to... Figure 2An insulated-gate bipolar transistor (IGBT) includes: a cell unit 100, which includes a first cell structure 100a and a second cell structure 100b; a gate transmission line 200 located on the cell unit 100; the gate transmission line 200 includes a first gate transmission line 200a and a second gate transmission line 200b spaced apart; the first gate transmission line 200a is connected to the gate of the first cell structure 100a, and the second gate transmission line 200b is connected to the gate of the second cell structure 100b; and a resistor lead 300 located on the cell unit 100, which includes a first resistor lead 300a and a second resistor lead 300b spaced apart; the first resistor lead 300a is connected to the gate of the first cell structure 100a; and the gate transmission line 200 is connected to the gate of the second cell structure 100b. The structure resistance of cell 100a is connected, and the second resistance lead 300b is connected to the structure resistance of the second cell structure 100b. The gate pad 400 is located on the cell unit 100. The first gate transmission line 200a is connected to the gate pad 400 through the first resistance lead 300a. The second gate transmission line 200b is connected to the gate pad 400 through the second resistance lead 300b. The equivalent value of the structure resistance of the first cell structure 100a is less than the equivalent value of the structure resistance of the second cell structure 100b. The Miller capacitance of the first cell structure 100a is greater than the Miller capacitance of the second cell structure 100b. The saturation current of the first cell structure 100a is less than the saturation current of the second cell structure 100b. Figure 1 The area within the dashed box represents cell 100.
[0027] In this embodiment, the gate pad 400 is adapted to be electrically connected to an external driving circuit. When an on signal is applied to the gate pad 400, since the equivalent value of the structural resistance of the first cell structure 100a is less than the equivalent value of the structural resistance of the second cell structure 100b, the time for the on signal to be transmitted from the second resistor lead 300b to the second gate transmission line 200b is delayed compared to the time for the on signal to be transmitted from the first resistor lead 300a to the first gate transmission line 200a. The first gate transmission line 200a is connected to the gate of the first cell structure 100a, and the second gate transmission line 200b is connected to the gate of the second cell structure 100b. This makes the conduction speed of the first cell structure 100a controlled by the first gate transmission line 200a faster than the conduction speed of the second cell structure 100b controlled by the second gate transmission line 200b. When a small current is applied to the gate pad 400 as the turn-on signal, the first cell structure 100a plays a major role. That is, when the second cell structure 100b is turned on, the insulated gate bipolar transistor (IGBT) has basically been turned on. Under small current, the turn-on stress of the IGBT is mainly controlled by the first cell structure 100a. Since the Miller capacitance of the first cell structure 100a is relatively large, the current change rate in the first cell structure 100a is relatively small, which can effectively suppress the reverse recovery voltage of the fast recovery diode. Thus, a smaller external drive resistor can be used to reduce the turn-on stress of the IGBT. When a large current is applied to the gate pad 400 as an on-state signal, the first cell structure 100a turns on first. Since the saturation current value of the first cell structure 100a is less than that of the second cell structure 100b, the first cell structure 100a only plays a major role in the initial stage. As the second cell structure 100b turns on, the turn-on process of the insulated gate bipolar transistor is mainly controlled by the second cell structure 100b. The Miller capacitance value of the second cell structure 100b is relatively small, and the current change rate in the second cell structure 100b is relatively large, which can significantly improve the turn-on speed of the insulated gate bipolar transistor, thereby reducing the turn-on loss of the insulated gate bipolar transistor. When a turn-off signal is applied to the gate pad 400, as described above, the first cell structure 100a turns off first. Under the premise that the total current of the semiconductor device remains constant, since the current proportion of the first cell structure 100a is relatively small, the turn-off process of the insulated-gate bipolar transistor (IGBT) is mainly controlled by the second cell structure 100b. The Miller capacitance value of the second cell structure 100b is relatively small, and the current change rate in the second cell structure 100b is relatively large, which can significantly improve the turn-off speed of the IGBT, thereby reducing the turn-off loss of the IGBT. In summary, the semiconductor device provided by this invention can simultaneously meet the requirements of low turn-on stress and low loss of the IGBT.
[0028] Furthermore, the semiconductor device provided by this invention requires only one driving resistor from an external driving circuit, without the need for additional processes and signal processing, while simultaneously meeting the requirements of low turn-on stress and low loss of an insulated gate bipolar transistor, resulting in low manufacturing costs. Therefore, the semiconductor device can achieve a comprehensive benefit of high output current capability, high conversion efficiency, and low manufacturing costs.
[0029] In one embodiment, the equivalent value of the structural resistance of the second cell structure 100b is greater than 1 times the equivalent value of the structural resistance of the first cell structure 100a, and less than or equal to 3 times the equivalent value of the structural resistance of the first cell structure 100a. For example, the equivalent value of the structural resistance of the second cell structure 100b is 1.5 times, 2 times, or 3 times the equivalent value of the structural resistance of the first cell structure 100a. If the equivalent value of the structural resistance of the second cell structure 100b is too large a multiple of the equivalent value of the structural resistance of the first cell structure 100a, the difference in conduction speed between the second cell structure 100b and the first cell structure 100a will increase, leading to increased energy consumption of the semiconductor device. Therefore, the equivalent value of the structural resistance of the second cell structure 100b is greater than 1 times the equivalent value of the structural resistance of the first cell structure 100a, and less than or equal to 3 times the equivalent value of the structural resistance of the first cell structure 100a. This balances the difference in conduction speed between the second cell structure 100b and the first cell structure 100a with the requirement for low power consumption of semiconductor devices. In this embodiment, preferably, the equivalent value of the structural resistance of the second cell structure 100b is 2 times the equivalent value of the structural resistance of the first cell structure 100a. It should be noted that in other embodiments, the equivalent value of the structural resistance of the second cell structure can be greater than 3 times the equivalent value of the structural resistance of the first cell structure, and is not limited to this.
[0030] In one embodiment, the Miller capacitance value of the first cell structure 100a is greater than 1 times the Miller capacitance value of the second cell structure 100b, and less than or equal to 3 times the Miller capacitance value of the second cell structure 100b. For example, the Miller capacitance value of the first cell structure 100a is 1.5 times, 2 times, or 3 times the Miller capacitance value of the second cell structure 100b. If the Miller capacitance value of the first cell structure 100a is too large a multiple of the Miller capacitance value of the second cell structure 100b, it will increase the energy consumption of the first cell structure 100a. Therefore, a Miller capacitance value of the first cell structure 100a that is greater than 1 times the Miller capacitance value of the second cell structure 100b, and less than or equal to 3 times the Miller capacitance value of the second cell structure 100b, can balance the requirements of low turn-on stress of the insulated gate bipolar transistor and low energy consumption of the first cell structure 100a. In this embodiment, preferably, the Miller capacitance value of the first cell structure 100a is twice the Miller capacitance value of the second cell structure 100b. It should be noted that in other embodiments, the Miller capacitance value of the first cell structure can be greater than three times the Miller capacitance value of the second cell structure, and is not limited thereto.
[0031] In one embodiment, the saturation current value of the second cell structure 100b is greater than 1 times the saturation current value of the first cell structure 100a, and less than or equal to 3 times the saturation current value of the first cell structure 100a. For example, the saturation current value of the second cell structure 100b is 1.5 times, 2 times, or 3 times the saturation current value of the first cell structure 100a. If the saturation current value of the second cell structure 100b is too large a multiple of the saturation current value of the first cell structure 100a, it will increase the energy consumption of the second cell structure 100b. Therefore, a saturation current value of the second cell structure 100b that is greater than 1 times the saturation current value of the first cell structure 100a, and less than or equal to 3 times the saturation current value of the first cell structure 100a, can balance the requirements of low turn-on loss, low turn-off loss of the insulated gate bipolar transistor, and low energy consumption of the second cell structure 100b. In this embodiment, preferably, the saturation current value of the second cell structure 100b is 2 times the saturation current value of the first cell structure 100a. It should be noted that in other embodiments, the saturation current value of the second cell structure can be more than three times the saturation current value of the first cell structure, and is not limited thereto.
[0032] In one embodiment, the insulated gate bipolar transistor (IGBT) further includes an insulating dielectric layer (not shown) located between the cell 100 and the gate transmission line 200, between the cell 100 and the resistor lead 300, and between the cell 100 and the gate pad 400. This prevents short circuits in the IGBT and improves its reliability.
[0033] refer to Figures 3 to 5 , Figure 3 for Figure 2 A magnified view of a portion of region A in the middle; Figure 4 for Figure 2 A magnified view of a portion of region B in the middle; Figure 5 for Figure 2 A partial enlarged view of region C. In one embodiment, the insulating dielectric layer has a first contact hole 500a, a second contact hole (not shown), a third contact hole 500b, and a fourth contact hole (not shown). The gate 110 of the first cell structure 100a is connected to the first gate transmission line 200a through the first contact hole 500a. The structural resistor (not shown) of the first cell structure 100a is connected to the first resistor lead 300a through the second contact hole. The gate 120 of the second cell structure 100b is connected to the second gate transmission line 200b through the third contact hole 500b. The structural resistor of the second cell structure 100b is connected to the second resistor lead 300b through the fourth contact hole.
[0034] Continue to refer to Figures 3 to 5 In one embodiment, the cell unit further includes a third cell structure having a ground gate 130, which is grounded. The potential of the ground gate 100c is zero.
[0035] In one embodiment, the number of gates 110 connected to the first gate transmission line 200a is greater than the number of gates 120 connected to the second gate transmission line 200b. That is, the number of first contact holes 500a is greater than the number of third contact holes 500b. This can be used to characterize that the Miller capacitance value of the first cell structure is greater than the Miller capacitance value of the second cell structure.
[0036] Figures 3 to 5 In the illustration, a first cell structure 100a has two gates 110 connected to the first gate transmission line 200a, a second cell structure 100b has one gate 120 connected to the second gate transmission line 200b, and a third cell structure has four ground gates 130. In other embodiments, the number of gates connected to the first gate transmission line in a first cell structure is not limited to these values, nor is the number of gates connected to the second gate transmission line in a second cell structure, nor is the number of ground gates in a third cell structure. The selection can be made according to actual needs, ensuring that the number of gates connected to the first gate transmission line is greater than the number of gates connected to the second gate transmission line.
[0037] In one embodiment, the material of the first gate transmission line 200a is polysilicon; or, the material of the first gate transmission line 200a is a metallic material, such as aluminum. In other embodiments, the material of the first gate transmission line 200a includes other conductive materials.
[0038] In one embodiment, there are multiple second contact holes and multiple fourth contact holes, and the spacing between adjacent second contact holes is smaller than the spacing between adjacent fourth contact holes. That is, there are multiple structural resistors in the first cell structure 100a and multiple structural resistors in the second cell structure 100b, and the spacing between adjacent structural resistors in the first cell structure 100a is smaller than the spacing between adjacent structural resistors in the second cell structure 100b. This can be used to characterize that the equivalent value of the structural resistor in the first cell structure is smaller than the equivalent value of the structural resistor in the second cell structure. In other embodiments, there may be only one structural resistor in the first cell structure 100a and only one structural resistor in the second cell structure 100b.
[0039] The number of second and fourth contact holes can be the same or different, as long as the equivalent value of the structural resistance of the first cell structure is less than the equivalent value of the structural resistance of the second cell structure.
[0040] In one embodiment, the material of the structural resistor in the first cell structure 100a includes, but is not limited to, polycrystalline silicon; the material of the structural resistor in the second cell structure 100b includes, but is not limited to, polycrystalline silicon.
[0041] In one embodiment, the cell unit 100 includes: a substrate (not shown); an emitter located on the substrate and a collector (not shown) located on the side of the substrate opposite to the emitter; wherein the collector (not shown) of the insulated gate bipolar transistor is connected to the anode of the fast recovery diode. The emitter of the first cell structure 100a is shared by the emitter of the second cell structure 100b, and the collector of the first cell structure 100a is shared by the collector of the second cell structure 100b.
[0042] It should be noted that the Miller capacitance value is the capacitance between the gate and the collector. The Miller capacitance value of the first cell structure 100a is the capacitance between the gate 110 and the collector of the first cell structure 100a, and the Miller capacitance value of the second cell structure 100b is the capacitance between the gate 120 and the collector of the second cell structure 100b.
[0043] In one embodiment, the surface of the substrate facing the emitter has a first trench, a second trench, a third trench, and a fourth trench (not shown) spaced apart. The gate 110 of the first cell structure 100a is located in the first trench, and the structural resistor of the first cell structure 100a is located in the second trench; the gate 120 of the second cell structure 100b is located in the third trench, and the structural resistor of the second cell structure 100b is located in the fourth trench. By embedding the gate and structural resistor inside the substrate to form longitudinal trenches, the density of the cell structure can be significantly increased, thereby improving the integration density of the insulated gate bipolar transistor; and the effect of improving the switching loss of the collector of the insulated gate bipolar transistor is enhanced.
[0044] It is known that the first and third trenches are surrounded by ion implantation regions. These ion implantation regions are used to form a first channel around the first trench when the gate 110 of the first cell structure 100a has an electrical signal; and to form a second channel around the third trench when the gate 120 of the second cell structure 100b has an electrical signal. The ratio of the ion implantation regions around the first and third trenches can be adjusted so that the number of first channels formed is greater than the number of second channels formed. This can be used to characterize that the saturation current value of the first cell structure 100a is less than the saturation current value of the second cell structure 100b.
[0045] In one embodiment, in conjunction with reference Figures 2 to 5 There are multiple first cell junctions 100a and second cell structures 100b, which are alternately arranged along a first direction X. The extension direction of the gate 110 of the first cell structure 100a is the same as the extension direction of the gate 120 of the second cell structure 10b, and the first direction X is perpendicular to the extension direction of the gate. The uniform distribution of the first cell junctions 100a and second cell structures 100b within the cell unit 100 enhances the ability to respond promptly to signal changes on the gate transmission line 200, thereby reducing the turn-on stress and switching losses of the insulated-gate bipolar transistor (IGBT).
[0046] In one embodiment, the first cell structure 100a includes a plurality of first sub-cell structures (not shown) continuously arranged along the second direction Y; the second cell structure 100b includes a plurality of second sub-cell structures (not shown) continuously arranged along the second direction Y; the extension direction of the gate 110 of the first cell structure 100a is the same as the extension direction of the gate 120 of the second cell structure 100b, and the second direction Y is parallel to the extension direction of the gate. Figure 1 In the diagram, the first direction X is perpendicular to the second direction Y.
[0047] In one embodiment, the insulated gate bipolar transistor further includes: an emitter pad 600 located on the cell unit 100 and corresponding to the emitter, the emitter pad 600 being connected to the emitter, and a gate transmission line 200 surrounding the emitter pad 600. This enhances signal coupling between the gate and emitter, optimizes current distribution in the semiconductor device, and improves the reliability and stability of the semiconductor device.
[0048] In one embodiment, the emitter pad 600 includes a plurality of emitter sub-pads 600a spaced apart along the second direction Y, and at least the gate transmission line 200 is located between adjacent emitter sub-pads 600a. When the first cell structure 100a includes a plurality of first sub-cell structures continuously arranged along the second direction Y, and the second cell structure 100b includes a plurality of second sub-cell structures continuously arranged along the second direction Y, the gate 110 of the first cell structure 100a and the gate 120 of the second cell structure 100b are relatively long along the second direction Y. By providing a plurality of emitter sub-pads 600a along the second direction Y and providing the gate transmission line 200 between adjacent emitter pads 600a, the deficiency of signal transmission capability caused by the long gate length can be compensated. Figure 1 The area enclosed by the thick solid line is the area of emitter pad 600a, which is also the area of emitter pad 600.
[0049] The description of the second direction Y is given in the description of the foregoing embodiments.
[0050] The emitter pad 600a corresponds one-to-one with the emitter. It can be seen that the emitter includes multiple emitter sub-electrodes spaced apart along the second direction Y. Figure 1 The illustration shows three emitter pads 600a and three emitter electrodes. In other embodiments, the number of emitters and emitter pads 600a are not limited.
[0051] It should be understood that the terms "mechanism," "device," "component," etc., used in this application are merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.
[0052] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention. In practical applications, the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and detail without departing from the spirit and scope of the present invention.
Claims
1. A semiconductor device, comprising: An insulated-gate bipolar transistor and a fast recovery diode are interconnected, characterized in that the insulated-gate bipolar transistor comprises: A cellular unit, wherein the cellular unit includes a first cellular structure and a second cellular structure; A gate transmission line is located on the cell unit; the gate transmission line includes a first gate transmission line and a second gate transmission line that are spaced apart; the first gate transmission line is connected to the gate of the first cell structure, and the second gate transmission line is connected to the gate of the second cell structure. A resistor lead is located on the cell unit. The resistor lead includes a first resistor lead and a second resistor lead that are spaced apart. The first resistor lead is connected to the structural resistance of the first cell structure, and the second resistor lead is connected to the structural resistance of the second cell structure. A gate pad is located on the cell unit, wherein the first gate transmission line is connected to the gate pad through the first resistor lead; and the second gate transmission line is connected to the gate pad through the second resistor lead. Wherein, the equivalent value of the structural resistance of the first cell structure is less than the equivalent value of the structural resistance of the second cell structure; the Miller capacitance of the first cell structure is greater than the Miller capacitance of the second cell structure; and the saturation current of the first cell structure is less than the saturation current of the second cell structure.
2. The semiconductor device according to claim 1, characterized in that, The equivalent value of the structural resistance of the second cell structure is greater than 1 times the equivalent value of the structural resistance of the first cell structure, and less than or equal to 3 times the equivalent value of the structural resistance of the first cell structure.
3. The semiconductor device according to claim 1, characterized in that, The Miller capacitance value of the first cell structure is greater than 1 times the Miller capacitance value of the second cell structure, and less than or equal to 3 times the Miller capacitance value of the second cell structure.
4. The semiconductor device according to claim 1, characterized in that, The saturation current value of the second cell structure is greater than 1 times the saturation current value of the first cell structure, and less than or equal to 3 times the saturation current value of the first cell structure.
5. The semiconductor device according to claim 1, characterized in that, There are multiple first cell structures and second cell structures, and the first cell structures and second cell structures are alternately arranged along a first direction; Wherein, the extension direction of the gate of the first cell structure is the same as the extension direction of the gate of the second cell structure, and the first direction is perpendicular to the extension direction of the gate.
6. The semiconductor device according to claim 1, characterized in that, The first cell structure includes a plurality of first sub-cell structures continuously arranged along a second direction; the second cell structure includes a plurality of second sub-cell structures continuously arranged along a second direction; the extension direction of the gate of the first cell structure is the same as the extension direction of the gate of the second cell structure, and the second direction is parallel to the extension direction of the gate.
7. The semiconductor device according to any one of claims 1-6, characterized in that, The cell unit includes: a substrate; an emitter located on the substrate and a collector located on the side of the substrate opposite to the emitter; the collector of the insulated gate bipolar transistor is connected to the anode of the fast recovery diode; The substrate has a first trench, a second trench, a third trench, and a fourth trench spaced apart on its surface facing the emitter. The gate of the first cell structure is located in the first trench, and the structural resistance of the first cell structure is located in the second trench. The gate of the second cell structure is located in the third trench, and the structural resistance of the second cell structure is located in the fourth trench. The insulated gate bipolar transistor further includes: an emitter pad located on the cell unit and corresponding to the emitter, the emitter pad being connected to the emitter, and the gate transmission line being arranged around the emitter pad.
8. The semiconductor device according to claim 7, characterized in that, The emitter pads include a plurality of emitter pads spaced apart along a second direction, and at least the gate transmission lines are located between adjacent emitter pads; Wherein, the extension direction of the gate of the first cell structure is the same as the extension direction of the gate of the second cell structure, and the second direction is parallel to the extension direction of the gate.
9. The semiconductor device according to claim 1, characterized in that, The insulated gate bipolar transistor further includes: an insulating dielectric layer located between the cell and the gate transmission line, between the cell and the resistor lead, and between the cell and the gate pad; The insulating dielectric layer has a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole. The gate of the first cell structure is connected to the first gate transmission line through the first contact hole. The structural resistor of the first cell structure is connected to the first resistor lead through the second contact hole. The gate of the second cell structure is connected to the second gate transmission line through the third contact hole. The structural resistor of the second cell structure is connected to the second resistor lead through the fourth contact hole.
10. The semiconductor device according to claim 1, characterized in that, The number of gates connected to the first gate transmission line is greater than the number of gates connected to the second gate transmission line.
11. The semiconductor device according to claim 9, characterized in that, There are multiple second contact holes and multiple fourth contact holes, and the spacing between adjacent second contact holes is smaller than the spacing between adjacent fourth contact holes.