Super-junction MOSFET device and preparation method thereof

Abstract

The invention provides a super junction MOSFET device and a preparation method thereof, the super junction MOSFET device comprises a substrate layer, a first epitaxial layer, a plurality of first P-type columns, a second epitaxial layer, a plurality of second P-type columns, a trench gate, a body region, a source region, an insulating layer, a source electrode metal layer and a plurality of contact parts, the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; the doping concentration of the second P-type column is greater than that of the first P-type column; the trench gate is located in the second epitaxial layer between two adjacent second P-type columns; the contact parts extend into the second P-type column from the source electrode metal layer, and the side face of at least one contact part is connected with the source region and the body region. According to the super-junction MOSFET device, the second epitaxial layer with higher doping concentration, the second P-type column with higher doping concentration and more contact parts are arranged, so that the on-resistance of the device is further reduced under the condition that the breakdown voltage is not reduced, and meanwhile, the EAS capability of the device is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology and relates to a superjunction MOSFET device and its fabrication method. Background Technology

[0002] Superjunction MOSFETs are revolutionary power semiconductor devices that overcome the "silicon limit" of traditional silicon-based devices through a three-dimensional charge-compensation structure, achieving a balance between low on-resistance and high voltage withstand in high-voltage, high-power applications. Due to their high integration, low on-resistance, fast switching speed, and low switching losses, superjunction MOSFETs are widely used in various power supplies, energy storage, and on-board charging applications. As application requirements become increasingly demanding, the reliability requirements for superjunction MOSFETs are also rising.

[0003] On-resistance directly affects power loss; the lower the on-resistance, the lower the power loss. Single-Pulse Avalanche Energy (EAS) calibrates the level of reverse avalanche breakdown energy a device can safely absorb. EAS characteristics directly relate to the device's safe operating area and lifetime. Compared to equivalent vertical double-diffused metal-oxide-semiconductor (VDMOS) devices, superjunction MOSFETs have significantly lower on-resistance, but their EAS capability is significantly lower. Existing superjunction MOSFET devices are limited by their structure and fabrication processes, making it difficult to improve their EAS capability while simultaneously reducing on-resistance.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a superjunction MOSFET device and its fabrication method, so as to solve the problem that the superjunction MOSFET device in the prior art is difficult to improve its EAS capability while reducing the on-resistance.

[0006] To achieve the above and other related objectives, the present invention provides a superjunction MOSFET device, comprising:

[0007] Substrate layer;

[0008] The first epitaxial layer is located on the substrate layer;

[0009] Multiple spaced and parallel first P-shaped pillars are located in the first epitaxial layer;

[0010] The second epitaxial layer is located on the first epitaxial layer, and the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer;

[0011] Multiple second P-type pillars are spaced apart and arranged in parallel in the second epitaxial layer. The multiple second P-type pillars correspond one-to-one with the multiple first P-type pillars and are in contact with each other. The doping concentration of the second P-type pillars is greater than that of the first P-type pillars.

[0012] The trench gate, body region, and source region are defined as follows: the trench gate is located in the second epitaxial layer between two adjacent second P-type pillars; the body region is located on the upper surface of the second epitaxial layer on both sides of the trench gate; and the source region is located on the upper surface of the body region.

[0013] An insulating layer is located on the second epitaxial layer;

[0014] A source metal layer is located on the insulating layer;

[0015] Multiple contact portions penetrate the insulating layer, with the top end of each contact portion connected to the source metal layer and the bottom end extending into the second P-shaped pillar. At least one side of each contact portion connects the source region and the body region.

[0016] Optionally, the height of the second P-shaped column is less than the height of the first P-shaped column, and the width of the second P-shaped column is greater than the width of the first P-shaped column.

[0017] Optionally, the first P-type pillar is made of boron-doped silicon, and the width of the first P-type pillar is not less than 3 micrometers and the height ranges from 30 to 40 micrometers; the second P-type pillar is made of boron-doped silicon, and the width of the second P-type pillar is not less than 4 micrometers and the height ranges from 5 to 10 micrometers.

[0018] Optionally, the trench grid is equidistant from the two second P-shaped posts located on either side thereof.

[0019] Optionally, the bottom surface of the trench grid is higher than the bottom surface of the second P-shaped post.

[0020] Optionally, the distance between any two adjacent contact portions is equal.

[0021] Optionally, the trench gate includes a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer surrounds the sidewalls and bottom surface of the gate conductive layer.

[0022] This invention also provides a method for fabricating a superjunction MOSFET device, comprising:

[0023] A first epitaxial layer is formed on the substrate layer;

[0024] Multiple spaced and parallel first P-shaped pillars are formed in the first epitaxial layer;

[0025] A second epitaxial layer is formed on the first epitaxial layer, wherein the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer;

[0026] Multiple second P-type pillars are formed in the second epitaxial layer, which are spaced apart and arranged in parallel. The multiple second P-type pillars correspond one-to-one with the multiple first P-type pillars and are in contact with each other. The doping concentration of the second P-type pillars is greater than that of the first P-type pillars.

[0027] A trench gate, a body region, and a source region are formed. The trench gate is located in the second epitaxial layer between two adjacent second P-type pillars. The body region is located on the upper surface of the second epitaxial layer on both sides of the trench gate. The source region is located on the upper surface of the body region.

[0028] An insulating layer is formed on the second epitaxial layer;

[0029] Multiple contact portions are formed, the contact portions penetrate the insulating layer and the bottom end of the contact portions extends into the second P-shaped post, and at least one side of the contact portion connects the source region and the body region;

[0030] A source metal layer is formed on the insulating layer, and the source metal layer is connected to the top end of the contact portion.

[0031] Optionally, the first P-shaped pillar is formed by forming a first trench in the first epitaxial layer and backfilling it, and the second P-shaped pillar is formed by forming a second trench in the second epitaxial layer and backfilling it.

[0032] Optionally, the height of the second P-shaped column is less than the height of the first P-shaped column, and the width of the second P-shaped column is greater than the width of the first P-shaped column.

[0033] As described above, the superjunction MOSFET device of the present invention includes a substrate layer, a first epitaxial layer, a plurality of spaced and parallel first P-type pillars, a second epitaxial layer, a plurality of spaced and parallel second P-type pillars, a trench gate, a body region, a source region, an insulating layer, a source metal layer, and a plurality of contacts. The first P-type pillars are located in the first epitaxial layer; the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; the second P-type pillars are located in the second epitaxial layer, and the doping concentration of the second P-type pillars is greater than that of the first P-type pillars; the trench gate is located in the second epitaxial layer between two adjacent second P-type pillars; the body region is located on the upper surface of the second epitaxial layer on both sides of the trench gate; and the source region is located on the upper surface of the body region. The plurality of contacts penetrate the insulating layer, with the top end of each contact connected to the source metal layer and the bottom end extending into the second P-type pillars. At least one contact has a side surface connected to the source region and the body region. In this invention, the drift region resistance is reduced by setting a second epitaxial layer with a higher doping concentration, thereby reducing the on-resistance of the device. A charge balance is achieved by using a second P-type pillar with a higher doping concentration and a wider width in conjunction with the second epitaxial layer, reducing the impedance of the body region and ensuring that the breakdown voltage of the device does not decrease. Furthermore, by setting more contacts in the wider second P-type pillar to connect the source metal layer with the body and source regions, the parasitic transistor is less likely to conduct during avalanche, improving the device's EAS capability. The superjunction MOSFET device of this invention, by setting a second epitaxial layer with a higher doping concentration, a second P-type pillar with a higher doping concentration, and more contacts, further reduces the on-resistance of the device without decreasing the breakdown voltage, while simultaneously improving the device's EAS capability. Attached Figure Description

[0034] Figure 1 The diagram shown is a schematic representation of the superjunction MOSFET device of the present invention in one embodiment.

[0035] Figure 2 The diagram shown is a flowchart illustrating the fabrication method of the superjunction MOSFET device of the present invention.

[0036] Figure 3 The diagram shown is a schematic of the structure obtained after forming a first epitaxial layer on a substrate layer in the fabrication method of the superjunction MOSFET device of the present invention.

[0037] Figure 4 The diagram shown is a schematic diagram of the structure obtained after forming a plurality of spaced and parallel first P-type pillars in the first epitaxial layer in the fabrication method of the superjunction MOSFET device of the present invention.

[0038] Figure 5 The diagram shown is a schematic of the structure obtained after forming a second epitaxial layer on the first epitaxial layer in the fabrication method of the superjunction MOSFET device of the present invention.

[0039] Figure 6 The diagram shows a schematic of the structure obtained after forming a plurality of spaced and parallel second P-type pillars in the second epitaxial layer in the fabrication method of the superjunction MOSFET device of the present invention.

[0040] Figure 7 The diagram shown is a schematic of the structure obtained after the initial body region is formed on the upper surface layer of the second epitaxial layer in the fabrication method of the superjunction MOSFET device of the present invention.

[0041] Figure 8 The diagram shown is a schematic of the structure obtained after forming a trench gate in the second epitaxial layer located between two adjacent second P-type pillars in the fabrication method of the superjunction MOSFET device of the present invention.

[0042] Figure 9 The diagram shown is a schematic of the structure obtained after the source region is formed on the upper surface layer of the body region in the fabrication method of the superjunction MOSFET device of the present invention.

[0043] Figure 10 The diagram shown is a schematic of the structure obtained after forming an insulating layer on the second epitaxial layer in the fabrication method of the superjunction MOSFET device of the present invention.

[0044] Figure 11 The diagram shown is a schematic of the structure obtained after forming multiple contacts in the fabrication method of the superjunction MOSFET device of the present invention.

[0045] Explanation of reference numerals in the attached figures

[0046] 1 Substrate layer 2 First epitaxial layer 3 First P-type pillar 4 Second epitaxial layer 5 Second P-type pillar 6 Trench gate 7 Body region 8 Source region 9 Insulating layer 10 Source metal layer 11 Contact 12 Initial body region S201~S207, S1001~S1003 Step Detailed Implementation

[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0049] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0050] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0051] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0052] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0053] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] Please see Figure 1 The diagram shows a schematic representation of a superjunction MOSFET device according to an embodiment of the present invention, including a substrate layer 1, a first epitaxial layer 2, and a plurality of spaced and parallel first P-type pillars 3. Figure 1 The example shows two first P-shaped pillars 3, with reference numeral 3 indicating one of them, a second epitaxial layer 4, and a plurality of spaced and parallel second P-shaped pillars 5. Figure 1 The example shows two second P-type pillars 5, denoted by 5, a trench gate 6, a body region 7, a source region 8, an insulating layer 9, a source metal layer 10, and multiple contacts 11. Figure 1The example shows six contact portions 11 (reference numeral 11 indicates one of them), wherein the first epitaxial layer 2 is located on the substrate layer 1; a plurality of spaced and parallel first P-type pillars 3 are located in the first epitaxial layer 2; a second epitaxial layer 4 is located on the first epitaxial layer 2, the doping concentration of the second epitaxial layer 4 being greater than the doping concentration of the first epitaxial layer 2; a plurality of spaced and parallel second P-type pillars 5 are located in the second epitaxial layer 4, the plurality of second P-type pillars 5 corresponding one-to-one with the plurality of first P-type pillars 3 and contacting each other, the doping concentration of the second P-type pillars 5 being greater than the first P-type pillars 3. The doping concentration of the P-type pillar 3; the trench gate 6 is located in the second epitaxial layer 4 between two adjacent second P-type pillars 5, the body region 7 is located on the upper surface of the second epitaxial layer 4 on both sides of the trench gate 6, the source region 8 is located on the upper surface of the body region 7; the insulating layer 9 is located on the second epitaxial layer 4; the source metal layer 10 is located on the insulating layer 9; a plurality of the contact portions 11 penetrate the insulating layer 9, the top end of the contact portion 11 is connected to the source metal layer 10, the bottom end extends into the second P-type pillar 5, and at least one side of the contact portion 11 is connected to the source region 8 and the body region 7.

[0055] In this invention, the drift region resistance is reduced by setting a second epitaxial layer 4 with a higher doping concentration, thereby reducing the on-resistance of the device. By setting a second P-type pillar 5 with a higher doping concentration and a wider width to cooperate with the second epitaxial layer 4 with a higher doping concentration to achieve charge balance matching, the impedance of the body region 7 is reduced, ensuring that the breakdown voltage of the device does not decrease. By setting more contacts 11 in the wider second P-type pillar 5 to connect the source metal layer 10 with the body region 7 and the source region 8, the parasitic transistor is less likely to conduct during avalanche, improving the device's EAS capability.

[0056] In this invention, the substrate layer 1, the first epitaxial layer 2, and the second epitaxial layer 4 are all N-type doped regions, and the doping concentration of the substrate layer 1 is greater than that of the second epitaxial layer 4, while the doping concentration of the second epitaxial layer 4 is greater than that of the first epitaxial layer 2. By providing a second epitaxial layer 4 on the first epitaxial layer 2 with a higher N-type doping concentration than the first epitaxial layer 2, the drift region resistance and channel resistance can be further reduced, thereby reducing the overall on-resistance of the device.

[0057] In some possible embodiments, the material of the substrate layer 1 includes p-doped silicon, and the thickness of the substrate layer 1 ranges from 100 to 900 micrometers, such as 200 micrometers, 500 micrometers, 800 micrometers, etc.

[0058] In some possible embodiments, the material of the first epitaxial layer 2 includes p-doped silicon, and the thickness of the first epitaxial layer 2 is not less than 30 micrometers, such as 30 micrometers, 50 micrometers, 70 micrometers, etc.

[0059] In some possible embodiments, the material of the second epitaxial layer 4 includes p-doped silicon, and the thickness of the second epitaxial layer 4 is in the range of 5-10 micrometers, such as 6 micrometers, 7.5 micrometers, 9 micrometers, etc.

[0060] In this invention, the first P-type pillar 3 is a P-type element doped region. Multiple first P-type pillars 3 are arranged horizontally and parallel to each other in the first epitaxial layer 2, with the upper surface of the first P-type pillar 3 and the upper surface of the first epitaxial layer 2 located on the same horizontal plane. The second P-type pillar 5 is a P-type element doped region. Multiple second P-type pillars 5 are arranged horizontally and parallel to each other in the second epitaxial layer 4, with the upper and lower surfaces of the second P-type pillar 5 respectively located on the same horizontal plane as the upper and lower surfaces of the second epitaxial layer 4. The second P-type pillar 5 corresponds one-to-one with the first P-type pillar 3 and is in contact with each other.

[0061] In this invention, the first P-type pillar 3 and the second P-type pillar 5, which correspond to each other, together form a P-type pillar structure. The doping concentration of the second P-type pillar 5 is greater than that of the first P-type pillar 3, and the width of the second P-type pillar 5 is greater than that of the first P-type pillar 3. By providing a second P-type pillar 5 on the first P-type pillar 3 that is wider and has a higher P-type element doping concentration than the first P-type pillar 3, and by having it cooperate with the second epitaxial layer 4 that has a higher N-type element doping concentration, charge balance matching is achieved, ensuring that the breakdown voltage of the device does not decrease.

[0062] In some possible embodiments, the height of the second P-shaped column 5 is less than the height of the first P-shaped column 3.

[0063] In some possible embodiments, the distance between any two adjacent first P-shaped posts 3 of the plurality of first P-shaped posts 3 may be equal or unequal. Similarly, the distance between any two adjacent second P-shaped posts 5 of the plurality of second P-shaped posts 5 may be equal or unequal.

[0064] In some possible embodiments, all the first P-type pillars 3 have the same structural features. The material of the first P-type pillars 3 includes boron-doped silicon. The width of the first P-type pillars 3 is not less than 3 micrometers, for example, 3 micrometers, 5 micrometers, 7 micrometers, etc. The height of the first P-type pillars 3 ranges from 30 to 40 micrometers, for example, 32 micrometers, 35 micrometers, 38 micrometers, etc.

[0065] In some possible embodiments, all the second P-type pillars 5 have the same structural features. The material of the second P-type pillars 5 includes boron-doped silicon. The width of the second P-type pillars 5 is not less than 4 micrometers, for example, 4 micrometers, 6 micrometers, 8 micrometers, etc. The height of the second epitaxial layer 4 ranges from 5 to 10 micrometers, for example, 6 micrometers, 7.5 micrometers, 9 micrometers, etc.

[0066] As an example, the trench grid 6 is provided in the second epitaxial layer 4 between any two adjacent second P-shaped pillars 5. The distance between each trench grid 6 and the two second P-shaped pillars 5 located on its two sides is equal.

[0067] In some embodiments, the bottom surface of the trench grid 6 is higher than the bottom surface of the second P-shaped post 5. The height of the trench grid 6 ranges from 1.5 to 3 micrometers, for example, 2 micrometers, 2.5 micrometers, etc.

[0068] In some embodiments, the trench gate 6 includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer surrounding the sidewalls and bottom surface of the gate conductive layer. The gate dielectric layer is made of silicon dioxide, and the gate conductive layer is made of polycrystalline silicon.

[0069] As an example, the body region 7 is a P-type element doped region obtained by ion implantation of the upper surface layer of the second epitaxial layer 4. The specific ion implantation parameters, such as dose, energy, and concentration, can be set according to actual needs. In order to ensure that the device turn-on voltage is not too high, the doping concentration of the body region 7 is required to be less than the doping concentration of the first P-type pillar 3 and the second P-type pillar 5, and the doping concentration of the body region 7 is much less than the doping concentration of the second P-type pillar 5.

[0070] In some possible embodiments, the material of the body region 7 includes boron-doped silicon. The height of the body region 7 is no greater than 1.5 micrometers, for example, 0.5 micrometers, 1 micrometer, 1.5 micrometers, etc.

[0071] As an example, the source region 8 is an N-type element-doped region obtained by ion implantation of the upper surface layer of the body region 7. Specific ion implantation parameters, such as dose, energy, and concentration, can be set according to actual needs. The source region 8 is tightly integrated with the trench gate 6 and the body region 7, reducing resistance through a vertical conductive path while maintaining high withstand voltage.

[0072] In some embodiments, the material of the source region 8 includes arsenic-doped silicon. The width of the source region 8 is no greater than 1 micrometer, for example, 1 micrometer, 0.5 micrometers, etc. The height of the source region 8 is no greater than 0.5 micrometers, for example, 0.4 micrometers, 0.2 micrometers, etc.

[0073] As an example, the insulating layer 9 is located on the second epitaxial layer 4, and the lower surface of the insulating layer 9 is in contact with the upper surfaces of the body region 7, the plurality of second P-type pillars 5, the trench gate 6, and the source region 8 located in the second epitaxial layer 4. The insulating layer 9 disposed between the source metal layer 10 and the second epitaxial layer 4 is used to isolate the source metal layer 10 and the trench gate 6, preventing the source metal layer 10 from being connected to the trench gate 6 and short-circuited.

[0074] In some embodiments, the insulating layer 9 is made of silicon dioxide.

[0075] As an example, the greater width of the second P-shaped post 5 allows for more space to accommodate more of the contacts 11, establishing connections between the source metal layer 10 and the body region 7 and the source region 8. To this end, multiple contacts 11 penetrating the insulating layer 9 are provided between each of the second P-shaped posts 5 and the source metal layer 10. The top end of each contact 11 connects to the source metal layer 10, and the bottom end extends into the second P-shaped post 5. At least one contact 11 is provided at each of the left and right ends of each second P-shaped post 5 to connect the source region 8 and the body region 7 to the source metal layer 10. By providing more contacts 11 between the second P-shaped posts 5 and the source metal layer 10, the impedance of the body region 7 can be increased, making it less likely for the parasitic transistor to conduct during avalanche, thus enhancing the device's EAS capability.

[0076] In some possible embodiments, in the direction from one second P-shaped post 5 to the adjacent second P-shaped post 5, for example... Figure 1 In the X direction shown, a second P-shaped post 5 is provided with three or more contact portions 11 arranged sequentially and at intervals along the X direction, and the distance between any two adjacent contact portions 11 is equal. For example Figure 1 The image shows a second P-shaped column 5 with three contact portions 11 arranged sequentially and at intervals along the X direction. The left and right contact portions 11 are in direct contact with the source region 8 and the body region 7, while the middle contact portion 11 is equidistant from the left and right contact portions 11 and is not in direct contact with the source region 8 and the body region 7.

[0077] In some possible embodiments, the plurality of contact portions 11 are arranged in a multi-row, multi-column array.

[0078] In some embodiments, the contact portion 11 is made of a combination of aluminum and gold. The height of the contact portion 11 ranges from 4 to 5 micrometers, for example, 4.2 micrometers, 4.5 micrometers, or 4.8 micrometers. The length of the contact portion 11 extending into the second P-shaped post 5 ranges from 0.5 to 1.5 micrometers, for example, 0.8 micrometers, 1 micrometer, or 1.2 micrometers.

[0079] The superjunction MOSFET device of the present invention further reduces the on-resistance of the device without reducing the breakdown voltage by setting the second epitaxial layer 4 with a higher doping concentration, the second P-type pillar 5 with a higher doping concentration, and a greater number of the contact portions 11. At the same time, it improves the EAS capability of the device.

[0080] This invention also provides a method for fabricating a superjunction MOSFET device, to prepare the superjunction MOSFET device described in any of the above embodiments. Please refer to [link to relevant documentation]. Figure 2 The diagram shows a flow chart of the fabrication method of the superjunction MOSFET device of the present invention, including the following steps:

[0081] S201: Forming a first epitaxial layer on a substrate;

[0082] S202: A plurality of spaced and parallel first P-shaped pillars are formed in the first epitaxial layer;

[0083] S203: A second epitaxial layer is formed on the first epitaxial layer, wherein the doping concentration of the second epitaxial layer is greater than the doping concentration of the first epitaxial layer;

[0084] S204: A plurality of spaced and parallel second P-type pillars are formed in the second epitaxial layer, the plurality of second P-type pillars correspond one-to-one with the plurality of first P-type pillars and are in contact with each other, and the doping concentration of the second P-type pillars is greater than the doping concentration of the first P-type pillars.

[0085] S205: Forming a trench gate, a body region, and a source region, wherein the trench gate is located in the second epitaxial layer between two adjacent second P-type pillars, the body region is located on the upper surface of the second epitaxial layer on both sides of the trench gate, and the source region is located on the upper surface of the body region;

[0086] S206: An insulating layer is formed on the second epitaxial layer;

[0087] S207: A plurality of contact portions are formed, the contact portions penetrating the insulating layer and the bottom end of the contact portions extending into the second P-shaped post, and at least one side of the contact portion connects the source region and the body region;

[0088] S208: A source metal layer is formed on the insulating layer, and the source metal layer is connected to the top end of the contact portion.

[0089] The following section, using a structural diagram, details the specific implementation methods of each of the above steps.

[0090] Please refer to the following first. Figure 3 Step S201: The first epitaxial layer 2 is formed on the substrate layer 1 by an epitaxial process. Both the substrate layer 1 and the first epitaxial layer 2 are N-type element-doped regions, and the doping concentration of the substrate layer 1 is greater than the doping concentration of the first epitaxial layer 2.

[0091] In some possible embodiments, the material of the substrate layer 1 includes p-doped silicon, and the thickness of the substrate layer 1 ranges from 100 to 900 micrometers, such as 200 micrometers, 500 micrometers, 800 micrometers, etc.

[0092] In some possible embodiments, the material of the first epitaxial layer 2 includes p-doped silicon, and the thickness of the first epitaxial layer 2 is not less than 30 micrometers, such as 30 micrometers, 50 micrometers, 70 micrometers, etc.

[0093] Please refer to the following: Figure 4 Execute step S202: In Figure 3 Based on the structure shown, multiple spaced and parallel deep trenches are first formed in the first epitaxial layer 2 by dry etching. Then, backfill material is filled into the deep trenches by chemical vapor deposition. Finally, excess material outside the deep trenches is removed by grinding or chemical mechanical polishing to ensure the surface of the first epitaxial layer 2 is flat, thus forming multiple spaced and parallel first P-type pillars 3 in the first epitaxial layer 2. The first P-type pillars 3 are P-type element doped regions.

[0094] In some possible embodiments, all the first P-type pillars 3 have the same structural features. The material of the first P-type pillars 3 includes boron-doped silicon, and the width of the first P-type pillars 3 is not less than 3 micrometers, for example, 3 micrometers, 5 micrometers, 7 micrometers, etc. The height of the first P-type pillars 3 ranges from 30 to 40 micrometers, for example, 32 micrometers, 35 micrometers, 38 micrometers, etc.

[0095] Please refer to the following: Figure 5 Execute step S203: In Figure 4 Based on the structure shown, a second epitaxial layer 4 is formed on the first epitaxial layer 2 using an epitaxial process. The second epitaxial layer 4 is an N-type doped region, and the doping concentration of the second epitaxial layer 4 is greater than the doping concentration of the first epitaxial layer 2, while the doping concentration of the second epitaxial layer 4 is less than the doping concentration of the substrate layer 1.

[0096] In some possible embodiments, the material of the second epitaxial layer 4 includes p-doped silicon. The thickness of the second epitaxial layer 4 is in the range of 5-10 micrometers, for example 6 micrometers, 7.5 micrometers, 9 micrometers, etc.

[0097] Please refer to the following: Figure 6 Execute step S204: In Figure 5 Based on the structure shown, multiple spaced and parallel shallow trenches are first formed in the second epitaxial layer 4 by dry etching. Then, backfill material is filled into the shallow trenches by chemical vapor deposition. Finally, excess material outside the shallow trenches is removed by grinding or chemical mechanical polishing to ensure a smooth surface of the second epitaxial layer 4, thus forming multiple spaced and parallel second P-type pillars 5 in the second epitaxial layer 4. Each of the multiple second P-type pillars 5 corresponds one-to-one with a multiple of the first P-type pillars 3, and the corresponding second P-type pillars 5 and first P-type pillars 3 are in contact with each other. The second P-type pillars 5 are P-type element doped regions, and the doping concentration of the second P-type pillars 5 is greater than that of the first P-type pillars 3.

[0098] In some possible embodiments, the width of the second P-shaped column 5 is greater than the width of the first P-shaped column 3, and the height of the second P-shaped column 5 is less than the height of the first P-shaped column 3.

[0099] In some possible embodiments, all the second P-type pillars 5 have the same structural features. The material of the second P-type pillars 5 includes boron-doped silicon. The width of the second P-type pillars 5 is not less than 4 micrometers, for example, 4 micrometers, 6 micrometers, 8 micrometers, etc. The thickness of the second epitaxial layer 4 ranges from 5 to 10 micrometers, for example, 6 micrometers, 7.5 micrometers, 9 micrometers, etc.

[0100] Please refer to the following: Figure 7-9 Execute step S205: In Figure 6 Based on the structure shown, ion implantation of the upper surface of the second epitaxial layer 4 was performed using p-type elements, followed by rapid thermal annealing to activate impurity atoms, repair lattice damage, and form the initial bulk region 12, resulting in the structure shown. Figure 7 The structure shown. In Figure 7 Based on the structure shown, a vertical trench is first formed in the second epitaxial layer 4 between adjacent second P-type pillars 5 using dry etching technology. Then, a gate dielectric layer is formed on the sidewall of the vertical trench, and a gate conductive layer is formed inside the vertical trench, so that the gate dielectric layer surrounds the sidewall and bottom surface of the gate conductive layer. Subsequently, excess material on the surface of the second epitaxial layer 4 is removed by chemical mechanical polishing, thus forming the trench gate 6. The initial body regions 12 located on both sides of the trench gate 6 form the body regions 7, resulting in the structure shown. Figure 8 The structure shown. In Figure 8Based on the structure shown, ion implantation is performed on the upper surface of the body region 7 located between the trench gate 6 and the second P-type pillar 5 using N-type elements. Rapid thermal annealing is then performed after ion implantation to activate impurity atoms and repair lattice damage, thereby forming the source regions 8 located on both sides of the trench gate 6, resulting in the structure shown. Figure 9 The structure shown.

[0101] In some embodiments, the bottom surface of the trench grid 6 is higher than the bottom surface of the second P-shaped post 5. The height of the trench grid 6 ranges from 1.5 to 3 micrometers, for example, 2 micrometers, 2.5 micrometers, etc.

[0102] In some embodiments, the gate dielectric layer is made of silicon dioxide, which is formed by thermal oxidation. The gate conductive layer is made of polycrystalline silicon.

[0103] As an example, when ion implantation is performed on the upper surface of the second epitaxial layer 4 using P-type elements, the specific ion implantation parameters, such as dose, energy, and concentration, are set according to actual needs, provided that the doping concentration of the body region 7 is less than the doping concentrations of the first P-type pillar 3 and the second P-type pillar 5. Similarly, when ion implantation is performed on the upper surface of the body region 7 located between the trench gate 6 and the second P-type pillar 5 using N-type elements, the specific ion implantation parameters, such as dose, energy, and concentration, are set according to actual needs.

[0104] In some embodiments, the distance between the trench grid 6 and the two second P-shaped posts 5 located on both sides thereon is equal.

[0105] In some embodiments, the bottom surface of the trench grid 6 is higher than the bottom surface of the second P-shaped post 5.

[0106] In some possible embodiments, the material of the body region 7 includes boron-doped silicon. The thickness of the body region 7 is no greater than 1.5 micrometers, for example, 0.5 micrometers, 1 micrometer, 1.5 micrometers, etc.

[0107] In some possible embodiments, the gate dielectric layer is made of silicon dioxide, and the gate conductive layer is made of polysilicon. The height of the trench gate 6 ranges from 1.5 to 3 micrometers, for example, 2 micrometers, 2.5 micrometers, etc.

[0108] In some embodiments, the material of the source region 8 includes arsenic-doped silicon. The width of the source region 8 is no greater than 1 micrometer, for example, 1 micrometer, 0.5 micrometers, etc. The thickness of the source region 8 is no greater than 0.5 micrometers, for example, 0.4 micrometers, 0.2 micrometers, etc.

[0109] Please refer to the following: Figure 10 Execute step S206: In Figure 9Based on the structure shown, the insulating layer 9 is formed on the second epitaxial layer 4 by chemical vapor deposition or other suitable methods. The lower surface of the insulating layer 9 is in contact with the upper surface of the body region 7, the plurality of second P-type pillars 5, the trench gate 6, and the source region 8 located in the second epitaxial layer 4.

[0110] In some embodiments, the insulating layer 9 is made of silicon dioxide.

[0111] Please refer to the following: Figure 11 Execute step S207: In Figure 10 Based on the structure shown, a portion of the insulating layer 9 and a portion of the second P-shaped pillars 5 located below the insulating layer 9 are first removed by photolithography and dry etching to form multiple trenches. Then, material is filled into the trenches obtained after removing a portion of the insulating layer 9 and a portion of the second P-shaped pillars 5 by chemical vapor deposition. Finally, excess material located outside the trenches is removed by grinding or chemical mechanical polishing to ensure that the surface of the insulating layer 9 is flat, thus forming the contact portion 11.

[0112] As an example, the top end of each contact portion 11 is connected to the source metal layer 10, and the bottom end extends into the second P-shaped pillar 5. Each of the second P-shaped pillar 5 has a contact portion 11 at both ends, so that the source region 8 and the body region 7 are connected to the source metal layer 10 through the contact portion 11. The source metal layer 10 located outside the two ends of the second P-shaped pillar 5 connects the body region 7 to the source metal layer 10.

[0113] In some embodiments, a plurality of contact portions 11 located in the same second P-shaped post 5 are arranged parallel to each other, and the distance between any two adjacent contact portions 11 is equal.

[0114] In some possible embodiments, in the direction from one second P-shaped post 5 to the adjacent second P-shaped post 5, for example... Figure 1 In the X direction shown, a second P-shaped post 5 is provided with three or more contact portions 11 arranged sequentially and at intervals along the X direction, and the distance between any two adjacent contact portions 11 is equal. For example Figure 1 The image shows a second P-shaped column 5 with three contact portions 11 arranged sequentially and at intervals along the X direction. The left and right contact portions 11 are in direct contact with the source region 8 and the body region 7, while the middle contact portion 11 is equidistant from the left and right contact portions 11 and is not in direct contact with the source region 8 and the body region 7.

[0115] In some possible embodiments, the plurality of contact portions 11 are arranged in a multi-row, multi-column array.

[0116] In some embodiments, the contact portion 11 is made of a combination of aluminum and gold. The height of the contact portion 11 ranges from 4 to 5 micrometers, for example, 4.2 micrometers, 4.5 micrometers, or 4.8 micrometers. The length of the contact portion 11 extending into the second P-shaped post 5 ranges from 0.5 to 1.5 micrometers, for example, 0.8 micrometers, 1 micrometer, or 1.2 micrometers.

[0117] Please refer back to this next section. Figure 1 Execute step S208: In Figure 11 Based on the structure shown, the source metal layer 10 is formed on the insulating layer 9 by chemical vapor deposition, and the source metal layer 10 is connected to the top of the contact portion 11.

[0118] The superjunction MOSFET device of the present invention can be obtained through steps S201-S208.

[0119] In summary, the superjunction MOSFET device of the present invention includes a substrate layer, a first epitaxial layer, a plurality of spaced and parallel first P-type pillars, a second epitaxial layer, a plurality of spaced and parallel second P-type pillars, a trench gate, a body region, a source region, an insulating layer, a source metal layer, and a plurality of contacts. The first P-type pillars are located in the first epitaxial layer; the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; the second P-type pillars are located in the second epitaxial layer, and the doping concentration of the second P-type pillars is greater than that of the first P-type pillars; the trench gate is located in the second epitaxial layer between two adjacent second P-type pillars; the body region is located on the upper surface of the second epitaxial layer on both sides of the trench gate; the source region is located on the upper surface of the body region; the plurality of contacts penetrate the insulating layer, with the top end of each contact connected to the source metal layer and the bottom end extending into the second P-type pillar; at least one contact has a side surface connecting the source region and the body region. In this invention, the drift region resistance is reduced by setting a second epitaxial layer with a higher doping concentration, thereby reducing the on-resistance of the device. A charge balance is achieved by using a second P-type pillar with a higher doping concentration and a wider width in conjunction with the second epitaxial layer, reducing the impedance of the body region and ensuring that the breakdown voltage of the device does not decrease. Furthermore, by setting more contacts in the wider second P-type pillar to connect the source metal layer with the body and source regions, the parasitic transistor is less likely to conduct during avalanche, improving the device's EAS capability. The superjunction MOSFET device of this invention, by setting a second epitaxial layer with a higher doping concentration, a second P-type pillar with a higher doping concentration, and more contacts, further reduces the on-resistance of the device without decreasing the breakdown voltage, while simultaneously improving the device's EAS capability. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0120] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A superjunction MOSFET device, characterized in that, include: Substrate layer; The first epitaxial layer is located on the substrate layer; Multiple spaced and parallel first P-shaped pillars are located in the first epitaxial layer; The second epitaxial layer is located on the first epitaxial layer, and the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; Multiple second P-type pillars are spaced apart and arranged in parallel in the second epitaxial layer. The multiple second P-type pillars correspond one-to-one with the multiple first P-type pillars and are in contact with each other. The doping concentration of the second P-type pillars is greater than that of the first P-type pillars. The trench gate, body region, and source region are defined as follows: the trench gate is located in the second epitaxial layer between two adjacent second P-type pillars; the body region is located on the upper surface of the second epitaxial layer on both sides of the trench gate; and the source region is located on the upper surface of the body region. An insulating layer is located on the second epitaxial layer; A source metal layer is located on the insulating layer; Multiple contact portions penetrate the insulating layer, with the top end of each contact portion connected to the source metal layer and the bottom end extending into the second P-shaped pillar. At least one side of each contact portion connects the source region and the body region.

2. The superjunction MOSFET device according to claim 1, characterized in that: The height of the second P-shaped column is less than the height of the first P-shaped column, and the width of the second P-shaped column is greater than the width of the first P-shaped column.

3. The superjunction MOSFET device according to claim 2, characterized in that: The first P-type pillar is made of boron-doped silicon, and the width of the first P-type pillar is not less than 3 micrometers and the height ranges from 30 to 40 micrometers; the second P-type pillar is made of boron-doped silicon, and the width of the second P-type pillar is not less than 4 micrometers and the height ranges from 5 to 10 micrometers.

4. The superjunction MOSFET device according to claim 1, characterized in that: The distance between the trench grid and the two second P-shaped posts located on both sides thereon is equal.

5. The superjunction MOSFET device according to claim 1, characterized in that: The bottom surface of the trench grid is higher than the bottom surface of the second P-shaped post.

6. The superjunction MOSFET device according to claim 1, characterized in that: The distance between any two adjacent contact portions is equal.

7. The superjunction MOSFET device according to claim 1, characterized in that: The trench gate includes a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer surrounds the sidewalls and bottom surface of the gate conductive layer.

8. A method for fabricating a superjunction MOSFET device, characterized in that, include: A first epitaxial layer is formed on the substrate layer; Multiple spaced and parallel first P-shaped pillars are formed in the first epitaxial layer; A second epitaxial layer is formed on the first epitaxial layer, wherein the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; Multiple second P-type pillars are formed in the second epitaxial layer, which are spaced apart and arranged in parallel. The multiple second P-type pillars correspond one-to-one with the multiple first P-type pillars and are in contact with each other. The doping concentration of the second P-type pillars is greater than that of the first P-type pillars. A trench gate, a body region, and a source region are formed. The trench gate is located in the second epitaxial layer between two adjacent second P-type pillars. The body region is located on the upper surface of the second epitaxial layer on both sides of the trench gate. The source region is located on the upper surface of the body region. An insulating layer is formed on the second epitaxial layer; Multiple contact portions are formed, the contact portions penetrate the insulating layer and the bottom end of the contact portions extends into the second P-shaped post, and at least one side of the contact portion connects the source region and the body region; A source metal layer is formed on the insulating layer, and the source metal layer is connected to the top end of the contact portion.

9. The method for fabricating a superjunction MOSFET device according to claim 8, characterized in that: The first P-shaped pillar is formed by forming a first trench in the first epitaxial layer and backfilling it, and the second P-shaped pillar is formed by forming a second trench in the second epitaxial layer and backfilling it.

10. The method for fabricating a superjunction MOSFET device according to claim 8, characterized in that: The height of the second P-shaped column is less than the height of the first P-shaped column, and the width of the second P-shaped column is greater than the width of the first P-shaped column.

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